llvm/llvm/test/CodeGen/X86/shuffle-combine-crash-4.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx | FileCheck %s

; Make sure that we do not infinitely-loop combining shuffle vectors.

@test24_id5239 = dso_local local_unnamed_addr global i64 0, align 8
define void @infiloop() {
; CHECK-LABEL: infiloop:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    pushq %rbp
; CHECK-NEXT:    .cfi_def_cfa_offset 16
; CHECK-NEXT:    .cfi_offset %rbp, -16
; CHECK-NEXT:    movq %rsp, %rbp
; CHECK-NEXT:    .cfi_def_cfa_register %rbp
; CHECK-NEXT:    andq $-32, %rsp
; CHECK-NEXT:    subq $64, %rsp
; CHECK-NEXT:    movabsq $506097522914230528, %rax # imm = 0x706050403020100
; CHECK-NEXT:    movq %rax, test24_id5239(%rip)
; CHECK-NEXT:    vmovaps {{.*#+}} ymm0 = [4,1,6,7,6,7,2,3,6,7,4,5,6,7,2,3,6,7,2,3,2,3,2,3,4,5,4,5,2,3,0,1]
; CHECK-NEXT:    vmovaps %ymm0, (%rsp)
; CHECK-NEXT:    movq %rbp, %rsp
; CHECK-NEXT:    popq %rbp
; CHECK-NEXT:    .cfi_def_cfa %rsp, 8
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
entry:
  %id5230 = alloca <32 x i8>, align 32
  store i8 0, ptr @test24_id5239, align 8
  store i8 1, ptr getelementptr inbounds (i8, ptr @test24_id5239, i64 1), align 1
  store i8 2, ptr getelementptr inbounds (i8, ptr @test24_id5239, i64 2), align 2
  store i8 3, ptr getelementptr inbounds (i8, ptr @test24_id5239, i64 3), align 1
  store i8 4, ptr getelementptr inbounds (i8, ptr @test24_id5239, i64 4), align 4
  store i8 5, ptr getelementptr inbounds (i8, ptr @test24_id5239, i64 5), align 1
  store i8 6, ptr getelementptr inbounds (i8, ptr @test24_id5239, i64 6), align 2
  store i8 7, ptr getelementptr inbounds (i8, ptr @test24_id5239, i64 7), align 1
  %0 = load <4 x i16>, ptr @test24_id5239, align 8
  %shuffle = shufflevector <4 x i16> %0, <4 x i16> poison, <16 x i32> <i32 0, i32 3, i32 3, i32 1, i32 3, i32 2, i32 3, i32 1, i32 3, i32 1, i32 1, i32 1, i32 2, i32 2, i32 1, i32 0>
  %1 = bitcast <16 x i16> %shuffle to <32 x i8>
  %2 = or <32 x i8> %1, <i8 4, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
  store volatile <32 x i8> %2, ptr %id5230, align 32
  ret void
}