/*
* Copyright (c) 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <clc/clc.h>
#include "math.h"
#include "sincos_helpers.h"
#include "../clcmacro.h"
_CLC_OVERLOAD _CLC_DEF float sin(float x)
{
int ix = as_int(x);
int ax = ix & 0x7fffffff;
float dx = as_float(ax);
float r0, r1;
int regn = __clc_argReductionS(&r0, &r1, dx);
float ss = __clc_sinf_piby4(r0, r1);
float cc = __clc_cosf_piby4(r0, r1);
float s = (regn & 1) != 0 ? cc : ss;
s = as_float(as_int(s) ^ ((regn > 1) << 31) ^ (ix ^ ax));
s = ax >= PINFBITPATT_SP32 ? as_float(QNANBITPATT_SP32) : s;
//Subnormals
s = x == 0.0f ? x : s;
return s;
}
_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, sin, float);
#ifdef cl_khr_fp64
#pragma OPENCL EXTENSION cl_khr_fp64 : enable
_CLC_OVERLOAD _CLC_DEF double sin(double x) {
double y = fabs(x);
double r, rr;
int regn;
if (y < 0x1.0p+47)
__clc_remainder_piby2_medium(y, &r, &rr, ®n);
else
__clc_remainder_piby2_large(y, &r, &rr, ®n);
double2 sc = __clc_sincos_piby4(r, rr);
int2 s = as_int2(regn & 1 ? sc.hi : sc.lo);
s.hi ^= ((regn > 1) << 31) ^ ((x < 0.0) << 31);
return isinf(x) | isnan(x) ? as_double(QNANBITPATT_DP64) : as_double(s);
}
_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, sin, double);
#endif
_CLC_DEFINE_UNARY_BUILTIN_FP16(sin)