aarch64-targetattr.c | Explore in Territory

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --check-globals
// RUN: %clang_cc1 -triple aarch64 -emit-llvm %s -o - | FileCheck %s

__attribute__((target("arch=armv8.2-a")))
// CHECK-LABEL: define {{[^@]+}}@v82
// CHECK-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void v82() {}
__attribute__((target("arch=armv8.2-a+sve")))
// CHECK-LABEL: define {{[^@]+}}@v82sve
// CHECK-SAME: () #[[ATTR1:[0-9]+]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void v82sve() {}
__attribute__((target("arch=armv8.2-a+sve2")))
// CHECK-LABEL: define {{[^@]+}}@v82sve2
// CHECK-SAME: () #[[ATTR2:[0-9]+]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void v82sve2() {}
__attribute__((target("arch=armv8.2-a+sve+sve2")))
// CHECK-LABEL: define {{[^@]+}}@v82svesve2
// CHECK-SAME: () #[[ATTR2]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void v82svesve2() {}
__attribute__((target("arch=armv8.6-a+sve2")))
// CHECK-LABEL: define {{[^@]+}}@v86sve2
// CHECK-SAME: () #[[ATTR3:[0-9]+]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void v86sve2() {}

__attribute__((target("cpu=cortex-a710")))
// CHECK-LABEL: define {{[^@]+}}@a710
// CHECK-SAME: () #[[ATTR4:[0-9]+]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void a710() {}
__attribute__((target("tune=cortex-a710")))
// CHECK-LABEL: define {{[^@]+}}@tunea710
// CHECK-SAME: () #[[ATTR5:[0-9]+]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void tunea710() {}
__attribute__((target("cpu=generic")))
// CHECK-LABEL: define {{[^@]+}}@generic
// CHECK-SAME: () #[[ATTR6:[0-9]+]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void generic() {}
__attribute__((target("tune=generic")))
// CHECK-LABEL: define {{[^@]+}}@tune
// CHECK-SAME: () #[[ATTR7:[0-9]+]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void tune() {}

__attribute__((target("cpu=neoverse-n1,tune=cortex-a710")))
// CHECK-LABEL: define {{[^@]+}}@n1tunea710
// CHECK-SAME: () #[[ATTR8:[0-9]+]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void n1tunea710() {}
__attribute__((target("sve,tune=cortex-a710")))
// CHECK-LABEL: define {{[^@]+}}@svetunea710
// CHECK-SAME: () #[[ATTR9:[0-9]+]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void svetunea710() {}
__attribute__((target("+sve,tune=cortex-a710")))
// CHECK-LABEL: define {{[^@]+}}@plussvetunea710
// CHECK-SAME: () #[[ATTR9]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void plussvetunea710() {}
__attribute__((target("cpu=neoverse-v1,+sve2")))
// CHECK-LABEL: define {{[^@]+}}@v1plussve2
// CHECK-SAME: () #[[ATTR10:[0-9]+]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void v1plussve2() {}
__attribute__((target("cpu=neoverse-v1+sve2")))
// CHECK-LABEL: define {{[^@]+}}@v1sve2
// CHECK-SAME: () #[[ATTR10]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void v1sve2() {}
__attribute__((target("cpu=neoverse-v1,+nosve")))
// CHECK-LABEL: define {{[^@]+}}@v1minussve
// CHECK-SAME: () #[[ATTR11:[0-9]+]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void v1minussve() {}
__attribute__((target("cpu=neoverse-v1,no-sve")))
// CHECK-LABEL: define {{[^@]+}}@v1nosve
// CHECK-SAME: () #[[ATTR11]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void v1nosve() {}
__attribute__((target("cpu=neoverse-v1+nosve")))
// CHECK-LABEL: define {{[^@]+}}@v1msve
// CHECK-SAME: () #[[ATTR11]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void v1msve() {}

__attribute__((target("+sve")))
// CHECK-LABEL: define {{[^@]+}}@plussve
// CHECK-SAME: () #[[ATTR12:[0-9]+]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void plussve() {}
__attribute__((target("+sve+nosve2")))
// CHECK-LABEL: define {{[^@]+}}@plussveplussve2
// CHECK-SAME: () #[[ATTR12]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void plussveplussve2() {}
__attribute__((target("sve,no-sve2")))
// CHECK-LABEL: define {{[^@]+}}@plussveminusnosve2
// CHECK-SAME: () #[[ATTR12]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void plussveminusnosve2() {}
__attribute__((target("+fp16")))
// CHECK-LABEL: define {{[^@]+}}@plusfp16
// CHECK-SAME: () #[[ATTR13:[0-9]+]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void plusfp16() {}

__attribute__((target("cpu=neoverse-n1,tune=cortex-a710,arch=armv8.6-a+sve2")))
// CHECK-LABEL: define {{[^@]+}}@all
// CHECK-SAME: () #[[ATTR14:[0-9]+]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void all() {}
__attribute__((target("cpu=neoverse-n1,tune=cortex-a710,arch=armv8.6-a+sve2,branch-protection=standard")))
// CHECK-LABEL: define {{[^@]+}}@allplusbranchprotection
// CHECK-SAME: () #[[ATTR15:[0-9]+]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void allplusbranchprotection() {}

__attribute__((target("+nosimd")))
// CHECK-LABEL: define {{[^@]+}}@plusnosimd
// CHECK-SAME: () #[[ATTR16:[0-9]+]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void plusnosimd() {}
__attribute__((target("no-simd")))
// CHECK-LABEL: define {{[^@]+}}@nosimd
// CHECK-SAME: () #[[ATTR16]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void nosimd() {}

// This isn't part of the standard interface, but test that -arch features should not apply anything else.
__attribute__((target("no-v9.3a")))
// CHECK-LABEL: define {{[^@]+}}@minusarch
// CHECK-SAME: () #[[ATTR17:[0-9]+]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void minusarch() {}

__attribute__((target("cpu=apple-m4")))
// CHECK-LABEL: define {{[^@]+}}@applem4
// CHECK-SAME: () #[[ATTR18:[0-9]+]] {
// CHECK-NEXT:  entry:
// CHECK-NEXT:    ret void
//
void applem4() {}

//.
// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" }
// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a710" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve2,+sve2-bitperm,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a" }
// CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR6]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+ete,+fp-armv8,+neon,+trbe,+v8a" }
// CHECK: attributes #[[ATTR7]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="generic" }
// CHECK: attributes #[[ATTR8]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+v8.1a,+v8.2a,+v8a" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR9]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+sve" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a" }
// CHECK: attributes #[[ATTR11]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,-sve" }
// CHECK: attributes #[[ATTR12]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+sve" }
// CHECK: attributes #[[ATTR13]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16" }
// CHECK: attributes #[[ATTR14]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "branch-target-enforcement" "guarded-control-stack" "no-trapping-math"="true" "sign-return-address"="non-leaf" "sign-return-address-key"="a_key" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR16]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
// CHECK: attributes #[[ATTR17]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-v9.3a" }
// CHECK: attributes #[[ATTR18]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m4" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fpac,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+sha3,+sme,+sme-f64f64,+sme-i16i64,+sme2,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8a,+wfxt" }
//.
// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
//.
llvm/clang/test/CodeGen/aarch64-targetattr.c
