//===- CodeGenSchedule.h - Scheduling Machine Models ------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file defines structures to encapsulate the machine model as described in // the target description. // //===----------------------------------------------------------------------===// #ifndef LLVM_UTILS_TABLEGEN_COMMON_CODEGENSCHEDULE_H #define LLVM_UTILS_TABLEGEN_COMMON_CODEGENSCHEDULE_H #include "llvm/ADT/APInt.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseSet.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringRef.h" #include "llvm/TableGen/Record.h" #include "llvm/TableGen/SetTheory.h" #include <cassert> #include <string> #include <utility> #include <vector> namespace llvm { class CodeGenTarget; class CodeGenSchedModels; class CodeGenInstruction; ConstRecVec; ConstRecIter; IdxVec; IdxIter; /// We have two kinds of SchedReadWrites. Explicitly defined and inferred /// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or /// may not be empty. TheDef is null for inferred sequences, and Sequence must /// be nonempty. /// /// IsVariadic controls whether the variants are expanded into multiple operands /// or a sequence of writes on one operand. struct CodeGenSchedRW { … }; /// Represent a transition between SchedClasses induced by SchedVariant. struct CodeGenSchedTransition { … }; /// Scheduling class. /// /// Each instruction description will be mapped to a scheduling class. There are /// four types of classes: /// /// 1) An explicitly defined itinerary class with ItinClassDef set. /// Writes and ReadDefs are empty. ProcIndices contains 0 for any processor. /// /// 2) An implied class with a list of SchedWrites and SchedReads that are /// defined in an instruction definition and which are common across all /// subtargets. ProcIndices contains 0 for any processor. /// /// 3) An implied class with a list of InstRW records that map instructions to /// SchedWrites and SchedReads per-processor. InstrClassMap should map the same /// instructions to this class. ProcIndices contains all the processors that /// provided InstrRW records for this class. ItinClassDef or Writes/Reads may /// still be defined for processors with no InstRW entry. /// /// 4) An inferred class represents a variant of another class that may be /// resolved at runtime. ProcIndices contains the set of processors that may /// require the class. ProcIndices are propagated through SchedClasses as /// variants are expanded. Multiple SchedClasses may be inferred from an /// itinerary class. Each inherits the processor index from the ItinRW record /// that mapped the itinerary class to the variant Writes or Reads. struct CodeGenSchedClass { … }; /// Represent the cost of allocating a register of register class RCDef. /// /// The cost of allocating a register is equivalent to the number of physical /// registers used by the register renamer. Register costs are defined at /// register class granularity. struct CodeGenRegisterCost { … }; /// A processor register file. /// /// This class describes a processor register file. Register file information is /// currently consumed by external tools like llvm-mca to predict dispatch /// stalls due to register pressure. struct CodeGenRegisterFile { … }; // Processor model. // // ModelName is a unique name used to name an instantiation of MCSchedModel. // // ModelDef is NULL for inferred Models. This happens when a processor defines // an itinerary but no machine model. If the processor defines neither a machine // model nor itinerary, then ModelDef remains pointing to NoModel. NoModel has // the special "NoModel" field set to true. // // ItinsDef always points to a valid record definition, but may point to the // default NoItineraries. NoItineraries has an empty list of InstrItinData // records. // // ItinDefList orders this processor's InstrItinData records by SchedClass idx. struct CodeGenProcModel { … }; /// Used to correlate instructions to MCInstPredicates specified by /// InstructionEquivalentClass tablegen definitions. /// /// Example: a XOR of a register with self, is a known zero-idiom for most /// X86 processors. /// /// Each processor can use a (potentially different) InstructionEquivalenceClass /// definition to classify zero-idioms. That means, XORrr is likely to appear /// in more than one equivalence class (where each class definition is /// contributed by a different processor). /// /// There is no guarantee that the same MCInstPredicate will be used to describe /// equivalence classes that identify XORrr as a zero-idiom. /// /// To be more specific, the requirements for being a zero-idiom XORrr may be /// different for different processors. /// /// Class PredicateInfo identifies a subset of processors that specify the same /// requirements (i.e. same MCInstPredicate and OperandMask) for an instruction /// opcode. /// /// Back to the example. Field `ProcModelMask` will have one bit set for every /// processor model that sees XORrr as a zero-idiom, and that specifies the same /// set of constraints. /// /// By construction, there can be multiple instances of PredicateInfo associated /// with a same instruction opcode. For example, different processors may define /// different constraints on the same opcode. /// /// Field OperandMask can be used as an extra constraint. /// It may be used to describe conditions that appy only to a subset of the /// operands of a machine instruction, and the operands subset may not be the /// same for all processor models. struct PredicateInfo { … }; /// A collection of PredicateInfo objects. /// /// There is at least one OpcodeInfo object for every opcode specified by a /// TIPredicate definition. class OpcodeInfo { … }; /// Used to group together tablegen instruction definitions that are subject /// to a same set of constraints (identified by an instance of OpcodeInfo). class OpcodeGroup { … }; /// An STIPredicateFunction descriptor used by tablegen backends to /// auto-generate the body of a predicate function as a member of tablegen'd /// class XXXGenSubtargetInfo. class STIPredicateFunction { … }; ProcModelMapTy; /// Top level container for machine model data. class CodeGenSchedModels { … }; } // namespace llvm #endif // LLVM_UTILS_TABLEGEN_COMMON_CODEGENSCHEDULE_H