llvm/llvm/utils/TableGen/InstrDocsEmitter.cpp

//===- InstrDocsEmitter.cpp - Opcode Documentation Generator --------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// InstrDocsEmitter generates restructured text documentation for the opcodes
// that can be used by MachineInstr. For each opcode, the documentation lists:
// * Opcode name
// * Assembly string
// * Flags (e.g. mayLoad, isBranch, ...)
// * Operands, including type and name
// * Operand constraints
// * Implicit register uses & defs
// * Predicates
//
//===----------------------------------------------------------------------===//

#include "Common/CodeGenDAGPatterns.h"
#include "Common/CodeGenInstruction.h"
#include "Common/CodeGenTarget.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
#include <string>
#include <vector>

usingnamespacellvm;

static void writeTitle(StringRef Str, raw_ostream &OS, char Kind = '-') { … }

static void writeHeader(StringRef Str, raw_ostream &OS, char Kind = '-') { … }

static std::string escapeForRST(StringRef Str) { … }

static void EmitInstrDocs(const RecordKeeper &RK, raw_ostream &OS) { … }

static TableGen::Emitter::Opt X("gen-instr-docs", EmitInstrDocs,
                                "Generate instruction documentation");