# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s
# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s
--- |
define <vscale x 1 x i8> @vload_nxv1i8(ptr %pa) #0 {
%va = load <vscale x 1 x i8>, ptr %pa, align 1
ret <vscale x 1 x i8> %va
}
define <vscale x 2 x i8> @vload_nxv2i8(ptr %pa) #0 {
%va = load <vscale x 2 x i8>, ptr %pa, align 2
ret <vscale x 2 x i8> %va
}
define <vscale x 4 x i8> @vload_nxv4i8(ptr %pa) #0 {
%va = load <vscale x 4 x i8>, ptr %pa, align 4
ret <vscale x 4 x i8> %va
}
define <vscale x 8 x i8> @vload_nxv8i8(ptr %pa) #0 {
%va = load <vscale x 8 x i8>, ptr %pa, align 8
ret <vscale x 8 x i8> %va
}
define <vscale x 16 x i8> @vload_nxv16i8(ptr %pa) #0 {
%va = load <vscale x 16 x i8>, ptr %pa, align 16
ret <vscale x 16 x i8> %va
}
define <vscale x 32 x i8> @vload_nxv32i8(ptr %pa) #0 {
%va = load <vscale x 32 x i8>, ptr %pa, align 32
ret <vscale x 32 x i8> %va
}
define <vscale x 64 x i8> @vload_nxv64i8(ptr %pa) #0 {
%va = load <vscale x 64 x i8>, ptr %pa, align 64
ret <vscale x 64 x i8> %va
}
define <vscale x 1 x i16> @vload_nxv1i16(ptr %pa) #0 {
%va = load <vscale x 1 x i16>, ptr %pa, align 2
ret <vscale x 1 x i16> %va
}
define <vscale x 2 x i16> @vload_nxv2i16(ptr %pa) #0 {
%va = load <vscale x 2 x i16>, ptr %pa, align 4
ret <vscale x 2 x i16> %va
}
define <vscale x 4 x i16> @vload_nxv4i16(ptr %pa) #0 {
%va = load <vscale x 4 x i16>, ptr %pa, align 8
ret <vscale x 4 x i16> %va
}
define <vscale x 8 x i16> @vload_nxv8i16(ptr %pa) #0 {
%va = load <vscale x 8 x i16>, ptr %pa, align 16
ret <vscale x 8 x i16> %va
}
define <vscale x 16 x i16> @vload_nxv16i16(ptr %pa) #0 {
%va = load <vscale x 16 x i16>, ptr %pa, align 32
ret <vscale x 16 x i16> %va
}
define <vscale x 32 x i16> @vload_nxv32i16(ptr %pa) #0 {
%va = load <vscale x 32 x i16>, ptr %pa, align 64
ret <vscale x 32 x i16> %va
}
define <vscale x 1 x i32> @vload_nxv1i32(ptr %pa) #0 {
%va = load <vscale x 1 x i32>, ptr %pa, align 4
ret <vscale x 1 x i32> %va
}
define <vscale x 2 x i32> @vload_nxv2i32(ptr %pa) #0 {
%va = load <vscale x 2 x i32>, ptr %pa, align 8
ret <vscale x 2 x i32> %va
}
define <vscale x 4 x i32> @vload_nxv4i32(ptr %pa) #0 {
%va = load <vscale x 4 x i32>, ptr %pa, align 16
ret <vscale x 4 x i32> %va
}
define <vscale x 8 x i32> @vload_nxv8i32(ptr %pa) #0 {
%va = load <vscale x 8 x i32>, ptr %pa, align 32
ret <vscale x 8 x i32> %va
}
define <vscale x 16 x i32> @vload_nxv16i32(ptr %pa) #0 {
%va = load <vscale x 16 x i32>, ptr %pa, align 64
ret <vscale x 16 x i32> %va
}
define <vscale x 1 x i64> @vload_nxv1i64(ptr %pa) #0 {
%va = load <vscale x 1 x i64>, ptr %pa, align 8
ret <vscale x 1 x i64> %va
}
define <vscale x 2 x i64> @vload_nxv2i64(ptr %pa) #0 {
%va = load <vscale x 2 x i64>, ptr %pa, align 16
ret <vscale x 2 x i64> %va
}
define <vscale x 4 x i64> @vload_nxv4i64(ptr %pa) #0 {
%va = load <vscale x 4 x i64>, ptr %pa, align 32
ret <vscale x 4 x i64> %va
}
define <vscale x 8 x i64> @vload_nxv8i64(ptr %pa) #0 {
%va = load <vscale x 8 x i64>, ptr %pa, align 64
ret <vscale x 8 x i64> %va
}
define <vscale x 16 x i8> @vload_nxv16i8_align1(ptr %pa) #0 {
%va = load <vscale x 16 x i8>, ptr %pa, align 1
ret <vscale x 16 x i8> %va
}
define <vscale x 16 x i8> @vload_nxv16i8_align2(ptr %pa) #0 {
%va = load <vscale x 16 x i8>, ptr %pa, align 2
ret <vscale x 16 x i8> %va
}
define <vscale x 16 x i8> @vload_nxv16i8_align16(ptr %pa) #0 {
%va = load <vscale x 16 x i8>, ptr %pa, align 16
ret <vscale x 16 x i8> %va
}
define <vscale x 16 x i8> @vload_nxv16i8_align64(ptr %pa) #0 {
%va = load <vscale x 16 x i8>, ptr %pa, align 64
ret <vscale x 16 x i8> %va
}
define <vscale x 4 x i16> @vload_nxv4i16_align1(ptr %pa) #0 {
%va = load <vscale x 4 x i16>, ptr %pa, align 1
ret <vscale x 4 x i16> %va
}
define <vscale x 4 x i16> @vload_nxv4i16_align2(ptr %pa) #0 {
%va = load <vscale x 4 x i16>, ptr %pa, align 2
ret <vscale x 4 x i16> %va
}
define <vscale x 4 x i16> @vload_nxv4i16_align4(ptr %pa) #0 {
%va = load <vscale x 4 x i16>, ptr %pa, align 4
ret <vscale x 4 x i16> %va
}
define <vscale x 4 x i16> @vload_nxv4i16_align8(ptr %pa) #0 {
%va = load <vscale x 4 x i16>, ptr %pa, align 8
ret <vscale x 4 x i16> %va
}
define <vscale x 4 x i16> @vload_nxv4i16_align16(ptr %pa) #0 {
%va = load <vscale x 4 x i16>, ptr %pa, align 16
ret <vscale x 4 x i16> %va
}
define <vscale x 2 x i32> @vload_nxv2i32_align2(ptr %pa) #0 {
%va = load <vscale x 2 x i32>, ptr %pa, align 2
ret <vscale x 2 x i32> %va
}
define <vscale x 2 x i32> @vload_nxv2i32_align4(ptr %pa) #0 {
%va = load <vscale x 2 x i32>, ptr %pa, align 4
ret <vscale x 2 x i32> %va
}
define <vscale x 2 x i32> @vload_nxv2i32_align8(ptr %pa) #0 {
%va = load <vscale x 2 x i32>, ptr %pa, align 8
ret <vscale x 2 x i32> %va
}
define <vscale x 2 x i32> @vload_nxv2i32_align16(ptr %pa) #0 {
%va = load <vscale x 2 x i32>, ptr %pa, align 16
ret <vscale x 2 x i32> %va
}
define <vscale x 2 x i32> @vload_nxv2i32_align256(ptr %pa) #0 {
%va = load <vscale x 2 x i32>, ptr %pa, align 256
ret <vscale x 2 x i32> %va
}
define <vscale x 2 x i64> @vload_nxv2i64_align4(ptr %pa) #0 {
%va = load <vscale x 2 x i64>, ptr %pa, align 4
ret <vscale x 2 x i64> %va
}
define <vscale x 2 x i64> @vload_nxv2i64_align8(ptr %pa) #0 {
%va = load <vscale x 2 x i64>, ptr %pa, align 8
ret <vscale x 2 x i64> %va
}
define <vscale x 2 x i64> @vload_nxv2i64_align16(ptr %pa) #0 {
%va = load <vscale x 2 x i64>, ptr %pa, align 16
ret <vscale x 2 x i64> %va
}
define <vscale x 2 x i64> @vload_nxv2i64_align32(ptr %pa) #0 {
%va = load <vscale x 2 x i64>, ptr %pa, align 32
ret <vscale x 2 x i64> %va
}
attributes #0 = { "target-features"="+v" }
...
---
name: vload_nxv1i8
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv1i8
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x s8>) from %ir.pa)
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 1 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s8>) from %ir.pa)
$v8 = COPY %1(<vscale x 1 x s8>)
PseudoRET implicit $v8
...
---
name: vload_nxv2i8
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv2i8
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s8>) from %ir.pa)
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 2 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s8>) from %ir.pa)
$v8 = COPY %1(<vscale x 2 x s8>)
PseudoRET implicit $v8
...
---
name: vload_nxv4i8
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv4i8
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s8>) from %ir.pa)
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 4 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s8>) from %ir.pa)
$v8 = COPY %1(<vscale x 4 x s8>)
PseudoRET implicit $v8
...
---
name: vload_nxv8i8
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv8i8
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s8>) from %ir.pa)
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 8 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 8 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s8>) from %ir.pa)
$v8 = COPY %1(<vscale x 8 x s8>)
PseudoRET implicit $v8
...
---
name: vload_nxv16i8
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv16i8
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa)
; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%0:_(p0) = COPY $x10
%1:_(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa)
$v8m2 = COPY %1(<vscale x 16 x s8>)
PseudoRET implicit $v8m2
...
---
name: vload_nxv32i8
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv32i8
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 32 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 32 x s8>) from %ir.pa)
; CHECK-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 32 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%0:_(p0) = COPY $x10
%1:_(<vscale x 32 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 32 x s8>) from %ir.pa)
$v8m4 = COPY %1(<vscale x 32 x s8>)
PseudoRET implicit $v8m4
...
---
name: vload_nxv64i8
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv64i8
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 64 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 64 x s8>) from %ir.pa)
; CHECK-NEXT: $v8m8 = COPY [[LOAD]](<vscale x 64 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8m8
%0:_(p0) = COPY $x10
%1:_(<vscale x 64 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 64 x s8>) from %ir.pa)
$v8m8 = COPY %1(<vscale x 64 x s8>)
PseudoRET implicit $v8m8
...
---
name: vload_nxv1i16
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv1i16
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x s16>) from %ir.pa)
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 1 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s16>) from %ir.pa)
$v8 = COPY %1(<vscale x 1 x s16>)
PseudoRET implicit $v8
...
---
name: vload_nxv2i16
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv2i16
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s16>) from %ir.pa)
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 2 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s16>) from %ir.pa)
$v8 = COPY %1(<vscale x 2 x s16>)
PseudoRET implicit $v8
...
---
name: vload_nxv4i16
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv4i16
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa)
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa)
$v8 = COPY %1(<vscale x 4 x s16>)
PseudoRET implicit $v8
...
---
name: vload_nxv8i16
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv8i16
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s16>) from %ir.pa)
; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 8 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%0:_(p0) = COPY $x10
%1:_(<vscale x 8 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s16>) from %ir.pa)
$v8m2 = COPY %1(<vscale x 8 x s16>)
PseudoRET implicit $v8m2
...
---
name: vload_nxv16i16
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv16i16
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s16>) from %ir.pa)
; CHECK-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 16 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%0:_(p0) = COPY $x10
%1:_(<vscale x 16 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s16>) from %ir.pa)
$v8m4 = COPY %1(<vscale x 16 x s16>)
PseudoRET implicit $v8m4
...
---
name: vload_nxv32i16
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv32i16
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 32 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 32 x s16>) from %ir.pa)
; CHECK-NEXT: $v8m8 = COPY [[LOAD]](<vscale x 32 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8m8
%0:_(p0) = COPY $x10
%1:_(<vscale x 32 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 32 x s16>) from %ir.pa)
$v8m8 = COPY %1(<vscale x 32 x s16>)
PseudoRET implicit $v8m8
...
---
name: vload_nxv1i32
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv1i32
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x s32>) from %ir.pa)
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 1 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s32>) from %ir.pa)
$v8 = COPY %1(<vscale x 1 x s32>)
PseudoRET implicit $v8
...
---
name: vload_nxv2i32
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv2i32
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa)
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa)
$v8 = COPY %1(<vscale x 2 x s32>)
PseudoRET implicit $v8
...
---
name: vload_nxv4i32
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv4i32
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s32>) from %ir.pa)
; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 4 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%0:_(p0) = COPY $x10
%1:_(<vscale x 4 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s32>) from %ir.pa)
$v8m2 = COPY %1(<vscale x 4 x s32>)
PseudoRET implicit $v8m2
...
---
name: vload_nxv8i32
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv8i32
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s32>) from %ir.pa)
; CHECK-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 8 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%0:_(p0) = COPY $x10
%1:_(<vscale x 8 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s32>) from %ir.pa)
$v8m4 = COPY %1(<vscale x 8 x s32>)
PseudoRET implicit $v8m4
...
---
name: vload_nxv16i32
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv16i32
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s32>) from %ir.pa)
; CHECK-NEXT: $v8m8 = COPY [[LOAD]](<vscale x 16 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8m8
%0:_(p0) = COPY $x10
%1:_(<vscale x 16 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s32>) from %ir.pa)
$v8m8 = COPY %1(<vscale x 16 x s32>)
PseudoRET implicit $v8m8
...
---
name: vload_nxv1i64
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv1i64
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x s64>) from %ir.pa)
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 1 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s64>) from %ir.pa)
$v8 = COPY %1(<vscale x 1 x s64>)
PseudoRET implicit $v8
...
---
name: vload_nxv2i64
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv2i64
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s64>) from %ir.pa)
; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 2 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%0:_(p0) = COPY $x10
%1:_(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>) from %ir.pa)
$v8m2 = COPY %1(<vscale x 2 x s64>)
PseudoRET implicit $v8m2
...
---
name: vload_nxv4i64
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv4i64
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s64>) from %ir.pa)
; CHECK-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 4 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%0:_(p0) = COPY $x10
%1:_(<vscale x 4 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s64>) from %ir.pa)
$v8m4 = COPY %1(<vscale x 4 x s64>)
PseudoRET implicit $v8m4
...
---
name: vload_nxv8i64
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv8i64
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s64>) from %ir.pa)
; CHECK-NEXT: $v8m8 = COPY [[LOAD]](<vscale x 8 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m8
%0:_(p0) = COPY $x10
%1:_(<vscale x 8 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s64>) from %ir.pa)
$v8m8 = COPY %1(<vscale x 8 x s64>)
PseudoRET implicit $v8m8
...
---
name: vload_nxv16i8_align1
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv16i8_align1
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 1)
; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%0:_(p0) = COPY $x10
%1:_(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 1)
$v8m2 = COPY %1(<vscale x 16 x s8>)
PseudoRET implicit $v8m2
...
---
name: vload_nxv16i8_align2
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv16i8_align2
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 2)
; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%0:_(p0) = COPY $x10
%1:_(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 2)
$v8m2 = COPY %1(<vscale x 16 x s8>)
PseudoRET implicit $v8m2
...
---
name: vload_nxv16i8_align16
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv16i8_align16
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa)
; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%0:_(p0) = COPY $x10
%1:_(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa)
$v8m2 = COPY %1(<vscale x 16 x s8>)
PseudoRET implicit $v8m2
...
---
name: vload_nxv16i8_align64
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv16i8_align64
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 64)
; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%0:_(p0) = COPY $x10
%1:_(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 64)
$v8m2 = COPY %1(<vscale x 16 x s8>)
PseudoRET implicit $v8m2
...
---
name: vload_nxv4i16_align1
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv4i16_align1
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s8>) from %ir.pa, align 1)
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 4 x s16>) = G_BITCAST [[LOAD]](<vscale x 8 x s8>)
; CHECK-NEXT: $v8 = COPY [[BITCAST]](<vscale x 4 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 1)
$v8 = COPY %1(<vscale x 4 x s16>)
PseudoRET implicit $v8
...
---
name: vload_nxv4i16_align2
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv4i16_align2
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 2)
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 2)
$v8 = COPY %1(<vscale x 4 x s16>)
PseudoRET implicit $v8
...
---
name: vload_nxv4i16_align4
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv4i16_align4
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 4)
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 4)
$v8 = COPY %1(<vscale x 4 x s16>)
PseudoRET implicit $v8
...
---
name: vload_nxv4i16_align8
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv4i16_align8
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa)
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa)
$v8 = COPY %1(<vscale x 4 x s16>)
PseudoRET implicit $v8
...
---
name: vload_nxv4i16_align16
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv4i16_align16
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 16)
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 16)
$v8 = COPY %1(<vscale x 4 x s16>)
PseudoRET implicit $v8
...
---
name: vload_nxv2i32_align2
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv2i32_align2
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s8>) from %ir.pa, align 2)
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x s32>) = G_BITCAST [[LOAD]](<vscale x 8 x s8>)
; CHECK-NEXT: $v8 = COPY [[BITCAST]](<vscale x 2 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 2)
$v8 = COPY %1(<vscale x 2 x s32>)
PseudoRET implicit $v8
...
---
name: vload_nxv2i32_align4
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv2i32_align4
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 4)
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 4)
$v8 = COPY %1(<vscale x 2 x s32>)
PseudoRET implicit $v8
...
---
name: vload_nxv2i32_align8
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv2i32_align8
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa)
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa)
$v8 = COPY %1(<vscale x 2 x s32>)
PseudoRET implicit $v8
...
---
name: vload_nxv2i32_align16
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv2i32_align16
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 16)
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 16)
$v8 = COPY %1(<vscale x 2 x s32>)
PseudoRET implicit $v8
...
---
name: vload_nxv2i32_align256
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv2i32_align256
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 256)
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 256)
$v8 = COPY %1(<vscale x 2 x s32>)
PseudoRET implicit $v8
...
---
name: vload_nxv2i64_align4
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv2i64_align4
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 4)
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x s64>) = G_BITCAST [[LOAD]](<vscale x 16 x s8>)
; CHECK-NEXT: $v8m2 = COPY [[BITCAST]](<vscale x 2 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%0:_(p0) = COPY $x10
%1:_(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 4)
$v8m2 = COPY %1(<vscale x 2 x s64>)
PseudoRET implicit $v8m2
...
---
name: vload_nxv2i64_align8
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv2i64_align8
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 8)
; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 2 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%0:_(p0) = COPY $x10
%1:_(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 8)
$v8m2 = COPY %1(<vscale x 2 x s64>)
PseudoRET implicit $v8m2
...
---
name: vload_nxv2i64_align16
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv2i64_align16
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s64>) from %ir.pa)
; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 2 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%0:_(p0) = COPY $x10
%1:_(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>) from %ir.pa)
$v8m2 = COPY %1(<vscale x 2 x s64>)
PseudoRET implicit $v8m2
...
---
name: vload_nxv2i64_align32
body: |
bb.1 (%ir-block.0):
liveins: $x10
; CHECK-LABEL: name: vload_nxv2i64_align32
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 32)
; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 2 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%0:_(p0) = COPY $x10
%1:_(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 32)
$v8m2 = COPY %1(<vscale x 2 x s64>)
PseudoRET implicit $v8m2
...
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