llvm/llvm/test/CodeGen/AArch64/optimize_combine_large_shifts.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=neon | FileCheck %s

define <16 x i8> @combine16ix8(<8 x i16> %0, <8 x i16> %1) {
; CHECK-LABEL: combine16ix8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp2 v0.16b, v0.16b, v1.16b
; CHECK-NEXT:    ushr v0.16b, v0.16b, #2
; CHECK-NEXT:    ret
  %3 = lshr <8 x i16> %0, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
  %4 = lshr <8 x i16> %1, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
  %5 = shufflevector <8 x i16> %3, <8 x i16> %4, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  %6 = trunc nuw nsw <16 x i16> %5 to <16 x i8>
  ret <16 x i8> %6
}

define <8 x i16> @combine32ix4(<4 x i32> %0, <4 x i32> %1) {
; CHECK-LABEL: combine32ix4:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp2 v0.8h, v0.8h, v1.8h
; CHECK-NEXT:    ushr v0.8h, v0.8h, #4
; CHECK-NEXT:    ret
  %3 = lshr <4 x i32> %0, <i32 20, i32 20, i32 20, i32 20>
  %4 = lshr <4 x i32> %1, <i32 20, i32 20, i32 20, i32 20>
  %5 = shufflevector <4 x i32> %3, <4 x i32> %4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  %6 = trunc nuw nsw <8 x i32> %5 to <8 x i16>
  ret <8 x i16> %6
}

define <4 x i32> @combine64ix2(<2 x i64> %0, <2 x i64> %1) {
; CHECK-LABEL: combine64ix2:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp2 v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ushr v0.4s, v0.4s, #8
; CHECK-NEXT:    ret
  %3 = lshr <2 x i64> %0, <i64 40, i64 40>
  %4 = lshr <2 x i64> %1, <i64 40, i64 40>
  %5 = shufflevector <2 x i64> %3, <2 x i64> %4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %6 = trunc nuw nsw <4 x i64> %5 to <4 x i32>
  ret <4 x i32> %6
}