llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctlz-rv64.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \
# RUN:   -simplify-mir -verify-machineinstrs %s -o - \
# RUN:   | FileCheck -check-prefix=RV64I %s

---
name:            ctlz_s32
legalized:       true
regBankSelected: true
body:             |
  bb.0.entry:
    ; RV64I-LABEL: name: ctlz_s32
    ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV64I-NEXT: [[CLZW:%[0-9]+]]:gpr = CLZW [[COPY]]
    ; RV64I-NEXT: $x10 = COPY [[CLZW]]
    ; RV64I-NEXT: PseudoRET implicit $x10
    %0:gprb(s64) = COPY $x10
    %1:gprb(s32) = G_TRUNC %0
    %2:gprb(s32) = G_CTLZ %1
    %3:gprb(s64) = G_ANYEXT %2
    $x10 = COPY %3(s64)
    PseudoRET implicit $x10

...
---
name:            ctlz_s64
legalized:       true
regBankSelected: true
body:             |
  bb.0.entry:
    ; RV64I-LABEL: name: ctlz_s64
    ; RV64I: [[CLZ:%[0-9]+]]:gpr = CLZ [[CLZ]]
    ; RV64I-NEXT: $x10 = COPY [[CLZ]]
    ; RV64I-NEXT: PseudoRET implicit $x10
    %0:gprb(s64) = COPY $x10
    %1:gprb(s64) = G_CTLZ %1
    $x10 = COPY %1(s64)
    PseudoRET implicit $x10

...