llvm/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/load-i1-misaligned.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -mtriple=amdgcn-amd-amdhsa --mcpu=gfx940 -passes=load-store-vectorizer -S -o - %s | FileCheck %s

; Don't crash when checking for misaligned accesses with sub-byte size.

define void @misaligned_access_i1(ptr addrspace(3) %in) #0 {
; CHECK-LABEL: define void @misaligned_access_i1(
; CHECK-SAME: ptr addrspace(3) [[IN:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT:    [[IN_GEP_1:%.*]] = getelementptr i1, ptr addrspace(3) [[IN]], i32 1
; CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i1>, ptr addrspace(3) [[IN_GEP_1]], align 4
; CHECK-NEXT:    [[TMP2:%.*]] = load <8 x i1>, ptr addrspace(3) [[IN]], align 1
; CHECK-NEXT:    ret void
;
  %in.gep.1 = getelementptr i1, ptr addrspace(3) %in, i32 1

  %1 = load <16 x i1>, ptr addrspace(3) %in.gep.1, align 4
  %2 = load <8 x i1>, ptr addrspace(3) %in, align 1
  ret void
}