llvm/llvm/test/Transforms/SLPVectorizer/revec-shufflevector.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes=slp-vectorizer,instcombine -S -slp-revec -slp-max-reg-size=1024 -slp-threshold=-100 %s | FileCheck %s

define void @test1(ptr %in, ptr %out) {
; CHECK-LABEL: @test1(
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[TMP0:%.*]] = load <8 x i32>, ptr [[IN:%.*]], align 1
; CHECK-NEXT:    [[TMP1:%.*]] = zext <8 x i32> [[TMP0]] to <8 x i64>
; CHECK-NEXT:    store <8 x i64> [[TMP1]], ptr [[OUT:%.*]], align 8
; CHECK-NEXT:    ret void
;
entry:
  %0 = load <8 x i32>, ptr %in, align 1
  %1 = shufflevector <8 x i32> %0, <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %2 = shufflevector <8 x i32> %0, <8 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  %3 = zext <4 x i32> %1 to <4 x i64>
  %4 = zext <4 x i32> %2 to <4 x i64>
  %5 = shufflevector <4 x i64> %3, <4 x i64> poison, <2 x i32> <i32 0, i32 1>
  %6 = shufflevector <4 x i64> %3, <4 x i64> poison, <2 x i32> <i32 2, i32 3>
  %7 = shufflevector <4 x i64> %4, <4 x i64> poison, <2 x i32> <i32 0, i32 1>
  %8 = shufflevector <4 x i64> %4, <4 x i64> poison, <2 x i32> <i32 2, i32 3>
  %9 = getelementptr inbounds i64, ptr %out, i64 0
  %10 = getelementptr inbounds i64, ptr %out, i64 2
  %11 = getelementptr inbounds i64, ptr %out, i64 4
  %12 = getelementptr inbounds i64, ptr %out, i64 6
  store <2 x i64> %5, ptr %9, align 8
  store <2 x i64> %6, ptr %10, align 8
  store <2 x i64> %7, ptr %11, align 8
  store <2 x i64> %8, ptr %12, align 8
  ret void
}

define void @test2(ptr %in, ptr %out) {
; CHECK-LABEL: @test2(
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[TMP0:%.*]] = load <8 x i32>, ptr [[IN:%.*]], align 1
; CHECK-NEXT:    [[TMP1:%.*]] = zext <8 x i32> [[TMP0]] to <8 x i64>
; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x i64> [[TMP1]], <8 x i64> poison, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT:    store <8 x i64> [[TMP2]], ptr [[OUT:%.*]], align 8
; CHECK-NEXT:    ret void
;
entry:
  %0 = load <8 x i32>, ptr %in, align 1
  %1 = shufflevector <8 x i32> %0, <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %2 = shufflevector <8 x i32> %0, <8 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  %3 = zext <4 x i32> %1 to <4 x i64>
  %4 = zext <4 x i32> %2 to <4 x i64>
  %5 = shufflevector <4 x i64> %3, <4 x i64> poison, <2 x i32> <i32 2, i32 3>
  %6 = shufflevector <4 x i64> %3, <4 x i64> poison, <2 x i32> <i32 0, i32 1>
  %7 = shufflevector <4 x i64> %4, <4 x i64> poison, <2 x i32> <i32 0, i32 1>
  %8 = shufflevector <4 x i64> %4, <4 x i64> poison, <2 x i32> <i32 2, i32 3>
  %9 = getelementptr inbounds i64, ptr %out, i64 0
  %10 = getelementptr inbounds i64, ptr %out, i64 2
  %11 = getelementptr inbounds i64, ptr %out, i64 4
  %12 = getelementptr inbounds i64, ptr %out, i64 6
  store <2 x i64> %5, ptr %9, align 8
  store <2 x i64> %6, ptr %10, align 8
  store <2 x i64> %7, ptr %11, align 8
  store <2 x i64> %8, ptr %12, align 8
  ret void
}

define void @test3(<16 x i32> %0, ptr %out) {
; CHECK-LABEL: @test3(
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0:%.*]], <16 x i32> poison, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT:    store <16 x i32> [[TMP1]], ptr [[OUT:%.*]], align 4
; CHECK-NEXT:    ret void
;
entry:
  %1 = shufflevector <16 x i32> %0, <16 x i32> poison, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
  %2 = shufflevector <16 x i32> %0, <16 x i32> poison, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
  %3 = shufflevector <16 x i32> %0, <16 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  %4 = shufflevector <16 x i32> %0, <16 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %5 = getelementptr inbounds i32, ptr %out, i64 0
  %6 = getelementptr inbounds i32, ptr %out, i64 4
  %7 = getelementptr inbounds i32, ptr %out, i64 8
  %8 = getelementptr inbounds i32, ptr %out, i64 12
  store <4 x i32> %1, ptr %5, align 4
  store <4 x i32> %2, ptr %6, align 4
  store <4 x i32> %3, ptr %7, align 4
  store <4 x i32> %4, ptr %8, align 4
  ret void
}