; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=ve-unknown-unknown < %s | FileCheck %s
define i8 @atomicrmw_usub_cond_i8(ptr %ptr, i8 %val) {
; CHECK-LABEL: atomicrmw_usub_cond_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: fencem 3
; CHECK-NEXT: and %s2, -4, %s0
; CHECK-NEXT: and %s0, 3, %s0
; CHECK-NEXT: sla.w.sx %s0, %s0, 3
; CHECK-NEXT: sla.w.sx %s3, (56)0, %s0
; CHECK-NEXT: ldl.sx %s5, (, %s2)
; CHECK-NEXT: xor %s3, -1, %s3
; CHECK-NEXT: and %s3, %s3, (32)0
; CHECK-NEXT: and %s4, %s1, (56)0
; CHECK-NEXT: .LBB0_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: or %s6, 0, %s5
; CHECK-NEXT: and %s5, %s6, (32)0
; CHECK-NEXT: srl %s5, %s5, %s0
; CHECK-NEXT: and %s7, %s5, (56)0
; CHECK-NEXT: subs.w.sx %s34, %s5, %s1
; CHECK-NEXT: cmpu.w %s7, %s7, %s4
; CHECK-NEXT: cmov.w.ge %s5, %s34, %s7
; CHECK-NEXT: and %s5, %s5, (56)0
; CHECK-NEXT: sla.w.sx %s5, %s5, %s0
; CHECK-NEXT: and %s7, %s6, %s3
; CHECK-NEXT: or %s5, %s7, %s5
; CHECK-NEXT: cas.w %s5, (%s2), %s6
; CHECK-NEXT: brne.w %s5, %s6, .LBB0_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
; CHECK-NEXT: and %s1, %s5, (32)0
; CHECK-NEXT: srl %s0, %s1, %s0
; CHECK-NEXT: fencem 3
; CHECK-NEXT: b.l.t (, %s10)
%result = atomicrmw usub_cond ptr %ptr, i8 %val seq_cst
ret i8 %result
}
define i16 @atomicrmw_usub_cond_i16(ptr %ptr, i16 %val) {
; CHECK-LABEL: atomicrmw_usub_cond_i16:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: fencem 3
; CHECK-NEXT: and %s2, -4, %s0
; CHECK-NEXT: and %s0, 3, %s0
; CHECK-NEXT: sla.w.sx %s0, %s0, 3
; CHECK-NEXT: sla.w.sx %s3, (48)0, %s0
; CHECK-NEXT: ldl.sx %s5, (, %s2)
; CHECK-NEXT: xor %s3, -1, %s3
; CHECK-NEXT: and %s3, %s3, (32)0
; CHECK-NEXT: and %s4, %s1, (48)0
; CHECK-NEXT: .LBB1_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: or %s6, 0, %s5
; CHECK-NEXT: and %s5, %s6, (32)0
; CHECK-NEXT: srl %s5, %s5, %s0
; CHECK-NEXT: and %s7, %s5, (48)0
; CHECK-NEXT: subs.w.sx %s34, %s5, %s1
; CHECK-NEXT: cmpu.w %s7, %s7, %s4
; CHECK-NEXT: cmov.w.ge %s5, %s34, %s7
; CHECK-NEXT: and %s5, %s5, (48)0
; CHECK-NEXT: sla.w.sx %s5, %s5, %s0
; CHECK-NEXT: and %s7, %s6, %s3
; CHECK-NEXT: or %s5, %s7, %s5
; CHECK-NEXT: cas.w %s5, (%s2), %s6
; CHECK-NEXT: brne.w %s5, %s6, .LBB1_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
; CHECK-NEXT: and %s1, %s5, (32)0
; CHECK-NEXT: srl %s0, %s1, %s0
; CHECK-NEXT: fencem 3
; CHECK-NEXT: b.l.t (, %s10)
%result = atomicrmw usub_cond ptr %ptr, i16 %val seq_cst
ret i16 %result
}
define i32 @atomicrmw_usub_cond_i32(ptr %ptr, i32 %val) {
; CHECK-LABEL: atomicrmw_usub_cond_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3
; CHECK-NEXT: ldl.sx %s2, (, %s0)
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: .LBB2_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: or %s3, 0, %s2
; CHECK-NEXT: subs.w.sx %s4, %s2, %s1
; CHECK-NEXT: cmpu.w %s5, %s2, %s1
; CHECK-NEXT: or %s2, 0, %s3
; CHECK-NEXT: cmov.w.ge %s2, %s4, %s5
; CHECK-NEXT: cas.w %s2, (%s0), %s3
; CHECK-NEXT: brne.w %s2, %s3, .LBB2_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: b.l.t (, %s10)
%result = atomicrmw usub_cond ptr %ptr, i32 %val seq_cst
ret i32 %result
}
define i64 @atomicrmw_usub_cond_sub_i64(ptr %ptr, i64 %val) {
; CHECK-LABEL: atomicrmw_usub_cond_sub_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s2, 0, %s0
; CHECK-NEXT: fencem 3
; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: .LBB3_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: or %s3, 0, %s0
; CHECK-NEXT: subs.l %s4, %s0, %s1
; CHECK-NEXT: cmpu.l %s5, %s0, %s1
; CHECK-NEXT: cmov.l.ge %s0, %s4, %s5
; CHECK-NEXT: cas.l %s0, (%s2), %s3
; CHECK-NEXT: brne.l %s0, %s3, .LBB3_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
; CHECK-NEXT: fencem 3
; CHECK-NEXT: b.l.t (, %s10)
%result = atomicrmw usub_cond ptr %ptr, i64 %val seq_cst
ret i64 %result
}
define i8 @atomicrmw_usub_sat_i8(ptr %ptr, i8 %val) {
; CHECK-LABEL: atomicrmw_usub_sat_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s3, %s1, (32)0
; CHECK-NEXT: fencem 3
; CHECK-NEXT: and %s1, -4, %s0
; CHECK-NEXT: and %s0, 3, %s0
; CHECK-NEXT: sla.w.sx %s0, %s0, 3
; CHECK-NEXT: sla.w.sx %s2, (56)0, %s0
; CHECK-NEXT: ldl.sx %s4, (, %s1)
; CHECK-NEXT: xor %s2, -1, %s2
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: and %s3, %s3, (56)0
; CHECK-NEXT: .LBB4_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: or %s5, 0, %s4
; CHECK-NEXT: and %s4, %s5, (32)0
; CHECK-NEXT: srl %s4, %s4, %s0
; CHECK-NEXT: and %s4, %s4, (56)0
; CHECK-NEXT: subs.w.sx %s6, %s4, %s3
; CHECK-NEXT: cmpu.w %s4, %s6, %s4
; CHECK-NEXT: cmov.w.gt %s6, (0)1, %s4
; CHECK-NEXT: sla.w.sx %s4, %s6, %s0
; CHECK-NEXT: and %s6, %s5, %s2
; CHECK-NEXT: or %s4, %s6, %s4
; CHECK-NEXT: cas.w %s4, (%s1), %s5
; CHECK-NEXT: brne.w %s4, %s5, .LBB4_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
; CHECK-NEXT: and %s1, %s4, (32)0
; CHECK-NEXT: srl %s0, %s1, %s0
; CHECK-NEXT: fencem 3
; CHECK-NEXT: b.l.t (, %s10)
%result = atomicrmw usub_sat ptr %ptr, i8 %val seq_cst
ret i8 %result
}
define i16 @atomicrmw_usub_sat_i16(ptr %ptr, i16 %val) {
; CHECK-LABEL: atomicrmw_usub_sat_i16:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s3, %s1, (32)0
; CHECK-NEXT: fencem 3
; CHECK-NEXT: and %s1, -4, %s0
; CHECK-NEXT: and %s0, 3, %s0
; CHECK-NEXT: sla.w.sx %s0, %s0, 3
; CHECK-NEXT: sla.w.sx %s2, (48)0, %s0
; CHECK-NEXT: ldl.sx %s4, (, %s1)
; CHECK-NEXT: xor %s2, -1, %s2
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: and %s3, %s3, (48)0
; CHECK-NEXT: .LBB5_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: or %s5, 0, %s4
; CHECK-NEXT: and %s4, %s5, (32)0
; CHECK-NEXT: srl %s4, %s4, %s0
; CHECK-NEXT: and %s4, %s4, (48)0
; CHECK-NEXT: subs.w.sx %s6, %s4, %s3
; CHECK-NEXT: cmpu.w %s4, %s6, %s4
; CHECK-NEXT: cmov.w.gt %s6, (0)1, %s4
; CHECK-NEXT: sla.w.sx %s4, %s6, %s0
; CHECK-NEXT: and %s6, %s5, %s2
; CHECK-NEXT: or %s4, %s6, %s4
; CHECK-NEXT: cas.w %s4, (%s1), %s5
; CHECK-NEXT: brne.w %s4, %s5, .LBB5_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
; CHECK-NEXT: and %s1, %s4, (32)0
; CHECK-NEXT: srl %s0, %s1, %s0
; CHECK-NEXT: fencem 3
; CHECK-NEXT: b.l.t (, %s10)
%result = atomicrmw usub_sat ptr %ptr, i16 %val seq_cst
ret i16 %result
}
define i32 @atomicrmw_usub_sat_i32(ptr %ptr, i32 %val) {
; CHECK-LABEL: atomicrmw_usub_sat_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3
; CHECK-NEXT: ldl.sx %s2, (, %s0)
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: .LBB6_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: or %s3, 0, %s2
; CHECK-NEXT: subs.w.sx %s2, %s2, %s1
; CHECK-NEXT: cmpu.w %s4, %s2, %s3
; CHECK-NEXT: cmov.w.gt %s2, (0)1, %s4
; CHECK-NEXT: cas.w %s2, (%s0), %s3
; CHECK-NEXT: brne.w %s2, %s3, .LBB6_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: b.l.t (, %s10)
%result = atomicrmw usub_sat ptr %ptr, i32 %val seq_cst
ret i32 %result
}
define i64 @atomicrmw_usub_sat_i64(ptr %ptr, i64 %val) {
; CHECK-LABEL: atomicrmw_usub_sat_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3
; CHECK-NEXT: ld %s2, (, %s0)
; CHECK-NEXT: .LBB7_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: or %s3, 0, %s2
; CHECK-NEXT: subs.l %s2, %s2, %s1
; CHECK-NEXT: cmpu.l %s4, %s2, %s3
; CHECK-NEXT: cmov.l.gt %s2, (0)1, %s4
; CHECK-NEXT: cas.l %s2, (%s0), %s3
; CHECK-NEXT: brne.l %s2, %s3, .LBB7_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: b.l.t (, %s10)
%result = atomicrmw usub_sat ptr %ptr, i64 %val seq_cst
ret i64 %result
}
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