llvm/llvm/test/CodeGen/X86/avx10_2satcvtds-x64-intrinsics.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2-256 | FileCheck %s

define i64 @test_x86_avx512_vcvttsd2si64(<2 x double> %a0) {
; CHECK-LABEL: test_x86_avx512_vcvttsd2si64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvttsd2sis %xmm0, %rcx # encoding: [0x62,0xf5,0xff,0x08,0x6d,0xc8]
; CHECK-NEXT:    vcvttsd2sis {sae}, %xmm0, %rax # encoding: [0x62,0xf5,0xff,0x18,0x6d,0xc0]
; CHECK-NEXT:    addq %rcx, %rax # encoding: [0x48,0x01,0xc8]
; CHECK-NEXT:    retq # encoding: [0xc3]
  %res0 = call i64 @llvm.x86.avx10.vcvttsd2sis64(<2 x double> %a0, i32 4) ;
  %res1 = call i64 @llvm.x86.avx10.vcvttsd2sis64(<2 x double> %a0, i32 8) ;
  %res2 = add i64 %res0, %res1
  ret i64 %res2
}
declare i64 @llvm.x86.avx10.vcvttsd2sis64(<2 x double>, i32) nounwind readnone

define i64 @test_x86_avx512_vcvttsd2usi64(<2 x double> %a0) {
; CHECK-LABEL: test_x86_avx512_vcvttsd2usi64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvttsd2usis %xmm0, %rcx # encoding: [0x62,0xf5,0xff,0x08,0x6c,0xc8]
; CHECK-NEXT:    vcvttsd2usis {sae}, %xmm0, %rax # encoding: [0x62,0xf5,0xff,0x18,0x6c,0xc0]
; CHECK-NEXT:    addq %rcx, %rax # encoding: [0x48,0x01,0xc8]
; CHECK-NEXT:    retq # encoding: [0xc3]
  %res0 = call i64 @llvm.x86.avx10.vcvttsd2usis64(<2 x double> %a0, i32 4) ;
  %res1 = call i64 @llvm.x86.avx10.vcvttsd2usis64(<2 x double> %a0, i32 8) ;
  %res2 = add i64 %res0, %res1
  ret i64 %res2
}
declare i64 @llvm.x86.avx10.vcvttsd2usis64(<2 x double>, i32) nounwind readnone

define i64 @test_x86_avx512_vcvttss2sis64(<4 x float> %a0) {
; CHECK-LABEL: test_x86_avx512_vcvttss2sis64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvttss2sis %xmm0, %rcx # encoding: [0x62,0xf5,0xfe,0x08,0x6d,0xc8]
; CHECK-NEXT:    vcvttss2sis {sae}, %xmm0, %rax # encoding: [0x62,0xf5,0xfe,0x18,0x6d,0xc0]
; CHECK-NEXT:    addq %rcx, %rax # encoding: [0x48,0x01,0xc8]
; CHECK-NEXT:    retq # encoding: [0xc3]
  %res0 = call i64 @llvm.x86.avx10.vcvttss2sis64(<4 x float> %a0, i32 4) ;
  %res1 = call i64 @llvm.x86.avx10.vcvttss2sis64(<4 x float> %a0, i32 8) ;
  %res2 = add i64 %res0, %res1
  ret i64 %res2
}
declare i64 @llvm.x86.avx10.vcvttss2sis64(<4 x float>, i32) nounwind readnone

define i64 @test_x86_avx512_vcvttss2usis64(<4 x float> %a0) {
; CHECK-LABEL: test_x86_avx512_vcvttss2usis64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvttss2usis %xmm0, %rcx # encoding: [0x62,0xf5,0xfe,0x08,0x6c,0xc8]
; CHECK-NEXT:    vcvttss2usis {sae}, %xmm0, %rax # encoding: [0x62,0xf5,0xfe,0x18,0x6c,0xc0]
; CHECK-NEXT:    addq %rcx, %rax # encoding: [0x48,0x01,0xc8]
; CHECK-NEXT:    retq # encoding: [0xc3]
  %res0 = call i64 @llvm.x86.avx10.vcvttss2usis64(<4 x float> %a0, i32 4) ;
  %res1 = call i64 @llvm.x86.avx10.vcvttss2usis64(<4 x float> %a0, i32 8) ;
  %res2 = add i64 %res0, %res1
  ret i64 %res2
}
declare i64 @llvm.x86.avx10.vcvttss2usis64(<4 x float>, i32) nounwind readnone