llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN:   -o - | FileCheck %s

---
name:            splat_zero_nxv1i1
legalized:       true
regBankSelected: false
body:             |
  bb.1:
    ; CHECK-LABEL: name: splat_zero_nxv1i1
    ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 1 x s1>) = G_VMCLR_VL [[C]](s32)
    ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 1 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s32) = G_CONSTANT i32 -1
    %1:_(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
    $v0 = COPY %1(<vscale x 1 x s1>)
    PseudoRET implicit $v0

...
---
name:            splat_zero_nxv2i1
legalized:       true
regBankSelected: false
body:             |
  bb.1:
    ; CHECK-LABEL: name: splat_zero_nxv2i1
    ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 2 x s1>) = G_VMCLR_VL [[C]](s32)
    ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 2 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s32) = G_CONSTANT i32 -1
    %1:_(<vscale x 2 x s1>) = G_VMCLR_VL %0(s32)
    $v0 = COPY %1(<vscale x 2 x s1>)
    PseudoRET implicit $v0

...
---
name:            splat_zero_nxv4i1
legalized:       true
regBankSelected: false
body:             |
  bb.1:
    ; CHECK-LABEL: name: splat_zero_nxv4i1
    ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 4 x s1>) = G_VMCLR_VL [[C]](s32)
    ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 4 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s32) = G_CONSTANT i32 -1
    %1:_(<vscale x 4 x s1>) = G_VMCLR_VL %0(s32)
    $v0 = COPY %1(<vscale x 4 x s1>)
    PseudoRET implicit $v0

...
---
name:            splat_zero_nxv8i1
legalized:       true
regBankSelected: false
body:             |
  bb.1:
    ; CHECK-LABEL: name: splat_zero_nxv8i1
    ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 8 x s1>) = G_VMCLR_VL [[C]](s32)
    ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 8 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s32) = G_CONSTANT i32 -1
    %1:_(<vscale x 8 x s1>) = G_VMCLR_VL %0(s32)
    $v0 = COPY %1(<vscale x 8 x s1>)
    PseudoRET implicit $v0

...
---
name:            splat_zero_nxv16i1
legalized:       true
regBankSelected: false
body:             |
  bb.1:
    ; CHECK-LABEL: name: splat_zero_nxv16i1
    ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 16 x s1>) = G_VMCLR_VL [[C]](s32)
    ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 16 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s32) = G_CONSTANT i32 -1
    %1:_(<vscale x 16 x s1>) = G_VMCLR_VL %0(s32)
    $v0 = COPY %1(<vscale x 16 x s1>)
    PseudoRET implicit $v0

...
---
name:            splat_zero_nxv32i1
legalized:       true
regBankSelected: false
body:             |
  bb.1:
    ; CHECK-LABEL: name: splat_zero_nxv32i1
    ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 32 x s1>) = G_VMCLR_VL [[C]](s32)
    ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 32 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s32) = G_CONSTANT i32 -1
    %1:_(<vscale x 32 x s1>) = G_VMCLR_VL %0(s32)
    $v0 = COPY %1(<vscale x 32 x s1>)
    PseudoRET implicit $v0

...
---
name:            splat_zero_nxv64i1
legalized:       true
regBankSelected: false
body:             |
  bb.1:
    ; CHECK-LABEL: name: splat_zero_nxv64i1
    ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 64 x s1>) = G_VMCLR_VL [[C]](s32)
    ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 64 x s1>)
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:_(s32) = G_CONSTANT i32 -1
    %1:_(<vscale x 64 x s1>) = G_VMCLR_VL %0(s32)
    $v0 = COPY %1(<vscale x 64 x s1>)
    PseudoRET implicit $v0

...