llvm/llvm/lib/MCA/Stages/InOrderIssueStage.cpp

//===---------------------- InOrderIssueStage.cpp ---------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
/// \file
///
/// InOrderIssueStage implements an in-order execution pipeline.
///
//===----------------------------------------------------------------------===//

#include "llvm/MCA/Stages/InOrderIssueStage.h"
#include "llvm/MCA/HardwareUnits/LSUnit.h"
#include "llvm/MCA/HardwareUnits/RegisterFile.h"
#include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
#include "llvm/MCA/Instruction.h"

#define DEBUG_TYPE …
namespace llvm {
namespace mca {

void StallInfo::clear() { … }

void StallInfo::update(const InstRef &Inst, unsigned Cycles, StallKind SK) { … }

void StallInfo::cycleEnd() { … }

InOrderIssueStage::InOrderIssueStage(const MCSubtargetInfo &STI,
                                     RegisterFile &PRF, CustomBehaviour &CB,
                                     LSUnitBase &LSU)
    : … { … }

unsigned InOrderIssueStage::getIssueWidth() const { … }

bool InOrderIssueStage::hasWorkToComplete() const { … }

bool InOrderIssueStage::isAvailable(const InstRef &IR) const { … }

static bool hasResourceHazard(const ResourceManager &RM, const InstRef &IR) { … }

static unsigned findFirstWriteBackCycle(const InstRef &IR) { … }

/// Return a number of cycles left until register requirements of the
/// instructions are met.
static unsigned checkRegisterHazard(const RegisterFile &PRF,
                                    const MCSubtargetInfo &STI,
                                    const InstRef &IR) { … }

bool InOrderIssueStage::canExecute(const InstRef &IR) { … }

static void addRegisterReadWrite(RegisterFile &PRF, Instruction &IS,
                                 unsigned SourceIndex,
                                 const MCSubtargetInfo &STI,
                                 SmallVectorImpl<unsigned> &UsedRegs) { … }

void InOrderIssueStage::notifyInstructionIssued(const InstRef &IR,
                                                ArrayRef<ResourceUse> UsedRes) { … }

void InOrderIssueStage::notifyInstructionDispatched(
    const InstRef &IR, unsigned Ops, ArrayRef<unsigned> UsedRegs) { … }

void InOrderIssueStage::notifyInstructionExecuted(const InstRef &IR) { … }

void InOrderIssueStage::notifyInstructionRetired(const InstRef &IR,
                                                 ArrayRef<unsigned> FreedRegs) { … }

llvm::Error InOrderIssueStage::execute(InstRef &IR) { … }

llvm::Error InOrderIssueStage::tryIssue(InstRef &IR) { … }

void InOrderIssueStage::updateIssuedInst() { … }

void InOrderIssueStage::updateCarriedOver() { … }

void InOrderIssueStage::retireInstruction(InstRef &IR) { … }

void InOrderIssueStage::notifyStallEvent() { … }

llvm::Error InOrderIssueStage::cycleStart() { … }

llvm::Error InOrderIssueStage::cycleEnd() { … }

} // namespace mca
} // namespace llvm