R600GenMCCodeEmitter.inc | Explore in Territory

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Machine Code Emitter                                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

uint64_t R600MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
    SmallVectorImpl<MCFixup> &Fixups,
    const MCSubtargetInfo &STI) const { … }

#ifdef GET_OPERAND_BIT_OFFSET
#undef GET_OPERAND_BIT_OFFSET

uint32_t R600MCCodeEmitter::getOperandBitOffset(const MCInst &MI,
    unsigned OpNum,
    const MCSubtargetInfo &STI) const {
  switch (MI.getOpcode()) {
    case R600::CF_CALL_FS_EG:
    case R600::CF_CALL_FS_R600:
    case R600::CF_END_CM:
    case R600::CF_END_EG:
    case R600::CF_END_R600:
    case R600::GROUP_BARRIER:
    case R600::INTERP_PAIR_XY:
    case R600::INTERP_PAIR_ZW:
    case R600::INTERP_VEC_LOAD:
    case R600::PAD: {
      break;
    }
    case R600::CF_TC_R600:
    case R600::CF_VC_R600: {
      switch (OpNum) {
      case 0:
        // op: ADDR
        return 0;
      case 1:
        // op: CNT
        return 42;
      }
      break;
    }
    case R600::CF_TC_EG:
    case R600::CF_VC_EG: {
      switch (OpNum) {
      case 0:
        // op: ADDR
        return 0;
      case 1:
        // op: COUNT
        return 42;
      }
      break;
    }
    case R600::CF_ALU:
    case R600::CF_ALU_BREAK:
    case R600::CF_ALU_CONTINUE:
    case R600::CF_ALU_ELSE_AFTER:
    case R600::CF_ALU_POP_AFTER:
    case R600::CF_ALU_PUSH_BEFORE: {
      switch (OpNum) {
      case 0:
        // op: ADDR
        return 0;
      case 1:
        // op: KCACHE_BANK0
        return 22;
      case 2:
        // op: KCACHE_BANK1
        return 26;
      case 3:
        // op: KCACHE_MODE0
        return 30;
      case 4:
        // op: KCACHE_MODE1
        return 32;
      case 5:
        // op: KCACHE_ADDR0
        return 34;
      case 6:
        // op: KCACHE_ADDR1
        return 42;
      case 7:
        // op: COUNT
        return 50;
      }
      break;
    }
    case R600::CF_ELSE_EG:
    case R600::CF_ELSE_R600:
    case R600::CF_JUMP_EG:
    case R600::CF_JUMP_R600:
    case R600::CF_PUSH_EG:
    case R600::POP_EG:
    case R600::POP_R600: {
      switch (OpNum) {
      case 0:
        // op: ADDR
        return 0;
      case 1:
        // op: POP_COUNT
        return 32;
      }
      break;
    }
    case R600::CF_CONTINUE_EG:
    case R600::CF_CONTINUE_R600:
    case R600::CF_PUSH_ELSE_R600:
    case R600::END_LOOP_EG:
    case R600::END_LOOP_R600:
    case R600::LOOP_BREAK_EG:
    case R600::LOOP_BREAK_R600:
    case R600::WHILE_LOOP_EG:
    case R600::WHILE_LOOP_R600: {
      switch (OpNum) {
      case 0:
        // op: ADDR
        return 0;
      }
      break;
    }
    case R600::ALU_CLAUSE:
    case R600::FETCH_CLAUSE: {
      switch (OpNum) {
      case 0:
        // op: addr
        return 0;
      }
      break;
    }
    case R600::TEX_VTX_CONSTBUF:
    case R600::TEX_VTX_TEXBUF: {
      switch (OpNum) {
      case 0:
        // op: dst_gpr
        return 32;
      case 1:
        // op: src_gpr
        return 16;
      case 3:
        // op: buffer_id
        return 8;
      }
      break;
    }
    case R600::LITERALS: {
      switch (OpNum) {
      case 0:
        // op: literal1
        return 0;
      case 1:
        // op: literal2
        return 32;
      }
      break;
    }
    case R600::RAT_WRITE_CACHELESS_32_eg:
    case R600::RAT_WRITE_CACHELESS_64_eg:
    case R600::RAT_WRITE_CACHELESS_128_eg: {
      switch (OpNum) {
      case 0:
        // op: rw_gpr
        return 15;
      case 1:
        // op: index_gpr
        return 23;
      case 2:
        // op: eop
        return 53;
      }
      break;
    }
    case R600::RAT_MSKOR:
    case R600::RAT_STORE_DWORD32:
    case R600::RAT_STORE_DWORD64:
    case R600::RAT_STORE_DWORD128: {
      switch (OpNum) {
      case 0:
        // op: rw_gpr
        return 15;
      case 1:
        // op: index_gpr
        return 23;
      }
      break;
    }
    case R600::LDS_CMPST: {
      switch (OpNum) {
      case 0:
        // op: src0
        return 0;
      case 1:
        // op: src0_rel
        return 9;
      case 3:
        // op: src1
        return 13;
      case 4:
        // op: src1_rel
        return 22;
      case 10:
        // op: pred_sel
        return 29;
      case 9:
        // op: last
        return 31;
      case 6:
        // op: src2
        return 32;
      case 7:
        // op: src2_rel
        return 41;
      case 11:
        // op: bank_swizzle
        return 50;
      }
      break;
    }
    case R600::LDS_ADD:
    case R600::LDS_AND:
    case R600::LDS_BYTE_WRITE:
    case R600::LDS_MAX_INT:
    case R600::LDS_MAX_UINT:
    case R600::LDS_MIN_INT:
    case R600::LDS_MIN_UINT:
    case R600::LDS_OR:
    case R600::LDS_SHORT_WRITE:
    case R600::LDS_SUB:
    case R600::LDS_WRITE:
    case R600::LDS_WRXCHG:
    case R600::LDS_XOR: {
      switch (OpNum) {
      case 0:
        // op: src0
        return 0;
      case 1:
        // op: src0_rel
        return 9;
      case 3:
        // op: src1
        return 13;
      case 4:
        // op: src1_rel
        return 22;
      case 7:
        // op: pred_sel
        return 29;
      case 6:
        // op: last
        return 31;
      case 8:
        // op: bank_swizzle
        return 50;
      }
      break;
    }
    case R600::TEX_GET_GRADIENTS_H:
    case R600::TEX_GET_GRADIENTS_V:
    case R600::TEX_GET_TEXTURE_RESINFO:
    case R600::TEX_LD:
    case R600::TEX_LDPTR:
    case R600::TEX_SAMPLE:
    case R600::TEX_SAMPLE_C:
    case R600::TEX_SAMPLE_C_G:
    case R600::TEX_SAMPLE_C_L:
    case R600::TEX_SAMPLE_C_LB:
    case R600::TEX_SAMPLE_G:
    case R600::TEX_SAMPLE_L:
    case R600::TEX_SAMPLE_LB:
    case R600::TEX_SET_GRADIENTS_H:
    case R600::TEX_SET_GRADIENTS_V: {
      switch (OpNum) {
      case 13:
        // op: RESOURCE_ID
        return 8;
      case 1:
        // op: SRC_GPR
        return 16;
      case 0:
        // op: DST_GPR
        return 32;
      case 9:
        // op: DST_SEL_X
        return 41;
      case 10:
        // op: DST_SEL_Y
        return 44;
      case 11:
        // op: DST_SEL_Z
        return 47;
      case 12:
        // op: DST_SEL_W
        return 50;
      case 15:
        // op: COORD_TYPE_X
        return 60;
      case 16:
        // op: COORD_TYPE_Y
        return 61;
      case 17:
        // op: COORD_TYPE_Z
        return 62;
      case 18:
        // op: COORD_TYPE_W
        return 63;
      }
      break;
    }
    case R600::RAT_ATOMIC_ADD_NORET:
    case R600::RAT_ATOMIC_ADD_RTN:
    case R600::RAT_ATOMIC_AND_NORET:
    case R600::RAT_ATOMIC_AND_RTN:
    case R600::RAT_ATOMIC_CMPXCHG_INT_NORET:
    case R600::RAT_ATOMIC_CMPXCHG_INT_RTN:
    case R600::RAT_ATOMIC_DEC_UINT_NORET:
    case R600::RAT_ATOMIC_DEC_UINT_RTN:
    case R600::RAT_ATOMIC_INC_UINT_NORET:
    case R600::RAT_ATOMIC_INC_UINT_RTN:
    case R600::RAT_ATOMIC_MAX_INT_NORET:
    case R600::RAT_ATOMIC_MAX_INT_RTN:
    case R600::RAT_ATOMIC_MAX_UINT_NORET:
    case R600::RAT_ATOMIC_MAX_UINT_RTN:
    case R600::RAT_ATOMIC_MIN_INT_NORET:
    case R600::RAT_ATOMIC_MIN_INT_RTN:
    case R600::RAT_ATOMIC_MIN_UINT_NORET:
    case R600::RAT_ATOMIC_MIN_UINT_RTN:
    case R600::RAT_ATOMIC_OR_NORET:
    case R600::RAT_ATOMIC_OR_RTN:
    case R600::RAT_ATOMIC_RSUB_NORET:
    case R600::RAT_ATOMIC_RSUB_RTN:
    case R600::RAT_ATOMIC_SUB_NORET:
    case R600::RAT_ATOMIC_SUB_RTN:
    case R600::RAT_ATOMIC_XCHG_INT_NORET:
    case R600::RAT_ATOMIC_XCHG_INT_RTN:
    case R600::RAT_ATOMIC_XOR_NORET:
    case R600::RAT_ATOMIC_XOR_RTN: {
      switch (OpNum) {
      case 1:
        // op: rw_gpr
        return 15;
      case 2:
        // op: index_gpr
        return 23;
      }
      break;
    }
    case R600::LDS_CMPST_RET: {
      switch (OpNum) {
      case 1:
        // op: src0
        return 0;
      case 2:
        // op: src0_rel
        return 9;
      case 4:
        // op: src1
        return 13;
      case 5:
        // op: src1_rel
        return 22;
      case 11:
        // op: pred_sel
        return 29;
      case 10:
        // op: last
        return 31;
      case 7:
        // op: src2
        return 32;
      case 8:
        // op: src2_rel
        return 41;
      case 12:
        // op: bank_swizzle
        return 50;
      }
      break;
    }
    case R600::LDS_ADD_RET:
    case R600::LDS_AND_RET:
    case R600::LDS_MAX_INT_RET:
    case R600::LDS_MAX_UINT_RET:
    case R600::LDS_MIN_INT_RET:
    case R600::LDS_MIN_UINT_RET:
    case R600::LDS_OR_RET:
    case R600::LDS_SUB_RET:
    case R600::LDS_WRXCHG_RET:
    case R600::LDS_XOR_RET: {
      switch (OpNum) {
      case 1:
        // op: src0
        return 0;
      case 2:
        // op: src0_rel
        return 9;
      case 4:
        // op: src1
        return 13;
      case 5:
        // op: src1_rel
        return 22;
      case 8:
        // op: pred_sel
        return 29;
      case 7:
        // op: last
        return 31;
      case 9:
        // op: bank_swizzle
        return 50;
      }
      break;
    }
    case R600::LDS_BYTE_READ_RET:
    case R600::LDS_READ_RET:
    case R600::LDS_SHORT_READ_RET:
    case R600::LDS_UBYTE_READ_RET:
    case R600::LDS_USHORT_READ_RET: {
      switch (OpNum) {
      case 1:
        // op: src0
        return 0;
      case 2:
        // op: src0_rel
        return 9;
      case 5:
        // op: pred_sel
        return 29;
      case 4:
        // op: last
        return 31;
      case 6:
        // op: bank_swizzle
        return 50;
      }
      break;
    }
    case R600::VTX_READ_8_cm:
    case R600::VTX_READ_8_eg:
    case R600::VTX_READ_16_cm:
    case R600::VTX_READ_16_eg:
    case R600::VTX_READ_32_cm:
    case R600::VTX_READ_32_eg:
    case R600::VTX_READ_64_cm:
    case R600::VTX_READ_64_eg:
    case R600::VTX_READ_128_cm:
    case R600::VTX_READ_128_eg: {
      switch (OpNum) {
      case 1:
        // op: src_gpr
        return 16;
      case 3:
        // op: buffer_id
        return 8;
      case 0:
        // op: dst_gpr
        return 32;
      }
      break;
    }
    case R600::EG_ExportBuf: {
      switch (OpNum) {
      case 2:
        // op: arraybase
        return 0;
      case 1:
        // op: type
        return 13;
      case 0:
        // op: gpr
        return 15;
      case 3:
        // op: arraySize
        return 32;
      case 4:
        // op: compMask
        return 44;
      case 6:
        // op: eop
        return 53;
      case 5:
        // op: inst
        return 54;
      }
      break;
    }
    case R600::R600_ExportBuf: {
      switch (OpNum) {
      case 2:
        // op: arraybase
        return 0;
      case 1:
        // op: type
        return 13;
      case 0:
        // op: gpr
        return 15;
      case 3:
        // op: arraySize
        return 32;
      case 4:
        // op: compMask
        return 44;
      case 6:
        // op: eop
        return 53;
      case 5:
        // op: inst
        return 55;
      }
      break;
    }
    case R600::EG_ExportSwz: {
      switch (OpNum) {
      case 2:
        // op: arraybase
        return 0;
      case 1:
        // op: type
        return 13;
      case 0:
        // op: gpr
        return 15;
      case 3:
        // op: sw_x
        return 32;
      case 4:
        // op: sw_y
        return 35;
      case 5:
        // op: sw_z
        return 38;
      case 6:
        // op: sw_w
        return 41;
      case 8:
        // op: eop
        return 53;
      case 7:
        // op: inst
        return 54;
      }
      break;
    }
    case R600::R600_ExportSwz: {
      switch (OpNum) {
      case 2:
        // op: arraybase
        return 0;
      case 1:
        // op: type
        return 13;
      case 0:
        // op: gpr
        return 15;
      case 3:
        // op: sw_x
        return 32;
      case 4:
        // op: sw_y
        return 35;
      case 5:
        // op: sw_z
        return 38;
      case 6:
        // op: sw_w
        return 41;
      case 8:
        // op: eop
        return 53;
      case 7:
        // op: inst
        return 55;
      }
      break;
    }
    case R600::RAT_STORE_TYPED_eg: {
      switch (OpNum) {
      case 2:
        // op: rat_id
        return 0;
      case 0:
        // op: rw_gpr
        return 15;
      case 1:
        // op: index_gpr
        return 23;
      case 3:
        // op: eop
        return 53;
      }
      break;
    }
    case R600::RAT_STORE_TYPED_cm: {
      switch (OpNum) {
      case 2:
        // op: rat_id
        return 0;
      case 0:
        // op: rw_gpr
        return 15;
      case 1:
        // op: index_gpr
        return 23;
      }
      break;
    }
    case R600::BFE_INT_eg:
    case R600::BFE_UINT_eg:
    case R600::BFI_INT_eg:
    case R600::BIT_ALIGN_INT_eg:
    case R600::CNDE_INT:
    case R600::CNDE_eg:
    case R600::CNDE_r600:
    case R600::CNDGE_INT:
    case R600::CNDGE_eg:
    case R600::CNDGE_r600:
    case R600::CNDGT_INT:
    case R600::CNDGT_eg:
    case R600::CNDGT_r600:
    case R600::FMA_eg:
    case R600::MULADD_IEEE_eg:
    case R600::MULADD_IEEE_r600:
    case R600::MULADD_INT24_cm:
    case R600::MULADD_UINT24_eg:
    case R600::MULADD_eg:
    case R600::MULADD_r600:
    case R600::MUL_LIT_eg:
    case R600::MUL_LIT_r600: {
      switch (OpNum) {
      case 3:
        // op: src0
        return 0;
      case 5:
        // op: src0_rel
        return 9;
      case 7:
        // op: src1
        return 13;
      case 9:
        // op: src1_rel
        return 22;
      case 16:
        // op: pred_sel
        return 29;
      case 15:
        // op: last
        return 31;
      case 4:
        // op: src0_neg
        return 12;
      case 8:
        // op: src1_neg
        return 25;
      case 0:
        // op: dst
        return 53;
      case 18:
        // op: bank_swizzle
        return 50;
      case 1:
        // op: dst_rel
        return 60;
      case 2:
        // op: clamp
        return 63;
      case 11:
        // op: src2
        return 32;
      case 13:
        // op: src2_rel
        return 41;
      case 12:
        // op: src2_neg
        return 44;
      }
      break;
    }
    case R600::BCNT_INT:
    case R600::CEIL:
    case R600::COS_cm:
    case R600::COS_eg:
    case R600::COS_r600:
    case R600::COS_r700:
    case R600::EXP_IEEE_cm:
    case R600::EXP_IEEE_eg:
    case R600::EXP_IEEE_r600:
    case R600::FFBH_UINT:
    case R600::FFBL_INT:
    case R600::FLOOR:
    case R600::FLT16_TO_FLT32:
    case R600::FLT32_TO_FLT16:
    case R600::FLT_TO_INT_eg:
    case R600::FLT_TO_INT_r600:
    case R600::FLT_TO_UINT_eg:
    case R600::FLT_TO_UINT_r600:
    case R600::FRACT:
    case R600::INTERP_LOAD_P0:
    case R600::INT_TO_FLT_eg:
    case R600::INT_TO_FLT_r600:
    case R600::LOG_CLAMPED_eg:
    case R600::LOG_CLAMPED_r600:
    case R600::LOG_IEEE_cm:
    case R600::LOG_IEEE_eg:
    case R600::LOG_IEEE_r600:
    case R600::MOV:
    case R600::MOVA_INT_eg:
    case R600::NOT_INT:
    case R600::RECIPSQRT_CLAMPED_cm:
    case R600::RECIPSQRT_CLAMPED_eg:
    case R600::RECIPSQRT_CLAMPED_r600:
    case R600::RECIPSQRT_IEEE_cm:
    case R600::RECIPSQRT_IEEE_eg:
    case R600::RECIPSQRT_IEEE_r600:
    case R600::RECIP_CLAMPED_cm:
    case R600::RECIP_CLAMPED_eg:
    case R600::RECIP_CLAMPED_r600:
    case R600::RECIP_IEEE_cm:
    case R600::RECIP_IEEE_eg:
    case R600::RECIP_IEEE_r600:
    case R600::RECIP_UINT_eg:
    case R600::RECIP_UINT_r600:
    case R600::RNDNE:
    case R600::SIN_cm:
    case R600::SIN_eg:
    case R600::SIN_r600:
    case R600::SIN_r700:
    case R600::TRUNC:
    case R600::UINT_TO_FLT_eg:
    case R600::UINT_TO_FLT_r600: {
      switch (OpNum) {
      case 5:
        // op: src0
        return 0;
      case 7:
        // op: src0_rel
        return 9;
      case 11:
        // op: pred_sel
        return 29;
      case 10:
        // op: last
        return 31;
      case 6:
        // op: src0_neg
        return 12;
      case 0:
        // op: dst
        return 53;
      case 13:
        // op: bank_swizzle
        return 50;
      case 3:
        // op: dst_rel
        return 60;
      case 4:
        // op: clamp
        return 63;
      case 8:
        // op: src0_abs
        return 32;
      case 1:
        // op: write
        return 36;
      case 2:
        // op: omod
        return 37;
      }
      break;
    }
    case R600::ADD:
    case R600::ADDC_UINT:
    case R600::ADD_INT:
    case R600::AND_INT:
    case R600::ASHR_eg:
    case R600::ASHR_r600:
    case R600::BFM_INT_eg:
    case R600::CUBE_eg_real:
    case R600::CUBE_r600_real:
    case R600::DOT4_eg:
    case R600::DOT4_r600:
    case R600::KILLGT:
    case R600::LSHL_eg:
    case R600::LSHL_r600:
    case R600::LSHR_eg:
    case R600::LSHR_r600:
    case R600::MAX:
    case R600::MAX_DX10:
    case R600::MAX_INT:
    case R600::MAX_UINT:
    case R600::MIN:
    case R600::MIN_DX10:
    case R600::MIN_INT:
    case R600::MIN_UINT:
    case R600::MUL:
    case R600::MULHI_INT_cm:
    case R600::MULHI_INT_cm24:
    case R600::MULHI_INT_eg:
    case R600::MULHI_INT_r600:
    case R600::MULHI_UINT24_eg:
    case R600::MULHI_UINT_cm:
    case R600::MULHI_UINT_cm24:
    case R600::MULHI_UINT_eg:
    case R600::MULHI_UINT_r600:
    case R600::MULLO_INT_cm:
    case R600::MULLO_INT_eg:
    case R600::MULLO_INT_r600:
    case R600::MULLO_UINT_cm:
    case R600::MULLO_UINT_eg:
    case R600::MULLO_UINT_r600:
    case R600::MUL_IEEE:
    case R600::MUL_INT24_cm:
    case R600::MUL_UINT24_eg:
    case R600::OR_INT:
    case R600::PRED_SETE:
    case R600::PRED_SETE_INT:
    case R600::PRED_SETGE:
    case R600::PRED_SETGE_INT:
    case R600::PRED_SETGT:
    case R600::PRED_SETGT_INT:
    case R600::PRED_SETNE:
    case R600::PRED_SETNE_INT:
    case R600::SETE:
    case R600::SETE_DX10:
    case R600::SETE_INT:
    case R600::SETGE_DX10:
    case R600::SETGE_INT:
    case R600::SETGE_UINT:
    case R600::SETGT_DX10:
    case R600::SETGT_INT:
    case R600::SETGT_UINT:
    case R600::SETNE_DX10:
    case R600::SETNE_INT:
    case R600::SGE:
    case R600::SGT:
    case R600::SNE:
    case R600::SUBB_UINT:
    case R600::SUB_INT:
    case R600::XOR_INT: {
      switch (OpNum) {
      case 7:
        // op: src0
        return 0;
      case 9:
        // op: src0_rel
        return 9;
      case 12:
        // op: src1
        return 13;
      case 14:
        // op: src1_rel
        return 22;
      case 18:
        // op: pred_sel
        return 29;
      case 17:
        // op: last
        return 31;
      case 8:
        // op: src0_neg
        return 12;
      case 13:
        // op: src1_neg
        return 25;
      case 0:
        // op: dst
        return 53;
      case 20:
        // op: bank_swizzle
        return 50;
      case 5:
        // op: dst_rel
        return 60;
      case 6:
        // op: clamp
        return 63;
      case 10:
        // op: src0_abs
        return 32;
      case 15:
        // op: src1_abs
        return 33;
      case 1:
        // op: update_exec_mask
        return 34;
      case 2:
        // op: update_pred
        return 35;
      case 3:
        // op: write
        return 36;
      case 4:
        // op: omod
        return 37;
      }
      break;
    }
    case R600::INTERP_XY:
    case R600::INTERP_ZW: {
      switch (OpNum) {
      case 7:
        // op: src0
        return 0;
      case 9:
        // op: src0_rel
        return 9;
      case 12:
        // op: src1
        return 13;
      case 14:
        // op: src1_rel
        return 22;
      case 18:
        // op: pred_sel
        return 29;
      case 17:
        // op: last
        return 31;
      case 8:
        // op: src0_neg
        return 12;
      case 13:
        // op: src1_neg
        return 25;
      case 0:
        // op: dst
        return 53;
      case 5:
        // op: dst_rel
        return 60;
      case 6:
        // op: clamp
        return 63;
      case 10:
        // op: src0_abs
        return 32;
      case 15:
        // op: src1_abs
        return 33;
      case 1:
        // op: update_exec_mask
        return 34;
      case 2:
        // op: update_pred
        return 35;
      case 3:
        // op: write
        return 36;
      case 4:
        // op: omod
        return 37;
      }
      break;
    }
  }
  std::string msg;
  raw_string_ostream Msg(msg);
  Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
  report_fatal_error(Msg.str().c_str());
}

#endif // GET_OPERAND_BIT_OFFSET
llvm/lib/Target/AMDGPU/R600GenMCCodeEmitter.inc
