/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM namespace llvm { namespace ARM { enum { … }; } // end namespace ARM } // end namespace llvm #endif // GET_INSTRINFO_ENUM #ifdef GET_INSTRINFO_SCHED_ENUM #undef GET_INSTRINFO_SCHED_ENUM namespace llvm { namespace ARM { namespace Sched { enum { NoInstrModel = 0, IIC_iALUi_WriteALU_ReadALU = 1, IIC_iALUr_WriteALU_ReadALU_ReadALU = 2, IIC_iALUsr_WriteALUsi_ReadALU = 3, IIC_iALUsr_WriteALUSsr_ReadALUsr = 4, IIC_Br_WriteBr = 5, IIC_Br_WriteBrL = 6, IIC_Br_WriteBrTbl = 7, IIC_iLoad_mBr = 8, IIC_iLoad_i = 9, IIC_iLoadiALU = 10, IIC_iLoad_d_r = 11, IIC_iMAC32_WriteMAC32_ReadMUL_ReadMUL_ReadMAC = 12, IIC_iCMOVi_WriteALU = 13, IIC_iMOVi_WriteALU = 14, IIC_iCMOVix2 = 15, IIC_iCMOVr_WriteALU = 16, IIC_iCMOVsr_WriteALU = 17, IIC_iMOVix2addpc = 18, IIC_iMOVix2ld = 19, IIC_iMOVix2 = 20, IIC_iMOVsi_WriteALU = 21, IIC_iMUL32_WriteMUL32_ReadMUL_ReadMUL = 22, IIC_iALUr_WriteALU_ReadALU = 23, IIC_iLoad_r = 24, IIC_iLoad_bh_r = 25, IIC_iStore_r = 26, IIC_iStore_bh_r = 27, IIC_iMAC64_WriteMAC64Lo_WriteMAC64Hi_ReadMUL_ReadMUL_ReadMAC_ReadMAC = 28, IIC_iMUL64_WriteMUL64Lo_WriteMUL64Hi_ReadMUL_ReadMUL = 29, IIC_iStore_d_r = 30, IIC_iStore_ru = 31, IIC_Br = 32, IIC_VMOVImm = 33, IIC_fpUNA64 = 34, IIC_fpUNA16 = 35, IIC_fpUNA32 = 36, IIC_iALUsi_WriteALUsi_ReadALUsr = 37, IIC_iCMOVsi_WriteALU = 38, IIC_iALUsi_WriteALUsi_ReadALU = 39, IIC_iStore_ru_WriteST = 40, IIC_iALUr_WriteALU = 41, IIC_iALUi_WriteALU = 42, IIC_iLoad_mu = 43, IIC_iPop_Br_WriteBrL = 44, IIC_iALUsr_WriteALUsr_ReadALUsr = 45, IIC_iBITi_WriteALU_ReadALU = 46, IIC_iBITr_WriteALU_ReadALU_ReadALU = 47, IIC_iBITsr_WriteALUsi_ReadALU = 48, IIC_iBITsr_WriteALUsr_ReadALUsr = 49, IIC_VDOTPROD = 50, IIC_iUNAsi = 51, WriteBrL = 52, WriteBr = 53, IIC_iUNAr_WriteALU = 54, IIC_iCMPi_WriteCMP_ReadALU = 55, IIC_iCMPr_WriteCMP_ReadALU_ReadALU = 56, IIC_iCMPsr_WriteCMPsi_ReadALU = 57, IIC_iCMPsr_WriteCMPsr_ReadALU = 58, IIC_fpSTAT = 59, IIC_iLoad_m = 60, IIC_iLoad_bh_ru = 61, IIC_iLoad_bh_iu = 62, IIC_iLoad_bh_si = 63, IIC_iLoad_d_ru = 64, IIC_iLoad_ru = 65, IIC_iLoad_iu = 66, IIC_iLoad_si = 67, IIC_iMOVr_WriteALU = 68, IIC_iMOVsr_WriteALU = 69, IIC_iMVNi_WriteALU = 70, IIC_iMVNr_WriteALU = 71, IIC_iMVNsr_WriteALU = 72, IIC_iBITsi_WriteALUsi_ReadALU = 73, IIC_Preload_WritePreLd = 74, IIC_iDIV_WriteDIV = 75, IIC_iMAC16_WriteMAC16_ReadMUL_ReadMUL_ReadMAC = 76, WriteMAC32_ReadMUL_ReadMUL_ReadMAC = 77, WriteMAC64Lo_WriteMAC64Hi_ReadMUL_ReadMUL_ReadMAC_ReadMAC = 78, WriteMUL64Lo_WriteMUL64Hi_ReadMUL_ReadMUL = 79, WriteMUL32_ReadMUL_ReadMUL = 80, IIC_iMUL16_WriteMUL16_ReadMUL_ReadMUL = 81, IIC_iStore_m = 82, IIC_iStore_mu = 83, IIC_iStore_bh_ru = 84, IIC_iStore_bh_iu = 85, IIC_iStore_bh_si = 86, IIC_iStore_d_ru = 87, IIC_iStore_iu = 88, IIC_iStore_si = 89, IIC_iEXTAr_WriteALUsr = 90, IIC_iEXTr_WriteALUsi = 91, IIC_iTSTi_WriteCMP_ReadALU = 92, IIC_iTSTr_WriteCMP_ReadALU_ReadALU = 93, IIC_iTSTsr_WriteCMPsi_ReadALU = 94, IIC_iTSTsr_WriteCMPsr_ReadALU = 95, IIC_iMUL64_WriteMAC64Lo_WriteMAC64Hi_ReadMUL_ReadMUL = 96, WriteALU_ReadALU_ReadALU = 97, IIC_VABAD = 98, IIC_VABAQ = 99, IIC_VSUBi4Q = 100, IIC_VBIND = 101, IIC_VBINQ = 102, IIC_VSUBi4D = 103, IIC_VUNAD = 104, IIC_VUNAQ = 105, IIC_VUNAiQ = 106, IIC_VUNAiD = 107, IIC_fpALU64_WriteFPALU64 = 108, IIC_fpALU16_WriteFPALU32 = 109, IIC_VBINi4D = 110, IIC_VSHLiD = 111, IIC_fpALU32_WriteFPALU32 = 112, IIC_VSUBiD = 113, IIC_VBINiQ = 114, IIC_VBINiD = 115, IIC_VMACD = 116, IIC_VMACQ = 117, IIC_VCNTiQ = 118, IIC_VCNTiD = 119, IIC_fpCMP64 = 120, IIC_fpCMP16 = 121, IIC_fpCMP32 = 122, WriteFPCVT = 123, IIC_fpCVTSH_WriteFPCVT = 124, IIC_fpCVTHS_WriteFPCVT = 125, IIC_fpCVTDS_WriteFPCVT = 126, IIC_fpCVTSD_WriteFPCVT = 127, IIC_fpDIV64_WriteFPDIV64 = 128, IIC_fpDIV16_WriteFPDIV32 = 129, IIC_fpDIV32_WriteFPDIV32 = 130, IIC_VMOVIS = 131, IIC_VMOVD = 132, IIC_VMOVQ = 133, IIC_VEXTD = 134, IIC_VEXTQ = 135, IIC_fpFMAC64_WriteFPMAC64_ReadFPMAC_ReadFPMUL_ReadFPMUL = 136, IIC_fpFMAC16_WriteFPMAC32_ReadFPMAC_ReadFPMUL_ReadFPMUL = 137, IIC_fpFMAC32_WriteFPMAC32_ReadFPMAC_ReadFPMUL_ReadFPMUL = 138, IIC_VFMACD = 139, IIC_VFMACQ = 140, IIC_VMOVSI = 141, IIC_VBINi4Q = 142, IIC_fpCVTDI = 143, IIC_VLD1dup_WriteVLD2 = 144, IIC_VLD1dupu = 145, IIC_VLD1dup = 146, IIC_VLD1dupu_WriteVLD1 = 147, IIC_VLD1ln = 148, IIC_VLD1lnu_WriteVLD1 = 149, IIC_VLD1ln_WriteVLD1 = 150, IIC_VLD1_WriteVLD1 = 151, IIC_VLD1x4_WriteVLD4 = 152, IIC_VLD1x2u_WriteVLD4 = 153, IIC_VLD1x3_WriteVLD3 = 154, IIC_VLD1x2u_WriteVLD3 = 155, IIC_VLD1u_WriteVLD1 = 156, IIC_VLD1x2_WriteVLD2 = 157, IIC_VLD1x2u_WriteVLD2 = 158, IIC_VLD2dup = 159, IIC_VLD2dupu_WriteVLD1 = 160, IIC_VLD2dup_WriteVLD2 = 161, IIC_VLD2ln_WriteVLD1 = 162, IIC_VLD2lnu_WriteVLD1 = 163, IIC_VLD2lnu = 164, IIC_VLD2_WriteVLD2 = 165, IIC_VLD2u_WriteVLD2 = 166, IIC_VLD2x2_WriteVLD4 = 167, IIC_VLD2x2u_WriteVLD4 = 168, IIC_VLD3dup_WriteVLD2 = 169, IIC_VLD3dupu_WriteVLD2 = 170, IIC_VLD3ln_WriteVLD2 = 171, IIC_VLD3lnu_WriteVLD2 = 172, IIC_VLD3_WriteVLD3 = 173, IIC_VLD3u_WriteVLD3 = 174, IIC_VLD4dup = 175, IIC_VLD4dup_WriteVLD2 = 176, IIC_VLD4dupu_WriteVLD2 = 177, IIC_VLD4ln_WriteVLD2 = 178, IIC_VLD4lnu_WriteVLD2 = 179, IIC_VLD4lnu = 180, IIC_VLD4_WriteVLD4 = 181, IIC_VLD4u_WriteVLD4 = 182, IIC_fpLoad_mu = 183, IIC_fpLoad_m = 184, IIC_fpLoad64 = 185, IIC_fpLoad16 = 186, IIC_fpLoad32 = 187, IIC_fpMAC64_WriteFPMAC64_ReadFPMAC_ReadFPMUL_ReadFPMUL = 188, IIC_fpMAC16 = 189, IIC_VMACi32D = 190, IIC_VMACi16D = 191, IIC_fpMAC32_WriteFPMAC32_ReadFPMAC_ReadFPMUL_ReadFPMUL = 192, IIC_VMACi32Q = 193, IIC_VMACi16Q = 194, IIC_fpMOVID_WriteFPMOV = 195, IIC_fpMOVIS_WriteFPMOV = 196, IIC_VQUNAiD = 197, IIC_VMOVN = 198, IIC_fpMOVSI_WriteFPMOV = 199, IIC_fpMOVDI_WriteFPMOV = 200, IIC_fpMUL64_WriteFPMUL64_ReadFPMUL_ReadFPMUL = 201, IIC_fpMUL16_WriteFPMUL32_ReadFPMUL_ReadFPMUL = 202, IIC_VMULi16D = 203, IIC_VMULi32D = 204, IIC_fpMUL32_WriteFPMUL32_ReadFPMUL_ReadFPMUL = 205, IIC_VFMULD = 206, IIC_VFMULQ = 207, IIC_VMULi16Q = 208, IIC_VMULi32Q = 209, IIC_VSHLiQ = 210, IIC_VPALiQ = 211, IIC_VPALiD = 212, IIC_VPBIND = 213, IIC_VQUNAiQ = 214, IIC_VSHLi4Q = 215, IIC_VSHLi4D = 216, IIC_VRECSD = 217, IIC_VRECSQ = 218, IIC_VMOVISL = 219, IIC_fpCVTID_WriteFPCVT = 220, IIC_fpCVTIH_WriteFPCVT = 221, IIC_fpCVTIS_WriteFPCVT = 222, IIC_fpSQRT64_WriteFPSQRT64 = 223, IIC_fpSQRT16 = 224, IIC_fpSQRT32_WriteFPSQRT32 = 225, IIC_VST1ln_WriteVST1 = 226, IIC_VST1lnu_WriteVST1 = 227, IIC_VST1_WriteVST1 = 228, IIC_VST1x4_WriteVST4 = 229, IIC_VST1x4u_WriteVST4 = 230, IIC_VLD1x4u_WriteVST4 = 231, IIC_VST1x3_WriteVST3 = 232, IIC_VST1x3u_WriteVST3 = 233, IIC_VLD1x3u_WriteVST3 = 234, IIC_VLD1u_WriteVST1 = 235, IIC_VST1x2_WriteVST2 = 236, IIC_VLD1x2u_WriteVST2 = 237, IIC_VST2ln_WriteVST1 = 238, IIC_VST2lnu_WriteVST1 = 239, IIC_VST2lnu = 240, IIC_VST2 = 241, IIC_VLD1u_WriteVST2 = 242, IIC_VST2_WriteVST2 = 243, IIC_VST2x2_WriteVST4 = 244, IIC_VST2x2u_WriteVST4 = 245, IIC_VLD1u_WriteVST4 = 246, IIC_VST3ln_WriteVST2 = 247, IIC_VST3lnu_WriteVST2 = 248, IIC_VST3lnu = 249, IIC_VST3ln = 250, IIC_VST3_WriteVST3 = 251, IIC_VST3u_WriteVST3 = 252, IIC_VST4ln_WriteVST2 = 253, IIC_VST4lnu_WriteVST2 = 254, IIC_VST4lnu = 255, IIC_VST4_WriteVST4 = 256, IIC_VST4u_WriteVST4 = 257, IIC_fpStore_mu = 258, IIC_fpStore_m = 259, IIC_fpStore64 = 260, IIC_fpStore16 = 261, IIC_fpStore32 = 262, IIC_VSUBiQ = 263, IIC_VTB1 = 264, IIC_VTB2 = 265, IIC_VTB3 = 266, IIC_VTB4 = 267, IIC_VTBX1 = 268, IIC_VTBX2 = 269, IIC_VTBX3 = 270, IIC_VTBX4 = 271, IIC_fpCVTDI_WriteFPCVT = 272, IIC_fpCVTHI_WriteFPCVT = 273, IIC_fpCVTSI_WriteFPCVT = 274, IIC_VPERMD = 275, IIC_VPERMQ = 276, IIC_VPERMQ3 = 277, IIC_iUNAsi_WriteALU = 278, IIC_iBITi_WriteALU = 279, IIC_iCMPsi_WriteCMPsi_ReadALU_ReadALU = 280, IIC_iCMPi_WriteCMP = 281, IIC_iCMPr_WriteCMP = 282, IIC_iCMPsi_WriteCMPsi = 283, IIC_iALUx = 284, WriteLd = 285, IIC_iLoad_bh_i_WriteLd = 286, IIC_iLoad_bh_iu_WriteLd = 287, IIC_iLoad_bh_si_WriteLd = 288, IIC_iLoad_d_ru_WriteLd = 289, IIC_iLoad_d_i_WriteLd = 290, IIC_iLoad_i_WriteLd = 291, IIC_iLoad_iu_WriteLd = 292, IIC_iLoad_si_WriteLd = 293, IIC_iMVNsi_WriteALU = 294, IIC_iALUsir_WriteALUsi_ReadALU = 295, IIC_iMUL16_WriteMAC16_ReadMUL_ReadMUL_ReadMAC = 296, IIC_iMAC32 = 297, WriteALU = 298, WriteST = 299, IIC_iStore_bh_i_WriteST = 300, IIC_iStore_bh_iu_WriteST = 301, IIC_iStore_bh_si_WriteST = 302, IIC_iStore_d_ru_WriteST = 303, IIC_iStore_d_r_WriteST = 304, IIC_iStore_iu_WriteST = 305, IIC_iStore_i_WriteST = 306, IIC_iStore_si_WriteST = 307, IIC_iEXTAsr_WriteALU_ReadALU = 308, IIC_iEXTr_WriteALU_ReadALU = 309, IIC_iTSTi_WriteCMP = 310, IIC_iTSTr_WriteCMP = 311, IIC_iTSTsi_WriteCMPsi = 312, IIC_iBITr_WriteALU = 313, IIC_iLoad_bh_r_WriteLd = 314, IIC_iLoad_r_WriteLd = 315, IIC_iPop_WriteLd = 316, IIC_iStore_m_WriteST = 317, IIC_iStore_bh_r_WriteST = 318, IIC_iStore_r_WriteST = 319, IIC_iTSTr_WriteALU = 320, ANDri_ORRri_EORri_BICri = 321, ANDrr_ORRrr_EORrr_BICrr = 322, ANDrsi_ORRrsi_EORrsi_BICrsi = 323, ANDrsr_ORRrsr_EORrsr_BICrsr = 324, MOVsra_glue_MOVsrl_glue = 325, MOVsr_MOVsi = 326, MVNsr = 327, MOVCCsi_MOVCCsr = 328, MVNr = 329, MOVCCi32imm = 330, MOVi32imm = 331, MOV_ga_pcrel = 332, MOV_ga_pcrel_ldr = 333, SEL = 334, BFC_BFI_UBFX_SBFX = 335, MULv5_MUL_SMMUL_SMMULR = 336, MLAv5_MLA_MLS_SMMLA_SMMLAR_SMMLS_SMMLSR = 337, SMULLv5_SMULL_UMULLv5 = 338, UMULL = 339, SMLAL_UMLALv5_UMLAL_UMAAL_SMLALv5_SMLALBB_SMLALBT_SMLALTB_SMLALTT = 340, SMLAD_SMLADX_SMLSD_SMLSDX = 341, SMLALD_SMLSLD = 342, SMLALDX_SMLSLDX = 343, SMUAD_SMUADX_SMUSD_SMUSDX = 344, SMULBB_SMULBT_SMULTB_SMULTT_SMULWB_SMULWT = 345, SMLABB_SMLABT_SMLATB_SMLATT_SMLAWB_SMLAWT = 346, LDRi12_PICLDR = 347, LDRrs = 348, LDRBi12_PICLDRH_PICLDRB_PICLDRSH_PICLDRSB_LDRH_LDRSH_LDRSB = 349, LDRHTii_LDRSHTii_LDRSBTii = 350, LDRHTi_LDRHTr_LDRH_POST_LDRH_PRE_LDRSHTi_LDRSHTr_LDRSH_POST_LDRSH_PRE_LDRSBTi_LDRSBTr_LDRSB_POST_LDRSB_PRE = 351, SXTB_SXTB16_SXTH_UXTB_UXTB16_UXTH = 352, t2SXTB_t2SXTB16_t2SXTH_t2UXTB_t2UXTB16_t2UXTH = 353, t2MOVCCi32imm = 354, t2MOVi32imm = 355, t2MOV_ga_pcrel = 356, t2MOVi16_ga_pcrel = 357, t2SEL = 358, t2BFC_t2UBFX_t2SBFX = 359, t2BFI = 360, QADD_QADD16_QADD8_QSUB_QSUB16_QSUB8_QDADD_QDSUB_QASX_QSAX_UQADD8_UQADD16_UQSUB8_UQSUB16_UQASX_UQSAX = 361, SSAT_SSAT16_USAT_USAT16_t2QADD_t2QADD16_t2QADD8_t2QSUB_t2QSUB16_t2QSUB8_t2QDADD_t2QDSUB_t2QASX_t2QSAX_t2UQADD8_t2UQADD16_t2UQSUB8_t2UQSUB16_t2UQASX_t2UQSAX = 362, t2SSAT_t2SSAT16_t2USAT_t2USAT16 = 363, SADD8_SADD16_SSUB8_SSUB16_SASX_SSAX_UADD8_UADD16_USUB8_USUB16_UASX_USAX = 364, t2SADD8_t2SADD16_t2SSUB8_t2SSUB16_t2SASX_t2SSAX_t2UADD8_t2UADD16_t2USUB8_t2USUB16_t2UASX_t2USAX = 365, SHADD8_SHADD16_SHSUB8_SHSUB16_SHASX_SHSAX_UHADD8_UHADD16_UHSUB8_UHSUB16_UHASX_UHSAX = 366, SXTAB_SXTAB16_SXTAH_UXTAB_UXTAB16_UXTAH = 367, t2SHADD8_t2SHADD16_t2SHSUB8_t2SHSUB16_t2SHASX_t2SHSAX_t2UHADD8_t2UHADD16_t2UHSUB8_t2UHSUB16_t2UHASX_t2UHSAX = 368, t2SXTAB_t2SXTAB16_t2SXTAH_t2UXTAB_t2UXTAB16_t2UXTAH = 369, USAD8 = 370, USADA8 = 371, SMUSD_SMUSDX = 372, t2MUL_t2SMMUL_t2SMMULR = 373, t2SMULBB_t2SMULBT_t2SMULTB_t2SMULTT_t2SMULWB_t2SMULWT = 374, t2SMUSD_t2SMUSDX = 375, t2MLA_t2MLS_t2SMMLA_t2SMMLAR_t2SMMLS_t2SMMLSR = 376, t2SMUAD_t2SMUADX = 377, SMLSD_SMLSDX = 378, t2SMLABB_t2SMLABT_t2SMLATB_t2SMLATT_t2SMLAWB_t2SMLAWT = 379, t2SMLSD_t2SMLSDX = 380, t2SMLAD_t2SMLADX = 381, SMULL = 382, t2SMULL_t2UMULL = 383, t2SMLAL_t2SMLALBB_t2SMLALBT_t2SMLALD_t2SMLALDX_t2SMLALTB_t2SMLALTT_t2UMLAL_t2SMLSLD_t2SMLSLDX_t2UMAAL = 384, SDIV_UDIV_t2SDIV_t2UDIV = 385, LDRi12 = 386, LDRBi12 = 387, LDRBrs = 388, t2LDRpci_pic = 389, t2LDRi12_t2LDRi8_t2LDRpci_tLDRi_tLDRpci_tLDRspi = 390, t2LDRs = 391, t2LDRBi12_t2LDRBi8_t2LDRBpci_t2LDRHi12_t2LDRHi8_t2LDRHpci_tLDRBi_tLDRHi = 392, t2LDRBs_t2LDRHs = 393, LDREX_LDREXB_LDREXD_LDREXH_tLDRpci_pic = 394, tLDRBr_tLDRHr = 395, tLDRr = 396, LDRH_PICLDRB_PICLDRH = 397, LDRcp = 398, t2LDRSBpcrel_t2LDRSHpcrel = 399, t2LDRSBi12_t2LDRSBi8_t2LDRSBpci_t2LDRSHi12_t2LDRSHi8_t2LDRSHpci = 400, t2LDRSBs_t2LDRSHs = 401, tLDRSB_tLDRSH = 402, LDRBT_POST_IMM_LDRBT_POST_REG_LDRB_POST_REG_LDRB_PRE_REG = 403, LDRB_POST_IMM_LDRB_PRE_IMM = 404, LDRT_POST_IMM_LDRT_POST_REG_LDR_POST_REG_LDR_PRE_REG = 405, LDR_POST_IMM_LDR_PRE_IMM = 406, LDRH_POST_LDRH_PRE_LDRHTi_LDRHTr = 407, LDRHTii = 408, t2LDRB_POST_imm_t2LDRB_PRE_imm_t2LDRH_POST_imm_t2LDRH_PRE_imm_t2LDR_POST_imm_t2LDR_PRE_imm = 409, t2LDRB_POST_t2LDRB_PRE_t2LDRH_POST_t2LDRH_PRE = 410, t2LDR_POST_t2LDR_PRE = 411, t2LDRBT_t2LDRHT = 412, t2LDRT = 413, t2LDRSB_POST_imm_t2LDRSB_PRE_imm_t2LDRSH_POST_imm_t2LDRSH_PRE_imm = 414, t2LDRSB_POST_t2LDRSB_PRE_t2LDRSH_POST_t2LDRSH_PRE = 415, t2LDRSBT_t2LDRSHT = 416, t2LDRDi8 = 417, LDRD = 418, LDRD_POST_LDRD_PRE = 419, t2LDRD_POST_t2LDRD_PRE = 420, LDMDA_LDMDB_LDMIA_LDMIB_t2LDMDB_t2LDMIA_sysLDMDA_sysLDMDB_sysLDMIA_sysLDMIB_tLDMIA = 421, LDMDA_UPD_LDMDB_UPD_LDMIA_UPD_LDMIB_UPD_tLDMIA_UPD_sysLDMDA_UPD_sysLDMDB_UPD_sysLDMIA_UPD_sysLDMIB_UPD_t2LDMDB_UPD_t2LDMIA_UPD = 422, LDMIA_RET_t2LDMIA_RET = 423, tPOP_RET = 424, tPOP = 425, PICSTR_STRi12 = 426, PICSTRB_PICSTRH_STRBi12_STRH = 427, STRrs = 428, STRBrs = 429, STREX_STREXB_STREXD_STREXH = 430, t2STRi12_t2STRi8_tSTRi_tSTRspi = 431, t2STRs = 432, t2STRBi12_t2STRBi8_t2STRHi12_t2STRHi8_tSTRBi_tSTRHi = 433, t2STRBs_t2STRHs = 434, tSTRBr_tSTRHr = 435, tSTRr = 436, STRBT_POST_IMM_STRBT_POST_REG_STRB_POST_REG_STRB_PRE_REG_STRH_POST_STRH_PRE_STRHTi_STRHTr = 437, STRB_POST_IMM_STRB_PRE_IMM = 438, STRT_POST_IMM_STRT_POST_REG_STR_POST_REG_STR_PRE_REG_STRi_preidx_STRr_preidx_STRBi_preidx_STRBr_preidx_STRH_preidx = 439, STR_POST_IMM_STR_PRE_IMM = 440, STRBT_POST_STRT_POST_t2STR_POST_imm_t2STR_PRE_imm_t2STRB_POST_imm_t2STRB_PRE_imm_t2STRH_POST_imm_t2STRH_PRE_imm = 441, t2STR_POST_t2STR_PRE_t2STRH_PRE = 442, t2STRB_POST_t2STRB_PRE_t2STRH_POST = 443, t2STR_preidx_t2STRB_preidx_t2STRH_preidx = 444, t2STRBT_t2STRHT = 445, t2STRT = 446, STRD = 447, t2STRDi8 = 448, t2STRD_POST_t2STRD_PRE = 449, STRD_POST_STRD_PRE = 450, STMDA_STMDB_STMIA_STMIB_sysSTMDA_sysSTMDB_sysSTMIA_sysSTMIB_t2STMDB_t2STMIA = 451, STMDA_UPD_STMDB_UPD_STMIA_UPD_STMIB_UPD_sysSTMDA_UPD_sysSTMDB_UPD_sysSTMIA_UPD_sysSTMIB_UPD_t2STMDB_UPD_t2STMIA_UPD_tSTMIA_UPD = 452, tPUSH = 453, LDRLIT_ga_abs_tLDRLIT_ga_abs = 454, LDRLIT_ga_pcrel_tLDRLIT_ga_pcrel = 455, LDRLIT_ga_pcrel_ldr = 456, t2IT = 457, ITasm = 458, VADDv16i8_VADDv2i64_VADDv4i32_VADDv8i16_VANDq_VBICq_VEORq_VORNq_VORRq_VBIFq_VBITq_VBSLq_VBSPq = 459, VADDv1i64_VADDv2i32_VADDv4i16_VADDv8i8_VANDd_VBICd_VEORd_VORNd_VORRd_VBIFd_VBITd_VBSLd_VBSPd = 460, VSUBv16i8_VSUBv2i64_VSUBv4i32_VSUBv8i16 = 461, VSUBv1i64_VSUBv2i32_VSUBv4i16_VSUBv8i8_VADDWsv2i64_VADDWsv4i32_VADDWsv8i16_VADDWuv2i64_VADDWuv4i32_VADDWuv8i16_VSUBWsv2i64_VSUBWsv4i32_VSUBWsv8i16_VSUBWuv2i64_VSUBWuv4i32_VSUBWuv8i16 = 462, VNEGf32q = 463, VNEGfd = 464, VNEGs16d_VNEGs32d_VNEGs8d_VADDLsv2i64_VADDLsv4i32_VADDLsv8i16_VADDLuv2i64_VADDLuv4i32_VADDLuv8i16_VSUBLsv2i64_VSUBLsv4i32_VSUBLsv8i16_VSUBLuv2i64_VSUBLuv4i32_VSUBLuv8i16_VPADDi16_VPADDi32_VPADDi8_VPADDLsv16i8_VPADDLsv2i32_VPADDLsv4i16_VPADDLsv4i32_VPADDLsv8i16_VPADDLsv8i8_VPADDLuv16i8_VPADDLuv2i32_VPADDLuv4i16_VPADDLuv4i32_VPADDLuv8i16_VPADDLuv8i8_VSHLLi16_VSHLLi32_VSHLLi8_VSHLLsv2i64_VSHLLsv4i32_VSHLLsv8i16_VSHLLuv2i64_VSHLLuv4i32_VSHLLuv8i16_VSHLiv16i8_VSHLiv1i64_VSHLiv2i32_VSHLiv2i64_VSHLiv4i16_VSHLiv4i32_VSHLiv8i16_VSHLiv8i8_VSHLsv1i64_VSHLsv2i32_VSHLsv4i16_VSHLsv8i8_VSHLuv1i64_VSHLuv2i32_VSHLuv4i16_VSHLuv8i8_VSHRsv16i8_VSHRsv1i64_VSHRsv2i32_VSHRsv2i64_VSHRsv4i16_VSHRsv4i32_VSHRsv8i16_VSHRsv8i8_VSHRuv16i8_VSHRuv1i64_VSHRuv2i32_VSHRuv2i64_VSHRuv4i16_VSHRuv4i32_VSHRuv8i16_VSHRuv8i8_VSLIv1i64_VSLIv2i32_VSLIv4i16_VSLIv8i8_VSRIv1i64_VSRIv2i32_VSRIv4i16_VSRIv8i8 = 465, VNEGs16q_VNEGs32q_VNEGs8q_VSHLsv16i8_VSHLsv2i64_VSHLsv4i32_VSHLsv8i16_VSHLuv16i8_VSHLuv2i64_VSHLuv4i32_VSHLuv8i16_VSLIv16i8_VSLIv2i64_VSLIv4i32_VSLIv8i16_VSRIv16i8_VSRIv2i64_VSRIv4i32_VSRIv8i16 = 466, VHADDsv16i8_VHADDsv4i32_VHADDsv8i16_VHADDuv16i8_VHADDuv4i32_VHADDuv8i16_VRHADDsv16i8_VRHADDsv4i32_VRHADDsv8i16_VRHADDuv16i8_VRHADDuv4i32_VRHADDuv8i16_VTSTv16i8_VTSTv4i32_VTSTv8i16 = 467, VHADDsv2i32_VHADDsv4i16_VHADDsv8i8_VHADDuv2i32_VHADDuv4i16_VHADDuv8i8_VRHADDsv2i32_VRHADDsv4i16_VRHADDsv8i8_VRHADDuv2i32_VRHADDuv4i16_VRHADDuv8i8_VTSTv2i32_VTSTv4i16_VTSTv8i8 = 468, VHSUBsv16i8_VHSUBsv4i32_VHSUBsv8i16_VHSUBuv16i8_VHSUBuv4i32_VHSUBuv8i16 = 469, VHSUBsv2i32_VHSUBsv4i16_VHSUBsv8i8_VHSUBuv2i32_VHSUBuv4i16_VHSUBuv8i8 = 470, VBICiv2i32_VBICiv4i16_VBICiv4i32_VBICiv8i16_VORRiv2i32_VORRiv4i16_VORRiv4i32_VORRiv8i16 = 471, VQSHLsiv16i8_VQSHLsiv1i64_VQSHLsiv2i32_VQSHLsiv2i64_VQSHLsiv4i16_VQSHLsiv4i32_VQSHLsiv8i16_VQSHLsiv8i8_VQSHLsuv16i8_VQSHLsuv1i64_VQSHLsuv2i32_VQSHLsuv2i64_VQSHLsuv4i16_VQSHLsuv4i32_VQSHLsuv8i16_VQSHLsuv8i8_VQSHLsv1i64_VQSHLsv2i32_VQSHLsv4i16_VQSHLsv8i8_VQSHLuiv16i8_VQSHLuiv1i64_VQSHLuiv2i32_VQSHLuiv2i64_VQSHLuiv4i16_VQSHLuiv4i32_VQSHLuiv8i16_VQSHLuiv8i8_VQSHLuv1i64_VQSHLuv2i32_VQSHLuv4i16_VQSHLuv8i8 = 472, VQSHLsv16i8_VQSHLsv2i64_VQSHLsv4i32_VQSHLsv8i16_VQSHLuv16i8_VQSHLuv2i64_VQSHLuv4i32_VQSHLuv8i16 = 473, VCLSv16i8_VCLSv4i32_VCLSv8i16_VCLZv16i8_VCLZv4i32_VCLZv8i16_VCNTq = 474, VCLSv2i32_VCLSv4i16_VCLSv8i8_VCLZv2i32_VCLZv4i16_VCLZv8i8_VCNTd = 475, VEXTd16_VEXTd32_VEXTd8 = 476, VEXTq16_VEXTq32_VEXTq64_VEXTq8 = 477, VREV16d8_VREV32d16_VREV32d8_VREV64d16_VREV64d32_VREV64d8 = 478, VREV16q8_VREV32q16_VREV32q8_VREV64q16_VREV64q32_VREV64q8 = 479, VABALsv2i64_VABALsv4i32_VABALsv8i16_VABALuv2i64_VABALuv4i32_VABALuv8i16_VABAsv2i32_VABAsv4i16_VABAsv8i8_VABAuv2i32_VABAuv4i16_VABAuv8i8 = 480, VABAsv16i8_VABAsv4i32_VABAsv8i16_VABAuv16i8_VABAuv4i32_VABAuv8i16 = 481, VPADALsv16i8_VPADALsv4i32_VPADALsv8i16_VPADALuv16i8_VPADALuv4i32_VPADALuv8i16 = 482, VPADALsv2i32_VPADALsv4i16_VPADALsv8i8_VPADALuv2i32_VPADALuv4i16_VPADALuv8i8_VRSRAsv16i8_VRSRAsv1i64_VRSRAsv2i32_VRSRAsv2i64_VRSRAsv4i16_VRSRAsv4i32_VRSRAsv8i16_VRSRAsv8i8_VRSRAuv16i8_VRSRAuv1i64_VRSRAuv2i32_VRSRAuv2i64_VRSRAuv4i16_VRSRAuv4i32_VRSRAuv8i16_VRSRAuv8i8_VSRAsv16i8_VSRAsv1i64_VSRAsv2i32_VSRAsv2i64_VSRAsv4i16_VSRAsv4i32_VSRAsv8i16_VSRAsv8i8_VSRAuv16i8_VSRAuv1i64_VSRAuv2i32_VSRAuv2i64_VSRAuv4i16_VSRAuv4i32_VSRAuv8i16_VSRAuv8i8 = 483, VACGEfd_VACGEhd_VACGTfd_VACGThd_VCEQfd_VCEQhd_VCGEfd_VCGEhd_VCGTfd_VCGThd = 484, VACGEfq_VACGEhq_VACGTfq_VACGThq_VCEQfq_VCEQhq_VCGEfq_VCGEhq_VCGTfq_VCGThq = 485, VCEQv16i8_VCEQv4i32_VCEQv8i16_VCGEsv16i8_VCGEsv4i32_VCGEsv8i16_VCGEuv16i8_VCGEuv4i32_VCGEuv8i16_VCGTsv16i8_VCGTsv4i32_VCGTsv8i16_VCGTuv16i8_VCGTuv4i32_VCGTuv8i16_VQSUBsv16i8_VQSUBsv2i64_VQSUBsv4i32_VQSUBsv8i16_VQSUBuv16i8_VQSUBuv2i64_VQSUBuv4i32_VQSUBuv8i16 = 486, VCEQv2i32_VCEQv4i16_VCEQv8i8_VCGEsv2i32_VCGEsv4i16_VCGEsv8i8_VCGEuv2i32_VCGEuv4i16_VCGEuv8i8_VCGTsv2i32_VCGTsv4i16_VCGTsv8i8_VCGTuv2i32_VCGTuv4i16_VCGTuv8i8_VQSUBsv1i64_VQSUBsv2i32_VQSUBsv4i16_VQSUBsv8i8_VQSUBuv1i64_VQSUBuv2i32_VQSUBuv4i16_VQSUBuv8i8 = 487, VCEQzv16i8_VCEQzv2f32_VCEQzv2i32_VCEQzv4f16_VCEQzv4f32_VCEQzv4i16_VCEQzv4i32_VCEQzv8f16_VCEQzv8i16_VCEQzv8i8_VCGEzv16i8_VCGEzv2f32_VCGEzv2i32_VCGEzv4f16_VCGEzv4f32_VCGEzv4i16_VCGEzv4i32_VCGEzv8f16_VCGEzv8i16_VCGEzv8i8_VCGTzv16i8_VCGTzv2f32_VCGTzv2i32_VCGTzv4f16_VCGTzv4f32_VCGTzv4i16_VCGTzv4i32_VCGTzv8f16_VCGTzv8i16_VCGTzv8i8_VCLEzv16i8_VCLEzv2f32_VCLEzv2i32_VCLEzv4f16_VCLEzv4f32_VCLEzv4i16_VCLEzv4i32_VCLEzv8f16_VCLEzv8i16_VCLEzv8i8_VCLTzv16i8_VCLTzv2f32_VCLTzv2i32_VCLTzv4f16_VCLTzv4f32_VCLTzv4i16_VCLTzv4i32_VCLTzv8f16_VCLTzv8i16_VCLTzv8i8 = 488, VRSHLsv16i8_VRSHLsv2i64_VRSHLsv4i32_VRSHLsv8i16_VRSHLuv16i8_VRSHLuv2i64_VRSHLuv4i32_VRSHLuv8i16_VQRSHLsv16i8_VQRSHLsv2i64_VQRSHLsv4i32_VQRSHLsv8i16_VQRSHLuv16i8_VQRSHLuv2i64_VQRSHLuv4i32_VQRSHLuv8i16 = 489, VRSHLsv1i64_VRSHLsv2i32_VRSHLsv4i16_VRSHLsv8i8_VRSHLuv1i64_VRSHLuv2i32_VRSHLuv4i16_VRSHLuv8i8_VQRSHLsv1i64_VQRSHLsv2i32_VQRSHLsv4i16_VQRSHLsv8i8_VQRSHLuv1i64_VQRSHLuv2i32_VQRSHLuv4i16_VQRSHLuv8i8_VRSHRsv16i8_VRSHRsv1i64_VRSHRsv2i32_VRSHRsv2i64_VRSHRsv4i16_VRSHRsv4i32_VRSHRsv8i16_VRSHRsv8i8_VRSHRuv16i8_VRSHRuv1i64_VRSHRuv2i32_VRSHRuv2i64_VRSHRuv4i16_VRSHRuv4i32_VRSHRuv8i16_VRSHRuv8i8 = 490, VABSfd = 491, VABSfq = 492, VABSv16i8_VABSv4i32_VABSv8i16 = 493, VABSv2i32_VABSv4i16_VABSv8i8 = 494, VQABSv16i8_VQABSv4i32_VQABSv8i16_VQNEGv16i8_VQNEGv4i32_VQNEGv8i16 = 495, VQABSv2i32_VQABSv4i16_VQABSv8i8_VQNEGv2i32_VQNEGv4i16_VQNEGv8i8 = 496, VQADDsv16i8_VQADDsv2i64_VQADDsv4i32_VQADDsv8i16_VQADDuv16i8_VQADDuv2i64_VQADDuv4i32_VQADDuv8i16 = 497, VQADDsv1i64_VQADDsv2i32_VQADDsv4i16_VQADDsv8i8_VQADDuv1i64_VQADDuv2i32_VQADDuv4i16_VQADDuv8i8 = 498, VRECPEd_VRECPEfd_VRECPEhd_VRSQRTEd_VRSQRTEfd_VRSQRTEhd = 499, VRECPEfq_VRECPEhq_VRECPEq_VRSQRTEfq_VRSQRTEhq_VRSQRTEq = 500, VADDHNv2i32_VADDHNv4i16_VADDHNv8i8_VSUBHNv2i32_VSUBHNv4i16_VSUBHNv8i8 = 501, VSHRNv2i32_VSHRNv4i16_VSHRNv8i8 = 502, VRADDHNv2i32_VRADDHNv4i16_VRADDHNv8i8_VRSUBHNv2i32_VRSUBHNv4i16_VRSUBHNv8i8 = 503, VRSHRNv2i32_VRSHRNv4i16_VRSHRNv8i8_VQSHRNsv2i32_VQSHRNsv4i16_VQSHRNsv8i8_VQSHRNuv2i32_VQSHRNuv4i16_VQSHRNuv8i8_VQSHRUNv2i32_VQSHRUNv4i16_VQSHRUNv8i8_VQRSHRNsv2i32_VQRSHRNsv4i16_VQRSHRNsv8i8_VQRSHRNuv2i32_VQRSHRNuv4i16_VQRSHRNuv8i8_VQRSHRUNv2i32_VQRSHRUNv4i16_VQRSHRUNv8i8 = 504, VTBL1 = 505, VTBX1 = 506, VTBL2 = 507, VTBX2 = 508, VTBL3_VTBL3Pseudo = 509, VTBX3_VTBX3Pseudo = 510, VTBL4_VTBL4Pseudo = 511, VTBX4_VTBX4Pseudo = 512, VSWPd_VSWPq = 513, VTRNd16_VTRNd32_VTRNd8_VUZPd16_VUZPd8_VZIPd16_VZIPd8 = 514, VTRNq16_VTRNq32_VTRNq8 = 515, VUZPq16_VUZPq32_VUZPq8_VZIPq16_VZIPq32_VZIPq8 = 516, VABSD_VNEGD = 517, VABSS_VNEGS = 518, VCMPD_VCMPZD_VCMPED_VCMPEZD = 519, VCMPS_VCMPZS_VCMPES_VCMPEZS = 520, VADDS_VSUBS = 521, VADDfd_VSUBfd_VABDfd_VABDhd_VMAXfd_VMAXhd_VMINfd_VMINhd = 522, VADDfq_VSUBfq_VABDfq_VABDhq_VMAXfq_VMAXhq_VMINfq_VMINhq = 523, VABDLsv2i64_VABDLsv4i32_VABDLsv8i16_VABDLuv2i64_VABDLuv4i32_VABDLuv8i16_VABDsv16i8_VABDsv4i32_VABDsv8i16_VABDuv16i8_VABDuv4i32_VABDuv8i16_VMAXsv16i8_VMAXsv4i32_VMAXsv8i16_VMAXuv16i8_VMAXuv4i32_VMAXuv8i16_VMINsv16i8_VMINsv4i32_VMINsv8i16_VMINuv16i8_VMINuv4i32_VMINuv8i16 = 524, VABDsv2i32_VABDsv4i16_VABDsv8i8_VABDuv2i32_VABDuv4i16_VABDuv8i8_VMAXsv2i32_VMAXsv4i16_VMAXsv8i8_VMAXuv2i32_VMAXuv4i16_VMAXuv8i8_VMINsv2i32_VMINsv4i16_VMINsv8i8_VMINuv2i32_VMINuv4i16_VMINuv8i8_VPMAXs16_VPMAXs32_VPMAXs8_VPMAXu16_VPMAXu32_VPMAXu8_VPMINs16_VPMINs32_VPMINs8_VPMINu16_VPMINu32_VPMINu8 = 525, VPADDf_VPMAXf_VPMAXh_VPMINf_VPMINh = 526, VADDD_VSUBD = 527, VRECPSfd_VRECPShd_VRSQRTSfd_VRSQRTShd = 528, VRECPSfq_VRECPShq_VRSQRTSfq_VRSQRTShq = 529, VMULS_VNMULS = 530, VMULfd = 531, VMULfq = 532, VMULpd_VMULslhd_VMULslv4i16_VMULv4i16_VMULv8i8_VQDMULHslv4i16_VQDMULHv4i16_VQRDMULHslv4i16_VQRDMULHv4i16_VMULLp8_VMULLslsv2i32_VMULLslsv4i16_VMULLsluv2i32_VMULLsluv4i16_VMULLsv4i32_VMULLsv8i16_VMULLuv4i32_VMULLuv8i16_VQDMULLslv2i32_VQDMULLslv4i16_VQDMULLv4i32 = 533, VMULpq_VMULslhq_VMULslv8i16_VMULv16i8_VMULv8i16_VQDMULHslv8i16_VQDMULHv8i16_VQRDMULHslv8i16_VQRDMULHv8i16 = 534, VMULslfd = 535, VMULslfq = 536, VMULslv2i32_VMULv2i32_VQDMULHslv2i32_VQDMULHv2i32_VQRDMULHslv2i32_VQRDMULHv2i32_VMULLsv2i64_VMULLuv2i64_VQDMULLv2i64 = 537, VMULslv4i32_VMULv4i32_VQDMULHslv4i32_VQDMULHv4i32_VQRDMULHslv4i32_VQRDMULHv4i32 = 538, VMULLp64 = 539, VMLAD_VMLSD_VNMLAD_VNMLSD = 540, VMLAH_VMLSH_VNMLAH_VNMLSH = 541, VMLALslsv2i32_VMLALsluv2i32_VMLALsv2i64_VMLALuv2i64_VMLAslv2i32_VMLAv2i32_VMLSLslsv2i32_VMLSLsluv2i32_VMLSLsv2i64_VMLSLuv2i64_VMLSslv2i32_VMLSv2i32_VQDMLALslv2i32_VQDMLALv2i64_VQDMLSLslv2i32_VQDMLSLv2i64 = 542, VMLALslsv4i16_VMLALsluv4i16_VMLALsv4i32_VMLALsv8i16_VMLALuv4i32_VMLALuv8i16_VMLAslv4i16_VMLAv4i16_VMLAv8i8_VMLSLslsv4i16_VMLSLsluv4i16_VMLSLsv4i32_VMLSLsv8i16_VMLSLuv4i32_VMLSLuv8i16_VMLSslv4i16_VMLSv4i16_VMLSv8i8_VQDMLALslv4i16_VQDMLALv4i32_VQDMLSLslv4i16_VQDMLSLv4i32 = 543, VMLAS_VMLSS_VNMLAS_VNMLSS = 544, VMLAfd_VMLAhd_VMLAslfd_VMLAslhd_VMLSfd_VMLShd_VMLSslfd_VMLSslhd = 545, VMLAfq_VMLAhq_VMLAslfq_VMLAslhq_VMLSfq_VMLShq_VMLSslfq_VMLSslhq = 546, VMLAslv4i32_VMLAv4i32_VMLSslv4i32_VMLSv4i32 = 547, VMLAslv8i16_VMLAv16i8_VMLAv8i16_VMLSslv8i16_VMLSv16i8_VMLSv8i16 = 548, VFMAD_VFMSD_VFNMAD_VFNMSD = 549, VFMAS_VFMSS_VFNMAS_VFNMSS = 550, VFNMAH_VFNMSH = 551, VFMAfd_VFMSfd = 552, VFMAfq_VFMSfq = 553, VCVTANSDf_VCVTANSDh_VCVTANSQf_VCVTANSQh_VCVTANUDf_VCVTANUDh_VCVTANUQf_VCVTANUQh_VCVTASD_VCVTASH_VCVTASS_VCVTAUD_VCVTAUH_VCVTAUS_VCVTBDH_VCVTMNSDf_VCVTMNSDh_VCVTMNSQf_VCVTMNSQh_VCVTMNUDf_VCVTMNUDh_VCVTMNUQf_VCVTMNUQh_VCVTMSD_VCVTMSH_VCVTMSS_VCVTMUD_VCVTMUH_VCVTMUS_VCVTNNSDf_VCVTNNSDh_VCVTNNSQf_VCVTNNSQh_VCVTNNUDf_VCVTNNUDh_VCVTNNUQf_VCVTNNUQh_VCVTNSD_VCVTNSH_VCVTNSS_VCVTNUD_VCVTNUH_VCVTNUS_VCVTPNSDf_VCVTPNSDh_VCVTPNSQf_VCVTPNSQh_VCVTPNUDf_VCVTPNUDh_VCVTPNUQf_VCVTPNUQh_VCVTPSD_VCVTPSH_VCVTPSS_VCVTPUD_VCVTPUH_VCVTPUS_VCVTTDH_VCVTTHD = 554, VCVTBHD = 555, VCVTBHS_VCVTTHS = 556, VCVTBSH_VCVTTSH = 557, VCVTDS = 558, VCVTSD = 559, VCVTf2h_VCVTf2sq_VCVTf2uq_VCVTf2xsq_VCVTf2xuq_VCVTh2f_VCVTh2sq_VCVTh2uq_VCVTh2xsq_VCVTh2xuq_VCVTs2fq_VCVTs2hq_VCVTu2fq_VCVTu2hq_VCVTxs2fq_VCVTxs2hq_VCVTxu2fq_VCVTxu2hq = 560, VCVTf2sd_VCVTf2ud_VCVTf2xsd_VCVTf2xud_VCVTh2sd_VCVTh2ud_VCVTh2xsd_VCVTh2xud_VCVTs2fd_VCVTs2hd_VCVTu2fd_VCVTu2hd_VCVTxs2fd_VCVTxs2hd_VCVTxu2fd_VCVTxu2hd = 561, VSITOD_VUITOD = 562, VSITOH_VUITOH = 563, VSITOS_VUITOS = 564, VTOSHD_VTOSIRD_VTOSIZD_VTOSLD_VTOUHD_VTOUIRD_VTOUIZD_VTOULD = 565, VTOSHH_VTOSIRH_VTOSIZH_VTOSLH_VTOUHH_VTOUIRH_VTOUIZH_VTOULH = 566, VTOSHS_VTOSIRS_VTOSIZS_VTOSLS_VTOUHS_VTOUIRS_VTOUIZS_VTOULS = 567, VMOVv16i8_VMOVv1i64_VMOVv2f32_VMOVv2i32_VMOVv2i64_VMOVv4f32_VMOVv4i16_VMOVv4i32_VMOVv8i16_VMOVv8i8_VMVNv2i32_VMVNv4i16_VMVNv4i32_VMVNv8i16 = 568, VMOVD_VMOVDcc_FCONSTD = 569, VMOVS_VMOVScc_FCONSTS = 570, VMVNd_VMVNq = 571, VMOVNv2i32_VMOVNv4i16_VMOVNv8i8 = 572, VMOVLsv2i64_VMOVLsv4i32_VMOVLsv8i16_VMOVLuv2i64_VMOVLuv4i32_VMOVLuv8i16 = 573, VQMOVNsuv2i32_VQMOVNsuv4i16_VQMOVNsuv8i8_VQMOVNsv2i32_VQMOVNsv4i16_VQMOVNsv8i8_VQMOVNuv2i32_VQMOVNuv4i16_VQMOVNuv8i8 = 574, VDUPLN16d_VDUPLN32d_VDUPLN8d = 575, VDUPLN16q_VDUPLN32q_VDUPLN8q = 576, VDUP16d_VDUP16q_VDUP32d_VDUP32q_VDUP8d_VDUP8q = 577, VMOVRS = 578, VMOVSR = 579, VSETLNi16_VSETLNi32_VSETLNi8 = 580, VMOVRRD_VMOVRRS = 581, VMOVDRR = 582, VMOVSRR = 583, VGETLNi32_VGETLNu16_VGETLNu8 = 584, VGETLNs16_VGETLNs8 = 585, VMRS_VMRS_FPCXTNS_VMRS_FPCXTS_VMRS_FPEXC_VMRS_FPINST_VMRS_FPINST2_VMRS_FPSCR_NZCVQC_VMRS_FPSID_VMRS_MVFR0_VMRS_MVFR1_VMRS_MVFR2_VMRS_P0_VMRS_VPR = 586, VMSR_VMSR_FPCXTNS_VMSR_FPCXTS_VMSR_FPEXC_VMSR_FPINST_VMSR_FPINST2_VMSR_FPSCR_NZCVQC_VMSR_FPSID_VMSR_P0_VMSR_VPR = 587, FMSTAT = 588, VLDRD = 589, VLDRS = 590, VSTRD = 591, VSTRS = 592, VLDMQIA = 593, VSTMQIA = 594, VLDMDIA_VLDMSIA = 595, VLDMDDB_UPD_VLDMDIA_UPD_VLDMSDB_UPD_VLDMSIA_UPD = 596, VSTMDIA_VSTMSIA = 597, VSTMDDB_UPD_VSTMDIA_UPD_VSTMSDB_UPD_VSTMSIA_UPD = 598, VLD1d16_VLD1d32_VLD1d64_VLD1d8 = 599, VLD1q16_VLD1q32_VLD1q64_VLD1q8 = 600, VLD1d16wb_fixed_VLD1d16wb_register_VLD1d32wb_fixed_VLD1d32wb_register_VLD1d64wb_fixed_VLD1d64wb_register_VLD1d8wb_fixed_VLD1d8wb_register = 601, VLD1q16wb_fixed_VLD1q16wb_register_VLD1q32wb_fixed_VLD1q32wb_register_VLD1q64wb_fixed_VLD1q64wb_register_VLD1q8wb_fixed_VLD1q8wb_register = 602, VLD1d16T_VLD1d32T_VLD1d64T_VLD1d8T_VLD1d64TPseudo_VLD1d64TPseudoWB_fixed_VLD1d64TPseudoWB_register = 603, VLD1d16Twb_fixed_VLD1d16Twb_register_VLD1d32Twb_fixed_VLD1d32Twb_register_VLD1d64Twb_fixed_VLD1d64Twb_register_VLD1d8Twb_fixed_VLD1d8Twb_register = 604, VLD1d16Q_VLD1d32Q_VLD1d64Q_VLD1d8Q_VLD1d64QPseudo_VLD1d64QPseudoWB_fixed_VLD1d64QPseudoWB_register = 605, VLD1d16Qwb_fixed_VLD1d16Qwb_register_VLD1d32Qwb_fixed_VLD1d32Qwb_register_VLD1d64Qwb_fixed_VLD1d64Qwb_register_VLD1d8Qwb_fixed_VLD1d8Qwb_register = 606, VLD2b16_VLD2b32_VLD2b8_VLD2d16_VLD2d32_VLD2d8 = 607, VLD2q16_VLD2q32_VLD2q8_VLD2q16Pseudo_VLD2q32Pseudo_VLD2q8Pseudo = 608, VLD2b16wb_fixed_VLD2b16wb_register_VLD2b32wb_fixed_VLD2b32wb_register_VLD2b8wb_fixed_VLD2b8wb_register_VLD2d16wb_fixed_VLD2d16wb_register_VLD2d32wb_fixed_VLD2d32wb_register_VLD2d8wb_fixed_VLD2d8wb_register = 609, VLD2q16wb_fixed_VLD2q16wb_register_VLD2q32wb_fixed_VLD2q32wb_register_VLD2q8wb_fixed_VLD2q8wb_register_VLD2q16PseudoWB_fixed_VLD2q16PseudoWB_register_VLD2q32PseudoWB_fixed_VLD2q32PseudoWB_register_VLD2q8PseudoWB_fixed_VLD2q8PseudoWB_register = 610, VLD3d16_VLD3d32_VLD3d8_VLD3q16_VLD3q32_VLD3q8 = 611, VLD3d16Pseudo_VLD3d32Pseudo_VLD3d8Pseudo_VLD3q16oddPseudo_VLD3q32oddPseudo_VLD3q8oddPseudo = 612, VLD3d16_UPD_VLD3d32_UPD_VLD3d8_UPD_VLD3q16_UPD_VLD3q32_UPD_VLD3q8_UPD = 613, VLD3d16Pseudo_UPD_VLD3d32Pseudo_UPD_VLD3d8Pseudo_UPD_VLD3q16Pseudo_UPD_VLD3q16oddPseudo_UPD_VLD3q32Pseudo_UPD_VLD3q32oddPseudo_UPD_VLD3q8Pseudo_UPD_VLD3q8oddPseudo_UPD = 614, VLD4d16_VLD4d32_VLD4d8_VLD4q16_VLD4q32_VLD4q8 = 615, VLD4d16Pseudo_VLD4d32Pseudo_VLD4d8Pseudo_VLD4q16oddPseudo_VLD4q32oddPseudo_VLD4q8oddPseudo = 616, VLD4d16_UPD_VLD4d32_UPD_VLD4d8_UPD_VLD4q16_UPD_VLD4q32_UPD_VLD4q8_UPD = 617, VLD4d16Pseudo_UPD_VLD4d32Pseudo_UPD_VLD4d8Pseudo_UPD_VLD4q16Pseudo_UPD_VLD4q16oddPseudo_UPD_VLD4q32Pseudo_UPD_VLD4q32oddPseudo_UPD_VLD4q8Pseudo_UPD_VLD4q8oddPseudo_UPD = 618, VLD1DUPd16_VLD1DUPd32_VLD1DUPd8 = 619, VLD1DUPq16_VLD1DUPq32_VLD1DUPq8 = 620, VLD1LNd16_VLD1LNd8 = 621, VLD1LNd32_VLD1LNq16Pseudo_VLD1LNq32Pseudo_VLD1LNq8Pseudo = 622, VLD1DUPd16wb_fixed_VLD1DUPd16wb_register_VLD1DUPd32wb_fixed_VLD1DUPd32wb_register_VLD1DUPd8wb_fixed_VLD1DUPd8wb_register_VLD1DUPq16wb_register_VLD1DUPq32wb_register_VLD1DUPq8wb_register = 623, VLD1DUPq16wb_fixed_VLD1DUPq32wb_fixed_VLD1DUPq8wb_fixed = 624, VLD1LNd16_UPD_VLD1LNd32_UPD_VLD1LNd8_UPD_VLD1LNq16Pseudo_UPD_VLD1LNq32Pseudo_UPD_VLD1LNq8Pseudo_UPD = 625, VLD2DUPd16_VLD2DUPd16x2_VLD2DUPd32_VLD2DUPd32x2_VLD2DUPd8_VLD2DUPd8x2 = 626, VLD2LNd16_VLD2LNd32_VLD2LNd8_VLD2LNq16_VLD2LNq32_VLD2LNd16Pseudo_VLD2LNd32Pseudo_VLD2LNd8Pseudo_VLD2LNq16Pseudo_VLD2LNq32Pseudo = 627, VLD2LNd16_UPD_VLD2LNd32_UPD_VLD2LNd8_UPD_VLD2LNq16_UPD_VLD2LNq32_UPD = 628, VLD2DUPd16wb_fixed_VLD2DUPd16wb_register_VLD2DUPd16x2wb_fixed_VLD2DUPd16x2wb_register_VLD2DUPd32wb_fixed_VLD2DUPd32wb_register_VLD2DUPd32x2wb_fixed_VLD2DUPd32x2wb_register_VLD2DUPd8wb_fixed_VLD2DUPd8wb_register_VLD2DUPd8x2wb_fixed_VLD2DUPd8x2wb_register = 629, VLD2LNd16Pseudo_UPD_VLD2LNd32Pseudo_UPD_VLD2LNd8Pseudo_UPD_VLD2LNq16Pseudo_UPD_VLD2LNq32Pseudo_UPD = 630, VLD3DUPd16_VLD3DUPd32_VLD3DUPd8_VLD3DUPq16_VLD3DUPq32_VLD3DUPq8_VLD3DUPd16Pseudo_VLD3DUPd32Pseudo_VLD3DUPd8Pseudo = 631, VLD3LNd16_VLD3LNd32_VLD3LNd8_VLD3LNq16_VLD3LNq32_VLD3LNd16Pseudo_VLD3LNd32Pseudo_VLD3LNd8Pseudo_VLD3LNq16Pseudo_VLD3LNq32Pseudo = 632, VLD3DUPd16_UPD_VLD3DUPd32_UPD_VLD3DUPd8_UPD_VLD3DUPq16_UPD_VLD3DUPq32_UPD_VLD3DUPq8_UPD = 633, VLD3LNd16_UPD_VLD3LNd32_UPD_VLD3LNd8_UPD_VLD3LNq16_UPD_VLD3LNq32_UPD = 634, VLD3DUPd16Pseudo_UPD_VLD3DUPd32Pseudo_UPD_VLD3DUPd8Pseudo_UPD = 635, VLD3LNd16Pseudo_UPD_VLD3LNd32Pseudo_UPD_VLD3LNd8Pseudo_UPD_VLD3LNq16Pseudo_UPD_VLD3LNq32Pseudo_UPD = 636, VLD4DUPd16_VLD4DUPd32_VLD4DUPd8_VLD4DUPq16_VLD4DUPq32_VLD4DUPq8 = 637, VLD4LNd16_VLD4LNd32_VLD4LNd8_VLD4LNq16_VLD4LNq32_VLD4LNd16Pseudo_VLD4LNd32Pseudo_VLD4LNd8Pseudo_VLD4LNq16Pseudo_VLD4LNq32Pseudo = 638, VLD4DUPd16Pseudo_VLD4DUPd32Pseudo_VLD4DUPd8Pseudo = 639, VLD4DUPd16_UPD_VLD4DUPd32_UPD_VLD4DUPd8_UPD_VLD4DUPq16_UPD_VLD4DUPq32_UPD_VLD4DUPq8_UPD = 640, VLD4LNd16_UPD_VLD4LNd32_UPD_VLD4LNd8_UPD_VLD4LNq16_UPD_VLD4LNq32_UPD = 641, VLD4DUPd16Pseudo_UPD_VLD4DUPd32Pseudo_UPD_VLD4DUPd8Pseudo_UPD = 642, VLD4LNd16Pseudo_UPD_VLD4LNd32Pseudo_UPD_VLD4LNd8Pseudo_UPD_VLD4LNq16Pseudo_UPD_VLD4LNq32Pseudo_UPD = 643, VST1d16_VST1d32_VST1d64_VST1d8 = 644, VST1q16_VST1q32_VST1q64_VST1q8 = 645, VST1d16wb_fixed_VST1d16wb_register_VST1d32wb_fixed_VST1d32wb_register_VST1d64wb_fixed_VST1d64wb_register_VST1d8wb_fixed_VST1d8wb_register = 646, VST1q16wb_fixed_VST1q16wb_register_VST1q32wb_fixed_VST1q32wb_register_VST1q64wb_fixed_VST1q64wb_register_VST1q8wb_fixed_VST1q8wb_register = 647, VST1d16T_VST1d32T_VST1d64T_VST1d8T_VST1d64TPseudo = 648, VST1d16Twb_fixed_VST1d16Twb_register_VST1d32Twb_fixed_VST1d32Twb_register_VST1d64Twb_fixed_VST1d64Twb_register_VST1d8Twb_fixed_VST1d8Twb_register = 649, VST1d64TPseudoWB_fixed_VST1d64TPseudoWB_register = 650, VST1d16Q_VST1d16QPseudo_VST1d32Q_VST1d32QPseudo_VST1d64Q_VST1d64QPseudo_VST1d8Q_VST1d8QPseudo = 651, VST1d16QPseudoWB_fixed_VST1d16QPseudoWB_register_VST1d32QPseudoWB_fixed_VST1d32QPseudoWB_register_VST1d64QPseudoWB_fixed_VST1d64QPseudoWB_register_VST1d8QPseudoWB_fixed_VST1d8QPseudoWB_register = 652, VST1d16Qwb_fixed_VST1d16Qwb_register_VST1d32Qwb_fixed_VST1d32Qwb_register_VST1d64Qwb_fixed_VST1d64Qwb_register_VST1d8Qwb_fixed_VST1d8Qwb_register = 653, VST2b16_VST2b32_VST2b8 = 654, VST2d16_VST2d32_VST2d8 = 655, VST2b16wb_fixed_VST2b16wb_register_VST2b32wb_fixed_VST2b32wb_register_VST2b8wb_fixed_VST2b8wb_register_VST2d16wb_fixed_VST2d16wb_register_VST2d32wb_fixed_VST2d32wb_register_VST2d8wb_fixed_VST2d8wb_register = 656, VST2q16_VST2q32_VST2q8_VST2q16Pseudo_VST2q32Pseudo_VST2q8Pseudo = 657, VST2q16wb_fixed_VST2q16wb_register_VST2q32wb_fixed_VST2q32wb_register_VST2q8wb_fixed_VST2q8wb_register = 658, VST2q16PseudoWB_fixed_VST2q16PseudoWB_register_VST2q32PseudoWB_fixed_VST2q32PseudoWB_register_VST2q8PseudoWB_fixed_VST2q8PseudoWB_register = 659, VST3d16_VST3d32_VST3d8_VST3q16_VST3q32_VST3q8_VST3d16Pseudo_VST3d32Pseudo_VST3d8Pseudo_VST3q16oddPseudo_VST3q32oddPseudo_VST3q8oddPseudo = 660, VST3d16_UPD_VST3d32_UPD_VST3d8_UPD_VST3q16_UPD_VST3q32_UPD_VST3q8_UPD_VST3d16Pseudo_UPD_VST3d32Pseudo_UPD_VST3d8Pseudo_UPD_VST3q16Pseudo_UPD_VST3q16oddPseudo_UPD_VST3q32Pseudo_UPD_VST3q32oddPseudo_UPD_VST3q8Pseudo_UPD_VST3q8oddPseudo_UPD = 661, VST4d16_VST4d32_VST4d8_VST4q16_VST4q32_VST4q8_VST4d16Pseudo_VST4d32Pseudo_VST4d8Pseudo_VST4q16oddPseudo_VST4q32oddPseudo_VST4q8oddPseudo = 662, VST4d16_UPD_VST4d32_UPD_VST4d8_UPD_VST4q16_UPD_VST4q32_UPD_VST4q8_UPD_VST4d16Pseudo_UPD_VST4d32Pseudo_UPD_VST4d8Pseudo_UPD_VST4q16Pseudo_UPD_VST4q16oddPseudo_UPD_VST4q32Pseudo_UPD_VST4q32oddPseudo_UPD_VST4q8Pseudo_UPD_VST4q8oddPseudo_UPD = 663, VST1LNd16_VST1LNd32_VST1LNd8_VST1LNq16Pseudo_VST1LNq32Pseudo_VST1LNq8Pseudo = 664, VST1LNd16_UPD_VST1LNd32_UPD_VST1LNd8_UPD_VST1LNq16Pseudo_UPD_VST1LNq32Pseudo_UPD_VST1LNq8Pseudo_UPD = 665, VST2LNd16_VST2LNd32_VST2LNd8_VST2LNq16_VST2LNq32_VST2LNd16Pseudo_VST2LNd32Pseudo_VST2LNd8Pseudo_VST2LNq16Pseudo_VST2LNq32Pseudo = 666, VST2LNd16_UPD_VST2LNd32_UPD_VST2LNd8_UPD_VST2LNq16_UPD_VST2LNq32_UPD = 667, VST2LNd16Pseudo_UPD_VST2LNd32Pseudo_UPD_VST2LNd8Pseudo_UPD_VST2LNq16Pseudo_UPD_VST2LNq32Pseudo_UPD = 668, VST3LNd16_VST3LNd32_VST3LNd8_VST3LNq16_VST3LNq32_VST3LNd16Pseudo_VST3LNd32Pseudo_VST3LNd8Pseudo = 669, VST3LNq16Pseudo_VST3LNq32Pseudo = 670, VST3LNd16_UPD_VST3LNd32_UPD_VST3LNd8_UPD_VST3LNq16_UPD_VST3LNq32_UPD = 671, VST3LNd16Pseudo_UPD_VST3LNd32Pseudo_UPD_VST3LNd8Pseudo_UPD_VST3LNq16Pseudo_UPD_VST3LNq32Pseudo_UPD = 672, VST4LNd16_VST4LNd32_VST4LNd8_VST4LNq16_VST4LNq32_VST4LNd16Pseudo_VST4LNd32Pseudo_VST4LNd8Pseudo_VST4LNq16Pseudo_VST4LNq32Pseudo = 673, VST4LNd16_UPD_VST4LNd32_UPD_VST4LNd8_UPD_VST4LNq16_UPD_VST4LNq32_UPD = 674, VST4LNd16Pseudo_UPD_VST4LNd32Pseudo_UPD_VST4LNd8Pseudo_UPD_VST4LNq16Pseudo_UPD_VST4LNq32Pseudo_UPD = 675, VDIVS = 676, VSQRTS = 677, VDIVD = 678, VSQRTD = 679, ABS = 680, COPY = 681, t2MOVCCi_t2MOVCCi16 = 682, t2MOVi_t2MOVi16 = 683, t2ABS = 684, t2USAD8_t2USADA8 = 685, t2SDIV_t2UDIV = 686, t2LDREX_t2LDREXB_t2LDREXD_t2LDREXH_t2LDA_t2LDAB_t2LDAEX_t2LDAEXB_t2LDAEXD_t2LDAEXH_t2LDAH = 687, LDA_LDAB_LDAEX_LDAEXB_LDAEXD_LDAEXH_LDAH = 688, LDRBT_POST = 689, MOVsr = 690, t2MOVSsr_t2MOVsr = 691, t2MOVsra_glue_t2MOVsrl_glue = 692, MOVTi16_ga_pcrel_MOVTi16_t2MOVTi16_ga_pcrel_t2MOVTi16 = 693, ADDSri_ADCri_ADDri_RSBSri_RSBri_RSCri_SBCri_t2ADDSri_t2ADCri_t2ADDri_t2ADDri12_t2RSBSri_t2RSBri_t2SBCri = 694, CLZ_t2CLZ = 695, t2ANDri_t2BICri_t2EORri_t2ORRri = 696, t2MVNCCi = 697, t2MVNi = 698, t2MVNr = 699, t2MVNs = 700, ADDSrr_ADCrr_ADDrr_RSBrr_RSCrr_SBCrr_t2ADDSrr_t2ADCrr_t2ADDrr_t2SBCrr = 701, CRC32B_CRC32CB_CRC32CH_CRC32CW_CRC32H_CRC32W_t2CRC32B_t2CRC32CB_t2CRC32CH_t2CRC32CW_t2CRC32H_t2CRC32W = 702, t2ANDrr_t2BICrr_t2EORrr = 703, ADDSrsi_ADCrsi_ADDrsi_RSBrsi_RSCrsi_SBCrsi = 704, t2ADDSrs = 705, t2ADCrs_t2ADDrs_t2SBCrs = 706, t2ANDrs_t2BICrs_t2EORrs_t2ORRrs = 707, t2RSBrs = 708, ADDSrsr = 709, ADCrsr_ADDrsr_RSBrsr_RSCrsr_SBCrsr = 710, ADR = 711, MVNi = 712, MVNsi = 713, t2MOVSsi_t2MOVsi = 714, ASRi_RORi = 715, ASRr_RORr_LSRi_LSRr_LSLi_LSLr = 716, CMPri_CMNri = 717, CMPrr_CMNzrr = 718, CMPrsi_CMNzrsi = 719, CMPrsr_CMNzrsr = 720, t2LDC2L_OFFSET_t2LDC2L_OPTION_t2LDC2L_POST_t2LDC2L_PRE_t2LDC2_OFFSET_t2LDC2_OPTION_t2LDC2_POST_t2LDC2_PRE_t2LDCL_OFFSET_t2LDCL_OPTION_t2LDCL_POST_t2LDCL_PRE_t2LDC_OFFSET_t2LDC_OPTION_t2LDC_POST_t2LDC_PRE_RRXi = 721, RBIT_REV_REV16_REVSH = 722, RRX = 723, TSTri = 724, TSTrr = 725, TSTrsi = 726, TSTrsr = 727, MRS_MRSbanked_MRSsys = 728, MSR_MSRbanked_MSRi = 729, SRSDA_SRSDA_UPD_SRSDB_SRSDB_UPD_SRSIA_SRSIA_UPD_SRSIB_SRSIB_UPD_t2SRSDB_t2SRSDB_UPD_t2SRSIA_t2SRSIA_UPD_RFEDA_RFEDA_UPD_RFEDB_RFEDB_UPD_RFEIA_RFEIA_UPD_RFEIB_RFEIB_UPD_t2RFEDB_t2RFEDBW_t2RFEIA_t2RFEIAW = 730, t2STREX_t2STREXB_t2STREXD_t2STREXH = 731, STL_STLB_STLEX_STLEXB_STLEXD_STLEXH_STLH = 732, t2STL_t2STLB_t2STLEX_t2STLEXB_t2STLEXD_t2STLEXH_t2STLH = 733, VABDfd_VABDhd = 734, VABDfq_VABDhq = 735, VABSD = 736, VABSH = 737, VABSS = 738, VABShd = 739, VABShq = 740, VACGEfd_VACGEhd_VACGTfd_VACGThd = 741, VACGEfq_VACGEhq_VACGTfq_VACGThq = 742, VADDH_VSUBH = 743, VADDfd_VSUBfd = 744, VADDhd_VSUBhd = 745, VADDfq_VSUBfq = 746, VADDhq_VSUBhq = 747, VLDRH = 748, VLDR_FPCXTNS_off_VLDR_FPCXTNS_post_VLDR_FPCXTNS_pre_VLDR_FPCXTS_off_VLDR_FPCXTS_post_VLDR_FPCXTS_pre_VLDR_FPSCR_NZCVQC_off_VLDR_FPSCR_NZCVQC_post_VLDR_FPSCR_NZCVQC_pre_VLDR_FPSCR_off_VLDR_FPSCR_post_VLDR_FPSCR_pre_VLDR_P0_off_VLDR_P0_post_VLDR_P0_pre_VLDR_VPR_off_VLDR_VPR_post_VLDR_VPR_pre = 749, VSTRH = 750, VSTR_FPCXTNS_off_VSTR_FPCXTNS_post_VSTR_FPCXTNS_pre_VSTR_FPCXTS_off_VSTR_FPCXTS_post_VSTR_FPCXTS_pre_VSTR_FPSCR_NZCVQC_off_VSTR_FPSCR_NZCVQC_post_VSTR_FPSCR_NZCVQC_pre_VSTR_FPSCR_off_VSTR_FPSCR_post_VSTR_FPSCR_pre_VSTR_P0_off_VSTR_P0_post_VSTR_P0_pre_VSTR_VPR_off_VSTR_VPR_post_VSTR_VPR_pre = 751, VABAsv2i32_VABAsv4i16_VABAsv8i8_VABAuv2i32_VABAuv4i16_VABAuv8i8 = 752, VABDsv2i32_VABDsv4i16_VABDsv8i8_VABDuv2i32_VABDuv4i16_VABDuv8i8 = 753, VABDsv16i8_VABDsv4i32_VABDsv8i16_VABDuv16i8_VABDuv4i32_VABDuv8i16 = 754, VABDLsv4i32_VABDLsv8i16_VABDLuv4i32_VABDLuv8i16 = 755, VADDv1i64_VADDv2i32_VADDv4i16_VADDv8i8 = 756, VSUBv1i64_VSUBv2i32_VSUBv4i16_VSUBv8i8 = 757, VADDv16i8_VADDv2i64_VADDv4i32_VADDv8i16 = 758, VADDLsv2i64_VADDLsv4i32_VADDLsv8i16_VADDLuv2i64_VADDLuv4i32_VADDLuv8i16_VSUBLsv2i64_VSUBLsv4i32_VSUBLsv8i16_VSUBLuv2i64_VSUBLuv4i32_VSUBLuv8i16 = 759, VANDd_VBICd_VEORd = 760, VANDq_VBICq_VEORq = 761, VBICiv2i32_VBICiv4i16 = 762, VBICiv4i32_VBICiv8i16 = 763, VBIFd_VBITd_VBSLd_VBSPd = 764, VBIFq_VBITq_VBSLq_VBSPq = 765, VCEQv16i8_VCEQv4i32_VCEQv8i16_VCGEsv16i8_VCGEsv4i32_VCGEsv8i16_VCGEuv16i8_VCGEuv4i32_VCGEuv8i16_VCGTsv16i8_VCGTsv4i32_VCGTsv8i16_VCGTuv16i8_VCGTuv4i32_VCGTuv8i16 = 766, VCEQv2i32_VCEQv4i16_VCEQv8i8_VCGEsv2i32_VCGEsv4i16_VCGEsv8i8_VCGEuv2i32_VCGEuv4i16_VCGEuv8i8_VCGTsv2i32_VCGTsv4i16_VCGTsv8i8_VCGTuv2i32_VCGTuv4i16_VCGTuv8i8 = 767, VCLZv16i8_VCLZv4i32_VCLZv8i16_VCNTq = 768, VCLZv2i32_VCLZv4i16_VCLZv8i8_VCNTd = 769, VCMPEH_VCMPEZH_VCMPH_VCMPZH = 770, VDUP16d_VDUP32d_VDUP8d = 771, VSELEQD_VSELEQH_VSELEQS_VSELGED_VSELGEH_VSELGES_VSELGTD_VSELGTH_VSELGTS_VSELVSD_VSELVSH_VSELVSS = 772, VFMAhd_VFMShd = 773, VFMAhq_VFMShq = 774, VHADDsv2i32_VHADDsv4i16_VHADDsv8i8_VHADDuv2i32_VHADDuv4i16_VHADDuv8i8 = 775, VHADDsv16i8_VHADDsv4i32_VHADDsv8i16_VHADDuv16i8_VHADDuv4i32_VHADDuv8i16 = 776, VMAXsv16i8_VMAXsv4i32_VMAXsv8i16_VMAXuv16i8_VMAXuv4i32_VMAXuv8i16_VMINsv16i8_VMINsv4i32_VMINsv8i16_VMINuv16i8_VMINuv4i32_VMINuv8i16 = 777, VPMAXf_VPMAXh_VPMINf_VPMINh = 778, VNEGH = 779, VNEGhd = 780, VNEGhq = 781, VNEGs16d_VNEGs32d_VNEGs8d = 782, VNEGs16q_VNEGs32q_VNEGs8q = 783, VPADDi16_VPADDi32_VPADDi8 = 784, VPADALsv2i32_VPADALsv4i16_VPADALsv8i8_VPADALuv2i32_VPADALuv4i16_VPADALuv8i8 = 785, VPADDLsv16i8_VPADDLsv2i32_VPADDLsv4i16_VPADDLsv4i32_VPADDLsv8i16_VPADDLsv8i8_VPADDLuv16i8_VPADDLuv2i32_VPADDLuv4i16_VPADDLuv4i32_VPADDLuv8i16_VPADDLuv8i8 = 786, VQABSv2i32_VQABSv4i16_VQABSv8i8 = 787, VQABSv16i8_VQABSv4i32_VQABSv8i16 = 788, VQDMLALslv2i32_VQDMLALv2i64_VQDMLSLslv2i32_VQDMLSLv2i64 = 789, VQDMLALslv4i16_VQDMLALv4i32_VQDMLSLslv4i16_VQDMLSLv4i32 = 790, VQDMULHslv2i32_VQDMULHv2i32_VQDMULLv2i64_VQRDMULHslv2i32_VQRDMULHv2i32 = 791, VQDMULHslv4i16_VQDMULHv4i16_VQDMULLslv2i32_VQDMULLslv4i16_VQDMULLv4i32_VQRDMULHslv4i16_VQRDMULHv4i16 = 792, VQDMULHslv4i32_VQDMULHv4i32_VQRDMULHslv4i32_VQRDMULHv4i32 = 793, VQDMULHslv8i16_VQDMULHv8i16_VQRDMULHslv8i16_VQRDMULHv8i16 = 794, VQSHRNsv2i32_VQSHRNsv4i16_VQSHRNsv8i8_VQSHRNuv2i32_VQSHRNuv4i16_VQSHRNuv8i8 = 795, VRSHLsv16i8_VRSHLsv2i64_VRSHLsv4i32_VRSHLsv8i16_VRSHLuv16i8_VRSHLuv2i64_VRSHLuv4i32_VRSHLuv8i16 = 796, VRSHLsv1i64_VRSHLsv2i32_VRSHLsv4i16_VRSHLsv8i8_VRSHLuv1i64_VRSHLuv2i32_VRSHLuv4i16_VRSHLuv8i8_VRSHRsv16i8_VRSHRsv1i64_VRSHRsv2i32_VRSHRsv2i64_VRSHRsv4i16_VRSHRsv4i32_VRSHRsv8i16_VRSHRsv8i8_VRSHRuv16i8_VRSHRuv1i64_VRSHRuv2i32_VRSHRuv2i64_VRSHRuv4i16_VRSHRuv4i32_VRSHRuv8i16_VRSHRuv8i8 = 797, VRSHRNv2i32_VRSHRNv4i16_VRSHRNv8i8 = 798, VST1d16T_VST1d32T_VST1d64T_VST1d8T = 799, VST1d16Q_VST1d32Q_VST1d64Q_VST1d8Q = 800, VST1d64QPseudo = 801, VST1LNd16_VST1LNd32_VST1LNd8 = 802, VST1LNdAsm_16_VST1LNdAsm_32_VST1LNdAsm_8 = 803, VST1d64QPseudoWB_fixed_VST1d64QPseudoWB_register = 804, VST1LNd16_UPD_VST1LNd32_UPD_VST1LNd8_UPD = 805, VST1LNdWB_fixed_Asm_16_VST1LNdWB_fixed_Asm_32_VST1LNdWB_fixed_Asm_8_VST1LNdWB_register_Asm_16_VST1LNdWB_register_Asm_32_VST1LNdWB_register_Asm_8 = 806, VST2q16_VST2q32_VST2q8 = 807, VST2LNd16_VST2LNd32_VST2LNd8 = 808, VST2LNdAsm_16_VST2LNdAsm_32_VST2LNdAsm_8 = 809, VST2LNd16Pseudo_VST2LNd32Pseudo_VST2LNd8Pseudo = 810, VST2LNq16_VST2LNq32 = 811, VST2LNqAsm_16_VST2LNqAsm_32 = 812, VST2LNd16_UPD_VST2LNd32_UPD_VST2LNd8_UPD = 813, VST2LNdWB_fixed_Asm_16_VST2LNdWB_fixed_Asm_32_VST2LNdWB_fixed_Asm_8_VST2LNdWB_register_Asm_16_VST2LNdWB_register_Asm_32_VST2LNdWB_register_Asm_8 = 814, VST2LNd16Pseudo_UPD_VST2LNd32Pseudo_UPD_VST2LNd8Pseudo_UPD = 815, VST2LNqWB_fixed_Asm_16_VST2LNqWB_fixed_Asm_32_VST2LNqWB_register_Asm_16_VST2LNqWB_register_Asm_32 = 816, VST3d16_VST3d32_VST3d8_VST3q16_VST3q32_VST3q8 = 817, VST3dAsm_16_VST3dAsm_32_VST3dAsm_8_VST3qAsm_16_VST3qAsm_32_VST3qAsm_8 = 818, VST3d16Pseudo_VST3d32Pseudo_VST3d8Pseudo = 819, VST3LNd16_VST3LNd32_VST3LNd8 = 820, VST3LNdAsm_16_VST3LNdAsm_32_VST3LNdAsm_8 = 821, VST3LNd16Pseudo_VST3LNd32Pseudo_VST3LNd8Pseudo = 822, VST3LNqAsm_16_VST3LNqAsm_32 = 823, VST3d16_UPD_VST3d32_UPD_VST3d8_UPD_VST3q16_UPD_VST3q32_UPD_VST3q8_UPD = 824, VST3dWB_fixed_Asm_16_VST3dWB_fixed_Asm_32_VST3dWB_fixed_Asm_8_VST3dWB_register_Asm_16_VST3dWB_register_Asm_32_VST3dWB_register_Asm_8_VST3qWB_fixed_Asm_16_VST3qWB_fixed_Asm_32_VST3qWB_fixed_Asm_8_VST3qWB_register_Asm_16_VST3qWB_register_Asm_32_VST3qWB_register_Asm_8 = 825, VST3LNd16_UPD_VST3LNd32_UPD_VST3LNd8_UPD = 826, VST3LNdWB_fixed_Asm_16_VST3LNdWB_fixed_Asm_32_VST3LNdWB_fixed_Asm_8_VST3LNdWB_register_Asm_16_VST3LNdWB_register_Asm_32_VST3LNdWB_register_Asm_8 = 827, VST3LNd16Pseudo_UPD_VST3LNd32Pseudo_UPD_VST3LNd8Pseudo_UPD = 828, VST3LNqWB_fixed_Asm_16_VST3LNqWB_fixed_Asm_32_VST3LNqWB_register_Asm_16_VST3LNqWB_register_Asm_32 = 829, VST4d16_VST4d32_VST4d8_VST4q16_VST4q32_VST4q8 = 830, VST4dAsm_16_VST4dAsm_32_VST4dAsm_8_VST4qAsm_16_VST4qAsm_32_VST4qAsm_8 = 831, VST4d16Pseudo_VST4d32Pseudo_VST4d8Pseudo = 832, VST4LNd16_VST4LNd32_VST4LNd8 = 833, VST4LNdAsm_16_VST4LNdAsm_32_VST4LNdAsm_8 = 834, VST4LNd16Pseudo_VST4LNd32Pseudo_VST4LNd8Pseudo = 835, VST4LNq16_VST4LNq32 = 836, VST4LNqAsm_16_VST4LNqAsm_32 = 837, VST4d16_UPD_VST4d32_UPD_VST4d8_UPD_VST4q16_UPD_VST4q32_UPD_VST4q8_UPD = 838, VST4dWB_fixed_Asm_16_VST4dWB_fixed_Asm_32_VST4dWB_fixed_Asm_8_VST4dWB_register_Asm_16_VST4dWB_register_Asm_32_VST4dWB_register_Asm_8_VST4qWB_fixed_Asm_16_VST4qWB_fixed_Asm_32_VST4qWB_fixed_Asm_8_VST4qWB_register_Asm_16_VST4qWB_register_Asm_32_VST4qWB_register_Asm_8 = 839, VST4LNd16_UPD_VST4LNd32_UPD_VST4LNd8_UPD = 840, VST4LNdWB_fixed_Asm_16_VST4LNdWB_fixed_Asm_32_VST4LNdWB_fixed_Asm_8_VST4LNdWB_register_Asm_16_VST4LNdWB_register_Asm_32_VST4LNdWB_register_Asm_8 = 841, VST4LNd16Pseudo_UPD_VST4LNd32Pseudo_UPD_VST4LNd8Pseudo_UPD = 842, VST4LNqWB_fixed_Asm_16_VST4LNqWB_fixed_Asm_32_VST4LNqWB_register_Asm_16_VST4LNqWB_register_Asm_32 = 843, BKPT_tBKPT_CDP_CDP2_t2CDP_t2CDP2_CLREX_t2CLREX_CONSTPOOL_ENTRY_COPY_STRUCT_BYVAL_I32_CPS1p_CPS2p_CPS3p_t2CPS1p_t2CPS2p_t2CPS3p_DBG_t2DBG_DMB_t2DMB_DSB_t2DSB_ERET_HINT_t2HINT_tHINT_HLT_tHLT_HVC_ISB_t2ISB_SETEND_tSETEND_SETPAN_t2SETPAN_SMC_t2SMC_SPACE_SWP_SWPB_TRAP_TRAPNaCl_UDF_t2DCPS1_t2DCPS2_t2DCPS3_t2SG_t2TT_t2TTA_t2TTAT_t2TTT_tCPS_CMP_SWAP_16_CMP_SWAP_32_CMP_SWAP_64_CMP_SWAP_8 = 844, t2HVC_tTRAP_SVC_tSVC = 845, t2UDF_tUDF_t__brkdiv0 = 846, LDC2L_OFFSET_LDC2L_OPTION_LDC2L_POST_LDC2L_PRE_LDC2_OFFSET_LDC2_OPTION_LDC2_POST_LDC2_PRE_LDCL_OFFSET_LDCL_OPTION_LDCL_POST_LDCL_PRE_LDC_OFFSET_LDC_OPTION_LDC_POST_LDC_PRE_STC2L_OFFSET_STC2L_OPTION_STC2L_POST_STC2L_PRE_STC2_OFFSET_STC2_OPTION_STC2_POST_STC2_PRE_STCL_OFFSET_STCL_OPTION_STCL_POST_STCL_PRE_STC_OFFSET_STC_OPTION_STC_POST_STC_PRE_t2STC2L_OFFSET_t2STC2L_OPTION_t2STC2L_POST_t2STC2L_PRE_t2STC2_OFFSET_t2STC2_OPTION_t2STC2_POST_t2STC2_PRE_t2STCL_OFFSET_t2STCL_OPTION_t2STCL_POST_t2STCL_PRE_t2STC_OFFSET_t2STC_OPTION_t2STC_POST_t2STC_PRE_MEMCPY = 847, t2LDC2L_OFFSET_t2LDC2L_OPTION_t2LDC2L_POST_t2LDC2L_PRE_t2LDC2_OFFSET_t2LDC2_OPTION_t2LDC2_POST_t2LDC2_PRE_t2LDCL_OFFSET_t2LDCL_OPTION_t2LDCL_POST_t2LDCL_PRE_t2LDC_OFFSET_t2LDC_OPTION_t2LDC_POST_t2LDC_PRE = 848, LDREX_LDREXB_LDREXD_LDREXH = 849, MCR_MCR2_MCRR_MCRR2_t2MCR_t2MCR2_t2MCRR_t2MCRR2_MRC_MRC2_t2MRC_t2MRC2_MRRC_MRRC2_t2MRRC_t2MRRC2_t2MRS_AR_t2MRS_M_t2MRSbanked_t2MRSsys_AR_t2MSR_AR_t2MSR_M_t2MSRbanked = 850, FLDMXDB_UPD_FLDMXIA_FLDMXIA_UPD_FSTMXDB_UPD_FSTMXIA_FSTMXIA_UPD = 851, ADJCALLSTACKDOWN_tADJCALLSTACKDOWN_ADJCALLSTACKUP_tADJCALLSTACKUP_Int_eh_sjlj_dispatchsetup_Int_eh_sjlj_longjmp_Int_eh_sjlj_setjmp_Int_eh_sjlj_setjmp_nofp_Int_eh_sjlj_setup_dispatch_t2Int_eh_sjlj_setjmp_t2Int_eh_sjlj_setjmp_nofp_tInt_eh_sjlj_longjmp_tInt_eh_sjlj_setjmp_t2SUBS_PC_LR_JUMPTABLE_ADDRS_JUMPTABLE_INSTS_JUMPTABLE_TBB_JUMPTABLE_TBH_tInt_WIN_eh_sjlj_longjmp_VLD1LNdAsm_16_VLD1LNdAsm_32_VLD1LNdAsm_8_VLD1LNdWB_fixed_Asm_16_VLD1LNdWB_fixed_Asm_32_VLD1LNdWB_fixed_Asm_8_VLD1LNdWB_register_Asm_16_VLD1LNdWB_register_Asm_32_VLD1LNdWB_register_Asm_8_VLD2LNdAsm_16_VLD2LNdAsm_32_VLD2LNdAsm_8_VLD2LNdWB_fixed_Asm_16_VLD2LNdWB_fixed_Asm_32_VLD2LNdWB_fixed_Asm_8_VLD2LNdWB_register_Asm_16_VLD2LNdWB_register_Asm_32_VLD2LNdWB_register_Asm_8_VLD2LNqAsm_16_VLD2LNqAsm_32_VLD2LNqWB_fixed_Asm_16_VLD2LNqWB_fixed_Asm_32_VLD2LNqWB_register_Asm_16_VLD2LNqWB_register_Asm_32_VLD3DUPdAsm_16_VLD3DUPdAsm_32_VLD3DUPdAsm_8_VLD3DUPdWB_fixed_Asm_16_VLD3DUPdWB_fixed_Asm_32_VLD3DUPdWB_fixed_Asm_8_VLD3DUPdWB_register_Asm_16_VLD3DUPdWB_register_Asm_32_VLD3DUPdWB_register_Asm_8_VLD3DUPqAsm_16_VLD3DUPqAsm_32_VLD3DUPqAsm_8_VLD3DUPqWB_fixed_Asm_16_VLD3DUPqWB_fixed_Asm_32_VLD3DUPqWB_fixed_Asm_8_VLD3DUPqWB_register_Asm_16_VLD3DUPqWB_register_Asm_32_VLD3DUPqWB_register_Asm_8_VLD3LNdAsm_16_VLD3LNdAsm_32_VLD3LNdAsm_8_VLD3LNdWB_fixed_Asm_16_VLD3LNdWB_fixed_Asm_32_VLD3LNdWB_fixed_Asm_8_VLD3LNdWB_register_Asm_16_VLD3LNdWB_register_Asm_32_VLD3LNdWB_register_Asm_8_VLD3LNqAsm_16_VLD3LNqAsm_32_VLD3LNqWB_fixed_Asm_16_VLD3LNqWB_fixed_Asm_32_VLD3LNqWB_register_Asm_16_VLD3LNqWB_register_Asm_32_VLD3dAsm_16_VLD3dAsm_32_VLD3dAsm_8_VLD3dWB_fixed_Asm_16_VLD3dWB_fixed_Asm_32_VLD3dWB_fixed_Asm_8_VLD3dWB_register_Asm_16_VLD3dWB_register_Asm_32_VLD3dWB_register_Asm_8_VLD3qAsm_16_VLD3qAsm_32_VLD3qAsm_8_VLD3qWB_fixed_Asm_16_VLD3qWB_fixed_Asm_32_VLD3qWB_fixed_Asm_8_VLD3qWB_register_Asm_16_VLD3qWB_register_Asm_32_VLD3qWB_register_Asm_8_VLD4DUPdAsm_16_VLD4DUPdAsm_32_VLD4DUPdAsm_8_VLD4DUPdWB_fixed_Asm_16_VLD4DUPdWB_fixed_Asm_32_VLD4DUPdWB_fixed_Asm_8_VLD4DUPdWB_register_Asm_16_VLD4DUPdWB_register_Asm_32_VLD4DUPdWB_register_Asm_8_VLD4DUPqAsm_16_VLD4DUPqAsm_32_VLD4DUPqAsm_8_VLD4DUPqWB_fixed_Asm_16_VLD4DUPqWB_fixed_Asm_32_VLD4DUPqWB_fixed_Asm_8_VLD4DUPqWB_register_Asm_16_VLD4DUPqWB_register_Asm_32_VLD4DUPqWB_register_Asm_8_VLD4LNdAsm_16_VLD4LNdAsm_32_VLD4LNdAsm_8_VLD4LNdWB_fixed_Asm_16_VLD4LNdWB_fixed_Asm_32_VLD4LNdWB_fixed_Asm_8_VLD4LNdWB_register_Asm_16_VLD4LNdWB_register_Asm_32_VLD4LNdWB_register_Asm_8_VLD4LNqAsm_16_VLD4LNqAsm_32_VLD4LNqWB_fixed_Asm_16_VLD4LNqWB_fixed_Asm_32_VLD4LNqWB_register_Asm_16_VLD4LNqWB_register_Asm_32_VLD4dAsm_16_VLD4dAsm_32_VLD4dAsm_8_VLD4dWB_fixed_Asm_16_VLD4dWB_fixed_Asm_32_VLD4dWB_fixed_Asm_8_VLD4dWB_register_Asm_16_VLD4dWB_register_Asm_32_VLD4dWB_register_Asm_8_VLD4qAsm_16_VLD4qAsm_32_VLD4qAsm_8_VLD4qWB_fixed_Asm_16_VLD4qWB_fixed_Asm_32_VLD4qWB_fixed_Asm_8_VLD4qWB_register_Asm_16_VLD4qWB_register_Asm_32_VLD4qWB_register_Asm_8_WIN__CHKSTK_WIN__DBZCHK = 852, SUBS_PC_LR = 853, B_t2B_tB_BX_CALL_tBXNS_RET_tBX_CALL_tBX_RET_tBX_RET_vararg_BX_BX_RET_BX_pred_tBX_tBXNS_Bcc_t2Bcc_tBcc_TAILJMPd_TAILJMPr_TAILJMPr4_tTAILJMPd_tTAILJMPdND_tTAILJMPr_TCRETURNdi_TCRETURNri_TCRETURNrinotr12_tCBNZ_tCBZ = 854, BXJ = 855, tBfar = 856, BL_tBL_BL_pred_tBLXi = 857, BLXi = 858, TPsoft_tTPsoft = 859, BLX_noip_BLX_pred_noip_BLX_BLX_pred_tBLXr_noip_tBLXNSr_tBLXr = 860, BCCi64_BCCZi64 = 861, BR_JTadd_tBR_JTr_t2TBB_t2TBH = 862, BR_JTr_t2BR_JT_t2TBB_JT_t2TBH_JT_tBRIND = 863, t2BXJ = 864, BR_JTm_i12_BR_JTm_rs = 865, tADDframe = 866, MOVi16_ga_pcrel_MOVi_MOVi16_MOVCCi16_tMOVi8 = 867, MOVr_MOVr_TC_tMOVSr_tMOVr = 868, MVNCCi_MOVCCi = 869, BMOVPCB_CALL_BMOVPCRX_CALL = 870, MOVCCr = 871, tMOVCCr_pseudo_tMOVi32imm = 872, tMVN = 873, MOVCCsi = 874, t2ASRri_tASRri_t2LSRri_tLSRri_t2LSLri_tLSLri_t2RORri_t2RRX = 875, LSRi_LSLi = 876, t2MOVCCasr_t2MOVCClsl_t2MOVCClsr_t2MOVCCror = 877, t2MOVCCr = 878, t2MOVTi16_ga_pcrel_t2MOVTi16 = 879, t2MOVr = 880, tROR = 881, t2ASRrr_tASRrr_t2LSRrr_tLSRrr_t2LSLrr_tLSLrr_t2RORrr = 882, MOVPCRX_MOVPCLR = 883, tMUL = 884, SADD16_SADD8_SSUB16_SSUB8_UADD16_UADD8_USUB16_USUB8 = 885, t2SADD16_t2SADD8_t2SSUB16_t2SSUB8_t2UADD16_t2UADD8_t2USUB16_t2USUB8 = 886, SHADD16_SHADD8_SHSUB16_SHSUB8_UHADD16_UHADD8_UHSUB16_UHSUB8 = 887, t2SHADD16_t2SHADD8_t2SHSUB16_t2SHSUB8_t2UHADD16_t2UHADD8_t2UHSUB16_t2UHSUB8 = 888, QADD16_QADD8_QSUB16_QSUB8_UQADD16_UQADD8_UQSUB16_UQSUB8 = 889, t2QADD_t2QADD16_t2QADD8_t2UQADD16_t2UQADD8_t2QSUB_t2QSUB16_t2QSUB8_t2UQSUB16_t2UQSUB8 = 890, QASX_QSAX_UQASX_UQSAX = 891, t2QASX_t2QSAX_t2UQASX_t2UQSAX = 892, SSAT_SSAT16_USAT_USAT16 = 893, QADD_QSUB = 894, SBFX_UBFX = 895, t2SBFX_t2UBFX = 896, SXTB_SXTH_UXTB_UXTH = 897, t2SXTB_t2SXTH_t2UXTB_t2UXTH = 898, tSXTB_tSXTH_tUXTB_tUXTH = 899, SXTAB_SXTAH_UXTAB_UXTAH = 900, t2SXTAB_t2SXTAH_t2UXTAB_t2UXTAH = 901, LDRConstPool_t2LDRConstPool_tLDRConstPool = 902, PICLDRB_PICLDRH = 903, PICLDRSB_PICLDRSH = 904, tLDR_postidx = 905, tLDRBi_tLDRHi = 906, tLDRi_tLDRpci_tLDRspi = 907, t2LDRBpcrel_t2LDRHpcrel_t2LDRpcrel = 908, LDR_PRE_IMM = 909, LDRB_PRE_IMM = 910, t2LDRB_PRE_imm = 911, t2LDRB_PRE = 912, LDR_PRE_REG = 913, LDRB_PRE_REG = 914, LDRH_PRE = 915, LDRSB_PRE_LDRSH_PRE = 916, t2LDRH_PRE_imm_t2LDR_PRE_imm = 917, t2LDRSB_PRE_imm_t2LDRSH_PRE_imm = 918, t2LDRH_PRE = 919, t2LDRSB_PRE_t2LDRSH_PRE = 920, t2LDR_PRE = 921, LDRD_PRE = 922, t2LDRD_PRE = 923, LDRT_POST_IMM = 924, LDRBT_POST_IMM = 925, LDRHTi = 926, LDRSBTi_LDRSHTi = 927, t2LDRB_POST_imm = 928, t2LDRB_POST = 929, LDRH_POST = 930, LDRSB_POST_LDRSH_POST = 931, LDR_POST_REG = 932, LDRB_POST_REG = 933, LDRT_POST = 934, PLDi12_t2PLDi12_PLDWi12_t2PLDWi12_t2PLDWi8_t2PLDWs_t2PLDi8_t2PLDpci_t2PLDs_PLIi12_PLIrs_t2PLIi12_t2PLIi8_t2PLIpci_t2PLIs = 935, PLDrs_PLDWrs = 936, VLLDM_VLLDM_T2 = 937, STRBi12_PICSTRB_PICSTRH = 938, t2STRBT = 939, STR_PRE_IMM = 940, STRB_PRE_IMM = 941, STRBi_preidx_STRBr_preidx_STRi_preidx_STRr_preidx_STRH_preidx = 942, t2STRH_PRE_imm_t2STRB_PRE_imm_t2STR_PRE_imm = 943, STRH_PRE = 944, t2STRH_PRE_t2STR_PRE = 945, t2STRB_PRE = 946, t2STRD_PRE = 947, STR_PRE_REG = 948, STRB_PRE_REG = 949, STRD_PRE = 950, STRT_POST_IMM = 951, STRBT_POST_IMM = 952, t2STRB_POST_imm_t2STR_POST_imm = 953, t2STRB_POST = 954, STRBT_POST_REG_STRB_POST_REG = 955, STRBT_POST_STRT_POST = 956, VLSTM_VLSTM_T2 = 957, VCVTASD_VCVTASH_VCVTASS_VCVTAUD_VCVTAUH_VCVTAUS_VCVTMSD_VCVTMSH_VCVTMSS_VCVTMUD_VCVTMUH_VCVTMUS_VCVTNSD_VCVTNSH_VCVTNSS_VCVTNUD_VCVTNUH_VCVTNUS_VCVTPSD_VCVTPSH_VCVTPSS_VCVTPUD_VCVTPUH_VCVTPUS_VCVTBDH_VCVTTDH_VCVTTHD = 958, VTOSLS_VTOUHS_VTOULS = 959, VJCVT = 960, VRINTAD_VRINTAH_VRINTAS_VRINTMD_VRINTMH_VRINTMS_VRINTND_VRINTNH_VRINTNS_VRINTPD_VRINTPH_VRINTPS_VRINTRD_VRINTRH_VRINTRS_VRINTXD_VRINTXH_VRINTXS_VRINTZD_VRINTZH_VRINTZS = 961, VSQRTH = 962, VMAXsv2i32_VMAXsv4i16_VMAXsv8i8_VMAXuv2i32_VMAXuv4i16_VMAXuv8i8_VMINsv2i32_VMINsv4i16_VMINsv8i8_VMINuv2i32_VMINuv4i16_VMINuv8i8 = 963, VUDOTD_VUDOTDI_VSDOTD_VSDOTDI_VUDOTQ_VUDOTQI_VSDOTQ_VSDOTQI = 964, FCONSTD = 965, FCONSTH = 966, FCONSTS = 967, VMOVHcc_VMOVH = 968, VINSH = 969, VSTMSIA = 970, VSTMSDB_UPD_VSTMSIA_UPD = 971, VRHADDsv16i8_VRHADDsv4i32_VRHADDsv8i16_VRHADDuv16i8_VRHADDuv4i32_VRHADDuv8i16 = 972, VRHADDsv2i32_VRHADDsv4i16_VRHADDsv8i8_VRHADDuv2i32_VRHADDuv4i16_VRHADDuv8i8 = 973, VMVNv2i32_VMVNv4i16_VMVNv4i32_VMVNv8i16 = 974, VMULpd_VMULv4i16_VMULv8i8_VMULslv4i16 = 975, VMULv2i32_VMULslv2i32 = 976, VQDMULHslv2i32_VQDMULHv2i32_VQRDMULHslv2i32_VQRDMULHv2i32 = 977, VQDMULHslv4i16_VQDMULHv4i16_VQRDMULHslv4i16_VQRDMULHv4i16 = 978, VMULpq_VMULv16i8_VMULv8i16_VMULslv8i16 = 979, VMLAslv2i32_VMLAv2i32_VMLSslv2i32_VMLSv2i32 = 980, VMLAslv4i16_VMLAv4i16_VMLAv8i8_VMLSslv4i16_VMLSv4i16_VMLSv8i8 = 981, VQRDMLAHslv2i32_VQRDMLAHv2i32_VQRDMLSHslv2i32_VQRDMLSHv2i32 = 982, VQRDMLAHslv4i16_VQRDMLAHv4i16_VQRDMLSHslv4i16_VQRDMLSHv4i16 = 983, VQRDMLAHslv4i32_VQRDMLAHv4i32_VQRDMLSHslv4i32_VQRDMLSHv4i32 = 984, VQRDMLAHslv8i16_VQRDMLAHv8i16_VQRDMLSHslv8i16_VQRDMLSHv8i16 = 985, VMULLp8_VMULLslsv2i32_VMULLslsv4i16_VMULLsluv2i32_VMULLsluv4i16_VMULLsv4i32_VMULLsv8i16_VMULLuv4i32_VMULLuv8i16 = 986, VSHLiv16i8_VSHLiv1i64_VSHLiv2i32_VSHLiv2i64_VSHLiv4i16_VSHLiv4i32_VSHLiv8i16_VSHLiv8i8_VSHLLi16_VSHLLi32_VSHLLi8_VSHLLsv2i64_VSHLLsv4i32_VSHLLsv8i16_VSHLLuv2i64_VSHLLuv4i32_VSHLLuv8i16_VSHRsv16i8_VSHRsv1i64_VSHRsv2i32_VSHRsv2i64_VSHRsv4i16_VSHRsv4i32_VSHRsv8i16_VSHRsv8i8_VSHRuv16i8_VSHRuv1i64_VSHRuv2i32_VSHRuv2i64_VSHRuv4i16_VSHRuv4i32_VSHRuv8i16_VSHRuv8i8 = 987, VQSHLsiv16i8_VQSHLsiv1i64_VQSHLsiv2i32_VQSHLsiv2i64_VQSHLsiv4i16_VQSHLsiv4i32_VQSHLsiv8i16_VQSHLsiv8i8_VQSHLsuv16i8_VQSHLsuv1i64_VQSHLsuv2i32_VQSHLsuv2i64_VQSHLsuv4i16_VQSHLsuv4i32_VQSHLsuv8i16_VQSHLsuv8i8_VQSHLuiv16i8_VQSHLuiv1i64_VQSHLuiv2i32_VQSHLuiv2i64_VQSHLuiv4i16_VQSHLuiv4i32_VQSHLuiv8i16_VQSHLuiv8i8 = 988, VRSHRsv16i8_VRSHRsv1i64_VRSHRsv2i32_VRSHRsv2i64_VRSHRsv4i16_VRSHRsv4i32_VRSHRsv8i16_VRSHRsv8i8_VRSHRuv16i8_VRSHRuv1i64_VRSHRuv2i32_VRSHRuv2i64_VRSHRuv4i16_VRSHRuv4i32_VRSHRuv8i16_VRSHRuv8i8 = 989, VSLIv1i64_VSLIv2i32_VSLIv4i16_VSLIv8i8_VSRIv1i64_VSRIv2i32_VSRIv4i16_VSRIv8i8 = 990, VSLIv16i8_VSLIv2i64_VSLIv4i32_VSLIv8i16_VSRIv16i8_VSRIv2i64_VSRIv4i32_VSRIv8i16 = 991, VPADDh = 992, VCADDv2f32_VCADDv4f16_VCMLAv2f32_VCMLAv2f32_indexed_VCMLAv4f16_VCMLAv4f16_indexed = 993, VCADDv4f32_VCADDv8f16_VCMLAv4f32_VCMLAv4f32_indexed_VCMLAv8f16_VCMLAv8f16_indexed = 994, VCVTf2sd_VCVTf2ud_VCVTf2xsd_VCVTf2xud_VCVTs2fd_VCVTu2fd_VCVTxs2fd_VCVTxu2fd = 995, VCVTf2sq_VCVTf2uq_VCVTs2fq_VCVTu2fq_VCVTf2xsq_VCVTf2xuq_VCVTxs2fq_VCVTxu2fq = 996, NEON_VMAXNMNDf_NEON_VMAXNMNDh_NEON_VMAXNMNQf_NEON_VMAXNMNQh_VFP_VMAXNMD_VFP_VMAXNMH_VFP_VMAXNMS_NEON_VMINNMNDf_NEON_VMINNMNDh_NEON_VMINNMNQf_NEON_VMINNMNQh_VFP_VMINNMD_VFP_VMINNMH_VFP_VMINNMS = 997, VMULhd = 998, VMULhq = 999, VRINTANDf_VRINTANDh_VRINTANQf_VRINTANQh_VRINTMNDf_VRINTMNDh_VRINTMNQf_VRINTMNQh_VRINTNNDf_VRINTNNDh_VRINTNNQf_VRINTNNQh_VRINTPNDf_VRINTPNDh_VRINTPNQf_VRINTPNQh_VRINTXNDf_VRINTXNDh_VRINTXNQf_VRINTXNQh_VRINTZNDf_VRINTZNDh_VRINTZNQf_VRINTZNQh = 1000, VMOVD0_VMOVQ0 = 1001, VTRNd16_VTRNd32_VTRNd8 = 1002, VLD2d16_VLD2d32_VLD2d8 = 1003, VLD2d16wb_fixed_VLD2d16wb_register_VLD2d32wb_fixed_VLD2d32wb_register_VLD2d8wb_fixed_VLD2d8wb_register = 1004, VLD3LNd32_VLD3LNq32_VLD3LNd32Pseudo_VLD3LNq32Pseudo = 1005, VLD3LNd32_UPD_VLD3LNq32_UPD = 1006, VLD3LNd32Pseudo_UPD_VLD3LNq32Pseudo_UPD = 1007, VLD4LNd32_VLD4LNq32_VLD4LNd32Pseudo_VLD4LNq32Pseudo = 1008, VLD4LNd32_UPD_VLD4LNq32_UPD = 1009, VLD4LNd32Pseudo_UPD_VLD4LNq32Pseudo_UPD = 1010, AESD_AESE_AESIMC_AESMC = 1011, SHA1SU0 = 1012, SHA1H_SHA1SU1 = 1013, SHA1C_SHA1M_SHA1P = 1014, SHA256SU0 = 1015, SHA256H_SHA256H2_SHA256SU1 = 1016, t2LDMIA_RET = 1017, tLDMIA_UPD_t2LDMDB_UPD_t2LDMIA_UPD = 1018, t2LDMDB_t2LDMIA_tLDMIA = 1019, t2LDRB_OFFSET_imm_t2LDRH_OFFSET_imm_t2LDRSB_OFFSET_imm_t2LDRSH_OFFSET_imm = 1020, t2LDRConstPool_tLDRConstPool = 1021, t2LDRLIT_ga_pcrel = 1022, tLDRLIT_ga_abs = 1023, tLDRLIT_ga_pcrel = 1024, t2LDREX_t2LDREXB_t2LDREXD_t2LDREXH = 1025, t2STMDB_t2STMIA = 1026, t2STMDB_UPD_t2STMIA_UPD_tSTMIA_UPD = 1027, tMOVSr_tMOVr = 1028, tMOVi8 = 1029, t2MSR_AR_t2MSR_M_t2MSRbanked_t2MRS_AR_t2MRS_M_t2MRSbanked_t2MRSsys_AR = 1030, t2CLREX = 1031, t2SMLAL_t2SMLALBB_t2SMLALBT_t2SMLALD_t2SMLALDX_t2SMLALTB_t2SMLALTT_t2SMLSLD_t2SMLSLDX = 1032, t2REV_t2REV16_t2REVSH_tREV_tREV16_tREVSH = 1033, t2CDP_t2CDP2 = 1034, t2MCR_t2MCR2_t2MCRR_t2MCRR2_t2MRC_t2MRC2_t2MRRC_t2MRRC2 = 1035, t2STC2L_OFFSET_t2STC2L_OPTION_t2STC2L_POST_t2STC2L_PRE_t2STC2_OFFSET_t2STC2_OPTION_t2STC2_POST_t2STC2_PRE_t2STCL_OFFSET_t2STCL_OPTION_t2STCL_POST_t2STCL_PRE_t2STC_OFFSET_t2STC_OPTION_t2STC_POST_t2STC_PRE = 1036, tCPS_t2ISB_t2DSB_t2DMB_t2HINT_tHINT = 1037, t2UDF_tUDF = 1038, tBKPT_t2DBG = 1039, Int_eh_sjlj_dispatchsetup_Int_eh_sjlj_longjmp_Int_eh_sjlj_setjmp_Int_eh_sjlj_setjmp_nofp_Int_eh_sjlj_setup_dispatch_t2Int_eh_sjlj_setjmp_t2Int_eh_sjlj_setjmp_nofp_tInt_eh_sjlj_longjmp_tInt_eh_sjlj_setjmp_ADJCALLSTACKDOWN_ADJCALLSTACKUP_tADJCALLSTACKDOWN_tADJCALLSTACKUP = 1040, CMP_SWAP_16_CMP_SWAP_32_CMP_SWAP_64_CMP_SWAP_8 = 1041, JUMPTABLE_ADDRS_JUMPTABLE_INSTS_JUMPTABLE_TBB_JUMPTABLE_TBH = 1042, MEMCPY = 1043, VSETLNi32 = 1044, VGETLNi32 = 1045, VLD1LNdAsm_16_VLD1LNdAsm_32_VLD1LNdAsm_8_VLD1LNdWB_fixed_Asm_16_VLD1LNdWB_fixed_Asm_32_VLD1LNdWB_fixed_Asm_8_VLD1LNdWB_register_Asm_16_VLD1LNdWB_register_Asm_32_VLD1LNdWB_register_Asm_8_VLD2LNdAsm_16_VLD2LNdAsm_32_VLD2LNdAsm_8_VLD2LNdWB_fixed_Asm_16_VLD2LNdWB_fixed_Asm_32_VLD2LNdWB_fixed_Asm_8_VLD2LNdWB_register_Asm_16_VLD2LNdWB_register_Asm_32_VLD2LNdWB_register_Asm_8_VLD2LNqAsm_16_VLD2LNqAsm_32_VLD2LNqWB_fixed_Asm_16_VLD2LNqWB_fixed_Asm_32_VLD2LNqWB_register_Asm_16_VLD2LNqWB_register_Asm_32_VLD3DUPdAsm_16_VLD3DUPdAsm_32_VLD3DUPdAsm_8_VLD3DUPdWB_fixed_Asm_16_VLD3DUPdWB_fixed_Asm_32_VLD3DUPdWB_fixed_Asm_8_VLD3DUPdWB_register_Asm_16_VLD3DUPdWB_register_Asm_32_VLD3DUPdWB_register_Asm_8_VLD3DUPqAsm_16_VLD3DUPqAsm_32_VLD3DUPqAsm_8_VLD3DUPqWB_fixed_Asm_16_VLD3DUPqWB_fixed_Asm_32_VLD3DUPqWB_fixed_Asm_8_VLD3DUPqWB_register_Asm_16_VLD3DUPqWB_register_Asm_32_VLD3DUPqWB_register_Asm_8_VLD3LNdAsm_16_VLD3LNdAsm_32_VLD3LNdAsm_8_VLD3LNdWB_fixed_Asm_16_VLD3LNdWB_fixed_Asm_32_VLD3LNdWB_fixed_Asm_8_VLD3LNdWB_register_Asm_16_VLD3LNdWB_register_Asm_32_VLD3LNdWB_register_Asm_8_VLD3LNqAsm_16_VLD3LNqAsm_32_VLD3LNqWB_fixed_Asm_16_VLD3LNqWB_fixed_Asm_32_VLD3LNqWB_register_Asm_16_VLD3LNqWB_register_Asm_32_VLD3dAsm_16_VLD3dAsm_32_VLD3dAsm_8_VLD3dWB_fixed_Asm_16_VLD3dWB_fixed_Asm_32_VLD3dWB_fixed_Asm_8_VLD3dWB_register_Asm_16_VLD3dWB_register_Asm_32_VLD3dWB_register_Asm_8_VLD3qAsm_16_VLD3qAsm_32_VLD3qAsm_8_VLD3qWB_fixed_Asm_16_VLD3qWB_fixed_Asm_32_VLD3qWB_fixed_Asm_8_VLD3qWB_register_Asm_16_VLD3qWB_register_Asm_32_VLD3qWB_register_Asm_8_VLD4DUPdAsm_16_VLD4DUPdAsm_32_VLD4DUPdAsm_8_VLD4DUPdWB_fixed_Asm_16_VLD4DUPdWB_fixed_Asm_32_VLD4DUPdWB_fixed_Asm_8_VLD4DUPdWB_register_Asm_16_VLD4DUPdWB_register_Asm_32_VLD4DUPdWB_register_Asm_8_VLD4DUPqAsm_16_VLD4DUPqAsm_32_VLD4DUPqAsm_8_VLD4DUPqWB_fixed_Asm_16_VLD4DUPqWB_fixed_Asm_32_VLD4DUPqWB_fixed_Asm_8_VLD4DUPqWB_register_Asm_16_VLD4DUPqWB_register_Asm_32_VLD4DUPqWB_register_Asm_8_VLD4LNdAsm_16_VLD4LNdAsm_32_VLD4LNdAsm_8_VLD4LNdWB_fixed_Asm_16_VLD4LNdWB_fixed_Asm_32_VLD4LNdWB_fixed_Asm_8_VLD4LNdWB_register_Asm_16_VLD4LNdWB_register_Asm_32_VLD4LNdWB_register_Asm_8_VLD4LNqAsm_16_VLD4LNqAsm_32_VLD4LNqWB_fixed_Asm_16_VLD4LNqWB_fixed_Asm_32_VLD4LNqWB_register_Asm_16_VLD4LNqWB_register_Asm_32_VLD4dAsm_16_VLD4dAsm_32_VLD4dAsm_8_VLD4dWB_fixed_Asm_16_VLD4dWB_fixed_Asm_32_VLD4dWB_fixed_Asm_8_VLD4dWB_register_Asm_16_VLD4dWB_register_Asm_32_VLD4dWB_register_Asm_8_VLD4qAsm_16_VLD4qAsm_32_VLD4qAsm_8_VLD4qWB_fixed_Asm_16_VLD4qWB_fixed_Asm_32_VLD4qWB_fixed_Asm_8_VLD4qWB_register_Asm_16_VLD4qWB_register_Asm_32_VLD4qWB_register_Asm_8 = 1046, VLD1d16QPseudo_VLD1d16QPseudoWB_fixed_VLD1d16QPseudoWB_register_VLD1d32QPseudo_VLD1d32QPseudoWB_fixed_VLD1d32QPseudoWB_register_VLD1d8QPseudo_VLD1d8QPseudoWB_fixed_VLD1d8QPseudoWB_register_VLD1q16HighQPseudo_VLD1q16HighQPseudo_UPD_VLD1q16LowQPseudo_UPD_VLD1q32HighQPseudo_VLD1q32HighQPseudo_UPD_VLD1q32LowQPseudo_UPD_VLD1q64HighQPseudo_VLD1q64HighQPseudo_UPD_VLD1q64LowQPseudo_UPD_VLD1q8HighQPseudo_VLD1q8HighQPseudo_UPD_VLD1q8LowQPseudo_UPD = 1047, VLD1d16TPseudo_VLD1d16TPseudoWB_fixed_VLD1d16TPseudoWB_register_VLD1d32TPseudo_VLD1d32TPseudoWB_fixed_VLD1d32TPseudoWB_register_VLD1d8TPseudo_VLD1d8TPseudoWB_fixed_VLD1d8TPseudoWB_register_VLD1q16HighTPseudo_VLD1q16HighTPseudo_UPD_VLD1q16LowTPseudo_UPD_VLD1q32HighTPseudo_VLD1q32HighTPseudo_UPD_VLD1q32LowTPseudo_UPD_VLD1q64HighTPseudo_VLD1q64HighTPseudo_UPD_VLD1q64LowTPseudo_UPD_VLD1q8HighTPseudo_VLD1q8HighTPseudo_UPD_VLD1q8LowTPseudo_UPD = 1048, VLD2DUPq16EvenPseudo_VLD2DUPq16OddPseudo_VLD2DUPq16OddPseudoWB_fixed_VLD2DUPq16OddPseudoWB_register_VLD2DUPq32EvenPseudo_VLD2DUPq32OddPseudo_VLD2DUPq32OddPseudoWB_fixed_VLD2DUPq32OddPseudoWB_register_VLD2DUPq8EvenPseudo_VLD2DUPq8OddPseudo_VLD2DUPq8OddPseudoWB_fixed_VLD2DUPq8OddPseudoWB_register = 1049, VLD3DUPq16EvenPseudo_VLD3DUPq16OddPseudo_VLD3DUPq32EvenPseudo_VLD3DUPq32OddPseudo_VLD3DUPq8EvenPseudo_VLD3DUPq8OddPseudo = 1050, VLD3DUPq16OddPseudo_UPD_VLD3DUPq32OddPseudo_UPD_VLD3DUPq8OddPseudo_UPD = 1051, VLD4DUPq16EvenPseudo_VLD4DUPq16OddPseudo_VLD4DUPq32EvenPseudo_VLD4DUPq32OddPseudo_VLD4DUPq8EvenPseudo_VLD4DUPq8OddPseudo = 1052, VLD4DUPq16OddPseudo_UPD_VLD4DUPq32OddPseudo_UPD_VLD4DUPq8OddPseudo_UPD = 1053, VST1d16TPseudo_VST1d32TPseudo_VST1d8TPseudo_VST1q16HighTPseudo_VST1q16HighTPseudo_UPD_VST1q16LowTPseudo_UPD_VST1q32HighTPseudo_VST1q32HighTPseudo_UPD_VST1q32LowTPseudo_UPD_VST1q64HighTPseudo_VST1q64HighTPseudo_UPD_VST1q64LowTPseudo_UPD_VST1q8HighTPseudo_VST1q8HighTPseudo_UPD_VST1q8LowTPseudo_UPD = 1054, VST1d16TPseudoWB_fixed_VST1d16TPseudoWB_register_VST1d32TPseudoWB_fixed_VST1d32TPseudoWB_register_VST1d8TPseudoWB_fixed_VST1d8TPseudoWB_register = 1055, VST1q16HighQPseudo_VST1q16HighQPseudo_UPD_VST1q16LowQPseudo_UPD_VST1q32HighQPseudo_VST1q32HighQPseudo_UPD_VST1q32LowQPseudo_UPD_VST1q64HighQPseudo_VST1q64HighQPseudo_UPD_VST1q64LowQPseudo_UPD_VST1q8HighQPseudo_VST1q8HighQPseudo_UPD_VST1q8LowQPseudo_UPD = 1056, VMOVD0 = 1057, t2CPS1p_t2CPS2p_t2CPS3p_t2SG_t2TT_t2TTA_t2TTAT_t2TTT = 1058, t2DBG = 1059, t2SUBS_PC_LR = 1060, COPY_TO_REGCLASS = 1061, COPY_STRUCT_BYVAL_I32 = 1062, t2CSEL_t2CSINC_t2CSINV_t2CSNEG = 1063, t2ADDrr_t2ADDSrr_t2SBCrr = 1064, t2ASRri_t2LSLri_t2LSRri = 1065, t2ASRrr_t2LSLrr_t2LSRrr_t2RORrr = 1066, t2CMNzrr = 1067, t2CMPri = 1068, t2CMPrr = 1069, t2ORRrr = 1070, t2REV_t2REV16_t2REVSH = 1071, t2RSBri_t2RSBSri = 1072, t2RSBrr_t2SUBSrr_t2SUBrr = 1073, t2TEQrr_t2TSTrr = 1074, t2STRi12 = 1075, t2STRBi12_t2STRHi12 = 1076, t2STMIA_UPD_t2STMDB_UPD = 1077, t2SETPAN_tHLT_tSETEND = 1078, tADC_tADDhirr_tADDrSP_tADDrr_tADDspr_tPICADD_tSBC_tSUBrr = 1079, tADDrSPi_tADDspi_tADR_tRSB_tSUBspi = 1080, tAND_tBIC_tEOR_tORR = 1081, tASRri_tLSLri_tLSRri = 1082, tCBNZ_tCBZ = 1083, tCMNz_tCMPhir_tCMPr = 1084, tCMPi8 = 1085, tCPS_tHINT = 1086, tMOVSr = 1087, tSTRBi_tSTRHi = 1088, tSTRi_tSTRspi = 1089, tSVC_tTRAP = 1090, tTST = 1091, tUDF = 1092, tB_tBX_tBXNS_tBcc = 1093, tBLXNSr_tBLXr = 1094, t2DMB_t2DSB_t2ISB = 1095, t2MCR_t2MCR2_t2MCRR_t2MCRR2_t2MRC_t2MRC2 = 1096, t2MOVSsi = 1097, t2MOVSsr = 1098, t2MUL = 1099, t2SMMLA_t2SMMLAR_t2SMMLS_t2SMMLSR = 1100, t2UXTAB_t2UXTAH = 1101, t2UXTAB16 = 1102, MVE_SQRSHR_MVE_SQSHL_MVE_SRSHR_MVE_UQRSHL_MVE_UQSHL_MVE_URSHR = 1103, MVE_ASRLi_MVE_ASRLr_MVE_LSLLi_MVE_LSLLr_MVE_LSRL_MVE_SQRSHRL_MVE_SQSHLL_MVE_SRSHRL_MVE_UQRSHLL_MVE_UQSHLL_MVE_URSHRL = 1104, t2CLRM = 1105, t2LDRBi12_t2LDRHi12 = 1106, t2LDRi12 = 1107, t2LDMDB_t2LDMIA = 1108, t2LDMDB_UPD_t2LDMIA_UPD = 1109, tADDi3_tADDi8_tSUBi3_tSUBi8 = 1110, t2ADDSri_t2ADDri = 1111, t2SUBSri_t2SUBri = 1112, t2LoopDec = 1113, MVE_VLDRBS16_MVE_VLDRBS32_MVE_VLDRBU16_MVE_VLDRBU32_MVE_VLDRBU8_MVE_VLDRHS32_MVE_VLDRHU16_MVE_VLDRHU32_MVE_VLDRWU32 = 1114, MVE_VLDRBS16_post_MVE_VLDRBS16_pre_MVE_VLDRBS32_post_MVE_VLDRBS32_pre_MVE_VLDRBU16_post_MVE_VLDRBU16_pre_MVE_VLDRBU32_post_MVE_VLDRBU32_pre_MVE_VLDRBU8_post_MVE_VLDRBU8_pre_MVE_VLDRHS32_post_MVE_VLDRHS32_pre_MVE_VLDRHU16_post_MVE_VLDRHU16_pre_MVE_VLDRHU32_post_MVE_VLDRHU32_pre_MVE_VLDRWU32_post_MVE_VLDRWU32_pre = 1115, MVE_VLDRBS16_rq_MVE_VLDRBS32_rq_MVE_VLDRBU16_rq_MVE_VLDRBU32_rq_MVE_VLDRBU8_rq_MVE_VLDRDU64_rq_MVE_VLDRDU64_rq_u_MVE_VLDRHS32_rq_MVE_VLDRHS32_rq_u_MVE_VLDRHU16_rq_MVE_VLDRHU16_rq_u_MVE_VLDRHU32_rq_MVE_VLDRHU32_rq_u_MVE_VLDRWU32_rq_MVE_VLDRWU32_rq_u = 1116, MVE_VLDRDU64_qi_MVE_VLDRWU32_qi = 1117, MVE_VLDRDU64_qi_pre_MVE_VLDRWU32_qi_pre = 1118, MVE_VLD20_16_MVE_VLD20_32_MVE_VLD20_8_MVE_VLD21_16_MVE_VLD21_32_MVE_VLD21_8_MVE_VLD40_16_MVE_VLD40_32_MVE_VLD40_8_MVE_VLD41_16_MVE_VLD41_32_MVE_VLD41_8_MVE_VLD42_16_MVE_VLD42_32_MVE_VLD42_8_MVE_VLD43_16_MVE_VLD43_32_MVE_VLD43_8 = 1119, MVE_VLD20_16_wb_MVE_VLD20_32_wb_MVE_VLD20_8_wb_MVE_VLD21_16_wb_MVE_VLD21_32_wb_MVE_VLD21_8_wb_MVE_VLD40_16_wb_MVE_VLD40_32_wb_MVE_VLD40_8_wb_MVE_VLD41_16_wb_MVE_VLD41_32_wb_MVE_VLD41_8_wb_MVE_VLD42_16_wb_MVE_VLD42_32_wb_MVE_VLD42_8_wb_MVE_VLD43_16_wb_MVE_VLD43_32_wb_MVE_VLD43_8_wb = 1120, MVE_VSTRB16_MVE_VSTRB32_MVE_VSTRBU8_MVE_VSTRH32_MVE_VSTRHU16_MVE_VSTRWU32 = 1121, MVE_VSTRB16_post_MVE_VSTRB16_pre_MVE_VSTRB32_post_MVE_VSTRB32_pre_MVE_VSTRBU8_post_MVE_VSTRBU8_pre_MVE_VSTRH32_post_MVE_VSTRH32_pre_MVE_VSTRHU16_post_MVE_VSTRHU16_pre_MVE_VSTRWU32_post_MVE_VSTRWU32_pre = 1122, MVE_VSTRB16_rq_MVE_VSTRB32_rq_MVE_VSTRB8_rq_MVE_VSTRD64_rq_MVE_VSTRD64_rq_u_MVE_VSTRH16_rq_MVE_VSTRH16_rq_u_MVE_VSTRH32_rq_MVE_VSTRH32_rq_u_MVE_VSTRW32_rq_MVE_VSTRW32_rq_u = 1123, MVE_VSTRD64_qi_MVE_VSTRD64_qi_pre_MVE_VSTRW32_qi_MVE_VSTRW32_qi_pre = 1124, MVE_VST20_16_MVE_VST20_16_wb_MVE_VST20_32_MVE_VST20_32_wb_MVE_VST20_8_MVE_VST20_8_wb_MVE_VST21_16_MVE_VST21_16_wb_MVE_VST21_32_MVE_VST21_32_wb_MVE_VST21_8_MVE_VST21_8_wb_MVE_VST40_16_MVE_VST40_16_wb_MVE_VST40_32_MVE_VST40_32_wb_MVE_VST40_8_MVE_VST40_8_wb_MVE_VST41_16_MVE_VST41_16_wb_MVE_VST41_32_MVE_VST41_32_wb_MVE_VST41_8_MVE_VST41_8_wb_MVE_VST42_16_MVE_VST42_16_wb_MVE_VST42_32_MVE_VST42_32_wb_MVE_VST42_8_MVE_VST42_8_wb_MVE_VST43_16_MVE_VST43_16_wb_MVE_VST43_32_MVE_VST43_32_wb_MVE_VST43_8_MVE_VST43_8_wb = 1125, MVE_VABAVs16_MVE_VABAVs32_MVE_VABAVs8_MVE_VABAVu16_MVE_VABAVu32_MVE_VABAVu8 = 1126, MVE_VABDs16_MVE_VABDs32_MVE_VABDs8_MVE_VABDu16_MVE_VABDu32_MVE_VABDu8 = 1127, MVE_VABSs16_MVE_VABSs32_MVE_VABSs8 = 1128, MVE_VADC_MVE_VADCI = 1129, MVE_VADD_qr_i16_MVE_VADD_qr_i32_MVE_VADD_qr_i8_MVE_VADDi16_MVE_VADDi32_MVE_VADDi8 = 1130, MVE_VAND = 1131, MVE_VBIC_MVE_VBICimmi16_MVE_VBICimmi32 = 1132, MVE_VBRSR16_MVE_VBRSR32_MVE_VBRSR8 = 1133, MVE_VCADDi16_MVE_VCADDi32_MVE_VCADDi8 = 1134, MVE_VCLSs16_MVE_VCLSs32_MVE_VCLSs8 = 1135, MVE_VCLZs16_MVE_VCLZs32_MVE_VCLZs8 = 1136, MVE_VDDUPu16_MVE_VDDUPu32_MVE_VDDUPu8_MVE_VDUP16_MVE_VDUP32_MVE_VDUP8_MVE_VDWDUPu16_MVE_VDWDUPu32_MVE_VDWDUPu8_MVE_VIDUPu16_MVE_VIDUPu32_MVE_VIDUPu8_MVE_VIWDUPu16_MVE_VIWDUPu32_MVE_VIWDUPu8 = 1137, MVE_VEOR = 1138, MVE_VHADD_qr_s16_MVE_VHADD_qr_s32_MVE_VHADD_qr_s8_MVE_VHADD_qr_u16_MVE_VHADD_qr_u32_MVE_VHADD_qr_u8_MVE_VHADDs16_MVE_VHADDs32_MVE_VHADDs8_MVE_VHADDu16_MVE_VHADDu32_MVE_VHADDu8 = 1139, MVE_VHCADDs16_MVE_VHCADDs32_MVE_VHCADDs8 = 1140, MVE_VHSUB_qr_s16_MVE_VHSUB_qr_s32_MVE_VHSUB_qr_s8_MVE_VHSUB_qr_u16_MVE_VHSUB_qr_u32_MVE_VHSUB_qr_u8_MVE_VHSUBs16_MVE_VHSUBs32_MVE_VHSUBs8_MVE_VHSUBu16_MVE_VHSUBu32_MVE_VHSUBu8 = 1141, MVE_VMAXAs16_MVE_VMAXAs32_MVE_VMAXAs8_MVE_VMAXs16_MVE_VMAXs32_MVE_VMAXs8_MVE_VMAXu16_MVE_VMAXu32_MVE_VMAXu8_MVE_VMINAs16_MVE_VMINAs32_MVE_VMINAs8_MVE_VMINs16_MVE_VMINs32_MVE_VMINs8_MVE_VMINu16_MVE_VMINu32_MVE_VMINu8 = 1142, MVE_VMAXAVs8_MVE_VMAXVs8_MVE_VMAXVu8_MVE_VMINAVs8_MVE_VMINVs8_MVE_VMINVu8 = 1143, MVE_VMAXAVs16_MVE_VMAXVs16_MVE_VMAXVu16_MVE_VMINAVs16_MVE_VMINVs16_MVE_VMINVu16 = 1144, MVE_VMAXAVs32_MVE_VMAXVs32_MVE_VMAXVu32_MVE_VMINAVs32_MVE_VMINVs32_MVE_VMINVu32 = 1145, MVE_VMOVNi16bh_MVE_VMOVNi16th_MVE_VMOVNi32bh_MVE_VMOVNi32th = 1146, MVE_VMOVLs16bh_MVE_VMOVLs16th_MVE_VMOVLs8bh_MVE_VMOVLs8th_MVE_VMOVLu16bh_MVE_VMOVLu16th_MVE_VMOVLu8bh_MVE_VMOVLu8th = 1147, MVE_VMULLBp16_MVE_VMULLBp8_MVE_VMULLTp16_MVE_VMULLTp8 = 1148, MVE_VMVN_MVE_VMVNimmi16_MVE_VMVNimmi32 = 1149, MVE_VNEGs16_MVE_VNEGs32_MVE_VNEGs8 = 1150, MVE_VORN = 1151, MVE_VORR_MVE_VORRimmi16_MVE_VORRimmi32 = 1152, MVE_VPSEL = 1153, MQPRCopy = 1154, MVE_VQABSs16_MVE_VQABSs32_MVE_VQABSs8 = 1155, MVE_VQADD_qr_s16_MVE_VQADD_qr_s32_MVE_VQADD_qr_s8_MVE_VQADD_qr_u16_MVE_VQADD_qr_u32_MVE_VQADD_qr_u8_MVE_VQADDs16_MVE_VQADDs32_MVE_VQADDs8_MVE_VQADDu16_MVE_VQADDu32_MVE_VQADDu8 = 1156, MVE_VQMOVNs16bh_MVE_VQMOVNs16th_MVE_VQMOVNs32bh_MVE_VQMOVNs32th_MVE_VQMOVNu16bh_MVE_VQMOVNu16th_MVE_VQMOVNu32bh_MVE_VQMOVNu32th_MVE_VQMOVUNs16bh_MVE_VQMOVUNs16th_MVE_VQMOVUNs32bh_MVE_VQMOVUNs32th = 1157, MVE_VQNEGs16_MVE_VQNEGs32_MVE_VQNEGs8 = 1158, MVE_VSHLC_MVE_VSHLL_imms16bh_MVE_VSHLL_imms16th_MVE_VSHLL_imms8bh_MVE_VSHLL_imms8th_MVE_VSHLL_immu16bh_MVE_VSHLL_immu16th_MVE_VSHLL_immu8bh_MVE_VSHLL_immu8th_MVE_VSHLL_lws16bh_MVE_VSHLL_lws16th_MVE_VSHLL_lws8bh_MVE_VSHLL_lws8th_MVE_VSHLL_lwu16bh_MVE_VSHLL_lwu16th_MVE_VSHLL_lwu8bh_MVE_VSHLL_lwu8th_MVE_VSHL_by_vecs16_MVE_VSHL_by_vecs32_MVE_VSHL_by_vecs8_MVE_VSHL_by_vecu16_MVE_VSHL_by_vecu32_MVE_VSHL_by_vecu8_MVE_VSHL_immi16_MVE_VSHL_immi32_MVE_VSHL_immi8_MVE_VSHL_qrs16_MVE_VSHL_qrs32_MVE_VSHL_qrs8_MVE_VSHL_qru16_MVE_VSHL_qru32_MVE_VSHL_qru8 = 1159, MVE_VQSHLU_imms16_MVE_VQSHLU_imms32_MVE_VQSHLU_imms8_MVE_VQSHL_by_vecs16_MVE_VQSHL_by_vecs32_MVE_VQSHL_by_vecs8_MVE_VQSHL_by_vecu16_MVE_VQSHL_by_vecu32_MVE_VQSHL_by_vecu8_MVE_VQSHL_qrs16_MVE_VQSHL_qrs32_MVE_VQSHL_qrs8_MVE_VQSHL_qru16_MVE_VQSHL_qru32_MVE_VQSHL_qru8_MVE_VQSHLimms16_MVE_VQSHLimms32_MVE_VQSHLimms8_MVE_VQSHLimmu16_MVE_VQSHLimmu32_MVE_VQSHLimmu8_MVE_VRSHL_by_vecs16_MVE_VRSHL_by_vecs32_MVE_VRSHL_by_vecs8_MVE_VRSHL_by_vecu16_MVE_VRSHL_by_vecu32_MVE_VRSHL_by_vecu8_MVE_VRSHL_qrs16_MVE_VRSHL_qrs32_MVE_VRSHL_qrs8_MVE_VRSHL_qru16_MVE_VRSHL_qru32_MVE_VRSHL_qru8 = 1160, MVE_VQRSHL_by_vecs16_MVE_VQRSHL_by_vecs32_MVE_VQRSHL_by_vecs8_MVE_VQRSHL_by_vecu16_MVE_VQRSHL_by_vecu32_MVE_VQRSHL_by_vecu8_MVE_VQRSHL_qrs16_MVE_VQRSHL_qrs32_MVE_VQRSHL_qrs8_MVE_VQRSHL_qru16_MVE_VQRSHL_qru32_MVE_VQRSHL_qru8 = 1161, MVE_VQRSHRNbhs16_MVE_VQRSHRNbhs32_MVE_VQRSHRNbhu16_MVE_VQRSHRNbhu32_MVE_VQRSHRNths16_MVE_VQRSHRNths32_MVE_VQRSHRNthu16_MVE_VQRSHRNthu32_MVE_VQRSHRUNs16bh_MVE_VQRSHRUNs16th_MVE_VQRSHRUNs32bh_MVE_VQRSHRUNs32th_MVE_VQSHRNbhs16_MVE_VQSHRNbhs32_MVE_VQSHRNbhu16_MVE_VQSHRNbhu32_MVE_VQSHRNths16_MVE_VQSHRNths32_MVE_VQSHRNthu16_MVE_VQSHRNthu32_MVE_VQSHRUNs16bh_MVE_VQSHRUNs16th_MVE_VQSHRUNs32bh_MVE_VQSHRUNs32th_MVE_VRSHRNi16bh_MVE_VRSHRNi16th_MVE_VRSHRNi32bh_MVE_VRSHRNi32th_MVE_VSHRNi16bh_MVE_VSHRNi16th_MVE_VSHRNi32bh_MVE_VSHRNi32th = 1162, MVE_VSHR_imms16_MVE_VSHR_imms32_MVE_VSHR_imms8_MVE_VSHR_immu16_MVE_VSHR_immu32_MVE_VSHR_immu8 = 1163, MVE_VRSHR_imms16_MVE_VRSHR_imms32_MVE_VRSHR_imms8_MVE_VRSHR_immu16_MVE_VRSHR_immu32_MVE_VRSHR_immu8 = 1164, MVE_VQSUB_qr_s16_MVE_VQSUB_qr_s32_MVE_VQSUB_qr_s8_MVE_VQSUB_qr_u16_MVE_VQSUB_qr_u32_MVE_VQSUB_qr_u8_MVE_VQSUBs16_MVE_VQSUBs32_MVE_VQSUBs8_MVE_VQSUBu16_MVE_VQSUBu32_MVE_VQSUBu8 = 1165, MVE_VREV16_8_MVE_VREV32_16_MVE_VREV32_8_MVE_VREV64_16_MVE_VREV64_32_MVE_VREV64_8 = 1166, MVE_VRHADDs16_MVE_VRHADDs32_MVE_VRHADDs8_MVE_VRHADDu16_MVE_VRHADDu32_MVE_VRHADDu8 = 1167, MVE_VSBC_MVE_VSBCI = 1168, MVE_VSLIimm16_MVE_VSLIimm32_MVE_VSLIimm8 = 1169, MVE_VSRIimm16_MVE_VSRIimm32_MVE_VSRIimm8 = 1170, MVE_VSUB_qr_i16_MVE_VSUB_qr_i32_MVE_VSUB_qr_i8_MVE_VSUBi16_MVE_VSUBi32_MVE_VSUBi8 = 1171, MVE_VABDf16_MVE_VABDf32 = 1172, MVE_VABSf16_MVE_VABSf32 = 1173, MVE_VADDf16_MVE_VADDf32 = 1174, MVE_VADD_qr_f16_MVE_VADD_qr_f32 = 1175, MVE_VADDLVs32acc_MVE_VADDLVs32no_acc_MVE_VADDLVu32acc_MVE_VADDLVu32no_acc = 1176, MVE_VADDVs16acc_MVE_VADDVs16no_acc_MVE_VADDVs32acc_MVE_VADDVs32no_acc_MVE_VADDVs8acc_MVE_VADDVs8no_acc_MVE_VADDVu16acc_MVE_VADDVu16no_acc_MVE_VADDVu32acc_MVE_VADDVu32no_acc_MVE_VADDVu8acc_MVE_VADDVu8no_acc = 1177, MVE_VCADDf16_MVE_VCADDf32 = 1178, MVE_VCMLAf16_MVE_VCMLAf32 = 1179, MVE_VCMULf16_MVE_VCMULf32 = 1180, MVE_VCMPi16_MVE_VCMPi16r_MVE_VCMPi32_MVE_VCMPi32r_MVE_VCMPi8_MVE_VCMPi8r_MVE_VCMPs16_MVE_VCMPs16r_MVE_VCMPs32_MVE_VCMPs32r_MVE_VCMPs8_MVE_VCMPs8r_MVE_VCMPu16_MVE_VCMPu16r_MVE_VCMPu32_MVE_VCMPu32r_MVE_VCMPu8_MVE_VCMPu8r_MVE_VPTv16i8_MVE_VPTv16i8r_MVE_VPTv16s8_MVE_VPTv16s8r_MVE_VPTv16u8_MVE_VPTv16u8r_MVE_VPTv4i32_MVE_VPTv4i32r_MVE_VPTv4s32_MVE_VPTv4s32r_MVE_VPTv4u32_MVE_VPTv4u32r_MVE_VPTv8i16_MVE_VPTv8i16r_MVE_VPTv8s16_MVE_VPTv8s16r_MVE_VPTv8u16_MVE_VPTv8u16r = 1181, MVE_VCMPf16_MVE_VCMPf16r_MVE_VCMPf32_MVE_VCMPf32r_MVE_VPTv4f32_MVE_VPTv4f32r_MVE_VPTv8f16_MVE_VPTv8f16r = 1182, MVE_VCVTf16s16_fix_MVE_VCVTf16s16n_MVE_VCVTf16u16_fix_MVE_VCVTf16u16n = 1183, MVE_VCVTf32s32_fix_MVE_VCVTf32s32n_MVE_VCVTf32u32_fix_MVE_VCVTf32u32n = 1184, MVE_VCVTs16f16_fix_MVE_VCVTs16f16a_MVE_VCVTs16f16m_MVE_VCVTs16f16n_MVE_VCVTs16f16p_MVE_VCVTs16f16z_MVE_VCVTu16f16_fix_MVE_VCVTu16f16a_MVE_VCVTu16f16m_MVE_VCVTu16f16n_MVE_VCVTu16f16p_MVE_VCVTu16f16z = 1185, MVE_VCVTs32f32_fix_MVE_VCVTs32f32a_MVE_VCVTs32f32m_MVE_VCVTs32f32n_MVE_VCVTs32f32p_MVE_VCVTs32f32z_MVE_VCVTu32f32_fix_MVE_VCVTu32f32a_MVE_VCVTu32f32m_MVE_VCVTu32f32n_MVE_VCVTu32f32p_MVE_VCVTu32f32z = 1186, MVE_VCVTf16f32bh_MVE_VCVTf16f32th = 1187, MVE_VCVTf32f16bh_MVE_VCVTf32f16th = 1188, MVE_VFMA_qr_Sf16_MVE_VFMA_qr_Sf32_MVE_VFMA_qr_f16_MVE_VFMA_qr_f32_MVE_VFMAf16_MVE_VFMAf32_MVE_VFMSf16_MVE_VFMSf32 = 1189, MVE_VMAXNMAVf16_MVE_VMAXNMAVf32_MVE_VMAXNMAf16_MVE_VMAXNMAf32_MVE_VMAXNMVf16_MVE_VMAXNMVf32_MVE_VMAXNMf16_MVE_VMAXNMf32_MVE_VMINNMAVf16_MVE_VMINNMAVf32_MVE_VMINNMAf16_MVE_VMINNMAf32_MVE_VMINNMVf16_MVE_VMINNMVf32_MVE_VMINNMf16_MVE_VMINNMf32 = 1190, MVE_VMOV_from_lane_32_MVE_VMOV_from_lane_s16_MVE_VMOV_from_lane_s8_MVE_VMOV_from_lane_u16_MVE_VMOV_from_lane_u8 = 1191, MVE_VMOV_rr_q = 1192, MVE_VMOVimmf32_MVE_VMOVimmi16_MVE_VMOVimmi32_MVE_VMOVimmi64_MVE_VMOVimmi8 = 1193, MVE_VMUL_qr_f16_MVE_VMUL_qr_f32_MVE_VMUL_qr_i16_MVE_VMUL_qr_i32_MVE_VMUL_qr_i8_MVE_VMULf16_MVE_VMULf32_MVE_VMULi16_MVE_VMULi32_MVE_VMULi8 = 1194, MVE_VMULHs16_MVE_VMULHs32_MVE_VMULHs8_MVE_VMULHu16_MVE_VMULHu32_MVE_VMULHu8_MVE_VQDMULH_qr_s16_MVE_VQDMULH_qr_s32_MVE_VQDMULH_qr_s8_MVE_VQDMULHi16_MVE_VQDMULHi32_MVE_VQDMULHi8_MVE_VQRDMULH_qr_s16_MVE_VQRDMULH_qr_s32_MVE_VQRDMULH_qr_s8_MVE_VQRDMULHi16_MVE_VQRDMULHi32_MVE_VQRDMULHi8_MVE_VRMULHs16_MVE_VRMULHs32_MVE_VRMULHs8_MVE_VRMULHu16_MVE_VRMULHu32_MVE_VRMULHu8 = 1195, MVE_VMULLBs16_MVE_VMULLBs32_MVE_VMULLBs8_MVE_VMULLBu16_MVE_VMULLBu32_MVE_VMULLBu8_MVE_VMULLTs16_MVE_VMULLTs32_MVE_VMULLTs8_MVE_VMULLTu16_MVE_VMULLTu32_MVE_VMULLTu8_MVE_VQDMULLs16bh_MVE_VQDMULLs16th_MVE_VQDMULLs32bh_MVE_VQDMULLs32th = 1196, MVE_VQDMULL_qr_s16bh_MVE_VQDMULL_qr_s16th_MVE_VQDMULL_qr_s32bh_MVE_VQDMULL_qr_s32th = 1197, MVE_VMLADAVas16_MVE_VMLADAVas32_MVE_VMLADAVas8_MVE_VMLADAVau16_MVE_VMLADAVau32_MVE_VMLADAVau8_MVE_VMLADAVaxs16_MVE_VMLADAVaxs32_MVE_VMLADAVaxs8_MVE_VMLADAVs16_MVE_VMLADAVs32_MVE_VMLADAVs8_MVE_VMLADAVu16_MVE_VMLADAVu32_MVE_VMLADAVu8_MVE_VMLADAVxs16_MVE_VMLADAVxs32_MVE_VMLADAVxs8_MVE_VMLAS_qr_i16_MVE_VMLAS_qr_i32_MVE_VMLAS_qr_i8_MVE_VMLA_qr_i16_MVE_VMLA_qr_i32_MVE_VMLA_qr_i8_MVE_VMLSDAVas16_MVE_VMLSDAVas32_MVE_VMLSDAVas8_MVE_VMLSDAVaxs16_MVE_VMLSDAVaxs32_MVE_VMLSDAVaxs8_MVE_VMLSDAVs16_MVE_VMLSDAVs32_MVE_VMLSDAVs8_MVE_VMLSDAVxs16_MVE_VMLSDAVxs32_MVE_VMLSDAVxs8_MVE_VQDMLADHXs16_MVE_VQDMLADHXs32_MVE_VQDMLADHXs8_MVE_VQDMLADHs16_MVE_VQDMLADHs32_MVE_VQDMLADHs8_MVE_VQDMLAH_qrs16_MVE_VQDMLAH_qrs32_MVE_VQDMLAH_qrs8_MVE_VQDMLASH_qrs16_MVE_VQDMLASH_qrs32_MVE_VQDMLASH_qrs8_MVE_VQDMLSDHXs16_MVE_VQDMLSDHXs32_MVE_VQDMLSDHXs8_MVE_VQDMLSDHs16_MVE_VQDMLSDHs32_MVE_VQDMLSDHs8_MVE_VQRDMLADHXs16_MVE_VQRDMLADHXs32_MVE_VQRDMLADHXs8_MVE_VQRDMLADHs16_MVE_VQRDMLADHs32_MVE_VQRDMLADHs8_MVE_VQRDMLAH_qrs16_MVE_VQRDMLAH_qrs32_MVE_VQRDMLAH_qrs8_MVE_VQRDMLASH_qrs16_MVE_VQRDMLASH_qrs32_MVE_VQRDMLASH_qrs8_MVE_VQRDMLSDHXs16_MVE_VQRDMLSDHXs32_MVE_VQRDMLSDHXs8_MVE_VQRDMLSDHs16_MVE_VQRDMLSDHs32_MVE_VQRDMLSDHs8 = 1198, MVE_VMLALDAVas16_MVE_VMLALDAVas32_MVE_VMLALDAVau16_MVE_VMLALDAVau32_MVE_VMLALDAVaxs16_MVE_VMLALDAVaxs32_MVE_VMLALDAVs16_MVE_VMLALDAVs32_MVE_VMLALDAVu16_MVE_VMLALDAVu32_MVE_VMLALDAVxs16_MVE_VMLALDAVxs32_MVE_VMLSLDAVas16_MVE_VMLSLDAVas32_MVE_VMLSLDAVaxs16_MVE_VMLSLDAVaxs32_MVE_VMLSLDAVs16_MVE_VMLSLDAVs32_MVE_VMLSLDAVxs16_MVE_VMLSLDAVxs32_MVE_VRMLALDAVHas32_MVE_VRMLALDAVHau32_MVE_VRMLALDAVHaxs32_MVE_VRMLALDAVHs32_MVE_VRMLALDAVHu32_MVE_VRMLALDAVHxs32_MVE_VRMLSLDAVHas32_MVE_VRMLSLDAVHaxs32_MVE_VRMLSLDAVHs32_MVE_VRMLSLDAVHxs32 = 1199, MVE_VNEGf16_MVE_VNEGf32 = 1200, MVE_VRINTf16A_MVE_VRINTf16M_MVE_VRINTf16N_MVE_VRINTf16P_MVE_VRINTf16X_MVE_VRINTf16Z_MVE_VRINTf32A_MVE_VRINTf32M_MVE_VRINTf32N_MVE_VRINTf32P_MVE_VRINTf32X_MVE_VRINTf32Z = 1201, MVE_VSUBf16_MVE_VSUBf32 = 1202, MVE_VSUB_qr_f16_MVE_VSUB_qr_f32 = 1203, MVE_VMOV_to_lane_16_MVE_VMOV_to_lane_32_MVE_VMOV_to_lane_8_MVE_VMOV_q_rr = 1204, MVE_VCTP16_MVE_VCTP32_MVE_VCTP64_MVE_VCTP8 = 1205, MVE_VPNOT = 1206, MVE_VPST = 1207, VCVTASD_VCVTASH_VCVTASS_VCVTAUD_VCVTAUH_VCVTAUS_VCVTMSD_VCVTMSH_VCVTMSS_VCVTMUD_VCVTMUH_VCVTMUS_VCVTNSD_VCVTNSH_VCVTNSS_VCVTNUD_VCVTNUH_VCVTNUS_VCVTPSD_VCVTPSH_VCVTPSS_VCVTPUD_VCVTPUH_VCVTPUS = 1208, VDIVH = 1209, VFMAH_VFMSH = 1210, VFP_VMAXNMD_VFP_VMAXNMH_VFP_VMAXNMS_VFP_VMINNMD_VFP_VMINNMH_VFP_VMINNMS = 1211, VMOVH = 1212, VMOVHR = 1213, VMOVD = 1214, VMOVS = 1215, VMOVRH = 1216, tSVC = 1217, t2HVC = 1218, t2SMC_ERET = 1219, tHINT = 1220, BUNDLE = 1221, t2LDRBpcrel_t2LDRHpcrel = 1222, t2LDRBpci_t2LDRHpci = 1223, t2LDRSBpci_t2LDRSHpci = 1224, t2LDRH_POST_imm = 1225, t2LDRH_PRE_imm = 1226, t2LDREX = 1227, t2LDREXB_t2LDREXH = 1228, t2STREX_t2STREXB_t2STREXH = 1229, t2LDRpci = 1230, t2PLDpci_t2PLIpci = 1231, tLDRpci = 1232, t2PLDWi12_t2PLDWi8_t2PLDi12_t2PLDi8_t2PLIi12_t2PLIi8 = 1233, t2PLDs_t2PLIs = 1234, t2TBB_JT_t2TBH_JT = 1235, t2TBB_t2TBH = 1236, t2RSBSrs_t2SUBrs = 1237, t2SUBSrs = 1238, t2BICrs_t2EORrs_t2ORRrs = 1239, t2ORNrs = 1240, t2CMNzrs = 1241, t2CMPrs = 1242, t2TEQrs_t2TSTrs = 1243, t2RRX = 1244, tLSLSri = 1245, t2CLZ = 1246, t2USAD8 = 1247, t2RBIT = 1248, t2PKHBT_t2PKHTB = 1249, VCVTASS_VCVTAUS_VCVTMSS_VCVTMUS_VCVTNSS_VCVTNUS_VCVTPSS_VCVTPUS = 1250, VFP_VMAXNMS_VFP_VMINNMS = 1251, VRINTAS_VRINTMS_VRINTNS_VRINTPS_VRINTRS_VRINTXS_VRINTZS = 1252, VCVTASD_VCVTAUD_VCVTMSD_VCVTMUD_VCVTNSD_VCVTNUD_VCVTPSD_VCVTPUD = 1253, VCVTTHD = 1254, VFP_VMAXNMD_VFP_VMINNMD = 1255, VRINTAD_VRINTMD_VRINTND_VRINTPD_VRINTRD_VRINTXD_VRINTZD = 1256, VCMPS = 1257, VCMPD = 1258, VSELEQS_VSELGES_VSELGTS_VSELVSS = 1259, VSELEQD_VSELGED_VSELGTD_VSELVSD = 1260, VMULD_VNMULD = 1261, tLDRspi = 1262, t2LDA_t2LDAEX = 1263, t2LDAEXD = 1264, t2STL_t2STLB_t2STLEX_t2STLEXB_t2STLEXH_t2STLH = 1265, MVE_VST20_16_MVE_VST20_32_MVE_VST20_8_MVE_VST21_16_MVE_VST21_32_MVE_VST21_8_MVE_VST40_16_MVE_VST40_32_MVE_VST40_8_MVE_VST41_16_MVE_VST41_32_MVE_VST41_8_MVE_VST42_16_MVE_VST42_32_MVE_VST42_8_MVE_VST43_16_MVE_VST43_32_MVE_VST43_8 = 1266, MVE_VSTRD64_qi_MVE_VSTRW32_qi = 1267, t2RSBSrs = 1268, t2ADCrs_t2SBCrs = 1269, t2ADDSrr_t2SBCrr = 1270, t2SUBSrr_t2RSBrr = 1271, t2ADCrr = 1272, t2BICrr_t2EORrr = 1273, t2ORNrr = 1274, tADDspi_tSUBspi = 1275, t2ADDri = 1276, t2ADDri12 = 1277, t2SUBri = 1278, t2SUBri12 = 1279, tADDrSP_tADDspr_tADDhirr = 1280, tADDrSPi = 1281, MVE_ASRLi_MVE_LSLLi_MVE_LSRL_MVE_SQSHLL_MVE_SRSHRL_MVE_UQSHLL_MVE_URSHRL = 1282, MVE_SQRSHR_MVE_UQRSHL = 1283, t2BF_LabelPseudo_t2BFLi_t2BFLr_t2BFi_t2BFic_t2BFr = 1284, MVE_LCTP = 1285, t2DLS_t2WLS_MVE_DLSTP_16_MVE_DLSTP_32_MVE_DLSTP_64_MVE_DLSTP_8_MVE_WLSTP_16_MVE_WLSTP_32_MVE_WLSTP_64_MVE_WLSTP_8 = 1286, t2LE = 1287, t2LEUpdate_MVE_LETP = 1288, VSHTOD_VSLTOD_VUHTOD_VULTOD = 1289, VMSR_VMSR_FPSCR_NZCVQC_VMSR_P0_VMSR_VPR = 1290, VMRS_P0_VMRS_VPR = 1291, VMRS_FPSCR_NZCVQC = 1292, VMRS = 1293, MVE_VMOV_q_rr = 1294, MVE_VADC = 1295, MVE_VADD_qr_i16_MVE_VADD_qr_i32_MVE_VADD_qr_i8 = 1296, MVE_VHADD_qr_s16_MVE_VHADD_qr_s32_MVE_VHADD_qr_s8_MVE_VHADD_qr_u16_MVE_VHADD_qr_u32_MVE_VHADD_qr_u8 = 1297, MVE_VHSUB_qr_s16_MVE_VHSUB_qr_s32_MVE_VHSUB_qr_s8_MVE_VHSUB_qr_u16_MVE_VHSUB_qr_u32_MVE_VHSUB_qr_u8 = 1298, MVE_VQADD_qr_s16_MVE_VQADD_qr_s32_MVE_VQADD_qr_s8_MVE_VQADD_qr_u16_MVE_VQADD_qr_u32_MVE_VQADD_qr_u8 = 1299, MVE_VQSUB_qr_s16_MVE_VQSUB_qr_s32_MVE_VQSUB_qr_s8_MVE_VQSUB_qr_u16_MVE_VQSUB_qr_u32_MVE_VQSUB_qr_u8 = 1300, MVE_VSHL_qrs16_MVE_VSHL_qrs32_MVE_VSHL_qrs8_MVE_VSHL_qru16_MVE_VSHL_qru32_MVE_VSHL_qru8 = 1301, MVE_VSUB_qr_i16_MVE_VSUB_qr_i32_MVE_VSUB_qr_i8 = 1302, MVE_VSHL_by_vecs16_MVE_VSHL_by_vecs32_MVE_VSHL_by_vecs8_MVE_VSHL_by_vecu16_MVE_VSHL_by_vecu32_MVE_VSHL_by_vecu8_MVE_VSHL_immi16_MVE_VSHL_immi32_MVE_VSHL_immi8_MVE_VSHLL_imms16bh_MVE_VSHLL_imms16th_MVE_VSHLL_imms8bh_MVE_VSHLL_imms8th_MVE_VSHLL_immu16bh_MVE_VSHLL_immu16th_MVE_VSHLL_immu8bh_MVE_VSHLL_immu8th_MVE_VSHLL_lws16bh_MVE_VSHLL_lws16th_MVE_VSHLL_lws8bh_MVE_VSHLL_lws8th_MVE_VSHLL_lwu16bh_MVE_VSHLL_lwu16th_MVE_VSHLL_lwu8bh_MVE_VSHLL_lwu8th = 1303, MVE_VSHRNi16bh_MVE_VSHRNi16th_MVE_VSHRNi32bh_MVE_VSHRNi32th = 1304, MVE_VDWDUPu16_MVE_VDWDUPu32_MVE_VDWDUPu8_MVE_VIWDUPu16_MVE_VIWDUPu32_MVE_VIWDUPu8 = 1305, MVE_VDDUPu16_MVE_VDDUPu32_MVE_VDDUPu8_MVE_VIDUPu16_MVE_VIDUPu32_MVE_VIDUPu8 = 1306, MVE_VQRSHL_qrs16_MVE_VQRSHL_qrs32_MVE_VQRSHL_qrs8_MVE_VQRSHL_qru16_MVE_VQRSHL_qru32_MVE_VQRSHL_qru8 = 1307, MVE_VQSHL_qrs16_MVE_VQSHL_qrs32_MVE_VQSHL_qrs8_MVE_VQSHL_qru16_MVE_VQSHL_qru32_MVE_VQSHL_qru8_MVE_VRSHL_qrs16_MVE_VRSHL_qrs32_MVE_VRSHL_qrs8_MVE_VRSHL_qru16_MVE_VRSHL_qru32_MVE_VRSHL_qru8 = 1308, MVE_VMAXNMAf16_MVE_VMAXNMAf32_MVE_VMAXNMf16_MVE_VMAXNMf32_MVE_VMINNMAf16_MVE_VMINNMAf32_MVE_VMINNMf16_MVE_VMINNMf32 = 1309, MVE_VADDLVs32acc_MVE_VADDLVu32acc = 1310, MVE_VADDVs16acc_MVE_VADDVs32acc_MVE_VADDVs8acc_MVE_VADDVu16acc_MVE_VADDVu32acc_MVE_VADDVu8acc = 1311, MVE_VMUL_qr_i16_MVE_VMUL_qr_i32_MVE_VMUL_qr_i8 = 1312, MVE_VQDMULH_qr_s16_MVE_VQDMULH_qr_s32_MVE_VQDMULH_qr_s8_MVE_VQRDMULH_qr_s16_MVE_VQRDMULH_qr_s32_MVE_VQRDMULH_qr_s8 = 1313, MVE_VMLAS_qr_i16_MVE_VMLAS_qr_i32_MVE_VMLAS_qr_i8_MVE_VMLA_qr_i16_MVE_VMLA_qr_i32_MVE_VMLA_qr_i8 = 1314, MVE_VQDMLAH_qrs16_MVE_VQDMLAH_qrs32_MVE_VQDMLAH_qrs8_MVE_VQDMLASH_qrs16_MVE_VQDMLASH_qrs32_MVE_VQDMLASH_qrs8_MVE_VQRDMLAH_qrs16_MVE_VQRDMLAH_qrs32_MVE_VQRDMLAH_qrs8_MVE_VQRDMLASH_qrs16_MVE_VQRDMLASH_qrs32_MVE_VQRDMLASH_qrs8 = 1315, MVE_VQDMLADHXs16_MVE_VQDMLADHXs32_MVE_VQDMLADHXs8_MVE_VQDMLADHs16_MVE_VQDMLADHs32_MVE_VQDMLADHs8_MVE_VQDMLSDHXs16_MVE_VQDMLSDHXs32_MVE_VQDMLSDHXs8_MVE_VQDMLSDHs16_MVE_VQDMLSDHs32_MVE_VQDMLSDHs8_MVE_VQRDMLADHXs16_MVE_VQRDMLADHXs32_MVE_VQRDMLADHXs8_MVE_VQRDMLADHs16_MVE_VQRDMLADHs32_MVE_VQRDMLADHs8_MVE_VQRDMLSDHXs16_MVE_VQRDMLSDHXs32_MVE_VQRDMLSDHXs8_MVE_VQRDMLSDHs16_MVE_VQRDMLSDHs32_MVE_VQRDMLSDHs8 = 1316, MVE_VMLALDAVas16_MVE_VMLALDAVas32_MVE_VMLALDAVau16_MVE_VMLALDAVau32_MVE_VMLALDAVaxs16_MVE_VMLALDAVaxs32_MVE_VMLSLDAVas16_MVE_VMLSLDAVas32_MVE_VMLSLDAVaxs16_MVE_VMLSLDAVaxs32_MVE_VRMLALDAVHas32_MVE_VRMLALDAVHau32_MVE_VRMLALDAVHaxs32_MVE_VRMLSLDAVHas32_MVE_VRMLSLDAVHaxs32 = 1317, MVE_VMLADAVas16_MVE_VMLADAVas32_MVE_VMLADAVas8_MVE_VMLADAVau16_MVE_VMLADAVau32_MVE_VMLADAVau8_MVE_VMLADAVaxs16_MVE_VMLADAVaxs32_MVE_VMLADAVaxs8_MVE_VMLSDAVas16_MVE_VMLSDAVas32_MVE_VMLSDAVas8_MVE_VMLSDAVaxs16_MVE_VMLSDAVaxs32_MVE_VMLSDAVaxs8 = 1318, MVE_VMULi16_MVE_VMULi32_MVE_VMULi8 = 1319, MVE_VMUL_qr_f16_MVE_VMUL_qr_f32 = 1320, MVE_VFMA_qr_Sf16_MVE_VFMA_qr_Sf32_MVE_VFMA_qr_f16_MVE_VFMA_qr_f32 = 1321, MVE_VPTv4f32r_MVE_VPTv8f16r = 1322, MVE_VPTv16i8r_MVE_VPTv16s8r_MVE_VPTv16u8r_MVE_VPTv4i32r_MVE_VPTv4s32r_MVE_VPTv4u32r_MVE_VPTv8i16r_MVE_VPTv8s16r_MVE_VPTv8u16r = 1323, MVE_VCMPi16r_MVE_VCMPi32r_MVE_VCMPi8r_MVE_VCMPs16r_MVE_VCMPs32r_MVE_VCMPs8r_MVE_VCMPu16r_MVE_VCMPu32r_MVE_VCMPu8r = 1324, MVE_VCMPf16r_MVE_VCMPf32r = 1325, SCHED_LIST_END = 1326 }; } // end namespace Sched } // end namespace ARM } // end namespace llvm #endif // GET_INSTRINFO_SCHED_ENUM #if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) namespace llvm { struct ARMInstrTable { MCInstrDesc Insts[4499]; static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo"); MCOperandInfo OperandInfo[3074]; static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps"); MCPhysReg ImplicitOps[233]; }; } // end namespace llvm #endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) #ifdef GET_INSTRINFO_MC_DESC #undef GET_INSTRINFO_MC_DESC namespace llvm { static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0); static constexpr unsigned ARMImpOpBase = sizeof ARMInstrTable::OperandInfo / (sizeof(MCPhysReg)); extern const ARMInstrTable ARMDescs = { { { 4498, 0, 0, 2, 846, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4498 = t__brkdiv0 { 4497, 4, 1, 2, 899, 0, 0, ARMImpOpBase + 0, 3028, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4497 = tUXTH { 4496, 4, 1, 2, 899, 0, 0, ARMImpOpBase + 0, 3028, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4496 = tUXTB { 4495, 1, 0, 2, 1092, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4495 = tUDF { 4494, 4, 0, 2, 1091, 0, 1, ARMImpOpBase + 0, 3028, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL }, // Inst #4494 = tTST { 4493, 0, 0, 2, 1090, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4493 = tTRAP { 4492, 4, 1, 2, 899, 0, 0, ARMImpOpBase + 0, 3028, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4492 = tSXTH { 4491, 4, 1, 2, 899, 0, 0, ARMImpOpBase + 0, 3028, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4491 = tSXTB { 4490, 3, 0, 2, 1217, 1, 0, ARMImpOpBase + 54, 858, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4490 = tSVC { 4489, 5, 1, 2, 1275, 0, 0, ARMImpOpBase + 0, 3006, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4489 = tSUBspi { 4488, 6, 2, 2, 1079, 0, 0, ARMImpOpBase + 0, 3000, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4488 = tSUBrr { 4487, 6, 2, 2, 1110, 0, 0, ARMImpOpBase + 0, 2984, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4487 = tSUBi8 { 4486, 6, 2, 2, 1110, 0, 0, ARMImpOpBase + 0, 2978, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4486 = tSUBi3 { 4485, 5, 0, 2, 1089, 0, 0, ARMImpOpBase + 0, 3050, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8aULL }, // Inst #4485 = tSTRspi { 4484, 5, 0, 2, 436, 0, 0, ARMImpOpBase + 0, 3041, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc89ULL }, // Inst #4484 = tSTRr { 4483, 5, 0, 2, 1089, 0, 0, ARMImpOpBase + 0, 3036, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc89ULL }, // Inst #4483 = tSTRi { 4482, 5, 0, 2, 435, 0, 0, ARMImpOpBase + 0, 3041, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc88ULL }, // Inst #4482 = tSTRHr { 4481, 5, 0, 2, 1088, 0, 0, ARMImpOpBase + 0, 3036, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc88ULL }, // Inst #4481 = tSTRHi { 4480, 5, 0, 2, 435, 0, 0, ARMImpOpBase + 0, 3041, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc87ULL }, // Inst #4480 = tSTRBr { 4479, 5, 0, 2, 1088, 0, 0, ARMImpOpBase + 0, 3036, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc87ULL }, // Inst #4479 = tSTRBi { 4478, 5, 1, 2, 1027, 0, 0, ARMImpOpBase + 0, 558, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4478 = tSTMIA_UPD { 4477, 1, 0, 2, 1078, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4477 = tSETEND { 4476, 6, 2, 2, 1079, 1, 0, ARMImpOpBase + 0, 2972, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x80c80ULL }, // Inst #4476 = tSBC { 4475, 5, 2, 2, 1080, 0, 0, ARMImpOpBase + 0, 3066, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4475 = tRSB { 4474, 6, 2, 2, 881, 0, 0, ARMImpOpBase + 0, 2972, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4474 = tROR { 4473, 4, 1, 2, 1033, 0, 0, ARMImpOpBase + 0, 3028, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4473 = tREVSH { 4472, 4, 1, 2, 1033, 0, 0, ARMImpOpBase + 0, 3028, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4472 = tREV16 { 4471, 4, 1, 2, 1033, 0, 0, ARMImpOpBase + 0, 3028, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4471 = tREV { 4470, 3, 0, 2, 453, 1, 1, ARMImpOpBase + 1, 584, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4470 = tPUSH { 4469, 3, 0, 2, 425, 1, 1, ARMImpOpBase + 1, 584, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // Inst #4469 = tPOP { 4468, 3, 1, 2, 1079, 0, 0, ARMImpOpBase + 0, 3071, 0|(1ULL<<MCID::NotDuplicable), 0xc80ULL }, // Inst #4468 = tPICADD { 4467, 6, 2, 2, 1081, 0, 0, ARMImpOpBase + 0, 2972, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4467 = tORR { 4466, 5, 2, 2, 873, 0, 0, ARMImpOpBase + 0, 3066, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4466 = tMVN { 4465, 6, 2, 2, 884, 0, 0, ARMImpOpBase + 0, 3060, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4465 = tMUL { 4464, 4, 1, 2, 1028, 0, 0, ARMImpOpBase + 0, 837, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4464 = tMOVr { 4463, 5, 2, 2, 1029, 0, 0, ARMImpOpBase + 0, 3055, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4463 = tMOVi8 { 4462, 2, 1, 2, 1087, 0, 1, ARMImpOpBase + 0, 587, 0|(1ULL<<MCID::MoveReg), 0xc80ULL }, // Inst #4462 = tMOVSr { 4461, 6, 2, 2, 882, 0, 0, ARMImpOpBase + 0, 2972, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4461 = tLSRrr { 4460, 6, 2, 2, 1082, 0, 0, ARMImpOpBase + 0, 2978, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4460 = tLSRri { 4459, 6, 2, 2, 882, 0, 0, ARMImpOpBase + 0, 2972, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4459 = tLSLrr { 4458, 6, 2, 2, 1082, 0, 0, ARMImpOpBase + 0, 2978, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4458 = tLSLri { 4457, 5, 1, 2, 1262, 0, 0, ARMImpOpBase + 0, 3050, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8aULL }, // Inst #4457 = tLDRspi { 4456, 5, 1, 2, 396, 0, 0, ARMImpOpBase + 0, 3041, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc89ULL }, // Inst #4456 = tLDRr { 4455, 4, 1, 2, 1232, 0, 0, ARMImpOpBase + 0, 3046, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8aULL }, // Inst #4455 = tLDRpci { 4454, 5, 1, 2, 907, 0, 0, ARMImpOpBase + 0, 3036, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc89ULL }, // Inst #4454 = tLDRi { 4453, 5, 1, 2, 402, 0, 0, ARMImpOpBase + 0, 3041, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc88ULL }, // Inst #4453 = tLDRSH { 4452, 5, 1, 2, 402, 0, 0, ARMImpOpBase + 0, 3041, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc87ULL }, // Inst #4452 = tLDRSB { 4451, 5, 1, 2, 395, 0, 0, ARMImpOpBase + 0, 3041, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc88ULL }, // Inst #4451 = tLDRHr { 4450, 5, 1, 2, 906, 0, 0, ARMImpOpBase + 0, 3036, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc88ULL }, // Inst #4450 = tLDRHi { 4449, 5, 1, 2, 395, 0, 0, ARMImpOpBase + 0, 3041, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc87ULL }, // Inst #4449 = tLDRBr { 4448, 5, 1, 2, 906, 0, 0, ARMImpOpBase + 0, 3036, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc87ULL }, // Inst #4448 = tLDRBi { 4447, 4, 0, 2, 1019, 0, 0, ARMImpOpBase + 0, 3032, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // Inst #4447 = tLDMIA { 4446, 2, 0, 12, 1040, 0, 10, ARMImpOpBase + 223, 587, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4446 = tInt_eh_sjlj_setjmp { 4445, 2, 0, 10, 1040, 0, 3, ARMImpOpBase + 5, 587, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #4445 = tInt_eh_sjlj_longjmp { 4444, 2, 0, 12, 852, 0, 3, ARMImpOpBase + 220, 152, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #4444 = tInt_WIN_eh_sjlj_longjmp { 4443, 1, 0, 2, 1078, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4443 = tHLT { 4442, 3, 0, 2, 1220, 0, 0, ARMImpOpBase + 0, 858, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4442 = tHINT { 4441, 6, 2, 2, 1081, 0, 0, ARMImpOpBase + 0, 2972, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4441 = tEOR { 4440, 2, 0, 2, 1086, 0, 0, ARMImpOpBase + 0, 13, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4440 = tCPS { 4439, 4, 0, 2, 1084, 0, 1, ARMImpOpBase + 0, 3028, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4439 = tCMPr { 4438, 4, 0, 2, 1085, 0, 1, ARMImpOpBase + 0, 563, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4438 = tCMPi8 { 4437, 4, 0, 2, 1084, 0, 1, ARMImpOpBase + 0, 837, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4437 = tCMPhir { 4436, 4, 0, 2, 1084, 0, 1, ARMImpOpBase + 0, 3028, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4436 = tCMNz { 4435, 2, 0, 2, 1083, 0, 0, ARMImpOpBase + 0, 3026, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4435 = tCBZ { 4434, 2, 0, 2, 1083, 0, 0, ARMImpOpBase + 0, 3026, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4434 = tCBNZ { 4433, 3, 0, 2, 1093, 0, 0, ARMImpOpBase + 0, 545, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4433 = tBcc { 4432, 3, 0, 2, 1093, 0, 0, ARMImpOpBase + 0, 535, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4432 = tBXNS { 4431, 3, 0, 2, 1093, 0, 0, ARMImpOpBase + 0, 535, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4431 = tBX { 4430, 3, 0, 2, 1094, 1, 1, ARMImpOpBase + 3, 3023, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4430 = tBLXr { 4429, 3, 0, 4, 857, 1, 1, ARMImpOpBase + 3, 431, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4429 = tBLXi { 4428, 3, 0, 2, 1094, 1, 1, ARMImpOpBase + 3, 3020, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4428 = tBLXNSr { 4427, 3, 0, 4, 857, 1, 1, ARMImpOpBase + 3, 431, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4427 = tBL { 4426, 1, 0, 2, 1039, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4426 = tBKPT { 4425, 6, 2, 2, 1081, 0, 0, ARMImpOpBase + 0, 2972, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4425 = tBIC { 4424, 3, 0, 2, 1093, 0, 0, ARMImpOpBase + 0, 545, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL }, // Inst #4424 = tB { 4423, 6, 2, 2, 882, 0, 0, ARMImpOpBase + 0, 2972, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4423 = tASRrr { 4422, 6, 2, 2, 1082, 0, 0, ARMImpOpBase + 0, 2978, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4422 = tASRri { 4421, 6, 2, 2, 1081, 0, 0, ARMImpOpBase + 0, 2972, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4421 = tAND { 4420, 4, 1, 2, 1080, 0, 0, ARMImpOpBase + 0, 3016, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4420 = tADR { 4419, 5, 1, 2, 1280, 0, 0, ARMImpOpBase + 0, 3011, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4419 = tADDspr { 4418, 5, 1, 2, 1275, 0, 0, ARMImpOpBase + 0, 3006, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4418 = tADDspi { 4417, 6, 2, 2, 1079, 0, 0, ARMImpOpBase + 0, 3000, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4417 = tADDrr { 4416, 5, 1, 2, 1281, 0, 0, ARMImpOpBase + 0, 2995, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4416 = tADDrSPi { 4415, 5, 1, 2, 1280, 0, 0, ARMImpOpBase + 0, 2990, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4415 = tADDrSP { 4414, 6, 2, 2, 1110, 0, 0, ARMImpOpBase + 0, 2984, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4414 = tADDi8 { 4413, 6, 2, 2, 1110, 0, 0, ARMImpOpBase + 0, 2978, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4413 = tADDi3 { 4412, 5, 1, 2, 1280, 0, 0, ARMImpOpBase + 0, 277, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4412 = tADDhirr { 4411, 6, 2, 2, 1079, 1, 0, ARMImpOpBase + 0, 2972, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x80c80ULL }, // Inst #4411 = tADC { 4410, 3, 1, 4, 1286, 0, 0, ARMImpOpBase + 0, 511, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4410 = t2WLS { 4409, 5, 1, 4, 898, 0, 0, ARMImpOpBase + 0, 494, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4409 = t2UXTH { 4408, 5, 1, 4, 353, 0, 0, ARMImpOpBase + 0, 494, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4408 = t2UXTB16 { 4407, 5, 1, 4, 898, 0, 0, ARMImpOpBase + 0, 494, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4407 = t2UXTB { 4406, 6, 1, 4, 1101, 0, 0, ARMImpOpBase + 0, 2879, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4406 = t2UXTAH { 4405, 6, 1, 4, 1102, 0, 0, ARMImpOpBase + 0, 2879, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4405 = t2UXTAB16 { 4404, 6, 1, 4, 1101, 0, 0, ARMImpOpBase + 0, 2879, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4404 = t2UXTAB { 4403, 5, 1, 4, 886, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4403 = t2USUB8 { 4402, 5, 1, 4, 886, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4402 = t2USUB16 { 4401, 5, 1, 4, 365, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4401 = t2USAX { 4400, 5, 1, 4, 363, 0, 0, ARMImpOpBase + 0, 2917, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4400 = t2USAT16 { 4399, 6, 1, 4, 363, 0, 0, ARMImpOpBase + 0, 2911, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4399 = t2USAT { 4398, 6, 1, 4, 685, 0, 0, ARMImpOpBase + 0, 2831, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4398 = t2USADA8 { 4397, 5, 1, 4, 1247, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4397 = t2USAD8 { 4396, 5, 1, 4, 890, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4396 = t2UQSUB8 { 4395, 5, 1, 4, 890, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4395 = t2UQSUB16 { 4394, 5, 1, 4, 892, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4394 = t2UQSAX { 4393, 5, 1, 4, 892, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4393 = t2UQASX { 4392, 5, 1, 4, 890, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4392 = t2UQADD8 { 4391, 5, 1, 4, 890, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4391 = t2UQADD16 { 4390, 6, 2, 4, 383, 0, 0, ARMImpOpBase + 0, 2831, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL }, // Inst #4390 = t2UMULL { 4389, 8, 2, 4, 384, 0, 0, ARMImpOpBase + 0, 2903, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4389 = t2UMLAL { 4388, 8, 2, 4, 384, 0, 0, ARMImpOpBase + 0, 2903, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4388 = t2UMAAL { 4387, 5, 1, 4, 888, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4387 = t2UHSUB8 { 4386, 5, 1, 4, 888, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4386 = t2UHSUB16 { 4385, 5, 1, 4, 368, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4385 = t2UHSAX { 4384, 5, 1, 4, 368, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4384 = t2UHASX { 4383, 5, 1, 4, 888, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4383 = t2UHADD8 { 4382, 5, 1, 4, 888, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4382 = t2UHADD16 { 4381, 5, 1, 4, 686, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4381 = t2UDIV { 4380, 1, 0, 4, 1038, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4380 = t2UDF { 4379, 6, 1, 4, 896, 0, 0, ARMImpOpBase + 0, 2897, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4379 = t2UBFX { 4378, 5, 1, 4, 365, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4378 = t2UASX { 4377, 5, 1, 4, 886, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4377 = t2UADD8 { 4376, 5, 1, 4, 886, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4376 = t2UADD16 { 4375, 4, 1, 4, 1058, 0, 0, ARMImpOpBase + 0, 2968, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4375 = t2TTT { 4374, 4, 1, 4, 1058, 0, 0, ARMImpOpBase + 0, 2968, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4374 = t2TTAT { 4373, 4, 1, 4, 1058, 0, 0, ARMImpOpBase + 0, 2968, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4373 = t2TTA { 4372, 4, 1, 4, 1058, 0, 0, ARMImpOpBase + 0, 2968, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4372 = t2TT { 4371, 5, 0, 4, 1243, 0, 1, ARMImpOpBase + 0, 479, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4371 = t2TSTrs { 4370, 4, 0, 4, 1074, 0, 1, ARMImpOpBase + 0, 2755, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4370 = t2TSTrr { 4369, 4, 0, 4, 310, 0, 1, ARMImpOpBase + 0, 2723, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4369 = t2TSTri { 4368, 3, 0, 4, 0, 0, 0, ARMImpOpBase + 0, 858, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4368 = t2TSB { 4367, 5, 0, 4, 1243, 0, 1, ARMImpOpBase + 0, 479, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4367 = t2TEQrs { 4366, 4, 0, 4, 1074, 0, 1, ARMImpOpBase + 0, 2755, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4366 = t2TEQrr { 4365, 4, 0, 4, 310, 0, 1, ARMImpOpBase + 0, 2723, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4365 = t2TEQri { 4364, 4, 0, 4, 1236, 0, 0, ARMImpOpBase + 0, 2964, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4364 = t2TBH { 4363, 4, 0, 4, 1236, 0, 0, ARMImpOpBase + 0, 2964, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4363 = t2TBB { 4362, 5, 1, 4, 898, 0, 0, ARMImpOpBase + 0, 494, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4362 = t2SXTH { 4361, 5, 1, 4, 353, 0, 0, ARMImpOpBase + 0, 494, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4361 = t2SXTB16 { 4360, 5, 1, 4, 898, 0, 0, ARMImpOpBase + 0, 494, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4360 = t2SXTB { 4359, 6, 1, 4, 901, 0, 0, ARMImpOpBase + 0, 2879, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4359 = t2SXTAH { 4358, 6, 1, 4, 369, 0, 0, ARMImpOpBase + 0, 2879, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4358 = t2SXTAB16 { 4357, 6, 1, 4, 901, 0, 0, ARMImpOpBase + 0, 2879, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4357 = t2SXTAB { 4356, 5, 1, 4, 1, 0, 0, ARMImpOpBase + 0, 2718, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4356 = t2SUBspImm12 { 4355, 6, 1, 4, 1, 0, 0, ARMImpOpBase + 0, 2712, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4355 = t2SUBspImm { 4354, 7, 1, 4, 1237, 0, 0, ARMImpOpBase + 0, 2705, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4354 = t2SUBrs { 4353, 6, 1, 4, 1073, 0, 0, ARMImpOpBase + 0, 2699, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4353 = t2SUBrr { 4352, 5, 1, 4, 1279, 0, 0, ARMImpOpBase + 0, 2694, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4352 = t2SUBri12 { 4351, 6, 1, 4, 1278, 0, 0, ARMImpOpBase + 0, 2688, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4351 = t2SUBri { 4350, 3, 0, 4, 1060, 0, 1, ARMImpOpBase + 66, 858, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL }, // Inst #4350 = t2SUBS_PC_LR { 4349, 6, 0, 4, 432, 0, 0, ARMImpOpBase + 0, 2818, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4349 = t2STRs { 4348, 5, 0, 4, 431, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4348 = t2STRi8 { 4347, 5, 0, 4, 1075, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4347 = t2STRi12 { 4346, 6, 1, 4, 945, 0, 0, ARMImpOpBase + 0, 2958, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4346 = t2STR_PRE { 4345, 6, 1, 4, 442, 0, 0, ARMImpOpBase + 0, 2958, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4345 = t2STR_POST { 4344, 5, 0, 4, 446, 0, 0, ARMImpOpBase + 0, 2781, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // Inst #4344 = t2STRT { 4343, 6, 0, 4, 434, 0, 0, ARMImpOpBase + 0, 2939, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4343 = t2STRHs { 4342, 5, 0, 4, 433, 0, 0, ARMImpOpBase + 0, 2781, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4342 = t2STRHi8 { 4341, 5, 0, 4, 1076, 0, 0, ARMImpOpBase + 0, 2781, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4341 = t2STRHi12 { 4340, 6, 1, 4, 945, 0, 0, ARMImpOpBase + 0, 2933, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4340 = t2STRH_PRE { 4339, 6, 1, 4, 443, 0, 0, ARMImpOpBase + 0, 2933, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4339 = t2STRH_POST { 4338, 5, 0, 4, 445, 0, 0, ARMImpOpBase + 0, 2781, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // Inst #4338 = t2STRHT { 4337, 5, 1, 4, 1229, 0, 0, ARMImpOpBase + 0, 2922, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4337 = t2STREXH { 4336, 6, 1, 4, 731, 0, 0, ARMImpOpBase + 0, 2927, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4336 = t2STREXD { 4335, 5, 1, 4, 1229, 0, 0, ARMImpOpBase + 0, 2922, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4335 = t2STREXB { 4334, 6, 1, 4, 1229, 0, 0, ARMImpOpBase + 0, 2952, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc94ULL }, // Inst #4334 = t2STREX { 4333, 6, 0, 4, 448, 0, 0, ARMImpOpBase + 0, 2803, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc91ULL }, // Inst #4333 = t2STRDi8 { 4332, 7, 1, 4, 947, 0, 0, ARMImpOpBase + 0, 2945, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc91ULL }, // Inst #4332 = t2STRD_PRE { 4331, 7, 1, 4, 449, 0, 0, ARMImpOpBase + 0, 2945, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc91ULL }, // Inst #4331 = t2STRD_POST { 4330, 6, 0, 4, 434, 0, 0, ARMImpOpBase + 0, 2939, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4330 = t2STRBs { 4329, 5, 0, 4, 433, 0, 0, ARMImpOpBase + 0, 2781, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4329 = t2STRBi8 { 4328, 5, 0, 4, 1076, 0, 0, ARMImpOpBase + 0, 2781, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4328 = t2STRBi12 { 4327, 6, 1, 4, 946, 0, 0, ARMImpOpBase + 0, 2933, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4327 = t2STRB_PRE { 4326, 6, 1, 4, 954, 0, 0, ARMImpOpBase + 0, 2933, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4326 = t2STRB_POST { 4325, 5, 0, 4, 939, 0, 0, ARMImpOpBase + 0, 2781, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // Inst #4325 = t2STRBT { 4324, 5, 1, 4, 1077, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4324 = t2STMIA_UPD { 4323, 4, 0, 4, 1026, 0, 0, ARMImpOpBase + 0, 873, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4323 = t2STMIA { 4322, 5, 1, 4, 1077, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4322 = t2STMDB_UPD { 4321, 4, 0, 4, 1026, 0, 0, ARMImpOpBase + 0, 873, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4321 = t2STMDB { 4320, 4, 0, 4, 1265, 0, 0, ARMImpOpBase + 0, 2772, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4320 = t2STLH { 4319, 5, 1, 4, 1265, 0, 0, ARMImpOpBase + 0, 2922, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4319 = t2STLEXH { 4318, 6, 1, 4, 733, 0, 0, ARMImpOpBase + 0, 2927, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4318 = t2STLEXD { 4317, 5, 1, 4, 1265, 0, 0, ARMImpOpBase + 0, 2922, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4317 = t2STLEXB { 4316, 5, 1, 4, 1265, 0, 0, ARMImpOpBase + 0, 2922, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4316 = t2STLEX { 4315, 4, 0, 4, 1265, 0, 0, ARMImpOpBase + 0, 2772, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4315 = t2STLB { 4314, 4, 0, 4, 1265, 0, 0, ARMImpOpBase + 0, 2772, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4314 = t2STL { 4313, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4313 = t2STC_PRE { 4312, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4312 = t2STC_POST { 4311, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 895, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4311 = t2STC_OPTION { 4310, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4310 = t2STC_OFFSET { 4309, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4309 = t2STCL_PRE { 4308, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4308 = t2STCL_POST { 4307, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 895, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4307 = t2STCL_OPTION { 4306, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4306 = t2STCL_OFFSET { 4305, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4305 = t2STC2_PRE { 4304, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4304 = t2STC2_POST { 4303, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 895, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4303 = t2STC2_OPTION { 4302, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4302 = t2STC2_OFFSET { 4301, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4301 = t2STC2L_PRE { 4300, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4300 = t2STC2L_POST { 4299, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 895, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4299 = t2STC2L_OPTION { 4298, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4298 = t2STC2L_OFFSET { 4297, 5, 1, 4, 886, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4297 = t2SSUB8 { 4296, 5, 1, 4, 886, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4296 = t2SSUB16 { 4295, 5, 1, 4, 365, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4295 = t2SSAX { 4294, 5, 1, 4, 363, 0, 0, ARMImpOpBase + 0, 2917, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4294 = t2SSAT16 { 4293, 6, 1, 4, 363, 0, 0, ARMImpOpBase + 0, 2911, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4293 = t2SSAT { 4292, 3, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 858, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4292 = t2SRSIA_UPD { 4291, 3, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 858, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4291 = t2SRSIA { 4290, 3, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 858, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4290 = t2SRSDB_UPD { 4289, 3, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 858, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4289 = t2SRSDB { 4288, 5, 1, 4, 375, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4288 = t2SMUSDX { 4287, 5, 1, 4, 375, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4287 = t2SMUSD { 4286, 5, 1, 4, 374, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4286 = t2SMULWT { 4285, 5, 1, 4, 374, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4285 = t2SMULWB { 4284, 5, 1, 4, 374, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4284 = t2SMULTT { 4283, 5, 1, 4, 374, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4283 = t2SMULTB { 4282, 6, 2, 4, 383, 0, 0, ARMImpOpBase + 0, 2831, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL }, // Inst #4282 = t2SMULL { 4281, 5, 1, 4, 374, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4281 = t2SMULBT { 4280, 5, 1, 4, 374, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4280 = t2SMULBB { 4279, 5, 1, 4, 377, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4279 = t2SMUADX { 4278, 5, 1, 4, 377, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4278 = t2SMUAD { 4277, 5, 1, 4, 373, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4277 = t2SMMULR { 4276, 5, 1, 4, 373, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4276 = t2SMMUL { 4275, 6, 1, 4, 1100, 0, 0, ARMImpOpBase + 0, 2831, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4275 = t2SMMLSR { 4274, 6, 1, 4, 1100, 0, 0, ARMImpOpBase + 0, 2831, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4274 = t2SMMLS { 4273, 6, 1, 4, 1100, 0, 0, ARMImpOpBase + 0, 2831, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4273 = t2SMMLAR { 4272, 6, 1, 4, 1100, 0, 0, ARMImpOpBase + 0, 2831, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4272 = t2SMMLA { 4271, 8, 2, 4, 1032, 0, 0, ARMImpOpBase + 0, 2903, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4271 = t2SMLSLDX { 4270, 8, 2, 4, 1032, 0, 0, ARMImpOpBase + 0, 2903, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4270 = t2SMLSLD { 4269, 6, 1, 4, 380, 0, 0, ARMImpOpBase + 0, 2831, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4269 = t2SMLSDX { 4268, 6, 1, 4, 380, 0, 0, ARMImpOpBase + 0, 2831, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4268 = t2SMLSD { 4267, 6, 1, 4, 379, 0, 0, ARMImpOpBase + 0, 2831, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4267 = t2SMLAWT { 4266, 6, 1, 4, 379, 0, 0, ARMImpOpBase + 0, 2831, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4266 = t2SMLAWB { 4265, 6, 1, 4, 379, 0, 0, ARMImpOpBase + 0, 2831, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4265 = t2SMLATT { 4264, 6, 1, 4, 379, 0, 0, ARMImpOpBase + 0, 2831, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4264 = t2SMLATB { 4263, 8, 2, 4, 1032, 0, 0, ARMImpOpBase + 0, 2903, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4263 = t2SMLALTT { 4262, 8, 2, 4, 1032, 0, 0, ARMImpOpBase + 0, 2903, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4262 = t2SMLALTB { 4261, 8, 2, 4, 1032, 0, 0, ARMImpOpBase + 0, 2903, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4261 = t2SMLALDX { 4260, 8, 2, 4, 1032, 0, 0, ARMImpOpBase + 0, 2903, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4260 = t2SMLALD { 4259, 8, 2, 4, 1032, 0, 0, ARMImpOpBase + 0, 2903, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4259 = t2SMLALBT { 4258, 8, 2, 4, 1032, 0, 0, ARMImpOpBase + 0, 2903, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4258 = t2SMLALBB { 4257, 8, 2, 4, 1032, 0, 0, ARMImpOpBase + 0, 2903, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4257 = t2SMLAL { 4256, 6, 1, 4, 381, 0, 0, ARMImpOpBase + 0, 2831, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4256 = t2SMLADX { 4255, 6, 1, 4, 381, 0, 0, ARMImpOpBase + 0, 2831, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4255 = t2SMLAD { 4254, 6, 1, 4, 379, 0, 0, ARMImpOpBase + 0, 2831, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4254 = t2SMLABT { 4253, 6, 1, 4, 379, 0, 0, ARMImpOpBase + 0, 2831, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4253 = t2SMLABB { 4252, 3, 0, 4, 1219, 1, 0, ARMImpOpBase + 54, 858, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4252 = t2SMC { 4251, 5, 1, 4, 888, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4251 = t2SHSUB8 { 4250, 5, 1, 4, 888, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4250 = t2SHSUB16 { 4249, 5, 1, 4, 368, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4249 = t2SHSAX { 4248, 5, 1, 4, 368, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4248 = t2SHASX { 4247, 5, 1, 4, 888, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4247 = t2SHADD8 { 4246, 5, 1, 4, 888, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4246 = t2SHADD16 { 4245, 2, 0, 4, 1058, 0, 0, ARMImpOpBase + 0, 540, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4245 = t2SG { 4244, 1, 0, 2, 1078, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4244 = t2SETPAN { 4243, 5, 1, 4, 358, 0, 0, ARMImpOpBase + 0, 159, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4243 = t2SEL { 4242, 5, 1, 4, 686, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4242 = t2SDIV { 4241, 6, 1, 4, 896, 0, 0, ARMImpOpBase + 0, 2897, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4241 = t2SBFX { 4240, 7, 1, 4, 1269, 1, 1, ARMImpOpBase + 63, 2681, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // Inst #4240 = t2SBCrs { 4239, 6, 1, 4, 1270, 1, 1, ARMImpOpBase + 63, 2675, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // Inst #4239 = t2SBCrr { 4238, 6, 1, 4, 694, 1, 1, ARMImpOpBase + 63, 2669, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // Inst #4238 = t2SBCri { 4237, 0, 0, 4, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4237 = t2SB { 4236, 5, 1, 4, 365, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4236 = t2SASX { 4235, 5, 1, 4, 886, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4235 = t2SADD8 { 4234, 5, 1, 4, 886, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4234 = t2SADD16 { 4233, 7, 1, 4, 708, 0, 0, ARMImpOpBase + 0, 2681, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4233 = t2RSBrs { 4232, 6, 1, 4, 1271, 0, 0, ARMImpOpBase + 0, 2675, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4232 = t2RSBrr { 4231, 6, 1, 4, 1072, 0, 0, ARMImpOpBase + 0, 2669, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4231 = t2RSBri { 4230, 5, 1, 4, 1244, 1, 0, ARMImpOpBase + 0, 2863, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4230 = t2RRX { 4229, 6, 1, 4, 1066, 0, 0, ARMImpOpBase + 0, 2675, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4229 = t2RORrr { 4228, 6, 1, 4, 875, 0, 0, ARMImpOpBase + 0, 2669, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4228 = t2RORri { 4227, 3, 0, 4, 730, 0, 1, ARMImpOpBase + 66, 535, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4227 = t2RFEIAW { 4226, 3, 0, 4, 730, 0, 1, ARMImpOpBase + 66, 535, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4226 = t2RFEIA { 4225, 3, 0, 4, 730, 0, 1, ARMImpOpBase + 66, 535, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4225 = t2RFEDBW { 4224, 3, 0, 4, 730, 0, 1, ARMImpOpBase + 66, 535, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4224 = t2RFEDB { 4223, 4, 1, 4, 1071, 0, 0, ARMImpOpBase + 0, 2755, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4223 = t2REVSH { 4222, 4, 1, 4, 1071, 0, 0, ARMImpOpBase + 0, 2755, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4222 = t2REV16 { 4221, 4, 1, 4, 1071, 0, 0, ARMImpOpBase + 0, 2755, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4221 = t2REV { 4220, 4, 1, 4, 1248, 0, 0, ARMImpOpBase + 0, 2755, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4220 = t2RBIT { 4219, 5, 1, 4, 890, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4219 = t2QSUB8 { 4218, 5, 1, 4, 890, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4218 = t2QSUB16 { 4217, 5, 1, 4, 890, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4217 = t2QSUB { 4216, 5, 1, 4, 892, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4216 = t2QSAX { 4215, 5, 1, 4, 362, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4215 = t2QDSUB { 4214, 5, 1, 4, 362, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4214 = t2QDADD { 4213, 5, 1, 4, 892, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4213 = t2QASX { 4212, 5, 1, 4, 890, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4212 = t2QADD8 { 4211, 5, 1, 4, 890, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4211 = t2QADD16 { 4210, 5, 1, 4, 890, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4210 = t2QADD { 4209, 5, 0, 4, 1234, 0, 0, ARMImpOpBase + 0, 2889, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4209 = t2PLIs { 4208, 3, 0, 4, 1231, 0, 0, ARMImpOpBase + 0, 2894, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc90ULL }, // Inst #4208 = t2PLIpci { 4207, 4, 0, 4, 1233, 0, 0, ARMImpOpBase + 0, 2885, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4207 = t2PLIi8 { 4206, 4, 0, 4, 1233, 0, 0, ARMImpOpBase + 0, 2885, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4206 = t2PLIi12 { 4205, 5, 0, 4, 1234, 0, 0, ARMImpOpBase + 0, 2889, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4205 = t2PLDs { 4204, 3, 0, 4, 1231, 0, 0, ARMImpOpBase + 0, 2894, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc90ULL }, // Inst #4204 = t2PLDpci { 4203, 4, 0, 4, 1233, 0, 0, ARMImpOpBase + 0, 2885, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4203 = t2PLDi8 { 4202, 4, 0, 4, 1233, 0, 0, ARMImpOpBase + 0, 2885, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4202 = t2PLDi12 { 4201, 5, 0, 4, 935, 0, 0, ARMImpOpBase + 0, 2889, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4201 = t2PLDWs { 4200, 4, 0, 4, 1233, 0, 0, ARMImpOpBase + 0, 2885, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4200 = t2PLDWi8 { 4199, 4, 0, 4, 1233, 0, 0, ARMImpOpBase + 0, 2885, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4199 = t2PLDWi12 { 4198, 6, 1, 4, 1249, 0, 0, ARMImpOpBase + 0, 2879, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4198 = t2PKHTB { 4197, 6, 1, 4, 1249, 0, 0, ARMImpOpBase + 0, 2879, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4197 = t2PKHBT { 4196, 5, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 2874, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4196 = t2PACG { 4195, 0, 0, 4, 0, 2, 1, ARMImpOpBase + 217, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4195 = t2PACBTI { 4194, 0, 0, 4, 0, 2, 1, ARMImpOpBase + 217, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4194 = t2PAC { 4193, 7, 1, 4, 1239, 0, 0, ARMImpOpBase + 0, 2681, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4193 = t2ORRrs { 4192, 6, 1, 4, 1070, 0, 0, ARMImpOpBase + 0, 2675, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4192 = t2ORRrr { 4191, 6, 1, 4, 696, 0, 0, ARMImpOpBase + 0, 2669, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4191 = t2ORRri { 4190, 7, 1, 4, 1240, 0, 0, ARMImpOpBase + 0, 2681, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4190 = t2ORNrs { 4189, 6, 1, 4, 1274, 0, 0, ARMImpOpBase + 0, 2675, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4189 = t2ORNrr { 4188, 6, 1, 4, 46, 0, 0, ARMImpOpBase + 0, 2669, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4188 = t2ORNri { 4187, 6, 1, 4, 700, 0, 0, ARMImpOpBase + 0, 2868, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4187 = t2MVNs { 4186, 5, 1, 4, 699, 0, 0, ARMImpOpBase + 0, 2863, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4186 = t2MVNr { 4185, 5, 1, 4, 698, 0, 0, ARMImpOpBase + 0, 2837, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL }, // Inst #4185 = t2MVNi { 4184, 5, 1, 4, 1099, 0, 0, ARMImpOpBase + 0, 2858, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL }, // Inst #4184 = t2MUL { 4183, 4, 0, 4, 1030, 0, 0, ARMImpOpBase + 0, 2854, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4183 = t2MSRbanked { 4182, 4, 0, 4, 1030, 0, 1, ARMImpOpBase + 0, 2854, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4182 = t2MSR_M { 4181, 4, 0, 4, 1030, 0, 1, ARMImpOpBase + 0, 2854, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4181 = t2MSR_AR { 4180, 3, 1, 4, 1030, 0, 0, ARMImpOpBase + 0, 535, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4180 = t2MRSsys_AR { 4179, 4, 1, 4, 1030, 0, 0, ARMImpOpBase + 0, 2723, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4179 = t2MRSbanked { 4178, 4, 1, 4, 1030, 0, 0, ARMImpOpBase + 0, 2723, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4178 = t2MRS_M { 4177, 3, 1, 4, 1030, 0, 0, ARMImpOpBase + 0, 535, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4177 = t2MRS_AR { 4176, 7, 2, 4, 1035, 0, 0, ARMImpOpBase + 0, 2847, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4176 = t2MRRC2 { 4175, 7, 2, 4, 1035, 0, 0, ARMImpOpBase + 0, 2847, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4175 = t2MRRC { 4174, 8, 1, 4, 1096, 0, 0, ARMImpOpBase + 0, 1033, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4174 = t2MRC2 { 4173, 8, 1, 4, 1096, 0, 0, ARMImpOpBase + 0, 1033, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4173 = t2MRC { 4172, 4, 1, 4, 692, 0, 1, ARMImpOpBase + 0, 2755, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4172 = t2MOVsrl_glue { 4171, 4, 1, 4, 692, 0, 1, ARMImpOpBase + 0, 2755, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4171 = t2MOVsra_glue { 4170, 5, 1, 4, 880, 0, 0, ARMImpOpBase + 0, 2842, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4170 = t2MOVr { 4169, 4, 1, 4, 683, 0, 0, ARMImpOpBase + 0, 2723, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL }, // Inst #4169 = t2MOVi16 { 4168, 5, 1, 4, 683, 0, 0, ARMImpOpBase + 0, 2837, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL }, // Inst #4168 = t2MOVi { 4167, 5, 1, 4, 879, 0, 0, ARMImpOpBase + 0, 464, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4167 = t2MOVTi16 { 4166, 6, 1, 4, 376, 0, 0, ARMImpOpBase + 0, 2831, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4166 = t2MLS { 4165, 6, 1, 4, 376, 0, 0, ARMImpOpBase + 0, 2831, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4165 = t2MLA { 4164, 7, 0, 4, 1096, 0, 0, ARMImpOpBase + 0, 2824, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4164 = t2MCRR2 { 4163, 7, 0, 4, 1096, 0, 0, ARMImpOpBase + 0, 2824, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4163 = t2MCRR { 4162, 8, 0, 4, 1096, 0, 0, ARMImpOpBase + 0, 966, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4162 = t2MCR2 { 4161, 8, 0, 4, 1096, 0, 0, ARMImpOpBase + 0, 966, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4161 = t2MCR { 4160, 6, 1, 4, 1066, 0, 0, ARMImpOpBase + 0, 2675, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4160 = t2LSRrr { 4159, 6, 1, 4, 1065, 0, 0, ARMImpOpBase + 0, 2669, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4159 = t2LSRri { 4158, 6, 1, 4, 1066, 0, 0, ARMImpOpBase + 0, 2675, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4158 = t2LSLrr { 4157, 6, 1, 4, 1065, 0, 0, ARMImpOpBase + 0, 2669, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4157 = t2LSLri { 4156, 3, 1, 4, 1288, 0, 0, ARMImpOpBase + 0, 455, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4156 = t2LEUpdate { 4155, 1, 0, 4, 1287, 0, 0, ARMImpOpBase + 0, 193, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4155 = t2LE { 4154, 6, 1, 4, 391, 0, 0, ARMImpOpBase + 0, 2818, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8fULL }, // Inst #4154 = t2LDRs { 4153, 4, 1, 4, 1230, 0, 0, ARMImpOpBase + 0, 2814, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL }, // Inst #4153 = t2LDRpci { 4152, 5, 1, 4, 390, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8eULL }, // Inst #4152 = t2LDRi8 { 4151, 5, 1, 4, 1107, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8bULL }, // Inst #4151 = t2LDRi12 { 4150, 6, 2, 4, 921, 0, 0, ARMImpOpBase + 0, 908, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4150 = t2LDR_PRE { 4149, 6, 2, 4, 411, 0, 0, ARMImpOpBase + 0, 908, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4149 = t2LDR_POST { 4148, 5, 1, 4, 413, 0, 0, ARMImpOpBase + 0, 2781, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // Inst #4148 = t2LDRT { 4147, 6, 1, 4, 401, 0, 0, ARMImpOpBase + 0, 2790, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4147 = t2LDRSHs { 4146, 4, 1, 4, 1224, 0, 0, ARMImpOpBase + 0, 2786, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL }, // Inst #4146 = t2LDRSHpci { 4145, 5, 1, 4, 400, 0, 0, ARMImpOpBase + 0, 914, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4145 = t2LDRSHi8 { 4144, 5, 1, 4, 400, 0, 0, ARMImpOpBase + 0, 914, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4144 = t2LDRSHi12 { 4143, 6, 2, 4, 920, 0, 0, ARMImpOpBase + 0, 908, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4143 = t2LDRSH_PRE { 4142, 6, 2, 4, 415, 0, 0, ARMImpOpBase + 0, 908, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4142 = t2LDRSH_POST { 4141, 5, 1, 4, 416, 0, 0, ARMImpOpBase + 0, 2781, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // Inst #4141 = t2LDRSHT { 4140, 6, 1, 4, 401, 0, 0, ARMImpOpBase + 0, 2790, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4140 = t2LDRSBs { 4139, 4, 1, 4, 1224, 0, 0, ARMImpOpBase + 0, 2786, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL }, // Inst #4139 = t2LDRSBpci { 4138, 5, 1, 4, 400, 0, 0, ARMImpOpBase + 0, 914, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4138 = t2LDRSBi8 { 4137, 5, 1, 4, 400, 0, 0, ARMImpOpBase + 0, 914, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4137 = t2LDRSBi12 { 4136, 6, 2, 4, 920, 0, 0, ARMImpOpBase + 0, 908, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4136 = t2LDRSB_PRE { 4135, 6, 2, 4, 415, 0, 0, ARMImpOpBase + 0, 908, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4135 = t2LDRSB_POST { 4134, 5, 1, 4, 416, 0, 0, ARMImpOpBase + 0, 2781, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // Inst #4134 = t2LDRSBT { 4133, 6, 1, 4, 393, 0, 0, ARMImpOpBase + 0, 2790, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4133 = t2LDRHs { 4132, 4, 1, 4, 1223, 0, 0, ARMImpOpBase + 0, 2786, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL }, // Inst #4132 = t2LDRHpci { 4131, 5, 1, 4, 392, 0, 0, ARMImpOpBase + 0, 914, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4131 = t2LDRHi8 { 4130, 5, 1, 4, 1106, 0, 0, ARMImpOpBase + 0, 914, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4130 = t2LDRHi12 { 4129, 6, 2, 4, 919, 0, 0, ARMImpOpBase + 0, 908, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4129 = t2LDRH_PRE { 4128, 6, 2, 4, 410, 0, 0, ARMImpOpBase + 0, 908, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4128 = t2LDRH_POST { 4127, 5, 1, 4, 412, 0, 0, ARMImpOpBase + 0, 2781, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // Inst #4127 = t2LDRHT { 4126, 4, 1, 4, 1228, 0, 0, ARMImpOpBase + 0, 2772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4126 = t2LDREXH { 4125, 5, 2, 4, 1025, 0, 0, ARMImpOpBase + 0, 2776, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL }, // Inst #4125 = t2LDREXD { 4124, 4, 1, 4, 1228, 0, 0, ARMImpOpBase + 0, 2772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4124 = t2LDREXB { 4123, 5, 1, 4, 1227, 0, 0, ARMImpOpBase + 0, 2809, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc94ULL }, // Inst #4123 = t2LDREX { 4122, 6, 2, 4, 417, 0, 0, ARMImpOpBase + 0, 2803, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc91ULL }, // Inst #4122 = t2LDRDi8 { 4121, 7, 3, 4, 923, 0, 0, ARMImpOpBase + 0, 2796, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc91ULL }, // Inst #4121 = t2LDRD_PRE { 4120, 7, 3, 4, 420, 0, 0, ARMImpOpBase + 0, 2796, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc91ULL }, // Inst #4120 = t2LDRD_POST { 4119, 6, 1, 4, 393, 0, 0, ARMImpOpBase + 0, 2790, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4119 = t2LDRBs { 4118, 4, 1, 4, 1223, 0, 0, ARMImpOpBase + 0, 2786, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL }, // Inst #4118 = t2LDRBpci { 4117, 5, 1, 4, 392, 0, 0, ARMImpOpBase + 0, 914, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4117 = t2LDRBi8 { 4116, 5, 1, 4, 1106, 0, 0, ARMImpOpBase + 0, 914, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4116 = t2LDRBi12 { 4115, 6, 2, 4, 912, 0, 0, ARMImpOpBase + 0, 908, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4115 = t2LDRB_PRE { 4114, 6, 2, 4, 929, 0, 0, ARMImpOpBase + 0, 908, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4114 = t2LDRB_POST { 4113, 5, 1, 4, 412, 0, 0, ARMImpOpBase + 0, 2781, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // Inst #4113 = t2LDRBT { 4112, 5, 1, 4, 1109, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // Inst #4112 = t2LDMIA_UPD { 4111, 4, 0, 4, 1108, 0, 0, ARMImpOpBase + 0, 873, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // Inst #4111 = t2LDMIA { 4110, 5, 1, 4, 1109, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // Inst #4110 = t2LDMDB_UPD { 4109, 4, 0, 4, 1108, 0, 0, ARMImpOpBase + 0, 873, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // Inst #4109 = t2LDMDB { 4108, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4108 = t2LDC_PRE { 4107, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4107 = t2LDC_POST { 4106, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 895, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4106 = t2LDC_OPTION { 4105, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4105 = t2LDC_OFFSET { 4104, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4104 = t2LDCL_PRE { 4103, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4103 = t2LDCL_POST { 4102, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 895, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4102 = t2LDCL_OPTION { 4101, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4101 = t2LDCL_OFFSET { 4100, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4100 = t2LDC2_PRE { 4099, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4099 = t2LDC2_POST { 4098, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 895, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4098 = t2LDC2_OPTION { 4097, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4097 = t2LDC2_OFFSET { 4096, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4096 = t2LDC2L_PRE { 4095, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4095 = t2LDC2L_POST { 4094, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 895, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4094 = t2LDC2L_OPTION { 4093, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 889, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4093 = t2LDC2L_OFFSET { 4092, 4, 1, 4, 687, 0, 0, ARMImpOpBase + 0, 2772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4092 = t2LDAH { 4091, 4, 1, 4, 687, 0, 0, ARMImpOpBase + 0, 2772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4091 = t2LDAEXH { 4090, 5, 2, 4, 1264, 0, 0, ARMImpOpBase + 0, 2776, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL }, // Inst #4090 = t2LDAEXD { 4089, 4, 1, 4, 687, 0, 0, ARMImpOpBase + 0, 2772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4089 = t2LDAEXB { 4088, 4, 1, 4, 1263, 0, 0, ARMImpOpBase + 0, 2772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4088 = t2LDAEX { 4087, 4, 1, 4, 687, 0, 0, ARMImpOpBase + 0, 2772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4087 = t2LDAB { 4086, 4, 1, 4, 1263, 0, 0, ARMImpOpBase + 0, 2772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4086 = t2LDA { 4085, 2, 0, 12, 1040, 0, 15, ARMImpOpBase + 39, 587, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4085 = t2Int_eh_sjlj_setjmp_nofp { 4084, 2, 0, 12, 1040, 0, 27, ARMImpOpBase + 190, 587, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4084 = t2Int_eh_sjlj_setjmp { 4083, 2, 0, 2, 457, 0, 1, ARMImpOpBase + 189, 13, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4083 = t2IT { 4082, 3, 0, 4, 1095, 0, 0, ARMImpOpBase + 0, 858, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4082 = t2ISB { 4081, 1, 0, 4, 1218, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4081 = t2HVC { 4080, 3, 0, 4, 1037, 0, 0, ARMImpOpBase + 0, 858, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4080 = t2HINT { 4079, 7, 1, 4, 1239, 0, 0, ARMImpOpBase + 0, 2681, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4079 = t2EORrs { 4078, 6, 1, 4, 1273, 0, 0, ARMImpOpBase + 0, 2675, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4078 = t2EORrr { 4077, 6, 1, 4, 696, 0, 0, ARMImpOpBase + 0, 2669, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4077 = t2EORri { 4076, 3, 0, 4, 1095, 0, 0, ARMImpOpBase + 0, 858, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4076 = t2DSB { 4075, 3, 0, 4, 1095, 0, 0, ARMImpOpBase + 0, 858, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4075 = t2DMB { 4074, 2, 1, 4, 1286, 0, 0, ARMImpOpBase + 0, 434, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4074 = t2DLS { 4073, 2, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 540, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4073 = t2DCPS3 { 4072, 2, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 540, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4072 = t2DCPS2 { 4071, 2, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 540, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4071 = t2DCPS1 { 4070, 3, 0, 4, 1059, 0, 0, ARMImpOpBase + 0, 858, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4070 = t2DBG { 4069, 4, 1, 4, 1063, 1, 0, ARMImpOpBase + 0, 2768, 0, 0xc80ULL }, // Inst #4069 = t2CSNEG { 4068, 4, 1, 4, 1063, 1, 0, ARMImpOpBase + 0, 2768, 0, 0xc80ULL }, // Inst #4068 = t2CSINV { 4067, 4, 1, 4, 1063, 1, 0, ARMImpOpBase + 0, 2768, 0, 0xc80ULL }, // Inst #4067 = t2CSINC { 4066, 4, 1, 4, 1063, 1, 0, ARMImpOpBase + 0, 2768, 0, 0xc80ULL }, // Inst #4066 = t2CSEL { 4065, 3, 1, 4, 702, 0, 0, ARMImpOpBase + 0, 315, 0, 0xc80ULL }, // Inst #4065 = t2CRC32W { 4064, 3, 1, 4, 702, 0, 0, ARMImpOpBase + 0, 315, 0, 0xc80ULL }, // Inst #4064 = t2CRC32H { 4063, 3, 1, 4, 702, 0, 0, ARMImpOpBase + 0, 315, 0, 0xc80ULL }, // Inst #4063 = t2CRC32CW { 4062, 3, 1, 4, 702, 0, 0, ARMImpOpBase + 0, 315, 0, 0xc80ULL }, // Inst #4062 = t2CRC32CH { 4061, 3, 1, 4, 702, 0, 0, ARMImpOpBase + 0, 315, 0, 0xc80ULL }, // Inst #4061 = t2CRC32CB { 4060, 3, 1, 4, 702, 0, 0, ARMImpOpBase + 0, 315, 0, 0xc80ULL }, // Inst #4060 = t2CRC32B { 4059, 3, 0, 4, 1058, 0, 0, ARMImpOpBase + 0, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4059 = t2CPS3p { 4058, 2, 0, 4, 1058, 0, 0, ARMImpOpBase + 0, 13, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4058 = t2CPS2p { 4057, 1, 0, 4, 1058, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4057 = t2CPS1p { 4056, 5, 0, 4, 1242, 0, 1, ARMImpOpBase + 0, 2763, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4056 = t2CMPrs { 4055, 4, 0, 4, 1069, 0, 1, ARMImpOpBase + 0, 2759, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4055 = t2CMPrr { 4054, 4, 0, 4, 1068, 0, 1, ARMImpOpBase + 0, 439, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4054 = t2CMPri { 4053, 5, 0, 4, 1241, 0, 1, ARMImpOpBase + 0, 2763, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4053 = t2CMNzrs { 4052, 4, 0, 4, 1067, 0, 1, ARMImpOpBase + 0, 2759, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4052 = t2CMNzrr { 4051, 4, 0, 4, 55, 0, 1, ARMImpOpBase + 0, 439, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4051 = t2CMNri { 4050, 4, 1, 4, 1246, 0, 0, ARMImpOpBase + 0, 2755, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4050 = t2CLZ { 4049, 3, 0, 4, 1105, 0, 0, ARMImpOpBase + 0, 584, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4049 = t2CLRM { 4048, 2, 0, 4, 1031, 0, 0, ARMImpOpBase + 0, 540, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4048 = t2CLREX { 4047, 8, 0, 4, 1034, 0, 0, ARMImpOpBase + 0, 823, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4047 = t2CDP2 { 4046, 8, 0, 4, 1034, 0, 0, ARMImpOpBase + 0, 823, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4046 = t2CDP { 4045, 3, 0, 4, 854, 0, 0, ARMImpOpBase + 0, 545, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4045 = t2Bcc { 4044, 3, 0, 4, 864, 0, 0, ARMImpOpBase + 0, 1059, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4044 = t2BXJ { 4043, 5, 0, 4, 0, 0, 0, ARMImpOpBase + 0, 2750, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4043 = t2BXAUT { 4042, 0, 0, 4, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4042 = t2BTI { 4041, 7, 1, 4, 1239, 0, 0, ARMImpOpBase + 0, 2681, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4041 = t2BICrs { 4040, 6, 1, 4, 1273, 0, 0, ARMImpOpBase + 0, 2675, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4040 = t2BICrr { 4039, 6, 1, 4, 696, 0, 0, ARMImpOpBase + 0, 2669, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4039 = t2BICri { 4038, 4, 0, 4, 1284, 0, 0, ARMImpOpBase + 0, 2742, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4038 = t2BFr { 4037, 4, 0, 4, 1284, 0, 0, ARMImpOpBase + 0, 2746, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4037 = t2BFic { 4036, 4, 0, 4, 1284, 0, 0, ARMImpOpBase + 0, 2738, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4036 = t2BFi { 4035, 4, 0, 4, 1284, 0, 0, ARMImpOpBase + 0, 2742, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4035 = t2BFLr { 4034, 4, 0, 4, 1284, 0, 0, ARMImpOpBase + 0, 2738, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4034 = t2BFLi { 4033, 6, 1, 4, 360, 0, 0, ARMImpOpBase + 0, 2732, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4033 = t2BFI { 4032, 5, 1, 4, 359, 0, 0, ARMImpOpBase + 0, 464, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4032 = t2BFC { 4031, 3, 0, 4, 854, 0, 0, ARMImpOpBase + 0, 545, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL }, // Inst #4031 = t2B { 4030, 5, 0, 4, 0, 0, 0, ARMImpOpBase + 0, 2727, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4030 = t2AUTG { 4029, 0, 0, 4, 0, 3, 0, ARMImpOpBase + 186, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4029 = t2AUT { 4028, 6, 1, 4, 1066, 0, 0, ARMImpOpBase + 0, 2675, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4028 = t2ASRrr { 4027, 6, 1, 4, 1065, 0, 0, ARMImpOpBase + 0, 2669, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4027 = t2ASRri { 4026, 7, 1, 4, 707, 0, 0, ARMImpOpBase + 0, 2681, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4026 = t2ANDrs { 4025, 6, 1, 4, 703, 0, 0, ARMImpOpBase + 0, 2675, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4025 = t2ANDrr { 4024, 6, 1, 4, 696, 0, 0, ARMImpOpBase + 0, 2669, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4024 = t2ANDri { 4023, 4, 1, 4, 1, 0, 0, ARMImpOpBase + 0, 2723, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4023 = t2ADR { 4022, 5, 1, 4, 1, 0, 0, ARMImpOpBase + 0, 2718, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4022 = t2ADDspImm12 { 4021, 6, 1, 4, 1, 0, 0, ARMImpOpBase + 0, 2712, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4021 = t2ADDspImm { 4020, 7, 1, 4, 706, 0, 0, ARMImpOpBase + 0, 2705, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4020 = t2ADDrs { 4019, 6, 1, 4, 1064, 0, 0, ARMImpOpBase + 0, 2699, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4019 = t2ADDrr { 4018, 5, 1, 4, 1277, 0, 0, ARMImpOpBase + 0, 2694, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4018 = t2ADDri12 { 4017, 6, 1, 4, 1276, 0, 0, ARMImpOpBase + 0, 2688, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4017 = t2ADDri { 4016, 7, 1, 4, 1269, 1, 1, ARMImpOpBase + 63, 2681, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // Inst #4016 = t2ADCrs { 4015, 6, 1, 4, 1272, 1, 1, ARMImpOpBase + 63, 2675, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // Inst #4015 = t2ADCrr { 4014, 6, 1, 4, 694, 1, 1, ARMImpOpBase + 63, 2669, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // Inst #4014 = t2ADCri { 4013, 5, 1, 4, 452, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // Inst #4013 = sysSTMIB_UPD { 4012, 4, 0, 4, 451, 0, 0, ARMImpOpBase + 0, 873, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // Inst #4012 = sysSTMIB { 4011, 5, 1, 4, 452, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // Inst #4011 = sysSTMIA_UPD { 4010, 4, 0, 4, 451, 0, 0, ARMImpOpBase + 0, 873, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // Inst #4010 = sysSTMIA { 4009, 5, 1, 4, 452, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // Inst #4009 = sysSTMDB_UPD { 4008, 4, 0, 4, 451, 0, 0, ARMImpOpBase + 0, 873, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // Inst #4008 = sysSTMDB { 4007, 5, 1, 4, 452, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // Inst #4007 = sysSTMDA_UPD { 4006, 4, 0, 4, 451, 0, 0, ARMImpOpBase + 0, 873, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // Inst #4006 = sysSTMDA { 4005, 5, 1, 4, 422, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL }, // Inst #4005 = sysLDMIB_UPD { 4004, 4, 0, 4, 421, 0, 0, ARMImpOpBase + 0, 873, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL }, // Inst #4004 = sysLDMIB { 4003, 5, 1, 4, 422, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL }, // Inst #4003 = sysLDMIA_UPD { 4002, 4, 0, 4, 421, 0, 0, ARMImpOpBase + 0, 873, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL }, // Inst #4002 = sysLDMIA { 4001, 5, 1, 4, 422, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL }, // Inst #4001 = sysLDMDB_UPD { 4000, 4, 0, 4, 421, 0, 0, ARMImpOpBase + 0, 873, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL }, // Inst #4000 = sysLDMDB { 3999, 5, 1, 4, 422, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL }, // Inst #3999 = sysLDMDA_UPD { 3998, 4, 0, 4, 421, 0, 0, ARMImpOpBase + 0, 873, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL }, // Inst #3998 = sysLDMDA { 3997, 6, 2, 4, 516, 0, 0, ARMImpOpBase + 0, 2637, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3997 = VZIPq8 { 3996, 6, 2, 4, 516, 0, 0, ARMImpOpBase + 0, 2637, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3996 = VZIPq32 { 3995, 6, 2, 4, 516, 0, 0, ARMImpOpBase + 0, 2637, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3995 = VZIPq16 { 3994, 6, 2, 4, 514, 0, 0, ARMImpOpBase + 0, 2631, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3994 = VZIPd8 { 3993, 6, 2, 4, 514, 0, 0, ARMImpOpBase + 0, 2631, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3993 = VZIPd16 { 3992, 6, 2, 4, 516, 0, 0, ARMImpOpBase + 0, 2637, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3992 = VUZPq8 { 3991, 6, 2, 4, 516, 0, 0, ARMImpOpBase + 0, 2637, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3991 = VUZPq32 { 3990, 6, 2, 4, 516, 0, 0, ARMImpOpBase + 0, 2637, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3990 = VUZPq16 { 3989, 6, 2, 4, 514, 0, 0, ARMImpOpBase + 0, 2631, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3989 = VUZPd8 { 3988, 6, 2, 4, 514, 0, 0, ARMImpOpBase + 0, 2631, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3988 = VUZPd16 { 3987, 4, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 641, 0, 0x11280ULL }, // Inst #3987 = VUSMMLA { 3986, 5, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #3986 = VUSDOTQI { 3985, 4, 1, 4, 50, 0, 0, ARMImpOpBase + 0, 641, 0, 0x11280ULL }, // Inst #3985 = VUSDOTQ { 3984, 5, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 627, 0, 0x11280ULL }, // Inst #3984 = VUSDOTDI { 3983, 4, 1, 4, 50, 0, 0, ARMImpOpBase + 0, 637, 0, 0x11280ULL }, // Inst #3983 = VUSDOTD { 3982, 4, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 641, 0, 0x11280ULL }, // Inst #3982 = VUMMLA { 3981, 5, 1, 4, 222, 0, 0, ARMImpOpBase + 0, 2387, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3981 = VULTOS { 3980, 5, 1, 4, 221, 0, 0, ARMImpOpBase + 0, 2387, 0, 0x8880ULL }, // Inst #3980 = VULTOH { 3979, 5, 1, 4, 1289, 0, 0, ARMImpOpBase + 0, 2382, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3979 = VULTOD { 3978, 4, 1, 4, 564, 0, 0, ARMImpOpBase + 0, 1683, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3978 = VUITOS { 3977, 4, 1, 4, 563, 0, 0, ARMImpOpBase + 0, 2392, 0, 0x8880ULL }, // Inst #3977 = VUITOH { 3976, 4, 1, 4, 562, 0, 0, ARMImpOpBase + 0, 1802, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3976 = VUITOD { 3975, 5, 1, 4, 222, 0, 0, ARMImpOpBase + 0, 2387, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3975 = VUHTOS { 3974, 5, 1, 4, 221, 0, 0, ARMImpOpBase + 0, 2387, 0, 0x8880ULL }, // Inst #3974 = VUHTOH { 3973, 5, 1, 4, 1289, 0, 0, ARMImpOpBase + 0, 2382, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3973 = VUHTOD { 3972, 5, 1, 4, 964, 0, 0, ARMImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #3972 = VUDOTQI { 3971, 4, 1, 4, 964, 0, 0, ARMImpOpBase + 0, 641, 0, 0x11280ULL }, // Inst #3971 = VUDOTQ { 3970, 5, 1, 4, 964, 0, 0, ARMImpOpBase + 0, 627, 0, 0x11280ULL }, // Inst #3970 = VUDOTDI { 3969, 4, 1, 4, 964, 0, 0, ARMImpOpBase + 0, 637, 0, 0x11280ULL }, // Inst #3969 = VUDOTD { 3968, 5, 1, 4, 468, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3968 = VTSTv8i8 { 3967, 5, 1, 4, 467, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3967 = VTSTv8i16 { 3966, 5, 1, 4, 467, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3966 = VTSTv4i32 { 3965, 5, 1, 4, 468, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3965 = VTSTv4i16 { 3964, 5, 1, 4, 468, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3964 = VTSTv2i32 { 3963, 5, 1, 4, 467, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3963 = VTSTv16i8 { 3962, 6, 2, 4, 515, 0, 0, ARMImpOpBase + 0, 2637, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3962 = VTRNq8 { 3961, 6, 2, 4, 515, 0, 0, ARMImpOpBase + 0, 2637, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3961 = VTRNq32 { 3960, 6, 2, 4, 515, 0, 0, ARMImpOpBase + 0, 2637, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3960 = VTRNq16 { 3959, 6, 2, 4, 1002, 0, 0, ARMImpOpBase + 0, 2631, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3959 = VTRNd8 { 3958, 6, 2, 4, 1002, 0, 0, ARMImpOpBase + 0, 2631, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3958 = VTRNd32 { 3957, 6, 2, 4, 1002, 0, 0, ARMImpOpBase + 0, 2631, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3957 = VTRNd16 { 3956, 5, 1, 4, 959, 0, 0, ARMImpOpBase + 0, 2387, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3956 = VTOULS { 3955, 5, 1, 4, 566, 0, 0, ARMImpOpBase + 0, 2387, 0, 0x8880ULL }, // Inst #3955 = VTOULH { 3954, 5, 1, 4, 565, 0, 0, ARMImpOpBase + 0, 2382, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3954 = VTOULD { 3953, 4, 1, 4, 567, 0, 0, ARMImpOpBase + 0, 1683, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3953 = VTOUIZS { 3952, 4, 1, 4, 566, 0, 0, ARMImpOpBase + 0, 2665, 0, 0x8880ULL }, // Inst #3952 = VTOUIZH { 3951, 4, 1, 4, 565, 0, 0, ARMImpOpBase + 0, 1806, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3951 = VTOUIZD { 3950, 4, 1, 4, 567, 1, 0, ARMImpOpBase + 71, 1683, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3950 = VTOUIRS { 3949, 4, 1, 4, 566, 1, 0, ARMImpOpBase + 71, 1683, 0, 0x8880ULL }, // Inst #3949 = VTOUIRH { 3948, 4, 1, 4, 565, 1, 0, ARMImpOpBase + 71, 1806, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3948 = VTOUIRD { 3947, 5, 1, 4, 959, 0, 0, ARMImpOpBase + 0, 2387, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3947 = VTOUHS { 3946, 5, 1, 4, 566, 0, 0, ARMImpOpBase + 0, 2387, 0, 0x8880ULL }, // Inst #3946 = VTOUHH { 3945, 5, 1, 4, 565, 0, 0, ARMImpOpBase + 0, 2382, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3945 = VTOUHD { 3944, 5, 1, 4, 959, 0, 0, ARMImpOpBase + 0, 2387, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3944 = VTOSLS { 3943, 5, 1, 4, 566, 0, 0, ARMImpOpBase + 0, 2387, 0, 0x8880ULL }, // Inst #3943 = VTOSLH { 3942, 5, 1, 4, 565, 0, 0, ARMImpOpBase + 0, 2382, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3942 = VTOSLD { 3941, 4, 1, 4, 567, 0, 0, ARMImpOpBase + 0, 1683, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3941 = VTOSIZS { 3940, 4, 1, 4, 566, 0, 0, ARMImpOpBase + 0, 2665, 0, 0x8880ULL }, // Inst #3940 = VTOSIZH { 3939, 4, 1, 4, 565, 0, 0, ARMImpOpBase + 0, 1806, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3939 = VTOSIZD { 3938, 4, 1, 4, 567, 1, 0, ARMImpOpBase + 71, 1683, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3938 = VTOSIRS { 3937, 4, 1, 4, 566, 1, 0, ARMImpOpBase + 71, 1683, 0, 0x8880ULL }, // Inst #3937 = VTOSIRH { 3936, 4, 1, 4, 565, 1, 0, ARMImpOpBase + 71, 1806, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3936 = VTOSIRD { 3935, 5, 1, 4, 567, 0, 0, ARMImpOpBase + 0, 2387, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3935 = VTOSHS { 3934, 5, 1, 4, 566, 0, 0, ARMImpOpBase + 0, 2387, 0, 0x8880ULL }, // Inst #3934 = VTOSHH { 3933, 5, 1, 4, 565, 0, 0, ARMImpOpBase + 0, 2382, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3933 = VTOSHD { 3932, 6, 1, 4, 512, 0, 0, ARMImpOpBase + 0, 2659, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL }, // Inst #3932 = VTBX4Pseudo { 3931, 6, 1, 4, 512, 0, 0, ARMImpOpBase + 0, 1654, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // Inst #3931 = VTBX4 { 3930, 6, 1, 4, 510, 0, 0, ARMImpOpBase + 0, 2659, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL }, // Inst #3930 = VTBX3Pseudo { 3929, 6, 1, 4, 510, 0, 0, ARMImpOpBase + 0, 1654, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // Inst #3929 = VTBX3 { 3928, 6, 1, 4, 508, 0, 0, ARMImpOpBase + 0, 2653, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // Inst #3928 = VTBX2 { 3927, 6, 1, 4, 506, 0, 0, ARMImpOpBase + 0, 1654, 0|(1ULL<<MCID::Predicable), 0x11480ULL }, // Inst #3927 = VTBX1 { 3926, 5, 1, 4, 511, 0, 0, ARMImpOpBase + 0, 2648, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL }, // Inst #3926 = VTBL4Pseudo { 3925, 5, 1, 4, 511, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // Inst #3925 = VTBL4 { 3924, 5, 1, 4, 509, 0, 0, ARMImpOpBase + 0, 2648, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL }, // Inst #3924 = VTBL3Pseudo { 3923, 5, 1, 4, 509, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // Inst #3923 = VTBL3 { 3922, 5, 1, 4, 507, 0, 0, ARMImpOpBase + 0, 2643, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // Inst #3922 = VTBL2 { 3921, 5, 1, 4, 505, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11480ULL }, // Inst #3921 = VTBL1 { 3920, 6, 2, 4, 513, 0, 0, ARMImpOpBase + 0, 2637, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3920 = VSWPq { 3919, 6, 2, 4, 513, 0, 0, ARMImpOpBase + 0, 2631, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3919 = VSWPd { 3918, 5, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #3918 = VSUDOTQI { 3917, 5, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 627, 0, 0x11280ULL }, // Inst #3917 = VSUDOTDI { 3916, 5, 1, 4, 757, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3916 = VSUBv8i8 { 3915, 5, 1, 4, 461, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3915 = VSUBv8i16 { 3914, 5, 1, 4, 461, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3914 = VSUBv4i32 { 3913, 5, 1, 4, 757, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3913 = VSUBv4i16 { 3912, 5, 1, 4, 461, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3912 = VSUBv2i64 { 3911, 5, 1, 4, 757, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3911 = VSUBv2i32 { 3910, 5, 1, 4, 757, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3910 = VSUBv1i64 { 3909, 5, 1, 4, 461, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3909 = VSUBv16i8 { 3908, 5, 1, 4, 747, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3908 = VSUBhq { 3907, 5, 1, 4, 745, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3907 = VSUBhd { 3906, 5, 1, 4, 746, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3906 = VSUBfq { 3905, 5, 1, 4, 744, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3905 = VSUBfd { 3904, 5, 1, 4, 462, 0, 0, ARMImpOpBase + 0, 1706, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3904 = VSUBWuv8i16 { 3903, 5, 1, 4, 462, 0, 0, ARMImpOpBase + 0, 1706, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3903 = VSUBWuv4i32 { 3902, 5, 1, 4, 462, 0, 0, ARMImpOpBase + 0, 1706, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3902 = VSUBWuv2i64 { 3901, 5, 1, 4, 462, 0, 0, ARMImpOpBase + 0, 1706, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3901 = VSUBWsv8i16 { 3900, 5, 1, 4, 462, 0, 0, ARMImpOpBase + 0, 1706, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3900 = VSUBWsv4i32 { 3899, 5, 1, 4, 462, 0, 0, ARMImpOpBase + 0, 1706, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3899 = VSUBWsv2i64 { 3898, 5, 1, 4, 521, 0, 0, ARMImpOpBase + 0, 1701, 0|(1ULL<<MCID::Predicable), 0x28800ULL }, // Inst #3898 = VSUBS { 3897, 5, 1, 4, 759, 0, 0, ARMImpOpBase + 0, 1660, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3897 = VSUBLuv8i16 { 3896, 5, 1, 4, 759, 0, 0, ARMImpOpBase + 0, 1660, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3896 = VSUBLuv4i32 { 3895, 5, 1, 4, 759, 0, 0, ARMImpOpBase + 0, 1660, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3895 = VSUBLuv2i64 { 3894, 5, 1, 4, 759, 0, 0, ARMImpOpBase + 0, 1660, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3894 = VSUBLsv8i16 { 3893, 5, 1, 4, 759, 0, 0, ARMImpOpBase + 0, 1660, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3893 = VSUBLsv4i32 { 3892, 5, 1, 4, 759, 0, 0, ARMImpOpBase + 0, 1660, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3892 = VSUBLsv2i64 { 3891, 5, 1, 4, 501, 0, 0, ARMImpOpBase + 0, 1696, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3891 = VSUBHNv8i8 { 3890, 5, 1, 4, 501, 0, 0, ARMImpOpBase + 0, 1696, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3890 = VSUBHNv4i16 { 3889, 5, 1, 4, 501, 0, 0, ARMImpOpBase + 0, 1696, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3889 = VSUBHNv2i32 { 3888, 5, 1, 4, 743, 0, 0, ARMImpOpBase + 0, 1691, 0, 0x8800ULL }, // Inst #3888 = VSUBH { 3887, 5, 1, 4, 527, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #3887 = VSUBD { 3886, 5, 1, 4, 751, 1, 0, ARMImpOpBase + 69, 2186, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #3886 = VSTR_VPR_pre { 3885, 5, 1, 4, 751, 1, 0, ARMImpOpBase + 69, 2186, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3885 = VSTR_VPR_post { 3884, 4, 0, 4, 751, 1, 0, ARMImpOpBase + 69, 2182, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3884 = VSTR_VPR_off { 3883, 6, 1, 4, 751, 0, 0, ARMImpOpBase + 0, 2625, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #3883 = VSTR_P0_pre { 3882, 6, 1, 4, 751, 0, 0, ARMImpOpBase + 0, 2625, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3882 = VSTR_P0_post { 3881, 5, 0, 4, 751, 0, 0, ARMImpOpBase + 0, 2191, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3881 = VSTR_P0_off { 3880, 5, 1, 4, 751, 0, 1, ARMImpOpBase + 71, 2186, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #3880 = VSTR_FPSCR_pre { 3879, 5, 1, 4, 751, 0, 1, ARMImpOpBase + 71, 2186, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3879 = VSTR_FPSCR_post { 3878, 4, 0, 4, 751, 0, 1, ARMImpOpBase + 71, 2182, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3878 = VSTR_FPSCR_off { 3877, 5, 1, 4, 751, 0, 1, ARMImpOpBase + 71, 2186, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #3877 = VSTR_FPSCR_NZCVQC_pre { 3876, 5, 1, 4, 751, 0, 1, ARMImpOpBase + 71, 2186, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3876 = VSTR_FPSCR_NZCVQC_post { 3875, 4, 0, 4, 751, 0, 1, ARMImpOpBase + 71, 2182, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3875 = VSTR_FPSCR_NZCVQC_off { 3874, 5, 1, 4, 751, 0, 1, ARMImpOpBase + 71, 2186, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #3874 = VSTR_FPCXTS_pre { 3873, 5, 1, 4, 751, 0, 1, ARMImpOpBase + 71, 2186, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3873 = VSTR_FPCXTS_post { 3872, 4, 0, 4, 751, 0, 1, ARMImpOpBase + 71, 2182, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3872 = VSTR_FPCXTS_off { 3871, 5, 1, 4, 751, 0, 1, ARMImpOpBase + 71, 2186, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #3871 = VSTR_FPCXTNS_pre { 3870, 5, 1, 4, 751, 0, 1, ARMImpOpBase + 71, 2186, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3870 = VSTR_FPCXTNS_post { 3869, 4, 0, 4, 751, 0, 1, ARMImpOpBase + 71, 2182, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3869 = VSTR_FPCXTNS_off { 3868, 5, 0, 4, 592, 0, 0, ARMImpOpBase + 0, 2177, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18b05ULL }, // Inst #3868 = VSTRS { 3867, 5, 0, 4, 750, 0, 0, ARMImpOpBase + 0, 2172, 0|(1ULL<<MCID::MayStore), 0x18b13ULL }, // Inst #3867 = VSTRH { 3866, 5, 0, 4, 591, 0, 0, ARMImpOpBase + 0, 385, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18b05ULL }, // Inst #3866 = VSTRD { 3865, 5, 1, 4, 971, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18be4ULL }, // Inst #3865 = VSTMSIA_UPD { 3864, 4, 0, 4, 970, 0, 0, ARMImpOpBase + 0, 873, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18b84ULL }, // Inst #3864 = VSTMSIA { 3863, 5, 1, 4, 971, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18be4ULL }, // Inst #3863 = VSTMSDB_UPD { 3862, 4, 0, 4, 594, 0, 0, ARMImpOpBase + 0, 2168, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18004ULL }, // Inst #3862 = VSTMQIA { 3861, 5, 1, 4, 598, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8be4ULL }, // Inst #3861 = VSTMDIA_UPD { 3860, 4, 0, 4, 597, 0, 0, ARMImpOpBase + 0, 873, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8b84ULL }, // Inst #3860 = VSTMDIA { 3859, 5, 1, 4, 598, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8be4ULL }, // Inst #3859 = VSTMDDB_UPD { 3858, 7, 1, 4, 663, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3858 = VST4q8oddPseudo_UPD { 3857, 5, 0, 4, 662, 0, 0, ARMImpOpBase + 0, 2477, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3857 = VST4q8oddPseudo { 3856, 10, 1, 4, 838, 0, 0, ARMImpOpBase + 0, 2615, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3856 = VST4q8_UPD { 3855, 7, 1, 4, 663, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3855 = VST4q8Pseudo_UPD { 3854, 8, 0, 4, 830, 0, 0, ARMImpOpBase + 0, 2607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3854 = VST4q8 { 3853, 7, 1, 4, 663, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3853 = VST4q32oddPseudo_UPD { 3852, 5, 0, 4, 662, 0, 0, ARMImpOpBase + 0, 2477, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3852 = VST4q32oddPseudo { 3851, 10, 1, 4, 838, 0, 0, ARMImpOpBase + 0, 2615, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3851 = VST4q32_UPD { 3850, 7, 1, 4, 663, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3850 = VST4q32Pseudo_UPD { 3849, 8, 0, 4, 830, 0, 0, ARMImpOpBase + 0, 2607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3849 = VST4q32 { 3848, 7, 1, 4, 663, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3848 = VST4q16oddPseudo_UPD { 3847, 5, 0, 4, 662, 0, 0, ARMImpOpBase + 0, 2477, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3847 = VST4q16oddPseudo { 3846, 10, 1, 4, 838, 0, 0, ARMImpOpBase + 0, 2615, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3846 = VST4q16_UPD { 3845, 7, 1, 4, 663, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3845 = VST4q16Pseudo_UPD { 3844, 8, 0, 4, 830, 0, 0, ARMImpOpBase + 0, 2607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3844 = VST4q16 { 3843, 10, 1, 4, 838, 0, 0, ARMImpOpBase + 0, 2615, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3843 = VST4d8_UPD { 3842, 7, 1, 4, 663, 0, 0, ARMImpOpBase + 0, 2452, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3842 = VST4d8Pseudo_UPD { 3841, 5, 0, 4, 832, 0, 0, ARMImpOpBase + 0, 2441, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3841 = VST4d8Pseudo { 3840, 8, 0, 4, 830, 0, 0, ARMImpOpBase + 0, 2607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3840 = VST4d8 { 3839, 10, 1, 4, 838, 0, 0, ARMImpOpBase + 0, 2615, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3839 = VST4d32_UPD { 3838, 7, 1, 4, 663, 0, 0, ARMImpOpBase + 0, 2452, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3838 = VST4d32Pseudo_UPD { 3837, 5, 0, 4, 832, 0, 0, ARMImpOpBase + 0, 2441, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3837 = VST4d32Pseudo { 3836, 8, 0, 4, 830, 0, 0, ARMImpOpBase + 0, 2607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3836 = VST4d32 { 3835, 10, 1, 4, 838, 0, 0, ARMImpOpBase + 0, 2615, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3835 = VST4d16_UPD { 3834, 7, 1, 4, 663, 0, 0, ARMImpOpBase + 0, 2452, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3834 = VST4d16Pseudo_UPD { 3833, 5, 0, 4, 832, 0, 0, ARMImpOpBase + 0, 2441, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3833 = VST4d16Pseudo { 3832, 8, 0, 4, 830, 0, 0, ARMImpOpBase + 0, 2607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3832 = VST4d16 { 3831, 11, 1, 4, 674, 0, 0, ARMImpOpBase + 0, 2596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3831 = VST4LNq32_UPD { 3830, 8, 1, 4, 675, 0, 0, ARMImpOpBase + 0, 2563, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3830 = VST4LNq32Pseudo_UPD { 3829, 6, 0, 4, 673, 0, 0, ARMImpOpBase + 0, 2557, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3829 = VST4LNq32Pseudo { 3828, 9, 0, 4, 836, 0, 0, ARMImpOpBase + 0, 2587, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3828 = VST4LNq32 { 3827, 11, 1, 4, 674, 0, 0, ARMImpOpBase + 0, 2596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3827 = VST4LNq16_UPD { 3826, 8, 1, 4, 675, 0, 0, ARMImpOpBase + 0, 2563, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3826 = VST4LNq16Pseudo_UPD { 3825, 6, 0, 4, 673, 0, 0, ARMImpOpBase + 0, 2557, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3825 = VST4LNq16Pseudo { 3824, 9, 0, 4, 836, 0, 0, ARMImpOpBase + 0, 2587, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3824 = VST4LNq16 { 3823, 11, 1, 4, 840, 0, 0, ARMImpOpBase + 0, 2596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3823 = VST4LNd8_UPD { 3822, 8, 1, 4, 842, 0, 0, ARMImpOpBase + 0, 2524, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3822 = VST4LNd8Pseudo_UPD { 3821, 6, 0, 4, 835, 0, 0, ARMImpOpBase + 0, 2518, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3821 = VST4LNd8Pseudo { 3820, 9, 0, 4, 833, 0, 0, ARMImpOpBase + 0, 2587, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3820 = VST4LNd8 { 3819, 11, 1, 4, 840, 0, 0, ARMImpOpBase + 0, 2596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3819 = VST4LNd32_UPD { 3818, 8, 1, 4, 842, 0, 0, ARMImpOpBase + 0, 2524, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3818 = VST4LNd32Pseudo_UPD { 3817, 6, 0, 4, 835, 0, 0, ARMImpOpBase + 0, 2518, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3817 = VST4LNd32Pseudo { 3816, 9, 0, 4, 833, 0, 0, ARMImpOpBase + 0, 2587, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3816 = VST4LNd32 { 3815, 11, 1, 4, 840, 0, 0, ARMImpOpBase + 0, 2596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3815 = VST4LNd16_UPD { 3814, 8, 1, 4, 842, 0, 0, ARMImpOpBase + 0, 2524, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3814 = VST4LNd16Pseudo_UPD { 3813, 6, 0, 4, 835, 0, 0, ARMImpOpBase + 0, 2518, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3813 = VST4LNd16Pseudo { 3812, 9, 0, 4, 833, 0, 0, ARMImpOpBase + 0, 2587, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3812 = VST4LNd16 { 3811, 7, 1, 4, 661, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3811 = VST3q8oddPseudo_UPD { 3810, 5, 0, 4, 660, 0, 0, ARMImpOpBase + 0, 2477, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3810 = VST3q8oddPseudo { 3809, 9, 1, 4, 824, 0, 0, ARMImpOpBase + 0, 2578, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3809 = VST3q8_UPD { 3808, 7, 1, 4, 661, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3808 = VST3q8Pseudo_UPD { 3807, 7, 0, 4, 817, 0, 0, ARMImpOpBase + 0, 2571, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3807 = VST3q8 { 3806, 7, 1, 4, 661, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3806 = VST3q32oddPseudo_UPD { 3805, 5, 0, 4, 660, 0, 0, ARMImpOpBase + 0, 2477, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3805 = VST3q32oddPseudo { 3804, 9, 1, 4, 824, 0, 0, ARMImpOpBase + 0, 2578, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3804 = VST3q32_UPD { 3803, 7, 1, 4, 661, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3803 = VST3q32Pseudo_UPD { 3802, 7, 0, 4, 817, 0, 0, ARMImpOpBase + 0, 2571, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3802 = VST3q32 { 3801, 7, 1, 4, 661, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3801 = VST3q16oddPseudo_UPD { 3800, 5, 0, 4, 660, 0, 0, ARMImpOpBase + 0, 2477, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3800 = VST3q16oddPseudo { 3799, 9, 1, 4, 824, 0, 0, ARMImpOpBase + 0, 2578, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3799 = VST3q16_UPD { 3798, 7, 1, 4, 661, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3798 = VST3q16Pseudo_UPD { 3797, 7, 0, 4, 817, 0, 0, ARMImpOpBase + 0, 2571, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3797 = VST3q16 { 3796, 9, 1, 4, 824, 0, 0, ARMImpOpBase + 0, 2578, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3796 = VST3d8_UPD { 3795, 7, 1, 4, 661, 0, 0, ARMImpOpBase + 0, 2452, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3795 = VST3d8Pseudo_UPD { 3794, 5, 0, 4, 819, 0, 0, ARMImpOpBase + 0, 2441, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3794 = VST3d8Pseudo { 3793, 7, 0, 4, 817, 0, 0, ARMImpOpBase + 0, 2571, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3793 = VST3d8 { 3792, 9, 1, 4, 824, 0, 0, ARMImpOpBase + 0, 2578, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3792 = VST3d32_UPD { 3791, 7, 1, 4, 661, 0, 0, ARMImpOpBase + 0, 2452, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3791 = VST3d32Pseudo_UPD { 3790, 5, 0, 4, 819, 0, 0, ARMImpOpBase + 0, 2441, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3790 = VST3d32Pseudo { 3789, 7, 0, 4, 817, 0, 0, ARMImpOpBase + 0, 2571, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3789 = VST3d32 { 3788, 9, 1, 4, 824, 0, 0, ARMImpOpBase + 0, 2578, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3788 = VST3d16_UPD { 3787, 7, 1, 4, 661, 0, 0, ARMImpOpBase + 0, 2452, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3787 = VST3d16Pseudo_UPD { 3786, 5, 0, 4, 819, 0, 0, ARMImpOpBase + 0, 2441, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3786 = VST3d16Pseudo { 3785, 7, 0, 4, 817, 0, 0, ARMImpOpBase + 0, 2571, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3785 = VST3d16 { 3784, 10, 1, 4, 671, 0, 0, ARMImpOpBase + 0, 2547, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3784 = VST3LNq32_UPD { 3783, 8, 1, 4, 672, 0, 0, ARMImpOpBase + 0, 2563, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3783 = VST3LNq32Pseudo_UPD { 3782, 6, 0, 4, 670, 0, 0, ARMImpOpBase + 0, 2557, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3782 = VST3LNq32Pseudo { 3781, 8, 0, 4, 669, 0, 0, ARMImpOpBase + 0, 2539, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3781 = VST3LNq32 { 3780, 10, 1, 4, 671, 0, 0, ARMImpOpBase + 0, 2547, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3780 = VST3LNq16_UPD { 3779, 8, 1, 4, 672, 0, 0, ARMImpOpBase + 0, 2563, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3779 = VST3LNq16Pseudo_UPD { 3778, 6, 0, 4, 670, 0, 0, ARMImpOpBase + 0, 2557, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3778 = VST3LNq16Pseudo { 3777, 8, 0, 4, 669, 0, 0, ARMImpOpBase + 0, 2539, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3777 = VST3LNq16 { 3776, 10, 1, 4, 826, 0, 0, ARMImpOpBase + 0, 2547, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3776 = VST3LNd8_UPD { 3775, 8, 1, 4, 828, 0, 0, ARMImpOpBase + 0, 2524, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3775 = VST3LNd8Pseudo_UPD { 3774, 6, 0, 4, 822, 0, 0, ARMImpOpBase + 0, 2518, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3774 = VST3LNd8Pseudo { 3773, 8, 0, 4, 820, 0, 0, ARMImpOpBase + 0, 2539, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3773 = VST3LNd8 { 3772, 10, 1, 4, 826, 0, 0, ARMImpOpBase + 0, 2547, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3772 = VST3LNd32_UPD { 3771, 8, 1, 4, 828, 0, 0, ARMImpOpBase + 0, 2524, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3771 = VST3LNd32Pseudo_UPD { 3770, 6, 0, 4, 822, 0, 0, ARMImpOpBase + 0, 2518, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3770 = VST3LNd32Pseudo { 3769, 8, 0, 4, 820, 0, 0, ARMImpOpBase + 0, 2539, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3769 = VST3LNd32 { 3768, 10, 1, 4, 826, 0, 0, ARMImpOpBase + 0, 2547, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3768 = VST3LNd16_UPD { 3767, 8, 1, 4, 828, 0, 0, ARMImpOpBase + 0, 2524, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3767 = VST3LNd16Pseudo_UPD { 3766, 6, 0, 4, 822, 0, 0, ARMImpOpBase + 0, 2518, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3766 = VST3LNd16Pseudo { 3765, 8, 0, 4, 820, 0, 0, ARMImpOpBase + 0, 2539, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3765 = VST3LNd16 { 3764, 7, 1, 4, 658, 0, 0, ARMImpOpBase + 0, 2465, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3764 = VST2q8wb_register { 3763, 6, 1, 4, 658, 0, 0, ARMImpOpBase + 0, 2459, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3763 = VST2q8wb_fixed { 3762, 7, 1, 4, 659, 0, 0, ARMImpOpBase + 0, 2532, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3762 = VST2q8PseudoWB_register { 3761, 6, 1, 4, 659, 0, 0, ARMImpOpBase + 0, 2446, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3761 = VST2q8PseudoWB_fixed { 3760, 5, 0, 4, 657, 0, 0, ARMImpOpBase + 0, 2441, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3760 = VST2q8Pseudo { 3759, 5, 0, 4, 807, 0, 0, ARMImpOpBase + 0, 2436, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3759 = VST2q8 { 3758, 7, 1, 4, 658, 0, 0, ARMImpOpBase + 0, 2465, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3758 = VST2q32wb_register { 3757, 6, 1, 4, 658, 0, 0, ARMImpOpBase + 0, 2459, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3757 = VST2q32wb_fixed { 3756, 7, 1, 4, 659, 0, 0, ARMImpOpBase + 0, 2532, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3756 = VST2q32PseudoWB_register { 3755, 6, 1, 4, 659, 0, 0, ARMImpOpBase + 0, 2446, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3755 = VST2q32PseudoWB_fixed { 3754, 5, 0, 4, 657, 0, 0, ARMImpOpBase + 0, 2441, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3754 = VST2q32Pseudo { 3753, 5, 0, 4, 807, 0, 0, ARMImpOpBase + 0, 2436, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3753 = VST2q32 { 3752, 7, 1, 4, 658, 0, 0, ARMImpOpBase + 0, 2465, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3752 = VST2q16wb_register { 3751, 6, 1, 4, 658, 0, 0, ARMImpOpBase + 0, 2459, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3751 = VST2q16wb_fixed { 3750, 7, 1, 4, 659, 0, 0, ARMImpOpBase + 0, 2532, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3750 = VST2q16PseudoWB_register { 3749, 6, 1, 4, 659, 0, 0, ARMImpOpBase + 0, 2446, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3749 = VST2q16PseudoWB_fixed { 3748, 5, 0, 4, 657, 0, 0, ARMImpOpBase + 0, 2441, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3748 = VST2q16Pseudo { 3747, 5, 0, 4, 807, 0, 0, ARMImpOpBase + 0, 2436, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3747 = VST2q16 { 3746, 7, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2495, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3746 = VST2d8wb_register { 3745, 6, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2489, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3745 = VST2d8wb_fixed { 3744, 5, 0, 4, 655, 0, 0, ARMImpOpBase + 0, 2472, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3744 = VST2d8 { 3743, 7, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2495, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3743 = VST2d32wb_register { 3742, 6, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2489, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3742 = VST2d32wb_fixed { 3741, 5, 0, 4, 655, 0, 0, ARMImpOpBase + 0, 2472, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3741 = VST2d32 { 3740, 7, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2495, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3740 = VST2d16wb_register { 3739, 6, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2489, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3739 = VST2d16wb_fixed { 3738, 5, 0, 4, 655, 0, 0, ARMImpOpBase + 0, 2472, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3738 = VST2d16 { 3737, 7, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2495, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3737 = VST2b8wb_register { 3736, 6, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2489, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3736 = VST2b8wb_fixed { 3735, 5, 0, 4, 654, 0, 0, ARMImpOpBase + 0, 2472, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3735 = VST2b8 { 3734, 7, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2495, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3734 = VST2b32wb_register { 3733, 6, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2489, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3733 = VST2b32wb_fixed { 3732, 5, 0, 4, 654, 0, 0, ARMImpOpBase + 0, 2472, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3732 = VST2b32 { 3731, 7, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2495, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3731 = VST2b16wb_register { 3730, 6, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2489, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3730 = VST2b16wb_fixed { 3729, 5, 0, 4, 654, 0, 0, ARMImpOpBase + 0, 2472, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3729 = VST2b16 { 3728, 9, 1, 4, 667, 0, 0, ARMImpOpBase + 0, 2509, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3728 = VST2LNq32_UPD { 3727, 8, 1, 4, 668, 0, 0, ARMImpOpBase + 0, 2524, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3727 = VST2LNq32Pseudo_UPD { 3726, 6, 0, 4, 666, 0, 0, ARMImpOpBase + 0, 2518, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3726 = VST2LNq32Pseudo { 3725, 7, 0, 4, 811, 0, 0, ARMImpOpBase + 0, 2502, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3725 = VST2LNq32 { 3724, 9, 1, 4, 667, 0, 0, ARMImpOpBase + 0, 2509, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3724 = VST2LNq16_UPD { 3723, 8, 1, 4, 668, 0, 0, ARMImpOpBase + 0, 2524, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3723 = VST2LNq16Pseudo_UPD { 3722, 6, 0, 4, 666, 0, 0, ARMImpOpBase + 0, 2518, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3722 = VST2LNq16Pseudo { 3721, 7, 0, 4, 811, 0, 0, ARMImpOpBase + 0, 2502, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3721 = VST2LNq16 { 3720, 9, 1, 4, 813, 0, 0, ARMImpOpBase + 0, 2509, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3720 = VST2LNd8_UPD { 3719, 8, 1, 4, 815, 0, 0, ARMImpOpBase + 0, 2428, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3719 = VST2LNd8Pseudo_UPD { 3718, 6, 0, 4, 810, 0, 0, ARMImpOpBase + 0, 2422, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3718 = VST2LNd8Pseudo { 3717, 7, 0, 4, 808, 0, 0, ARMImpOpBase + 0, 2502, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3717 = VST2LNd8 { 3716, 9, 1, 4, 813, 0, 0, ARMImpOpBase + 0, 2509, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3716 = VST2LNd32_UPD { 3715, 8, 1, 4, 815, 0, 0, ARMImpOpBase + 0, 2428, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3715 = VST2LNd32Pseudo_UPD { 3714, 6, 0, 4, 810, 0, 0, ARMImpOpBase + 0, 2422, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3714 = VST2LNd32Pseudo { 3713, 7, 0, 4, 808, 0, 0, ARMImpOpBase + 0, 2502, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3713 = VST2LNd32 { 3712, 9, 1, 4, 813, 0, 0, ARMImpOpBase + 0, 2509, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3712 = VST2LNd16_UPD { 3711, 8, 1, 4, 815, 0, 0, ARMImpOpBase + 0, 2428, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3711 = VST2LNd16Pseudo_UPD { 3710, 6, 0, 4, 810, 0, 0, ARMImpOpBase + 0, 2422, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3710 = VST2LNd16Pseudo { 3709, 7, 0, 4, 808, 0, 0, ARMImpOpBase + 0, 2502, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3709 = VST2LNd16 { 3708, 7, 1, 4, 647, 0, 0, ARMImpOpBase + 0, 2495, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3708 = VST1q8wb_register { 3707, 6, 1, 4, 647, 0, 0, ARMImpOpBase + 0, 2489, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3707 = VST1q8wb_fixed { 3706, 7, 1, 4, 1054, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3706 = VST1q8LowTPseudo_UPD { 3705, 7, 1, 4, 1056, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3705 = VST1q8LowQPseudo_UPD { 3704, 7, 1, 4, 1054, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3704 = VST1q8HighTPseudo_UPD { 3703, 5, 0, 4, 1054, 0, 0, ARMImpOpBase + 0, 2477, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3703 = VST1q8HighTPseudo { 3702, 7, 1, 4, 1056, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3702 = VST1q8HighQPseudo_UPD { 3701, 5, 0, 4, 1056, 0, 0, ARMImpOpBase + 0, 2477, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3701 = VST1q8HighQPseudo { 3700, 5, 0, 4, 645, 0, 0, ARMImpOpBase + 0, 2472, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3700 = VST1q8 { 3699, 7, 1, 4, 647, 0, 0, ARMImpOpBase + 0, 2495, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3699 = VST1q64wb_register { 3698, 6, 1, 4, 647, 0, 0, ARMImpOpBase + 0, 2489, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3698 = VST1q64wb_fixed { 3697, 7, 1, 4, 1054, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3697 = VST1q64LowTPseudo_UPD { 3696, 7, 1, 4, 1056, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3696 = VST1q64LowQPseudo_UPD { 3695, 7, 1, 4, 1054, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3695 = VST1q64HighTPseudo_UPD { 3694, 5, 0, 4, 1054, 0, 0, ARMImpOpBase + 0, 2477, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3694 = VST1q64HighTPseudo { 3693, 7, 1, 4, 1056, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3693 = VST1q64HighQPseudo_UPD { 3692, 5, 0, 4, 1056, 0, 0, ARMImpOpBase + 0, 2477, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3692 = VST1q64HighQPseudo { 3691, 5, 0, 4, 645, 0, 0, ARMImpOpBase + 0, 2472, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3691 = VST1q64 { 3690, 7, 1, 4, 647, 0, 0, ARMImpOpBase + 0, 2495, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3690 = VST1q32wb_register { 3689, 6, 1, 4, 647, 0, 0, ARMImpOpBase + 0, 2489, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3689 = VST1q32wb_fixed { 3688, 7, 1, 4, 1054, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3688 = VST1q32LowTPseudo_UPD { 3687, 7, 1, 4, 1056, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3687 = VST1q32LowQPseudo_UPD { 3686, 7, 1, 4, 1054, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3686 = VST1q32HighTPseudo_UPD { 3685, 5, 0, 4, 1054, 0, 0, ARMImpOpBase + 0, 2477, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3685 = VST1q32HighTPseudo { 3684, 7, 1, 4, 1056, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3684 = VST1q32HighQPseudo_UPD { 3683, 5, 0, 4, 1056, 0, 0, ARMImpOpBase + 0, 2477, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3683 = VST1q32HighQPseudo { 3682, 5, 0, 4, 645, 0, 0, ARMImpOpBase + 0, 2472, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3682 = VST1q32 { 3681, 7, 1, 4, 647, 0, 0, ARMImpOpBase + 0, 2495, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3681 = VST1q16wb_register { 3680, 6, 1, 4, 647, 0, 0, ARMImpOpBase + 0, 2489, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3680 = VST1q16wb_fixed { 3679, 7, 1, 4, 1054, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3679 = VST1q16LowTPseudo_UPD { 3678, 7, 1, 4, 1056, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3678 = VST1q16LowQPseudo_UPD { 3677, 7, 1, 4, 1054, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3677 = VST1q16HighTPseudo_UPD { 3676, 5, 0, 4, 1054, 0, 0, ARMImpOpBase + 0, 2477, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3676 = VST1q16HighTPseudo { 3675, 7, 1, 4, 1056, 0, 0, ARMImpOpBase + 0, 2482, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3675 = VST1q16HighQPseudo_UPD { 3674, 5, 0, 4, 1056, 0, 0, ARMImpOpBase + 0, 2477, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3674 = VST1q16HighQPseudo { 3673, 5, 0, 4, 645, 0, 0, ARMImpOpBase + 0, 2472, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3673 = VST1q16 { 3672, 7, 1, 4, 646, 0, 0, ARMImpOpBase + 0, 2465, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3672 = VST1d8wb_register { 3671, 6, 1, 4, 646, 0, 0, ARMImpOpBase + 0, 2459, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3671 = VST1d8wb_fixed { 3670, 7, 1, 4, 649, 0, 0, ARMImpOpBase + 0, 2465, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3670 = VST1d8Twb_register { 3669, 6, 1, 4, 649, 0, 0, ARMImpOpBase + 0, 2459, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3669 = VST1d8Twb_fixed { 3668, 7, 1, 4, 1055, 0, 0, ARMImpOpBase + 0, 2452, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3668 = VST1d8TPseudoWB_register { 3667, 6, 1, 4, 1055, 0, 0, ARMImpOpBase + 0, 2446, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3667 = VST1d8TPseudoWB_fixed { 3666, 5, 0, 4, 1054, 0, 0, ARMImpOpBase + 0, 2441, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3666 = VST1d8TPseudo { 3665, 5, 0, 4, 799, 0, 0, ARMImpOpBase + 0, 2436, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3665 = VST1d8T { 3664, 7, 1, 4, 653, 0, 0, ARMImpOpBase + 0, 2465, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3664 = VST1d8Qwb_register { 3663, 6, 1, 4, 653, 0, 0, ARMImpOpBase + 0, 2459, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3663 = VST1d8Qwb_fixed { 3662, 7, 1, 4, 652, 0, 0, ARMImpOpBase + 0, 2452, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3662 = VST1d8QPseudoWB_register { 3661, 6, 1, 4, 652, 0, 0, ARMImpOpBase + 0, 2446, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3661 = VST1d8QPseudoWB_fixed { 3660, 5, 0, 4, 651, 0, 0, ARMImpOpBase + 0, 2441, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3660 = VST1d8QPseudo { 3659, 5, 0, 4, 800, 0, 0, ARMImpOpBase + 0, 2436, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3659 = VST1d8Q { 3658, 5, 0, 4, 644, 0, 0, ARMImpOpBase + 0, 2436, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3658 = VST1d8 { 3657, 7, 1, 4, 646, 0, 0, ARMImpOpBase + 0, 2465, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3657 = VST1d64wb_register { 3656, 6, 1, 4, 646, 0, 0, ARMImpOpBase + 0, 2459, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3656 = VST1d64wb_fixed { 3655, 7, 1, 4, 649, 0, 0, ARMImpOpBase + 0, 2465, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3655 = VST1d64Twb_register { 3654, 6, 1, 4, 649, 0, 0, ARMImpOpBase + 0, 2459, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3654 = VST1d64Twb_fixed { 3653, 7, 1, 4, 650, 0, 0, ARMImpOpBase + 0, 2452, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3653 = VST1d64TPseudoWB_register { 3652, 6, 1, 4, 650, 0, 0, ARMImpOpBase + 0, 2446, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3652 = VST1d64TPseudoWB_fixed { 3651, 5, 0, 4, 648, 0, 0, ARMImpOpBase + 0, 2441, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3651 = VST1d64TPseudo { 3650, 5, 0, 4, 799, 0, 0, ARMImpOpBase + 0, 2436, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3650 = VST1d64T { 3649, 7, 1, 4, 653, 0, 0, ARMImpOpBase + 0, 2465, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3649 = VST1d64Qwb_register { 3648, 6, 1, 4, 653, 0, 0, ARMImpOpBase + 0, 2459, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3648 = VST1d64Qwb_fixed { 3647, 7, 1, 4, 804, 0, 0, ARMImpOpBase + 0, 2452, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3647 = VST1d64QPseudoWB_register { 3646, 6, 1, 4, 804, 0, 0, ARMImpOpBase + 0, 2446, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3646 = VST1d64QPseudoWB_fixed { 3645, 5, 0, 4, 801, 0, 0, ARMImpOpBase + 0, 2441, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3645 = VST1d64QPseudo { 3644, 5, 0, 4, 800, 0, 0, ARMImpOpBase + 0, 2436, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3644 = VST1d64Q { 3643, 5, 0, 4, 644, 0, 0, ARMImpOpBase + 0, 2436, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3643 = VST1d64 { 3642, 7, 1, 4, 646, 0, 0, ARMImpOpBase + 0, 2465, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3642 = VST1d32wb_register { 3641, 6, 1, 4, 646, 0, 0, ARMImpOpBase + 0, 2459, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3641 = VST1d32wb_fixed { 3640, 7, 1, 4, 649, 0, 0, ARMImpOpBase + 0, 2465, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3640 = VST1d32Twb_register { 3639, 6, 1, 4, 649, 0, 0, ARMImpOpBase + 0, 2459, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3639 = VST1d32Twb_fixed { 3638, 7, 1, 4, 1055, 0, 0, ARMImpOpBase + 0, 2452, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3638 = VST1d32TPseudoWB_register { 3637, 6, 1, 4, 1055, 0, 0, ARMImpOpBase + 0, 2446, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3637 = VST1d32TPseudoWB_fixed { 3636, 5, 0, 4, 1054, 0, 0, ARMImpOpBase + 0, 2441, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3636 = VST1d32TPseudo { 3635, 5, 0, 4, 799, 0, 0, ARMImpOpBase + 0, 2436, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3635 = VST1d32T { 3634, 7, 1, 4, 653, 0, 0, ARMImpOpBase + 0, 2465, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3634 = VST1d32Qwb_register { 3633, 6, 1, 4, 653, 0, 0, ARMImpOpBase + 0, 2459, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3633 = VST1d32Qwb_fixed { 3632, 7, 1, 4, 652, 0, 0, ARMImpOpBase + 0, 2452, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3632 = VST1d32QPseudoWB_register { 3631, 6, 1, 4, 652, 0, 0, ARMImpOpBase + 0, 2446, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3631 = VST1d32QPseudoWB_fixed { 3630, 5, 0, 4, 651, 0, 0, ARMImpOpBase + 0, 2441, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3630 = VST1d32QPseudo { 3629, 5, 0, 4, 800, 0, 0, ARMImpOpBase + 0, 2436, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3629 = VST1d32Q { 3628, 5, 0, 4, 644, 0, 0, ARMImpOpBase + 0, 2436, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3628 = VST1d32 { 3627, 7, 1, 4, 646, 0, 0, ARMImpOpBase + 0, 2465, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3627 = VST1d16wb_register { 3626, 6, 1, 4, 646, 0, 0, ARMImpOpBase + 0, 2459, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3626 = VST1d16wb_fixed { 3625, 7, 1, 4, 649, 0, 0, ARMImpOpBase + 0, 2465, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3625 = VST1d16Twb_register { 3624, 6, 1, 4, 649, 0, 0, ARMImpOpBase + 0, 2459, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3624 = VST1d16Twb_fixed { 3623, 7, 1, 4, 1055, 0, 0, ARMImpOpBase + 0, 2452, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3623 = VST1d16TPseudoWB_register { 3622, 6, 1, 4, 1055, 0, 0, ARMImpOpBase + 0, 2446, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3622 = VST1d16TPseudoWB_fixed { 3621, 5, 0, 4, 1054, 0, 0, ARMImpOpBase + 0, 2441, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3621 = VST1d16TPseudo { 3620, 5, 0, 4, 799, 0, 0, ARMImpOpBase + 0, 2436, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3620 = VST1d16T { 3619, 7, 1, 4, 653, 0, 0, ARMImpOpBase + 0, 2465, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3619 = VST1d16Qwb_register { 3618, 6, 1, 4, 653, 0, 0, ARMImpOpBase + 0, 2459, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3618 = VST1d16Qwb_fixed { 3617, 7, 1, 4, 652, 0, 0, ARMImpOpBase + 0, 2452, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3617 = VST1d16QPseudoWB_register { 3616, 6, 1, 4, 652, 0, 0, ARMImpOpBase + 0, 2446, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3616 = VST1d16QPseudoWB_fixed { 3615, 5, 0, 4, 651, 0, 0, ARMImpOpBase + 0, 2441, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3615 = VST1d16QPseudo { 3614, 5, 0, 4, 800, 0, 0, ARMImpOpBase + 0, 2436, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3614 = VST1d16Q { 3613, 5, 0, 4, 644, 0, 0, ARMImpOpBase + 0, 2436, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3613 = VST1d16 { 3612, 8, 1, 4, 665, 0, 0, ARMImpOpBase + 0, 2428, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #3612 = VST1LNq8Pseudo_UPD { 3611, 6, 0, 4, 664, 0, 0, ARMImpOpBase + 0, 2422, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #3611 = VST1LNq8Pseudo { 3610, 8, 1, 4, 665, 0, 0, ARMImpOpBase + 0, 2428, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #3610 = VST1LNq32Pseudo_UPD { 3609, 6, 0, 4, 664, 0, 0, ARMImpOpBase + 0, 2422, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #3609 = VST1LNq32Pseudo { 3608, 8, 1, 4, 665, 0, 0, ARMImpOpBase + 0, 2428, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #3608 = VST1LNq16Pseudo_UPD { 3607, 6, 0, 4, 664, 0, 0, ARMImpOpBase + 0, 2422, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #3607 = VST1LNq16Pseudo { 3606, 8, 1, 4, 805, 0, 0, ARMImpOpBase + 0, 2414, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #3606 = VST1LNd8_UPD { 3605, 6, 0, 4, 802, 0, 0, ARMImpOpBase + 0, 2408, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #3605 = VST1LNd8 { 3604, 8, 1, 4, 805, 0, 0, ARMImpOpBase + 0, 2414, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #3604 = VST1LNd32_UPD { 3603, 6, 0, 4, 802, 0, 0, ARMImpOpBase + 0, 2408, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #3603 = VST1LNd32 { 3602, 8, 1, 4, 805, 0, 0, ARMImpOpBase + 0, 2414, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #3602 = VST1LNd16_UPD { 3601, 6, 0, 4, 802, 0, 0, ARMImpOpBase + 0, 2408, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #3601 = VST1LNd16 { 3600, 6, 1, 4, 990, 0, 0, ARMImpOpBase + 0, 2370, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3600 = VSRIv8i8 { 3599, 6, 1, 4, 991, 0, 0, ARMImpOpBase + 0, 2364, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3599 = VSRIv8i16 { 3598, 6, 1, 4, 991, 0, 0, ARMImpOpBase + 0, 2364, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3598 = VSRIv4i32 { 3597, 6, 1, 4, 990, 0, 0, ARMImpOpBase + 0, 2370, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3597 = VSRIv4i16 { 3596, 6, 1, 4, 991, 0, 0, ARMImpOpBase + 0, 2364, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3596 = VSRIv2i64 { 3595, 6, 1, 4, 990, 0, 0, ARMImpOpBase + 0, 2370, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3595 = VSRIv2i32 { 3594, 6, 1, 4, 990, 0, 0, ARMImpOpBase + 0, 2370, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3594 = VSRIv1i64 { 3593, 6, 1, 4, 991, 0, 0, ARMImpOpBase + 0, 2364, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3593 = VSRIv16i8 { 3592, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2370, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3592 = VSRAuv8i8 { 3591, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2364, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3591 = VSRAuv8i16 { 3590, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2364, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3590 = VSRAuv4i32 { 3589, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2370, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3589 = VSRAuv4i16 { 3588, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2364, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3588 = VSRAuv2i64 { 3587, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2370, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3587 = VSRAuv2i32 { 3586, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2370, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3586 = VSRAuv1i64 { 3585, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2364, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3585 = VSRAuv16i8 { 3584, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2370, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3584 = VSRAsv8i8 { 3583, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2364, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3583 = VSRAsv8i16 { 3582, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2364, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3582 = VSRAsv4i32 { 3581, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2370, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3581 = VSRAsv4i16 { 3580, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2364, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3580 = VSRAsv2i64 { 3579, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2370, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3579 = VSRAsv2i32 { 3578, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2370, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3578 = VSRAsv1i64 { 3577, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2364, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3577 = VSRAsv16i8 { 3576, 4, 1, 4, 677, 0, 0, ARMImpOpBase + 0, 1683, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3576 = VSQRTS { 3575, 4, 1, 4, 962, 0, 0, ARMImpOpBase + 0, 1679, 0, 0x8780ULL }, // Inst #3575 = VSQRTH { 3574, 4, 1, 4, 679, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3574 = VSQRTD { 3573, 4, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 641, 0, 0x11280ULL }, // Inst #3573 = VSMMLA { 3572, 5, 1, 4, 222, 0, 0, ARMImpOpBase + 0, 2387, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3572 = VSLTOS { 3571, 5, 1, 4, 221, 0, 0, ARMImpOpBase + 0, 2387, 0, 0x8880ULL }, // Inst #3571 = VSLTOH { 3570, 5, 1, 4, 1289, 0, 0, ARMImpOpBase + 0, 2382, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3570 = VSLTOD { 3569, 6, 1, 4, 990, 0, 0, ARMImpOpBase + 0, 2402, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3569 = VSLIv8i8 { 3568, 6, 1, 4, 991, 0, 0, ARMImpOpBase + 0, 2396, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3568 = VSLIv8i16 { 3567, 6, 1, 4, 991, 0, 0, ARMImpOpBase + 0, 2396, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3567 = VSLIv4i32 { 3566, 6, 1, 4, 990, 0, 0, ARMImpOpBase + 0, 2402, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3566 = VSLIv4i16 { 3565, 6, 1, 4, 991, 0, 0, ARMImpOpBase + 0, 2396, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3565 = VSLIv2i64 { 3564, 6, 1, 4, 990, 0, 0, ARMImpOpBase + 0, 2402, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3564 = VSLIv2i32 { 3563, 6, 1, 4, 990, 0, 0, ARMImpOpBase + 0, 2402, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3563 = VSLIv1i64 { 3562, 6, 1, 4, 991, 0, 0, ARMImpOpBase + 0, 2396, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3562 = VSLIv16i8 { 3561, 4, 1, 4, 564, 0, 0, ARMImpOpBase + 0, 1683, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3561 = VSITOS { 3560, 4, 1, 4, 563, 0, 0, ARMImpOpBase + 0, 2392, 0, 0x8880ULL }, // Inst #3560 = VSITOH { 3559, 4, 1, 4, 562, 0, 0, ARMImpOpBase + 0, 1802, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3559 = VSITOD { 3558, 5, 1, 4, 222, 0, 0, ARMImpOpBase + 0, 2387, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3558 = VSHTOS { 3557, 5, 1, 4, 221, 0, 0, ARMImpOpBase + 0, 2387, 0, 0x8880ULL }, // Inst #3557 = VSHTOH { 3556, 5, 1, 4, 1289, 0, 0, ARMImpOpBase + 0, 2382, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3556 = VSHTOD { 3555, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1810, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3555 = VSHRuv8i8 { 3554, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1815, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3554 = VSHRuv8i16 { 3553, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1815, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3553 = VSHRuv4i32 { 3552, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1810, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3552 = VSHRuv4i16 { 3551, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1815, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3551 = VSHRuv2i64 { 3550, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1810, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3550 = VSHRuv2i32 { 3549, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1810, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3549 = VSHRuv1i64 { 3548, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1815, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3548 = VSHRuv16i8 { 3547, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1810, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3547 = VSHRsv8i8 { 3546, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1815, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3546 = VSHRsv8i16 { 3545, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1815, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3545 = VSHRsv4i32 { 3544, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1810, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3544 = VSHRsv4i16 { 3543, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1815, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3543 = VSHRsv2i64 { 3542, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1810, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3542 = VSHRsv2i32 { 3541, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1810, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3541 = VSHRsv1i64 { 3540, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1815, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3540 = VSHRsv16i8 { 3539, 5, 1, 4, 502, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3539 = VSHRNv8i8 { 3538, 5, 1, 4, 502, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3538 = VSHRNv4i16 { 3537, 5, 1, 4, 502, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3537 = VSHRNv2i32 { 3536, 5, 1, 4, 465, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3536 = VSHLuv8i8 { 3535, 5, 1, 4, 466, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3535 = VSHLuv8i16 { 3534, 5, 1, 4, 466, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3534 = VSHLuv4i32 { 3533, 5, 1, 4, 465, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3533 = VSHLuv4i16 { 3532, 5, 1, 4, 466, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3532 = VSHLuv2i64 { 3531, 5, 1, 4, 465, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3531 = VSHLuv2i32 { 3530, 5, 1, 4, 465, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3530 = VSHLuv1i64 { 3529, 5, 1, 4, 466, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3529 = VSHLuv16i8 { 3528, 5, 1, 4, 465, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3528 = VSHLsv8i8 { 3527, 5, 1, 4, 466, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3527 = VSHLsv8i16 { 3526, 5, 1, 4, 466, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3526 = VSHLsv4i32 { 3525, 5, 1, 4, 465, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3525 = VSHLsv4i16 { 3524, 5, 1, 4, 466, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3524 = VSHLsv2i64 { 3523, 5, 1, 4, 465, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3523 = VSHLsv2i32 { 3522, 5, 1, 4, 465, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3522 = VSHLsv1i64 { 3521, 5, 1, 4, 466, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3521 = VSHLsv16i8 { 3520, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 2357, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3520 = VSHLiv8i8 { 3519, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 2352, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3519 = VSHLiv8i16 { 3518, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 2352, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3518 = VSHLiv4i32 { 3517, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 2357, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3517 = VSHLiv4i16 { 3516, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 2352, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3516 = VSHLiv2i64 { 3515, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 2357, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3515 = VSHLiv2i32 { 3514, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 2357, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3514 = VSHLiv1i64 { 3513, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 2352, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3513 = VSHLiv16i8 { 3512, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1832, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3512 = VSHLLuv8i16 { 3511, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1832, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3511 = VSHLLuv4i32 { 3510, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1832, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3510 = VSHLLuv2i64 { 3509, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1832, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3509 = VSHLLsv8i16 { 3508, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1832, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3508 = VSHLLsv4i32 { 3507, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1832, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3507 = VSHLLsv2i64 { 3506, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1832, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3506 = VSHLLi8 { 3505, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1832, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3505 = VSHLLi32 { 3504, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1832, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3504 = VSHLLi16 { 3503, 6, 1, 4, 580, 0, 0, ARMImpOpBase + 0, 2376, 0|(1ULL<<MCID::Predicable), 0x10e00ULL }, // Inst #3503 = VSETLNi8 { 3502, 6, 1, 4, 1044, 0, 0, ARMImpOpBase + 0, 2376, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::InsertSubreg), 0x10e00ULL }, // Inst #3502 = VSETLNi32 { 3501, 6, 1, 4, 580, 0, 0, ARMImpOpBase + 0, 2376, 0|(1ULL<<MCID::Predicable), 0x10e00ULL }, // Inst #3501 = VSETLNi16 { 3500, 3, 1, 4, 1259, 1, 0, ARMImpOpBase + 0, 1878, 0, 0x8800ULL }, // Inst #3500 = VSELVSS { 3499, 3, 1, 4, 772, 1, 0, ARMImpOpBase + 0, 1875, 0, 0x8800ULL }, // Inst #3499 = VSELVSH { 3498, 3, 1, 4, 1260, 1, 0, ARMImpOpBase + 0, 1498, 0, 0x8800ULL }, // Inst #3498 = VSELVSD { 3497, 3, 1, 4, 1259, 1, 0, ARMImpOpBase + 0, 1878, 0, 0x8800ULL }, // Inst #3497 = VSELGTS { 3496, 3, 1, 4, 772, 1, 0, ARMImpOpBase + 0, 1875, 0, 0x8800ULL }, // Inst #3496 = VSELGTH { 3495, 3, 1, 4, 1260, 1, 0, ARMImpOpBase + 0, 1498, 0, 0x8800ULL }, // Inst #3495 = VSELGTD { 3494, 3, 1, 4, 1259, 1, 0, ARMImpOpBase + 0, 1878, 0, 0x8800ULL }, // Inst #3494 = VSELGES { 3493, 3, 1, 4, 772, 1, 0, ARMImpOpBase + 0, 1875, 0, 0x8800ULL }, // Inst #3493 = VSELGEH { 3492, 3, 1, 4, 1260, 1, 0, ARMImpOpBase + 0, 1498, 0, 0x8800ULL }, // Inst #3492 = VSELGED { 3491, 3, 1, 4, 1259, 1, 0, ARMImpOpBase + 0, 1878, 0, 0x8800ULL }, // Inst #3491 = VSELEQS { 3490, 3, 1, 4, 772, 1, 0, ARMImpOpBase + 0, 1875, 0, 0x8800ULL }, // Inst #3490 = VSELEQH { 3489, 3, 1, 4, 1260, 1, 0, ARMImpOpBase + 0, 1498, 0, 0x8800ULL }, // Inst #3489 = VSELEQD { 3488, 5, 1, 4, 964, 0, 0, ARMImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #3488 = VSDOTQI { 3487, 4, 1, 4, 964, 0, 0, ARMImpOpBase + 0, 641, 0, 0x11280ULL }, // Inst #3487 = VSDOTQ { 3486, 5, 1, 4, 964, 0, 0, ARMImpOpBase + 0, 627, 0, 0x11280ULL }, // Inst #3486 = VSDOTDI { 3485, 4, 1, 4, 964, 0, 0, ARMImpOpBase + 0, 637, 0, 0x11280ULL }, // Inst #3485 = VSDOTD { 3484, 3, 0, 4, 0, 0, 0, ARMImpOpBase + 0, 584, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3484 = VSCCLRMS { 3483, 3, 0, 4, 0, 0, 0, ARMImpOpBase + 0, 584, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3483 = VSCCLRMD { 3482, 5, 1, 4, 503, 0, 0, ARMImpOpBase + 0, 1696, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3482 = VRSUBHNv8i8 { 3481, 5, 1, 4, 503, 0, 0, ARMImpOpBase + 0, 1696, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3481 = VRSUBHNv4i16 { 3480, 5, 1, 4, 503, 0, 0, ARMImpOpBase + 0, 1696, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3480 = VRSUBHNv2i32 { 3479, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2370, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3479 = VRSRAuv8i8 { 3478, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2364, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3478 = VRSRAuv8i16 { 3477, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2364, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3477 = VRSRAuv4i32 { 3476, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2370, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3476 = VRSRAuv4i16 { 3475, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2364, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3475 = VRSRAuv2i64 { 3474, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2370, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3474 = VRSRAuv2i32 { 3473, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2370, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3473 = VRSRAuv1i64 { 3472, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2364, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3472 = VRSRAuv16i8 { 3471, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2370, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3471 = VRSRAsv8i8 { 3470, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2364, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3470 = VRSRAsv8i16 { 3469, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2364, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3469 = VRSRAsv4i32 { 3468, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2370, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3468 = VRSRAsv4i16 { 3467, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2364, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3467 = VRSRAsv2i64 { 3466, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2370, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3466 = VRSRAsv2i32 { 3465, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2370, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3465 = VRSRAsv1i64 { 3464, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2364, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3464 = VRSRAsv16i8 { 3463, 5, 1, 4, 529, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3463 = VRSQRTShq { 3462, 5, 1, 4, 528, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3462 = VRSQRTShd { 3461, 5, 1, 4, 529, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3461 = VRSQRTSfq { 3460, 5, 1, 4, 528, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3460 = VRSQRTSfd { 3459, 4, 1, 4, 500, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3459 = VRSQRTEq { 3458, 4, 1, 4, 500, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3458 = VRSQRTEhq { 3457, 4, 1, 4, 499, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3457 = VRSQRTEhd { 3456, 4, 1, 4, 500, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3456 = VRSQRTEfq { 3455, 4, 1, 4, 499, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3455 = VRSQRTEfd { 3454, 4, 1, 4, 499, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3454 = VRSQRTEd { 3453, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1810, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3453 = VRSHRuv8i8 { 3452, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1815, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3452 = VRSHRuv8i16 { 3451, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1815, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3451 = VRSHRuv4i32 { 3450, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1810, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3450 = VRSHRuv4i16 { 3449, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1815, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3449 = VRSHRuv2i64 { 3448, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1810, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3448 = VRSHRuv2i32 { 3447, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1810, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3447 = VRSHRuv1i64 { 3446, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1815, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3446 = VRSHRuv16i8 { 3445, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1810, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3445 = VRSHRsv8i8 { 3444, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1815, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3444 = VRSHRsv8i16 { 3443, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1815, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3443 = VRSHRsv4i32 { 3442, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1810, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3442 = VRSHRsv4i16 { 3441, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1815, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3441 = VRSHRsv2i64 { 3440, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1810, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3440 = VRSHRsv2i32 { 3439, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1810, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3439 = VRSHRsv1i64 { 3438, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1815, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3438 = VRSHRsv16i8 { 3437, 5, 1, 4, 798, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3437 = VRSHRNv8i8 { 3436, 5, 1, 4, 798, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3436 = VRSHRNv4i16 { 3435, 5, 1, 4, 798, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3435 = VRSHRNv2i32 { 3434, 5, 1, 4, 797, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3434 = VRSHLuv8i8 { 3433, 5, 1, 4, 796, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3433 = VRSHLuv8i16 { 3432, 5, 1, 4, 796, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3432 = VRSHLuv4i32 { 3431, 5, 1, 4, 797, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3431 = VRSHLuv4i16 { 3430, 5, 1, 4, 796, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3430 = VRSHLuv2i64 { 3429, 5, 1, 4, 797, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3429 = VRSHLuv2i32 { 3428, 5, 1, 4, 797, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3428 = VRSHLuv1i64 { 3427, 5, 1, 4, 796, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3427 = VRSHLuv16i8 { 3426, 5, 1, 4, 797, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3426 = VRSHLsv8i8 { 3425, 5, 1, 4, 796, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3425 = VRSHLsv8i16 { 3424, 5, 1, 4, 796, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3424 = VRSHLsv4i32 { 3423, 5, 1, 4, 797, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3423 = VRSHLsv4i16 { 3422, 5, 1, 4, 796, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3422 = VRSHLsv2i64 { 3421, 5, 1, 4, 797, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3421 = VRSHLsv2i32 { 3420, 5, 1, 4, 797, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3420 = VRSHLsv1i64 { 3419, 5, 1, 4, 796, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3419 = VRSHLsv16i8 { 3418, 4, 1, 4, 1252, 0, 0, ARMImpOpBase + 0, 1683, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3418 = VRINTZS { 3417, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 625, 0, 0x11000ULL }, // Inst #3417 = VRINTZNQh { 3416, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 625, 0, 0x11000ULL }, // Inst #3416 = VRINTZNQf { 3415, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1789, 0, 0x11000ULL }, // Inst #3415 = VRINTZNDh { 3414, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1789, 0, 0x11000ULL }, // Inst #3414 = VRINTZNDf { 3413, 4, 1, 4, 961, 0, 0, ARMImpOpBase + 0, 1679, 0, 0x8780ULL }, // Inst #3413 = VRINTZH { 3412, 4, 1, 4, 1256, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3412 = VRINTZD { 3411, 4, 1, 4, 1252, 0, 0, ARMImpOpBase + 0, 1683, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3411 = VRINTXS { 3410, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 625, 0, 0x11000ULL }, // Inst #3410 = VRINTXNQh { 3409, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 625, 0, 0x11000ULL }, // Inst #3409 = VRINTXNQf { 3408, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1789, 0, 0x11000ULL }, // Inst #3408 = VRINTXNDh { 3407, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1789, 0, 0x11000ULL }, // Inst #3407 = VRINTXNDf { 3406, 4, 1, 4, 961, 0, 0, ARMImpOpBase + 0, 1679, 0, 0x8780ULL }, // Inst #3406 = VRINTXH { 3405, 4, 1, 4, 1256, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3405 = VRINTXD { 3404, 4, 1, 4, 1252, 0, 0, ARMImpOpBase + 0, 1683, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3404 = VRINTRS { 3403, 4, 1, 4, 961, 0, 0, ARMImpOpBase + 0, 1679, 0, 0x8780ULL }, // Inst #3403 = VRINTRH { 3402, 4, 1, 4, 1256, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3402 = VRINTRD { 3401, 2, 1, 4, 1252, 0, 0, ARMImpOpBase + 0, 1795, 0, 0x8780ULL }, // Inst #3401 = VRINTPS { 3400, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 625, 0, 0x11000ULL }, // Inst #3400 = VRINTPNQh { 3399, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 625, 0, 0x11000ULL }, // Inst #3399 = VRINTPNQf { 3398, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1789, 0, 0x11000ULL }, // Inst #3398 = VRINTPNDh { 3397, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1789, 0, 0x11000ULL }, // Inst #3397 = VRINTPNDf { 3396, 2, 1, 4, 961, 0, 0, ARMImpOpBase + 0, 2362, 0, 0x8780ULL }, // Inst #3396 = VRINTPH { 3395, 2, 1, 4, 1256, 0, 0, ARMImpOpBase + 0, 1789, 0, 0x8780ULL }, // Inst #3395 = VRINTPD { 3394, 2, 1, 4, 1252, 0, 0, ARMImpOpBase + 0, 1795, 0, 0x8780ULL }, // Inst #3394 = VRINTNS { 3393, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 625, 0, 0x11000ULL }, // Inst #3393 = VRINTNNQh { 3392, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 625, 0, 0x11000ULL }, // Inst #3392 = VRINTNNQf { 3391, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1789, 0, 0x11000ULL }, // Inst #3391 = VRINTNNDh { 3390, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1789, 0, 0x11000ULL }, // Inst #3390 = VRINTNNDf { 3389, 2, 1, 4, 961, 0, 0, ARMImpOpBase + 0, 2362, 0, 0x8780ULL }, // Inst #3389 = VRINTNH { 3388, 2, 1, 4, 1256, 0, 0, ARMImpOpBase + 0, 1789, 0, 0x8780ULL }, // Inst #3388 = VRINTND { 3387, 2, 1, 4, 1252, 0, 0, ARMImpOpBase + 0, 1795, 0, 0x8780ULL }, // Inst #3387 = VRINTMS { 3386, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 625, 0, 0x11000ULL }, // Inst #3386 = VRINTMNQh { 3385, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 625, 0, 0x11000ULL }, // Inst #3385 = VRINTMNQf { 3384, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1789, 0, 0x11000ULL }, // Inst #3384 = VRINTMNDh { 3383, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1789, 0, 0x11000ULL }, // Inst #3383 = VRINTMNDf { 3382, 2, 1, 4, 961, 0, 0, ARMImpOpBase + 0, 2362, 0, 0x8780ULL }, // Inst #3382 = VRINTMH { 3381, 2, 1, 4, 1256, 0, 0, ARMImpOpBase + 0, 1789, 0, 0x8780ULL }, // Inst #3381 = VRINTMD { 3380, 2, 1, 4, 1252, 0, 0, ARMImpOpBase + 0, 1795, 0, 0x8780ULL }, // Inst #3380 = VRINTAS { 3379, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 625, 0, 0x11000ULL }, // Inst #3379 = VRINTANQh { 3378, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 625, 0, 0x11000ULL }, // Inst #3378 = VRINTANQf { 3377, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1789, 0, 0x11000ULL }, // Inst #3377 = VRINTANDh { 3376, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1789, 0, 0x11000ULL }, // Inst #3376 = VRINTANDf { 3375, 2, 1, 4, 961, 0, 0, ARMImpOpBase + 0, 2362, 0, 0x8780ULL }, // Inst #3375 = VRINTAH { 3374, 2, 1, 4, 1256, 0, 0, ARMImpOpBase + 0, 1789, 0, 0x8780ULL }, // Inst #3374 = VRINTAD { 3373, 5, 1, 4, 973, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3373 = VRHADDuv8i8 { 3372, 5, 1, 4, 972, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3372 = VRHADDuv8i16 { 3371, 5, 1, 4, 972, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3371 = VRHADDuv4i32 { 3370, 5, 1, 4, 973, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3370 = VRHADDuv4i16 { 3369, 5, 1, 4, 973, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3369 = VRHADDuv2i32 { 3368, 5, 1, 4, 972, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3368 = VRHADDuv16i8 { 3367, 5, 1, 4, 973, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3367 = VRHADDsv8i8 { 3366, 5, 1, 4, 972, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3366 = VRHADDsv8i16 { 3365, 5, 1, 4, 972, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3365 = VRHADDsv4i32 { 3364, 5, 1, 4, 973, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3364 = VRHADDsv4i16 { 3363, 5, 1, 4, 973, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3363 = VRHADDsv2i32 { 3362, 5, 1, 4, 972, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3362 = VRHADDsv16i8 { 3361, 4, 1, 4, 479, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3361 = VREV64q8 { 3360, 4, 1, 4, 479, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3360 = VREV64q32 { 3359, 4, 1, 4, 479, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3359 = VREV64q16 { 3358, 4, 1, 4, 478, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3358 = VREV64d8 { 3357, 4, 1, 4, 478, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3357 = VREV64d32 { 3356, 4, 1, 4, 478, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3356 = VREV64d16 { 3355, 4, 1, 4, 479, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3355 = VREV32q8 { 3354, 4, 1, 4, 479, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3354 = VREV32q16 { 3353, 4, 1, 4, 478, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3353 = VREV32d8 { 3352, 4, 1, 4, 478, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3352 = VREV32d16 { 3351, 4, 1, 4, 479, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3351 = VREV16q8 { 3350, 4, 1, 4, 478, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3350 = VREV16d8 { 3349, 5, 1, 4, 529, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3349 = VRECPShq { 3348, 5, 1, 4, 528, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3348 = VRECPShd { 3347, 5, 1, 4, 529, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3347 = VRECPSfq { 3346, 5, 1, 4, 528, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3346 = VRECPSfd { 3345, 4, 1, 4, 500, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3345 = VRECPEq { 3344, 4, 1, 4, 500, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3344 = VRECPEhq { 3343, 4, 1, 4, 499, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3343 = VRECPEhd { 3342, 4, 1, 4, 500, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3342 = VRECPEfq { 3341, 4, 1, 4, 499, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3341 = VRECPEfd { 3340, 4, 1, 4, 499, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3340 = VRECPEd { 3339, 5, 1, 4, 503, 0, 0, ARMImpOpBase + 0, 1696, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3339 = VRADDHNv8i8 { 3338, 5, 1, 4, 503, 0, 0, ARMImpOpBase + 0, 1696, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3338 = VRADDHNv4i16 { 3337, 5, 1, 4, 503, 0, 0, ARMImpOpBase + 0, 1696, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3337 = VRADDHNv2i32 { 3336, 5, 1, 4, 487, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3336 = VQSUBuv8i8 { 3335, 5, 1, 4, 486, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3335 = VQSUBuv8i16 { 3334, 5, 1, 4, 486, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3334 = VQSUBuv4i32 { 3333, 5, 1, 4, 487, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3333 = VQSUBuv4i16 { 3332, 5, 1, 4, 486, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3332 = VQSUBuv2i64 { 3331, 5, 1, 4, 487, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3331 = VQSUBuv2i32 { 3330, 5, 1, 4, 487, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3330 = VQSUBuv1i64 { 3329, 5, 1, 4, 486, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3329 = VQSUBuv16i8 { 3328, 5, 1, 4, 487, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3328 = VQSUBsv8i8 { 3327, 5, 1, 4, 486, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3327 = VQSUBsv8i16 { 3326, 5, 1, 4, 486, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3326 = VQSUBsv4i32 { 3325, 5, 1, 4, 487, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3325 = VQSUBsv4i16 { 3324, 5, 1, 4, 486, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3324 = VQSUBsv2i64 { 3323, 5, 1, 4, 487, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3323 = VQSUBsv2i32 { 3322, 5, 1, 4, 487, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3322 = VQSUBsv1i64 { 3321, 5, 1, 4, 486, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3321 = VQSUBsv16i8 { 3320, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3320 = VQSHRUNv8i8 { 3319, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3319 = VQSHRUNv4i16 { 3318, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3318 = VQSHRUNv2i32 { 3317, 5, 1, 4, 795, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3317 = VQSHRNuv8i8 { 3316, 5, 1, 4, 795, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3316 = VQSHRNuv4i16 { 3315, 5, 1, 4, 795, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3315 = VQSHRNuv2i32 { 3314, 5, 1, 4, 795, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3314 = VQSHRNsv8i8 { 3313, 5, 1, 4, 795, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3313 = VQSHRNsv4i16 { 3312, 5, 1, 4, 795, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3312 = VQSHRNsv2i32 { 3311, 5, 1, 4, 472, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3311 = VQSHLuv8i8 { 3310, 5, 1, 4, 473, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3310 = VQSHLuv8i16 { 3309, 5, 1, 4, 473, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3309 = VQSHLuv4i32 { 3308, 5, 1, 4, 472, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3308 = VQSHLuv4i16 { 3307, 5, 1, 4, 473, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3307 = VQSHLuv2i64 { 3306, 5, 1, 4, 472, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3306 = VQSHLuv2i32 { 3305, 5, 1, 4, 472, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3305 = VQSHLuv1i64 { 3304, 5, 1, 4, 473, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3304 = VQSHLuv16i8 { 3303, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2357, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3303 = VQSHLuiv8i8 { 3302, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2352, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3302 = VQSHLuiv8i16 { 3301, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2352, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3301 = VQSHLuiv4i32 { 3300, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2357, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3300 = VQSHLuiv4i16 { 3299, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2352, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3299 = VQSHLuiv2i64 { 3298, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2357, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3298 = VQSHLuiv2i32 { 3297, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2357, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3297 = VQSHLuiv1i64 { 3296, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2352, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3296 = VQSHLuiv16i8 { 3295, 5, 1, 4, 472, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3295 = VQSHLsv8i8 { 3294, 5, 1, 4, 473, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3294 = VQSHLsv8i16 { 3293, 5, 1, 4, 473, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3293 = VQSHLsv4i32 { 3292, 5, 1, 4, 472, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3292 = VQSHLsv4i16 { 3291, 5, 1, 4, 473, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3291 = VQSHLsv2i64 { 3290, 5, 1, 4, 472, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3290 = VQSHLsv2i32 { 3289, 5, 1, 4, 472, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3289 = VQSHLsv1i64 { 3288, 5, 1, 4, 473, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3288 = VQSHLsv16i8 { 3287, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2357, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3287 = VQSHLsuv8i8 { 3286, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2352, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3286 = VQSHLsuv8i16 { 3285, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2352, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3285 = VQSHLsuv4i32 { 3284, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2357, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3284 = VQSHLsuv4i16 { 3283, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2352, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3283 = VQSHLsuv2i64 { 3282, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2357, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3282 = VQSHLsuv2i32 { 3281, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2357, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3281 = VQSHLsuv1i64 { 3280, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2352, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3280 = VQSHLsuv16i8 { 3279, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2357, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3279 = VQSHLsiv8i8 { 3278, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2352, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3278 = VQSHLsiv8i16 { 3277, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2352, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3277 = VQSHLsiv4i32 { 3276, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2357, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3276 = VQSHLsiv4i16 { 3275, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2352, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3275 = VQSHLsiv2i64 { 3274, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2357, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3274 = VQSHLsiv2i32 { 3273, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2357, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3273 = VQSHLsiv1i64 { 3272, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2352, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3272 = VQSHLsiv16i8 { 3271, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3271 = VQRSHRUNv8i8 { 3270, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3270 = VQRSHRUNv4i16 { 3269, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3269 = VQRSHRUNv2i32 { 3268, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3268 = VQRSHRNuv8i8 { 3267, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3267 = VQRSHRNuv4i16 { 3266, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3266 = VQRSHRNuv2i32 { 3265, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3265 = VQRSHRNsv8i8 { 3264, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3264 = VQRSHRNsv4i16 { 3263, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2347, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3263 = VQRSHRNsv2i32 { 3262, 5, 1, 4, 490, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3262 = VQRSHLuv8i8 { 3261, 5, 1, 4, 489, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3261 = VQRSHLuv8i16 { 3260, 5, 1, 4, 489, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3260 = VQRSHLuv4i32 { 3259, 5, 1, 4, 490, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3259 = VQRSHLuv4i16 { 3258, 5, 1, 4, 489, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3258 = VQRSHLuv2i64 { 3257, 5, 1, 4, 490, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3257 = VQRSHLuv2i32 { 3256, 5, 1, 4, 490, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3256 = VQRSHLuv1i64 { 3255, 5, 1, 4, 489, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3255 = VQRSHLuv16i8 { 3254, 5, 1, 4, 490, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3254 = VQRSHLsv8i8 { 3253, 5, 1, 4, 489, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3253 = VQRSHLsv8i16 { 3252, 5, 1, 4, 489, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3252 = VQRSHLsv4i32 { 3251, 5, 1, 4, 490, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3251 = VQRSHLsv4i16 { 3250, 5, 1, 4, 489, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3250 = VQRSHLsv2i64 { 3249, 5, 1, 4, 490, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3249 = VQRSHLsv2i32 { 3248, 5, 1, 4, 490, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3248 = VQRSHLsv1i64 { 3247, 5, 1, 4, 489, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3247 = VQRSHLsv16i8 { 3246, 5, 1, 4, 794, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3246 = VQRDMULHv8i16 { 3245, 5, 1, 4, 793, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3245 = VQRDMULHv4i32 { 3244, 5, 1, 4, 978, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3244 = VQRDMULHv4i16 { 3243, 5, 1, 4, 977, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3243 = VQRDMULHv2i32 { 3242, 6, 1, 4, 794, 0, 0, ARMImpOpBase + 0, 2336, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3242 = VQRDMULHslv8i16 { 3241, 6, 1, 4, 793, 0, 0, ARMImpOpBase + 0, 2324, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3241 = VQRDMULHslv4i32 { 3240, 6, 1, 4, 978, 0, 0, ARMImpOpBase + 0, 2330, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3240 = VQRDMULHslv4i16 { 3239, 6, 1, 4, 977, 0, 0, ARMImpOpBase + 0, 2318, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3239 = VQRDMULHslv2i32 { 3238, 6, 1, 4, 985, 0, 0, ARMImpOpBase + 0, 1648, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3238 = VQRDMLSHv8i16 { 3237, 6, 1, 4, 984, 0, 0, ARMImpOpBase + 0, 1648, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3237 = VQRDMLSHv4i32 { 3236, 6, 1, 4, 983, 0, 0, ARMImpOpBase + 0, 1654, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3236 = VQRDMLSHv4i16 { 3235, 6, 1, 4, 982, 0, 0, ARMImpOpBase + 0, 1654, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3235 = VQRDMLSHv2i32 { 3234, 7, 1, 4, 985, 0, 0, ARMImpOpBase + 0, 2241, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL }, // Inst #3234 = VQRDMLSHslv8i16 { 3233, 7, 1, 4, 984, 0, 0, ARMImpOpBase + 0, 2227, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL }, // Inst #3233 = VQRDMLSHslv4i32 { 3232, 7, 1, 4, 983, 0, 0, ARMImpOpBase + 0, 2234, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3232 = VQRDMLSHslv4i16 { 3231, 7, 1, 4, 982, 0, 0, ARMImpOpBase + 0, 2220, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3231 = VQRDMLSHslv2i32 { 3230, 6, 1, 4, 985, 0, 0, ARMImpOpBase + 0, 1648, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3230 = VQRDMLAHv8i16 { 3229, 6, 1, 4, 984, 0, 0, ARMImpOpBase + 0, 1648, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3229 = VQRDMLAHv4i32 { 3228, 6, 1, 4, 983, 0, 0, ARMImpOpBase + 0, 1654, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3228 = VQRDMLAHv4i16 { 3227, 6, 1, 4, 982, 0, 0, ARMImpOpBase + 0, 1654, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3227 = VQRDMLAHv2i32 { 3226, 7, 1, 4, 985, 0, 0, ARMImpOpBase + 0, 2241, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL }, // Inst #3226 = VQRDMLAHslv8i16 { 3225, 7, 1, 4, 984, 0, 0, ARMImpOpBase + 0, 2227, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL }, // Inst #3225 = VQRDMLAHslv4i32 { 3224, 7, 1, 4, 983, 0, 0, ARMImpOpBase + 0, 2234, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3224 = VQRDMLAHslv4i16 { 3223, 7, 1, 4, 982, 0, 0, ARMImpOpBase + 0, 2220, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3223 = VQRDMLAHslv2i32 { 3222, 4, 1, 4, 496, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3222 = VQNEGv8i8 { 3221, 4, 1, 4, 495, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3221 = VQNEGv8i16 { 3220, 4, 1, 4, 495, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3220 = VQNEGv4i32 { 3219, 4, 1, 4, 496, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3219 = VQNEGv4i16 { 3218, 4, 1, 4, 496, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3218 = VQNEGv2i32 { 3217, 4, 1, 4, 495, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3217 = VQNEGv16i8 { 3216, 4, 1, 4, 574, 0, 0, ARMImpOpBase + 0, 645, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3216 = VQMOVNuv8i8 { 3215, 4, 1, 4, 574, 0, 0, ARMImpOpBase + 0, 645, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3215 = VQMOVNuv4i16 { 3214, 4, 1, 4, 574, 0, 0, ARMImpOpBase + 0, 645, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3214 = VQMOVNuv2i32 { 3213, 4, 1, 4, 574, 0, 0, ARMImpOpBase + 0, 645, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3213 = VQMOVNsv8i8 { 3212, 4, 1, 4, 574, 0, 0, ARMImpOpBase + 0, 645, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3212 = VQMOVNsv4i16 { 3211, 4, 1, 4, 574, 0, 0, ARMImpOpBase + 0, 645, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3211 = VQMOVNsv2i32 { 3210, 4, 1, 4, 574, 0, 0, ARMImpOpBase + 0, 645, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3210 = VQMOVNsuv8i8 { 3209, 4, 1, 4, 574, 0, 0, ARMImpOpBase + 0, 645, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3209 = VQMOVNsuv4i16 { 3208, 4, 1, 4, 574, 0, 0, ARMImpOpBase + 0, 645, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3208 = VQMOVNsuv2i32 { 3207, 5, 1, 4, 792, 0, 0, ARMImpOpBase + 0, 1660, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3207 = VQDMULLv4i32 { 3206, 5, 1, 4, 791, 0, 0, ARMImpOpBase + 0, 1660, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3206 = VQDMULLv2i64 { 3205, 6, 1, 4, 792, 0, 0, ARMImpOpBase + 0, 2312, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3205 = VQDMULLslv4i16 { 3204, 6, 1, 4, 792, 0, 0, ARMImpOpBase + 0, 2306, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3204 = VQDMULLslv2i32 { 3203, 5, 1, 4, 794, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3203 = VQDMULHv8i16 { 3202, 5, 1, 4, 793, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3202 = VQDMULHv4i32 { 3201, 5, 1, 4, 978, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3201 = VQDMULHv4i16 { 3200, 5, 1, 4, 977, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3200 = VQDMULHv2i32 { 3199, 6, 1, 4, 794, 0, 0, ARMImpOpBase + 0, 2336, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3199 = VQDMULHslv8i16 { 3198, 6, 1, 4, 793, 0, 0, ARMImpOpBase + 0, 2324, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3198 = VQDMULHslv4i32 { 3197, 6, 1, 4, 978, 0, 0, ARMImpOpBase + 0, 2330, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3197 = VQDMULHslv4i16 { 3196, 6, 1, 4, 977, 0, 0, ARMImpOpBase + 0, 2318, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3196 = VQDMULHslv2i32 { 3195, 6, 1, 4, 790, 0, 0, ARMImpOpBase + 0, 1642, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3195 = VQDMLSLv4i32 { 3194, 6, 1, 4, 789, 0, 0, ARMImpOpBase + 0, 1642, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3194 = VQDMLSLv2i64 { 3193, 7, 1, 4, 790, 0, 0, ARMImpOpBase + 0, 2213, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3193 = VQDMLSLslv4i16 { 3192, 7, 1, 4, 789, 0, 0, ARMImpOpBase + 0, 2206, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3192 = VQDMLSLslv2i32 { 3191, 6, 1, 4, 790, 0, 0, ARMImpOpBase + 0, 1642, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3191 = VQDMLALv4i32 { 3190, 6, 1, 4, 789, 0, 0, ARMImpOpBase + 0, 1642, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3190 = VQDMLALv2i64 { 3189, 7, 1, 4, 790, 0, 0, ARMImpOpBase + 0, 2213, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3189 = VQDMLALslv4i16 { 3188, 7, 1, 4, 789, 0, 0, ARMImpOpBase + 0, 2206, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3188 = VQDMLALslv2i32 { 3187, 5, 1, 4, 498, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3187 = VQADDuv8i8 { 3186, 5, 1, 4, 497, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3186 = VQADDuv8i16 { 3185, 5, 1, 4, 497, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3185 = VQADDuv4i32 { 3184, 5, 1, 4, 498, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3184 = VQADDuv4i16 { 3183, 5, 1, 4, 497, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3183 = VQADDuv2i64 { 3182, 5, 1, 4, 498, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3182 = VQADDuv2i32 { 3181, 5, 1, 4, 498, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3181 = VQADDuv1i64 { 3180, 5, 1, 4, 497, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3180 = VQADDuv16i8 { 3179, 5, 1, 4, 498, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3179 = VQADDsv8i8 { 3178, 5, 1, 4, 497, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3178 = VQADDsv8i16 { 3177, 5, 1, 4, 497, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3177 = VQADDsv4i32 { 3176, 5, 1, 4, 498, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3176 = VQADDsv4i16 { 3175, 5, 1, 4, 497, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3175 = VQADDsv2i64 { 3174, 5, 1, 4, 498, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3174 = VQADDsv2i32 { 3173, 5, 1, 4, 498, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3173 = VQADDsv1i64 { 3172, 5, 1, 4, 497, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3172 = VQADDsv16i8 { 3171, 4, 1, 4, 787, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3171 = VQABSv8i8 { 3170, 4, 1, 4, 788, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3170 = VQABSv8i16 { 3169, 4, 1, 4, 788, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3169 = VQABSv4i32 { 3168, 4, 1, 4, 787, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3168 = VQABSv4i16 { 3167, 4, 1, 4, 787, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3167 = VQABSv2i32 { 3166, 4, 1, 4, 788, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3166 = VQABSv16i8 { 3165, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3165 = VPMINu8 { 3164, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3164 = VPMINu32 { 3163, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3163 = VPMINu16 { 3162, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3162 = VPMINs8 { 3161, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3161 = VPMINs32 { 3160, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3160 = VPMINs16 { 3159, 5, 1, 4, 778, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3159 = VPMINh { 3158, 5, 1, 4, 778, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3158 = VPMINf { 3157, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3157 = VPMAXu8 { 3156, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3156 = VPMAXu32 { 3155, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3155 = VPMAXu16 { 3154, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3154 = VPMAXs8 { 3153, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3153 = VPMAXs32 { 3152, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3152 = VPMAXs16 { 3151, 5, 1, 4, 778, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3151 = VPMAXh { 3150, 5, 1, 4, 778, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3150 = VPMAXf { 3149, 5, 1, 4, 784, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3149 = VPADDi8 { 3148, 5, 1, 4, 784, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3148 = VPADDi32 { 3147, 5, 1, 4, 784, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3147 = VPADDi16 { 3146, 5, 1, 4, 992, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3146 = VPADDh { 3145, 5, 1, 4, 526, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3145 = VPADDf { 3144, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3144 = VPADDLuv8i8 { 3143, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3143 = VPADDLuv8i16 { 3142, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3142 = VPADDLuv4i32 { 3141, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3141 = VPADDLuv4i16 { 3140, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3140 = VPADDLuv2i32 { 3139, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3139 = VPADDLuv16i8 { 3138, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3138 = VPADDLsv8i8 { 3137, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3137 = VPADDLsv8i16 { 3136, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3136 = VPADDLsv4i32 { 3135, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3135 = VPADDLsv4i16 { 3134, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3134 = VPADDLsv2i32 { 3133, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3133 = VPADDLsv16i8 { 3132, 5, 1, 4, 785, 0, 0, ARMImpOpBase + 0, 397, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3132 = VPADALuv8i8 { 3131, 5, 1, 4, 482, 0, 0, ARMImpOpBase + 0, 2342, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3131 = VPADALuv8i16 { 3130, 5, 1, 4, 482, 0, 0, ARMImpOpBase + 0, 2342, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3130 = VPADALuv4i32 { 3129, 5, 1, 4, 785, 0, 0, ARMImpOpBase + 0, 397, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3129 = VPADALuv4i16 { 3128, 5, 1, 4, 785, 0, 0, ARMImpOpBase + 0, 397, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3128 = VPADALuv2i32 { 3127, 5, 1, 4, 482, 0, 0, ARMImpOpBase + 0, 2342, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3127 = VPADALuv16i8 { 3126, 5, 1, 4, 785, 0, 0, ARMImpOpBase + 0, 397, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3126 = VPADALsv8i8 { 3125, 5, 1, 4, 482, 0, 0, ARMImpOpBase + 0, 2342, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3125 = VPADALsv8i16 { 3124, 5, 1, 4, 482, 0, 0, ARMImpOpBase + 0, 2342, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3124 = VPADALsv4i32 { 3123, 5, 1, 4, 785, 0, 0, ARMImpOpBase + 0, 397, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3123 = VPADALsv4i16 { 3122, 5, 1, 4, 785, 0, 0, ARMImpOpBase + 0, 397, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3122 = VPADALsv2i32 { 3121, 5, 1, 4, 482, 0, 0, ARMImpOpBase + 0, 2342, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3121 = VPADALsv16i8 { 3120, 5, 1, 4, 459, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3120 = VORRq { 3119, 5, 1, 4, 471, 0, 0, ARMImpOpBase + 0, 1721, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // Inst #3119 = VORRiv8i16 { 3118, 5, 1, 4, 471, 0, 0, ARMImpOpBase + 0, 1721, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // Inst #3118 = VORRiv4i32 { 3117, 5, 1, 4, 471, 0, 0, ARMImpOpBase + 0, 1716, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // Inst #3117 = VORRiv4i16 { 3116, 5, 1, 4, 471, 0, 0, ARMImpOpBase + 0, 1716, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // Inst #3116 = VORRiv2i32 { 3115, 5, 1, 4, 460, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3115 = VORRd { 3114, 5, 1, 4, 459, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3114 = VORNq { 3113, 5, 1, 4, 460, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3113 = VORNd { 3112, 5, 1, 4, 530, 0, 0, ARMImpOpBase + 0, 1701, 0|(1ULL<<MCID::Predicable), 0x28800ULL }, // Inst #3112 = VNMULS { 3111, 5, 1, 4, 202, 0, 0, ARMImpOpBase + 0, 1691, 0, 0x8800ULL }, // Inst #3111 = VNMULH { 3110, 5, 1, 4, 1261, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #3110 = VNMULD { 3109, 6, 1, 4, 544, 0, 0, ARMImpOpBase + 0, 1869, 0|(1ULL<<MCID::Predicable), 0x28800ULL }, // Inst #3109 = VNMLSS { 3108, 6, 1, 4, 541, 0, 0, ARMImpOpBase + 0, 1849, 0, 0x8800ULL }, // Inst #3108 = VNMLSH { 3107, 6, 1, 4, 540, 0, 0, ARMImpOpBase + 0, 1654, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #3107 = VNMLSD { 3106, 6, 1, 4, 544, 0, 0, ARMImpOpBase + 0, 1869, 0|(1ULL<<MCID::Predicable), 0x28800ULL }, // Inst #3106 = VNMLAS { 3105, 6, 1, 4, 541, 0, 0, ARMImpOpBase + 0, 1849, 0, 0x8800ULL }, // Inst #3105 = VNMLAH { 3104, 6, 1, 4, 540, 0, 0, ARMImpOpBase + 0, 1654, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #3104 = VNMLAD { 3103, 4, 1, 4, 783, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3103 = VNEGs8q { 3102, 4, 1, 4, 782, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3102 = VNEGs8d { 3101, 4, 1, 4, 783, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3101 = VNEGs32q { 3100, 4, 1, 4, 782, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3100 = VNEGs32d { 3099, 4, 1, 4, 783, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3099 = VNEGs16q { 3098, 4, 1, 4, 782, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3098 = VNEGs16d { 3097, 4, 1, 4, 781, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3097 = VNEGhq { 3096, 4, 1, 4, 780, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3096 = VNEGhd { 3095, 4, 1, 4, 464, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3095 = VNEGfd { 3094, 4, 1, 4, 463, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3094 = VNEGf32q { 3093, 4, 1, 4, 518, 0, 0, ARMImpOpBase + 0, 1683, 0|(1ULL<<MCID::Predicable), 0x28780ULL }, // Inst #3093 = VNEGS { 3092, 4, 1, 4, 779, 0, 0, ARMImpOpBase + 0, 1679, 0, 0x8780ULL }, // Inst #3092 = VNEGH { 3091, 4, 1, 4, 517, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3091 = VNEGD { 3090, 4, 1, 4, 974, 0, 0, ARMImpOpBase + 0, 2286, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL }, // Inst #3090 = VMVNv8i16 { 3089, 4, 1, 4, 974, 0, 0, ARMImpOpBase + 0, 2286, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL }, // Inst #3089 = VMVNv4i32 { 3088, 4, 1, 4, 974, 0, 0, ARMImpOpBase + 0, 861, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL }, // Inst #3088 = VMVNv4i16 { 3087, 4, 1, 4, 974, 0, 0, ARMImpOpBase + 0, 861, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL }, // Inst #3087 = VMVNv2i32 { 3086, 4, 1, 4, 571, 0, 0, ARMImpOpBase + 0, 1687, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3086 = VMVNq { 3085, 4, 1, 4, 571, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3085 = VMVNd { 3084, 5, 1, 4, 975, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3084 = VMULv8i8 { 3083, 5, 1, 4, 979, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3083 = VMULv8i16 { 3082, 5, 1, 4, 538, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3082 = VMULv4i32 { 3081, 5, 1, 4, 975, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3081 = VMULv4i16 { 3080, 5, 1, 4, 976, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3080 = VMULv2i32 { 3079, 5, 1, 4, 979, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3079 = VMULv16i8 { 3078, 6, 1, 4, 979, 0, 0, ARMImpOpBase + 0, 2336, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3078 = VMULslv8i16 { 3077, 6, 1, 4, 538, 0, 0, ARMImpOpBase + 0, 2324, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3077 = VMULslv4i32 { 3076, 6, 1, 4, 975, 0, 0, ARMImpOpBase + 0, 2330, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3076 = VMULslv4i16 { 3075, 6, 1, 4, 976, 0, 0, ARMImpOpBase + 0, 2318, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3075 = VMULslv2i32 { 3074, 6, 1, 4, 534, 0, 0, ARMImpOpBase + 0, 2336, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3074 = VMULslhq { 3073, 6, 1, 4, 533, 0, 0, ARMImpOpBase + 0, 2330, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3073 = VMULslhd { 3072, 6, 1, 4, 536, 0, 0, ARMImpOpBase + 0, 2324, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3072 = VMULslfq { 3071, 6, 1, 4, 535, 0, 0, ARMImpOpBase + 0, 2318, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3071 = VMULslfd { 3070, 5, 1, 4, 979, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3070 = VMULpq { 3069, 5, 1, 4, 975, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3069 = VMULpd { 3068, 5, 1, 4, 999, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3068 = VMULhq { 3067, 5, 1, 4, 998, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3067 = VMULhd { 3066, 5, 1, 4, 532, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3066 = VMULfq { 3065, 5, 1, 4, 531, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3065 = VMULfd { 3064, 5, 1, 4, 530, 0, 0, ARMImpOpBase + 0, 1701, 0|(1ULL<<MCID::Predicable), 0x28800ULL }, // Inst #3064 = VMULS { 3063, 5, 1, 4, 986, 0, 0, ARMImpOpBase + 0, 1660, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3063 = VMULLuv8i16 { 3062, 5, 1, 4, 986, 0, 0, ARMImpOpBase + 0, 1660, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3062 = VMULLuv4i32 { 3061, 5, 1, 4, 537, 0, 0, ARMImpOpBase + 0, 1660, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3061 = VMULLuv2i64 { 3060, 5, 1, 4, 986, 0, 0, ARMImpOpBase + 0, 1660, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3060 = VMULLsv8i16 { 3059, 5, 1, 4, 986, 0, 0, ARMImpOpBase + 0, 1660, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3059 = VMULLsv4i32 { 3058, 5, 1, 4, 537, 0, 0, ARMImpOpBase + 0, 1660, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3058 = VMULLsv2i64 { 3057, 6, 1, 4, 986, 0, 0, ARMImpOpBase + 0, 2312, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3057 = VMULLsluv4i16 { 3056, 6, 1, 4, 986, 0, 0, ARMImpOpBase + 0, 2306, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3056 = VMULLsluv2i32 { 3055, 6, 1, 4, 986, 0, 0, ARMImpOpBase + 0, 2312, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3055 = VMULLslsv4i16 { 3054, 6, 1, 4, 986, 0, 0, ARMImpOpBase + 0, 2306, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3054 = VMULLslsv2i32 { 3053, 5, 1, 4, 986, 0, 0, ARMImpOpBase + 0, 1660, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3053 = VMULLp8 { 3052, 3, 1, 4, 539, 0, 0, ARMImpOpBase + 0, 1862, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3052 = VMULLp64 { 3051, 5, 1, 4, 202, 0, 0, ARMImpOpBase + 0, 1691, 0, 0x8800ULL }, // Inst #3051 = VMULH { 3050, 5, 1, 4, 1261, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #3050 = VMULD { 3049, 3, 0, 4, 1290, 0, 1, ARMImpOpBase + 69, 535, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3049 = VMSR_VPR { 3048, 4, 1, 4, 1290, 0, 0, ARMImpOpBase + 0, 2302, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3048 = VMSR_P0 { 3047, 3, 0, 4, 587, 0, 1, ARMImpOpBase + 71, 1059, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3047 = VMSR_FPSID { 3046, 4, 1, 4, 1290, 0, 0, ARMImpOpBase + 0, 2298, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3046 = VMSR_FPSCR_NZCVQC { 3045, 3, 0, 4, 587, 0, 1, ARMImpOpBase + 71, 1059, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3045 = VMSR_FPINST2 { 3044, 3, 0, 4, 587, 0, 1, ARMImpOpBase + 71, 1059, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3044 = VMSR_FPINST { 3043, 3, 0, 4, 587, 0, 1, ARMImpOpBase + 71, 1059, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3043 = VMSR_FPEXC { 3042, 3, 0, 4, 587, 0, 0, ARMImpOpBase + 0, 535, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3042 = VMSR_FPCXTS { 3041, 3, 0, 4, 587, 0, 0, ARMImpOpBase + 0, 535, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3041 = VMSR_FPCXTNS { 3040, 3, 0, 4, 1290, 0, 1, ARMImpOpBase + 71, 1059, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3040 = VMSR { 3039, 3, 1, 4, 1291, 1, 0, ARMImpOpBase + 69, 535, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3039 = VMRS_VPR { 3038, 4, 1, 4, 1291, 0, 0, ARMImpOpBase + 0, 2294, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3038 = VMRS_P0 { 3037, 3, 1, 4, 586, 1, 0, ARMImpOpBase + 71, 1059, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3037 = VMRS_MVFR2 { 3036, 3, 1, 4, 586, 1, 0, ARMImpOpBase + 71, 1059, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3036 = VMRS_MVFR1 { 3035, 3, 1, 4, 586, 1, 0, ARMImpOpBase + 71, 1059, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3035 = VMRS_MVFR0 { 3034, 3, 1, 4, 586, 1, 0, ARMImpOpBase + 71, 1059, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3034 = VMRS_FPSID { 3033, 4, 1, 4, 1292, 1, 0, ARMImpOpBase + 71, 2290, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3033 = VMRS_FPSCR_NZCVQC { 3032, 3, 1, 4, 586, 1, 0, ARMImpOpBase + 71, 1059, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3032 = VMRS_FPINST2 { 3031, 3, 1, 4, 586, 1, 0, ARMImpOpBase + 71, 1059, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3031 = VMRS_FPINST { 3030, 3, 1, 4, 586, 1, 0, ARMImpOpBase + 71, 1059, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3030 = VMRS_FPEXC { 3029, 3, 1, 4, 586, 0, 0, ARMImpOpBase + 0, 535, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3029 = VMRS_FPCXTS { 3028, 3, 1, 4, 586, 0, 0, ARMImpOpBase + 0, 535, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3028 = VMRS_FPCXTNS { 3027, 3, 1, 4, 1293, 1, 0, ARMImpOpBase + 71, 1059, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3027 = VMRS { 3026, 4, 1, 4, 568, 0, 0, ARMImpOpBase + 0, 861, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3026 = VMOVv8i8 { 3025, 4, 1, 4, 568, 0, 0, ARMImpOpBase + 0, 2286, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3025 = VMOVv8i16 { 3024, 4, 1, 4, 568, 0, 0, ARMImpOpBase + 0, 2286, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3024 = VMOVv4i32 { 3023, 4, 1, 4, 568, 0, 0, ARMImpOpBase + 0, 861, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3023 = VMOVv4i16 { 3022, 4, 1, 4, 568, 0, 0, ARMImpOpBase + 0, 2286, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3022 = VMOVv4f32 { 3021, 4, 1, 4, 568, 0, 0, ARMImpOpBase + 0, 2286, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3021 = VMOVv2i64 { 3020, 4, 1, 4, 568, 0, 0, ARMImpOpBase + 0, 861, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3020 = VMOVv2i32 { 3019, 4, 1, 4, 568, 0, 0, ARMImpOpBase + 0, 861, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3019 = VMOVv2f32 { 3018, 4, 1, 4, 568, 0, 0, ARMImpOpBase + 0, 861, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3018 = VMOVv1i64 { 3017, 4, 1, 4, 568, 0, 0, ARMImpOpBase + 0, 2286, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3017 = VMOVv16i8 { 3016, 6, 2, 4, 583, 0, 0, ARMImpOpBase + 0, 2280, 0|(1ULL<<MCID::Predicable), 0x18a80ULL }, // Inst #3016 = VMOVSRR { 3015, 4, 1, 4, 579, 0, 0, ARMImpOpBase + 0, 2276, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::Predicable), 0x18a00ULL }, // Inst #3015 = VMOVSR { 3014, 4, 1, 4, 1215, 0, 0, ARMImpOpBase + 0, 1683, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3014 = VMOVS { 3013, 4, 1, 4, 578, 0, 0, ARMImpOpBase + 0, 2272, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::Predicable), 0x18900ULL }, // Inst #3013 = VMOVRS { 3012, 6, 2, 4, 581, 0, 0, ARMImpOpBase + 0, 2266, 0|(1ULL<<MCID::Predicable), 0x18980ULL }, // Inst #3012 = VMOVRRS { 3011, 5, 2, 4, 581, 0, 0, ARMImpOpBase + 0, 2261, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtractSubreg), 0x18980ULL }, // Inst #3011 = VMOVRRD { 3010, 4, 1, 4, 1216, 0, 0, ARMImpOpBase + 0, 2257, 0, 0x8900ULL }, // Inst #3010 = VMOVRH { 3009, 4, 1, 4, 572, 0, 0, ARMImpOpBase + 0, 645, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3009 = VMOVNv8i8 { 3008, 4, 1, 4, 572, 0, 0, ARMImpOpBase + 0, 645, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3008 = VMOVNv4i16 { 3007, 4, 1, 4, 572, 0, 0, ARMImpOpBase + 0, 645, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3007 = VMOVNv2i32 { 3006, 4, 1, 4, 573, 0, 0, ARMImpOpBase + 0, 1820, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3006 = VMOVLuv8i16 { 3005, 4, 1, 4, 573, 0, 0, ARMImpOpBase + 0, 1820, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3005 = VMOVLuv4i32 { 3004, 4, 1, 4, 573, 0, 0, ARMImpOpBase + 0, 1820, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3004 = VMOVLuv2i64 { 3003, 4, 1, 4, 573, 0, 0, ARMImpOpBase + 0, 1820, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3003 = VMOVLsv8i16 { 3002, 4, 1, 4, 573, 0, 0, ARMImpOpBase + 0, 1820, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3002 = VMOVLsv4i32 { 3001, 4, 1, 4, 573, 0, 0, ARMImpOpBase + 0, 1820, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3001 = VMOVLsv2i64 { 3000, 4, 1, 4, 1213, 0, 0, ARMImpOpBase + 0, 2253, 0, 0x8a00ULL }, // Inst #3000 = VMOVHR { 2999, 2, 1, 4, 1212, 0, 0, ARMImpOpBase + 0, 1795, 0, 0x8780ULL }, // Inst #2999 = VMOVH { 2998, 5, 1, 4, 582, 0, 0, ARMImpOpBase + 0, 2248, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::RegSequence), 0x18a80ULL }, // Inst #2998 = VMOVDRR { 2997, 4, 1, 4, 1214, 0, 0, ARMImpOpBase + 0, 1675, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2997 = VMOVD { 2996, 4, 1, 4, 50, 0, 0, ARMImpOpBase + 0, 641, 0, 0x11280ULL }, // Inst #2996 = VMMLA { 2995, 6, 1, 4, 981, 0, 0, ARMImpOpBase + 0, 1654, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2995 = VMLSv8i8 { 2994, 6, 1, 4, 548, 0, 0, ARMImpOpBase + 0, 1648, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2994 = VMLSv8i16 { 2993, 6, 1, 4, 547, 0, 0, ARMImpOpBase + 0, 1648, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2993 = VMLSv4i32 { 2992, 6, 1, 4, 981, 0, 0, ARMImpOpBase + 0, 1654, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2992 = VMLSv4i16 { 2991, 6, 1, 4, 980, 0, 0, ARMImpOpBase + 0, 1654, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2991 = VMLSv2i32 { 2990, 6, 1, 4, 548, 0, 0, ARMImpOpBase + 0, 1648, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2990 = VMLSv16i8 { 2989, 7, 1, 4, 548, 0, 0, ARMImpOpBase + 0, 2241, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2989 = VMLSslv8i16 { 2988, 7, 1, 4, 547, 0, 0, ARMImpOpBase + 0, 2227, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2988 = VMLSslv4i32 { 2987, 7, 1, 4, 981, 0, 0, ARMImpOpBase + 0, 2234, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2987 = VMLSslv4i16 { 2986, 7, 1, 4, 980, 0, 0, ARMImpOpBase + 0, 2220, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2986 = VMLSslv2i32 { 2985, 7, 1, 4, 546, 0, 0, ARMImpOpBase + 0, 2241, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2985 = VMLSslhq { 2984, 7, 1, 4, 545, 0, 0, ARMImpOpBase + 0, 2234, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2984 = VMLSslhd { 2983, 7, 1, 4, 546, 0, 0, ARMImpOpBase + 0, 2227, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2983 = VMLSslfq { 2982, 7, 1, 4, 545, 0, 0, ARMImpOpBase + 0, 2220, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2982 = VMLSslfd { 2981, 6, 1, 4, 546, 0, 0, ARMImpOpBase + 0, 1648, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2981 = VMLShq { 2980, 6, 1, 4, 545, 0, 0, ARMImpOpBase + 0, 1654, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2980 = VMLShd { 2979, 6, 1, 4, 546, 0, 0, ARMImpOpBase + 0, 1648, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2979 = VMLSfq { 2978, 6, 1, 4, 545, 0, 0, ARMImpOpBase + 0, 1654, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2978 = VMLSfd { 2977, 6, 1, 4, 544, 0, 0, ARMImpOpBase + 0, 1869, 0|(1ULL<<MCID::Predicable), 0x28800ULL }, // Inst #2977 = VMLSS { 2976, 6, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 1642, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2976 = VMLSLuv8i16 { 2975, 6, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 1642, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2975 = VMLSLuv4i32 { 2974, 6, 1, 4, 542, 0, 0, ARMImpOpBase + 0, 1642, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2974 = VMLSLuv2i64 { 2973, 6, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 1642, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2973 = VMLSLsv8i16 { 2972, 6, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 1642, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2972 = VMLSLsv4i32 { 2971, 6, 1, 4, 542, 0, 0, ARMImpOpBase + 0, 1642, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2971 = VMLSLsv2i64 { 2970, 7, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 2213, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2970 = VMLSLsluv4i16 { 2969, 7, 1, 4, 542, 0, 0, ARMImpOpBase + 0, 2206, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2969 = VMLSLsluv2i32 { 2968, 7, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 2213, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2968 = VMLSLslsv4i16 { 2967, 7, 1, 4, 542, 0, 0, ARMImpOpBase + 0, 2206, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2967 = VMLSLslsv2i32 { 2966, 6, 1, 4, 541, 0, 0, ARMImpOpBase + 0, 1849, 0, 0x8800ULL }, // Inst #2966 = VMLSH { 2965, 6, 1, 4, 540, 0, 0, ARMImpOpBase + 0, 1654, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2965 = VMLSD { 2964, 6, 1, 4, 981, 0, 0, ARMImpOpBase + 0, 1654, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2964 = VMLAv8i8 { 2963, 6, 1, 4, 548, 0, 0, ARMImpOpBase + 0, 1648, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2963 = VMLAv8i16 { 2962, 6, 1, 4, 547, 0, 0, ARMImpOpBase + 0, 1648, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2962 = VMLAv4i32 { 2961, 6, 1, 4, 981, 0, 0, ARMImpOpBase + 0, 1654, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2961 = VMLAv4i16 { 2960, 6, 1, 4, 980, 0, 0, ARMImpOpBase + 0, 1654, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2960 = VMLAv2i32 { 2959, 6, 1, 4, 548, 0, 0, ARMImpOpBase + 0, 1648, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2959 = VMLAv16i8 { 2958, 7, 1, 4, 548, 0, 0, ARMImpOpBase + 0, 2241, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2958 = VMLAslv8i16 { 2957, 7, 1, 4, 547, 0, 0, ARMImpOpBase + 0, 2227, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2957 = VMLAslv4i32 { 2956, 7, 1, 4, 981, 0, 0, ARMImpOpBase + 0, 2234, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2956 = VMLAslv4i16 { 2955, 7, 1, 4, 980, 0, 0, ARMImpOpBase + 0, 2220, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2955 = VMLAslv2i32 { 2954, 7, 1, 4, 546, 0, 0, ARMImpOpBase + 0, 2241, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2954 = VMLAslhq { 2953, 7, 1, 4, 545, 0, 0, ARMImpOpBase + 0, 2234, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2953 = VMLAslhd { 2952, 7, 1, 4, 546, 0, 0, ARMImpOpBase + 0, 2227, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2952 = VMLAslfq { 2951, 7, 1, 4, 545, 0, 0, ARMImpOpBase + 0, 2220, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2951 = VMLAslfd { 2950, 6, 1, 4, 546, 0, 0, ARMImpOpBase + 0, 1648, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2950 = VMLAhq { 2949, 6, 1, 4, 545, 0, 0, ARMImpOpBase + 0, 1654, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2949 = VMLAhd { 2948, 6, 1, 4, 546, 0, 0, ARMImpOpBase + 0, 1648, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2948 = VMLAfq { 2947, 6, 1, 4, 545, 0, 0, ARMImpOpBase + 0, 1654, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2947 = VMLAfd { 2946, 6, 1, 4, 544, 0, 0, ARMImpOpBase + 0, 1869, 0|(1ULL<<MCID::Predicable), 0x28800ULL }, // Inst #2946 = VMLAS { 2945, 6, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 1642, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2945 = VMLALuv8i16 { 2944, 6, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 1642, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2944 = VMLALuv4i32 { 2943, 6, 1, 4, 542, 0, 0, ARMImpOpBase + 0, 1642, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2943 = VMLALuv2i64 { 2942, 6, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 1642, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2942 = VMLALsv8i16 { 2941, 6, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 1642, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2941 = VMLALsv4i32 { 2940, 6, 1, 4, 542, 0, 0, ARMImpOpBase + 0, 1642, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2940 = VMLALsv2i64 { 2939, 7, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 2213, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2939 = VMLALsluv4i16 { 2938, 7, 1, 4, 542, 0, 0, ARMImpOpBase + 0, 2206, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2938 = VMLALsluv2i32 { 2937, 7, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 2213, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2937 = VMLALslsv4i16 { 2936, 7, 1, 4, 542, 0, 0, ARMImpOpBase + 0, 2206, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2936 = VMLALslsv2i32 { 2935, 6, 1, 4, 541, 0, 0, ARMImpOpBase + 0, 1849, 0, 0x8800ULL }, // Inst #2935 = VMLAH { 2934, 6, 1, 4, 540, 0, 0, ARMImpOpBase + 0, 1654, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2934 = VMLAD { 2933, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2933 = VMINuv8i8 { 2932, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2932 = VMINuv8i16 { 2931, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2931 = VMINuv4i32 { 2930, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2930 = VMINuv4i16 { 2929, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2929 = VMINuv2i32 { 2928, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2928 = VMINuv16i8 { 2927, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2927 = VMINsv8i8 { 2926, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2926 = VMINsv8i16 { 2925, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2925 = VMINsv4i32 { 2924, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2924 = VMINsv4i16 { 2923, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2923 = VMINsv2i32 { 2922, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2922 = VMINsv16i8 { 2921, 5, 1, 4, 523, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2921 = VMINhq { 2920, 5, 1, 4, 522, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2920 = VMINhd { 2919, 5, 1, 4, 523, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2919 = VMINfq { 2918, 5, 1, 4, 522, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2918 = VMINfd { 2917, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2917 = VMAXuv8i8 { 2916, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2916 = VMAXuv8i16 { 2915, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2915 = VMAXuv4i32 { 2914, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2914 = VMAXuv4i16 { 2913, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2913 = VMAXuv2i32 { 2912, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2912 = VMAXuv16i8 { 2911, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2911 = VMAXsv8i8 { 2910, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2910 = VMAXsv8i16 { 2909, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2909 = VMAXsv4i32 { 2908, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2908 = VMAXsv4i16 { 2907, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2907 = VMAXsv2i32 { 2906, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2906 = VMAXsv16i8 { 2905, 5, 1, 4, 523, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2905 = VMAXhq { 2904, 5, 1, 4, 522, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2904 = VMAXhd { 2903, 5, 1, 4, 523, 0, 0, ARMImpOpBase + 0, 1670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2903 = VMAXfq { 2902, 5, 1, 4, 522, 0, 0, ARMImpOpBase + 0, 1665, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2902 = VMAXfd { 2901, 4, 0, 4, 957, 35, 3, ARMImpOpBase + 148, 2202, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b84ULL }, // Inst #2901 = VLSTM_T2 { 2900, 4, 0, 4, 957, 19, 3, ARMImpOpBase + 126, 2202, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b84ULL }, // Inst #2900 = VLSTM { 2899, 4, 0, 4, 937, 0, 35, ARMImpOpBase + 91, 2202, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b84ULL }, // Inst #2899 = VLLDM_T2 { 2898, 4, 0, 4, 937, 0, 19, ARMImpOpBase + 72, 2202, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b84ULL }, // Inst #2898 = VLLDM { 2897, 5, 1, 4, 749, 0, 1, ARMImpOpBase + 69, 2186, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #2897 = VLDR_VPR_pre { 2896, 5, 1, 4, 749, 0, 1, ARMImpOpBase + 69, 2186, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2896 = VLDR_VPR_post { 2895, 4, 0, 4, 749, 0, 1, ARMImpOpBase + 69, 2182, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2895 = VLDR_VPR_off { 2894, 6, 2, 4, 749, 0, 0, ARMImpOpBase + 0, 2196, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #2894 = VLDR_P0_pre { 2893, 6, 2, 4, 749, 0, 0, ARMImpOpBase + 0, 2196, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2893 = VLDR_P0_post { 2892, 5, 1, 4, 749, 0, 0, ARMImpOpBase + 0, 2191, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2892 = VLDR_P0_off { 2891, 5, 1, 4, 749, 1, 0, ARMImpOpBase + 71, 2186, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #2891 = VLDR_FPSCR_pre { 2890, 5, 1, 4, 749, 1, 0, ARMImpOpBase + 71, 2186, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2890 = VLDR_FPSCR_post { 2889, 4, 0, 4, 749, 1, 0, ARMImpOpBase + 71, 2182, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2889 = VLDR_FPSCR_off { 2888, 5, 1, 4, 749, 1, 0, ARMImpOpBase + 71, 2186, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #2888 = VLDR_FPSCR_NZCVQC_pre { 2887, 5, 1, 4, 749, 1, 0, ARMImpOpBase + 71, 2186, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2887 = VLDR_FPSCR_NZCVQC_post { 2886, 4, 0, 4, 749, 1, 0, ARMImpOpBase + 71, 2182, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2886 = VLDR_FPSCR_NZCVQC_off { 2885, 5, 1, 4, 749, 1, 0, ARMImpOpBase + 71, 2186, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #2885 = VLDR_FPCXTS_pre { 2884, 5, 1, 4, 749, 1, 0, ARMImpOpBase + 71, 2186, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2884 = VLDR_FPCXTS_post { 2883, 4, 0, 4, 749, 1, 0, ARMImpOpBase + 71, 2182, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2883 = VLDR_FPCXTS_off { 2882, 5, 1, 4, 749, 1, 0, ARMImpOpBase + 71, 2186, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #2882 = VLDR_FPCXTNS_pre { 2881, 5, 1, 4, 749, 1, 0, ARMImpOpBase + 71, 2186, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2881 = VLDR_FPCXTNS_post { 2880, 4, 0, 4, 749, 1, 0, ARMImpOpBase + 71, 2182, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2880 = VLDR_FPCXTNS_off { 2879, 5, 1, 4, 590, 0, 0, ARMImpOpBase + 0, 2177, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x18b05ULL }, // Inst #2879 = VLDRS { 2878, 5, 1, 4, 748, 0, 0, ARMImpOpBase + 0, 2172, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x18b13ULL }, // Inst #2878 = VLDRH { 2877, 5, 1, 4, 589, 0, 0, ARMImpOpBase + 0, 385, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x18b05ULL }, // Inst #2877 = VLDRD { 2876, 5, 1, 4, 596, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x18be4ULL }, // Inst #2876 = VLDMSIA_UPD { 2875, 4, 0, 4, 595, 0, 0, ARMImpOpBase + 0, 873, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x18b84ULL }, // Inst #2875 = VLDMSIA { 2874, 5, 1, 4, 596, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x18be4ULL }, // Inst #2874 = VLDMSDB_UPD { 2873, 4, 1, 4, 593, 0, 0, ARMImpOpBase + 0, 2168, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x18004ULL }, // Inst #2873 = VLDMQIA { 2872, 5, 1, 4, 596, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x8be4ULL }, // Inst #2872 = VLDMDIA_UPD { 2871, 4, 0, 4, 595, 0, 0, ARMImpOpBase + 0, 873, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x8b84ULL }, // Inst #2871 = VLDMDIA { 2870, 5, 1, 4, 596, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x8be4ULL }, // Inst #2870 = VLDMDDB_UPD { 2869, 8, 2, 4, 618, 0, 0, ARMImpOpBase + 0, 1976, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2869 = VLD4q8oddPseudo_UPD { 2868, 6, 1, 4, 616, 0, 0, ARMImpOpBase + 0, 1970, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2868 = VLD4q8oddPseudo { 2867, 10, 5, 4, 617, 0, 0, ARMImpOpBase + 0, 2130, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2867 = VLD4q8_UPD { 2866, 8, 2, 4, 618, 0, 0, ARMImpOpBase + 0, 1976, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2866 = VLD4q8Pseudo_UPD { 2865, 8, 4, 4, 615, 0, 0, ARMImpOpBase + 0, 2122, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2865 = VLD4q8 { 2864, 8, 2, 4, 618, 0, 0, ARMImpOpBase + 0, 1976, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2864 = VLD4q32oddPseudo_UPD { 2863, 6, 1, 4, 616, 0, 0, ARMImpOpBase + 0, 1970, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2863 = VLD4q32oddPseudo { 2862, 10, 5, 4, 617, 0, 0, ARMImpOpBase + 0, 2130, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2862 = VLD4q32_UPD { 2861, 8, 2, 4, 618, 0, 0, ARMImpOpBase + 0, 1976, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2861 = VLD4q32Pseudo_UPD { 2860, 8, 4, 4, 615, 0, 0, ARMImpOpBase + 0, 2122, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2860 = VLD4q32 { 2859, 8, 2, 4, 618, 0, 0, ARMImpOpBase + 0, 1976, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2859 = VLD4q16oddPseudo_UPD { 2858, 6, 1, 4, 616, 0, 0, ARMImpOpBase + 0, 1970, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2858 = VLD4q16oddPseudo { 2857, 10, 5, 4, 617, 0, 0, ARMImpOpBase + 0, 2130, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2857 = VLD4q16_UPD { 2856, 8, 2, 4, 618, 0, 0, ARMImpOpBase + 0, 1976, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2856 = VLD4q16Pseudo_UPD { 2855, 8, 4, 4, 615, 0, 0, ARMImpOpBase + 0, 2122, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2855 = VLD4q16 { 2854, 10, 5, 4, 617, 0, 0, ARMImpOpBase + 0, 2130, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2854 = VLD4d8_UPD { 2853, 7, 2, 4, 618, 0, 0, ARMImpOpBase + 0, 2066, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2853 = VLD4d8Pseudo_UPD { 2852, 5, 1, 4, 616, 0, 0, ARMImpOpBase + 0, 1952, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2852 = VLD4d8Pseudo { 2851, 8, 4, 4, 615, 0, 0, ARMImpOpBase + 0, 2122, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2851 = VLD4d8 { 2850, 10, 5, 4, 617, 0, 0, ARMImpOpBase + 0, 2130, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2850 = VLD4d32_UPD { 2849, 7, 2, 4, 618, 0, 0, ARMImpOpBase + 0, 2066, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2849 = VLD4d32Pseudo_UPD { 2848, 5, 1, 4, 616, 0, 0, ARMImpOpBase + 0, 1952, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2848 = VLD4d32Pseudo { 2847, 8, 4, 4, 615, 0, 0, ARMImpOpBase + 0, 2122, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2847 = VLD4d32 { 2846, 10, 5, 4, 617, 0, 0, ARMImpOpBase + 0, 2130, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2846 = VLD4d16_UPD { 2845, 7, 2, 4, 618, 0, 0, ARMImpOpBase + 0, 2066, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2845 = VLD4d16Pseudo_UPD { 2844, 5, 1, 4, 616, 0, 0, ARMImpOpBase + 0, 1952, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2844 = VLD4d16Pseudo { 2843, 8, 4, 4, 615, 0, 0, ARMImpOpBase + 0, 2122, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2843 = VLD4d16 { 2842, 15, 5, 4, 1009, 0, 0, ARMImpOpBase + 0, 2153, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2842 = VLD4LNq32_UPD { 2841, 9, 2, 4, 1010, 0, 0, ARMImpOpBase + 0, 2113, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2841 = VLD4LNq32Pseudo_UPD { 2840, 7, 1, 4, 1008, 0, 0, ARMImpOpBase + 0, 2106, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2840 = VLD4LNq32Pseudo { 2839, 13, 4, 4, 1008, 0, 0, ARMImpOpBase + 0, 2140, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2839 = VLD4LNq32 { 2838, 15, 5, 4, 641, 0, 0, ARMImpOpBase + 0, 2153, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2838 = VLD4LNq16_UPD { 2837, 9, 2, 4, 643, 0, 0, ARMImpOpBase + 0, 2113, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2837 = VLD4LNq16Pseudo_UPD { 2836, 7, 1, 4, 638, 0, 0, ARMImpOpBase + 0, 2106, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2836 = VLD4LNq16Pseudo { 2835, 13, 4, 4, 638, 0, 0, ARMImpOpBase + 0, 2140, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2835 = VLD4LNq16 { 2834, 15, 5, 4, 641, 0, 0, ARMImpOpBase + 0, 2153, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2834 = VLD4LNd8_UPD { 2833, 9, 2, 4, 643, 0, 0, ARMImpOpBase + 0, 2050, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2833 = VLD4LNd8Pseudo_UPD { 2832, 7, 1, 4, 638, 0, 0, ARMImpOpBase + 0, 2043, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2832 = VLD4LNd8Pseudo { 2831, 13, 4, 4, 638, 0, 0, ARMImpOpBase + 0, 2140, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2831 = VLD4LNd8 { 2830, 15, 5, 4, 1009, 0, 0, ARMImpOpBase + 0, 2153, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2830 = VLD4LNd32_UPD { 2829, 9, 2, 4, 1010, 0, 0, ARMImpOpBase + 0, 2050, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2829 = VLD4LNd32Pseudo_UPD { 2828, 7, 1, 4, 1008, 0, 0, ARMImpOpBase + 0, 2043, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2828 = VLD4LNd32Pseudo { 2827, 13, 4, 4, 1008, 0, 0, ARMImpOpBase + 0, 2140, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2827 = VLD4LNd32 { 2826, 15, 5, 4, 641, 0, 0, ARMImpOpBase + 0, 2153, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2826 = VLD4LNd16_UPD { 2825, 9, 2, 4, 643, 0, 0, ARMImpOpBase + 0, 2050, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2825 = VLD4LNd16Pseudo_UPD { 2824, 7, 1, 4, 638, 0, 0, ARMImpOpBase + 0, 2043, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2824 = VLD4LNd16Pseudo { 2823, 13, 4, 4, 638, 0, 0, ARMImpOpBase + 0, 2140, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2823 = VLD4LNd16 { 2822, 10, 5, 4, 640, 0, 0, ARMImpOpBase + 0, 2130, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2822 = VLD4DUPq8_UPD { 2821, 8, 2, 4, 1053, 0, 0, ARMImpOpBase + 0, 1976, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2821 = VLD4DUPq8OddPseudo_UPD { 2820, 6, 1, 4, 1052, 0, 0, ARMImpOpBase + 0, 1970, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2820 = VLD4DUPq8OddPseudo { 2819, 6, 1, 4, 1052, 0, 0, ARMImpOpBase + 0, 1970, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2819 = VLD4DUPq8EvenPseudo { 2818, 8, 4, 4, 637, 0, 0, ARMImpOpBase + 0, 2122, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2818 = VLD4DUPq8 { 2817, 10, 5, 4, 640, 0, 0, ARMImpOpBase + 0, 2130, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2817 = VLD4DUPq32_UPD { 2816, 8, 2, 4, 1053, 0, 0, ARMImpOpBase + 0, 1976, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2816 = VLD4DUPq32OddPseudo_UPD { 2815, 6, 1, 4, 1052, 0, 0, ARMImpOpBase + 0, 1970, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2815 = VLD4DUPq32OddPseudo { 2814, 6, 1, 4, 1052, 0, 0, ARMImpOpBase + 0, 1970, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2814 = VLD4DUPq32EvenPseudo { 2813, 8, 4, 4, 637, 0, 0, ARMImpOpBase + 0, 2122, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2813 = VLD4DUPq32 { 2812, 10, 5, 4, 640, 0, 0, ARMImpOpBase + 0, 2130, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2812 = VLD4DUPq16_UPD { 2811, 8, 2, 4, 1053, 0, 0, ARMImpOpBase + 0, 1976, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2811 = VLD4DUPq16OddPseudo_UPD { 2810, 6, 1, 4, 1052, 0, 0, ARMImpOpBase + 0, 1970, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2810 = VLD4DUPq16OddPseudo { 2809, 6, 1, 4, 1052, 0, 0, ARMImpOpBase + 0, 1970, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2809 = VLD4DUPq16EvenPseudo { 2808, 8, 4, 4, 637, 0, 0, ARMImpOpBase + 0, 2122, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2808 = VLD4DUPq16 { 2807, 10, 5, 4, 640, 0, 0, ARMImpOpBase + 0, 2130, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2807 = VLD4DUPd8_UPD { 2806, 7, 2, 4, 642, 0, 0, ARMImpOpBase + 0, 2066, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2806 = VLD4DUPd8Pseudo_UPD { 2805, 5, 1, 4, 639, 0, 0, ARMImpOpBase + 0, 1952, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2805 = VLD4DUPd8Pseudo { 2804, 8, 4, 4, 637, 0, 0, ARMImpOpBase + 0, 2122, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2804 = VLD4DUPd8 { 2803, 10, 5, 4, 640, 0, 0, ARMImpOpBase + 0, 2130, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2803 = VLD4DUPd32_UPD { 2802, 7, 2, 4, 642, 0, 0, ARMImpOpBase + 0, 2066, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2802 = VLD4DUPd32Pseudo_UPD { 2801, 5, 1, 4, 639, 0, 0, ARMImpOpBase + 0, 1952, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2801 = VLD4DUPd32Pseudo { 2800, 8, 4, 4, 637, 0, 0, ARMImpOpBase + 0, 2122, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2800 = VLD4DUPd32 { 2799, 10, 5, 4, 640, 0, 0, ARMImpOpBase + 0, 2130, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2799 = VLD4DUPd16_UPD { 2798, 7, 2, 4, 642, 0, 0, ARMImpOpBase + 0, 2066, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2798 = VLD4DUPd16Pseudo_UPD { 2797, 5, 1, 4, 639, 0, 0, ARMImpOpBase + 0, 1952, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2797 = VLD4DUPd16Pseudo { 2796, 8, 4, 4, 637, 0, 0, ARMImpOpBase + 0, 2122, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2796 = VLD4DUPd16 { 2795, 8, 2, 4, 614, 0, 0, ARMImpOpBase + 0, 1976, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2795 = VLD3q8oddPseudo_UPD { 2794, 6, 1, 4, 612, 0, 0, ARMImpOpBase + 0, 1970, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2794 = VLD3q8oddPseudo { 2793, 9, 4, 4, 613, 0, 0, ARMImpOpBase + 0, 2073, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2793 = VLD3q8_UPD { 2792, 8, 2, 4, 614, 0, 0, ARMImpOpBase + 0, 1976, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2792 = VLD3q8Pseudo_UPD { 2791, 7, 3, 4, 611, 0, 0, ARMImpOpBase + 0, 2059, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2791 = VLD3q8 { 2790, 8, 2, 4, 614, 0, 0, ARMImpOpBase + 0, 1976, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2790 = VLD3q32oddPseudo_UPD { 2789, 6, 1, 4, 612, 0, 0, ARMImpOpBase + 0, 1970, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2789 = VLD3q32oddPseudo { 2788, 9, 4, 4, 613, 0, 0, ARMImpOpBase + 0, 2073, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2788 = VLD3q32_UPD { 2787, 8, 2, 4, 614, 0, 0, ARMImpOpBase + 0, 1976, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2787 = VLD3q32Pseudo_UPD { 2786, 7, 3, 4, 611, 0, 0, ARMImpOpBase + 0, 2059, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2786 = VLD3q32 { 2785, 8, 2, 4, 614, 0, 0, ARMImpOpBase + 0, 1976, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2785 = VLD3q16oddPseudo_UPD { 2784, 6, 1, 4, 612, 0, 0, ARMImpOpBase + 0, 1970, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2784 = VLD3q16oddPseudo { 2783, 9, 4, 4, 613, 0, 0, ARMImpOpBase + 0, 2073, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2783 = VLD3q16_UPD { 2782, 8, 2, 4, 614, 0, 0, ARMImpOpBase + 0, 1976, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2782 = VLD3q16Pseudo_UPD { 2781, 7, 3, 4, 611, 0, 0, ARMImpOpBase + 0, 2059, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2781 = VLD3q16 { 2780, 9, 4, 4, 613, 0, 0, ARMImpOpBase + 0, 2073, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2780 = VLD3d8_UPD { 2779, 7, 2, 4, 614, 0, 0, ARMImpOpBase + 0, 2066, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2779 = VLD3d8Pseudo_UPD { 2778, 5, 1, 4, 612, 0, 0, ARMImpOpBase + 0, 1952, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2778 = VLD3d8Pseudo { 2777, 7, 3, 4, 611, 0, 0, ARMImpOpBase + 0, 2059, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2777 = VLD3d8 { 2776, 9, 4, 4, 613, 0, 0, ARMImpOpBase + 0, 2073, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2776 = VLD3d32_UPD { 2775, 7, 2, 4, 614, 0, 0, ARMImpOpBase + 0, 2066, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2775 = VLD3d32Pseudo_UPD { 2774, 5, 1, 4, 612, 0, 0, ARMImpOpBase + 0, 1952, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2774 = VLD3d32Pseudo { 2773, 7, 3, 4, 611, 0, 0, ARMImpOpBase + 0, 2059, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2773 = VLD3d32 { 2772, 9, 4, 4, 613, 0, 0, ARMImpOpBase + 0, 2073, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2772 = VLD3d16_UPD { 2771, 7, 2, 4, 614, 0, 0, ARMImpOpBase + 0, 2066, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2771 = VLD3d16Pseudo_UPD { 2770, 5, 1, 4, 612, 0, 0, ARMImpOpBase + 0, 1952, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2770 = VLD3d16Pseudo { 2769, 7, 3, 4, 611, 0, 0, ARMImpOpBase + 0, 2059, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2769 = VLD3d16 { 2768, 13, 4, 4, 1006, 0, 0, ARMImpOpBase + 0, 2093, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2768 = VLD3LNq32_UPD { 2767, 9, 2, 4, 1007, 0, 0, ARMImpOpBase + 0, 2113, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2767 = VLD3LNq32Pseudo_UPD { 2766, 7, 1, 4, 1005, 0, 0, ARMImpOpBase + 0, 2106, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2766 = VLD3LNq32Pseudo { 2765, 11, 3, 4, 1005, 0, 0, ARMImpOpBase + 0, 2082, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2765 = VLD3LNq32 { 2764, 13, 4, 4, 634, 0, 0, ARMImpOpBase + 0, 2093, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2764 = VLD3LNq16_UPD { 2763, 9, 2, 4, 636, 0, 0, ARMImpOpBase + 0, 2113, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2763 = VLD3LNq16Pseudo_UPD { 2762, 7, 1, 4, 632, 0, 0, ARMImpOpBase + 0, 2106, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2762 = VLD3LNq16Pseudo { 2761, 11, 3, 4, 632, 0, 0, ARMImpOpBase + 0, 2082, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2761 = VLD3LNq16 { 2760, 13, 4, 4, 634, 0, 0, ARMImpOpBase + 0, 2093, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2760 = VLD3LNd8_UPD { 2759, 9, 2, 4, 636, 0, 0, ARMImpOpBase + 0, 2050, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2759 = VLD3LNd8Pseudo_UPD { 2758, 7, 1, 4, 632, 0, 0, ARMImpOpBase + 0, 2043, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2758 = VLD3LNd8Pseudo { 2757, 11, 3, 4, 632, 0, 0, ARMImpOpBase + 0, 2082, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2757 = VLD3LNd8 { 2756, 13, 4, 4, 1006, 0, 0, ARMImpOpBase + 0, 2093, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2756 = VLD3LNd32_UPD { 2755, 9, 2, 4, 1007, 0, 0, ARMImpOpBase + 0, 2050, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2755 = VLD3LNd32Pseudo_UPD { 2754, 7, 1, 4, 1005, 0, 0, ARMImpOpBase + 0, 2043, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2754 = VLD3LNd32Pseudo { 2753, 11, 3, 4, 1005, 0, 0, ARMImpOpBase + 0, 2082, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2753 = VLD3LNd32 { 2752, 13, 4, 4, 634, 0, 0, ARMImpOpBase + 0, 2093, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2752 = VLD3LNd16_UPD { 2751, 9, 2, 4, 636, 0, 0, ARMImpOpBase + 0, 2050, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2751 = VLD3LNd16Pseudo_UPD { 2750, 7, 1, 4, 632, 0, 0, ARMImpOpBase + 0, 2043, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2750 = VLD3LNd16Pseudo { 2749, 11, 3, 4, 632, 0, 0, ARMImpOpBase + 0, 2082, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2749 = VLD3LNd16 { 2748, 9, 4, 4, 633, 0, 0, ARMImpOpBase + 0, 2073, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2748 = VLD3DUPq8_UPD { 2747, 8, 2, 4, 1051, 0, 0, ARMImpOpBase + 0, 1976, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2747 = VLD3DUPq8OddPseudo_UPD { 2746, 6, 1, 4, 1050, 0, 0, ARMImpOpBase + 0, 1970, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2746 = VLD3DUPq8OddPseudo { 2745, 6, 1, 4, 1050, 0, 0, ARMImpOpBase + 0, 1970, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2745 = VLD3DUPq8EvenPseudo { 2744, 7, 3, 4, 631, 0, 0, ARMImpOpBase + 0, 2059, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2744 = VLD3DUPq8 { 2743, 9, 4, 4, 633, 0, 0, ARMImpOpBase + 0, 2073, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2743 = VLD3DUPq32_UPD { 2742, 8, 2, 4, 1051, 0, 0, ARMImpOpBase + 0, 1976, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2742 = VLD3DUPq32OddPseudo_UPD { 2741, 6, 1, 4, 1050, 0, 0, ARMImpOpBase + 0, 1970, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2741 = VLD3DUPq32OddPseudo { 2740, 6, 1, 4, 1050, 0, 0, ARMImpOpBase + 0, 1970, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2740 = VLD3DUPq32EvenPseudo { 2739, 7, 3, 4, 631, 0, 0, ARMImpOpBase + 0, 2059, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2739 = VLD3DUPq32 { 2738, 9, 4, 4, 633, 0, 0, ARMImpOpBase + 0, 2073, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2738 = VLD3DUPq16_UPD { 2737, 8, 2, 4, 1051, 0, 0, ARMImpOpBase + 0, 1976, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2737 = VLD3DUPq16OddPseudo_UPD { 2736, 6, 1, 4, 1050, 0, 0, ARMImpOpBase + 0, 1970, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2736 = VLD3DUPq16OddPseudo { 2735, 6, 1, 4, 1050, 0, 0, ARMImpOpBase + 0, 1970, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2735 = VLD3DUPq16EvenPseudo { 2734, 7, 3, 4, 631, 0, 0, ARMImpOpBase + 0, 2059, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2734 = VLD3DUPq16 { 2733, 9, 4, 4, 633, 0, 0, ARMImpOpBase + 0, 2073, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2733 = VLD3DUPd8_UPD { 2732, 7, 2, 4, 635, 0, 0, ARMImpOpBase + 0, 2066, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2732 = VLD3DUPd8Pseudo_UPD { 2731, 5, 1, 4, 631, 0, 0, ARMImpOpBase + 0, 1952, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2731 = VLD3DUPd8Pseudo { 2730, 7, 3, 4, 631, 0, 0, ARMImpOpBase + 0, 2059, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2730 = VLD3DUPd8 { 2729, 9, 4, 4, 633, 0, 0, ARMImpOpBase + 0, 2073, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2729 = VLD3DUPd32_UPD { 2728, 7, 2, 4, 635, 0, 0, ARMImpOpBase + 0, 2066, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2728 = VLD3DUPd32Pseudo_UPD { 2727, 5, 1, 4, 631, 0, 0, ARMImpOpBase + 0, 1952, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2727 = VLD3DUPd32Pseudo { 2726, 7, 3, 4, 631, 0, 0, ARMImpOpBase + 0, 2059, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2726 = VLD3DUPd32 { 2725, 9, 4, 4, 633, 0, 0, ARMImpOpBase + 0, 2073, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2725 = VLD3DUPd16_UPD { 2724, 7, 2, 4, 635, 0, 0, ARMImpOpBase + 0, 2066, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2724 = VLD3DUPd16Pseudo_UPD { 2723, 5, 1, 4, 631, 0, 0, ARMImpOpBase + 0, 1952, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2723 = VLD3DUPd16Pseudo { 2722, 7, 3, 4, 631, 0, 0, ARMImpOpBase + 0, 2059, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2722 = VLD3DUPd16 { 2721, 7, 2, 4, 610, 0, 0, ARMImpOpBase + 0, 1895, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2721 = VLD2q8wb_register { 2720, 6, 2, 4, 610, 0, 0, ARMImpOpBase + 0, 1889, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2720 = VLD2q8wb_fixed { 2719, 7, 2, 4, 610, 0, 0, ARMImpOpBase + 0, 1963, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2719 = VLD2q8PseudoWB_register { 2718, 6, 2, 4, 610, 0, 0, ARMImpOpBase + 0, 1957, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2718 = VLD2q8PseudoWB_fixed { 2717, 5, 1, 4, 608, 0, 0, ARMImpOpBase + 0, 1952, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2717 = VLD2q8Pseudo { 2716, 5, 1, 4, 608, 0, 0, ARMImpOpBase + 0, 385, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2716 = VLD2q8 { 2715, 7, 2, 4, 610, 0, 0, ARMImpOpBase + 0, 1895, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2715 = VLD2q32wb_register { 2714, 6, 2, 4, 610, 0, 0, ARMImpOpBase + 0, 1889, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL },<TRUNCATED>#ifdef __GNUC__#pragma GCC diagnostic push#pragma GCC diagnostic ignored "-Woverlength-strings"#endif#ifdef __GNUC__#pragma GCC diagnostic pop#endif#endif // GET_INSTRINFO_MC_DESC#ifdef GET_INSTRINFO_HEADER#undef GET_INSTRINFO_HEADER#endif // GET_INSTRINFO_HEADER#ifdef GET_INSTRINFO_HELPER_DECLS#undef GET_INSTRINFO_HELPER_DECLS#endif // GET_INSTRINFO_HELPER_DECLS#ifdef GET_INSTRINFO_HELPERS#undef GET_INSTRINFO_HELPERS#endif // GET_INSTRINFO_HELPERS#ifdef GET_INSTRINFO_CTOR_DTOR#undef GET_INSTRINFO_CTOR_DTOR#endif // GET_INSTRINFO_CTOR_DTOR#ifdef GET_INSTRINFO_OPERAND_ENUM#undef GET_INSTRINFO_OPERAND_ENUM#endif //GET_INSTRINFO_OPERAND_ENUM#ifdef GET_INSTRINFO_NAMED_OPS#undef GET_INSTRINFO_NAMED_OPS#endif //GET_INSTRINFO_NAMED_OPS#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM#undef GET_INSTRINFO_OPERAND_TYPES_ENUM#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM#ifdef GET_INSTRINFO_OPERAND_TYPE#undef GET_INSTRINFO_OPERAND_TYPE#endif // GET_INSTRINFO_OPERAND_TYPE#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE#undef GET_INSTRINFO_MEM_OPERAND_SIZE#endif // GET_INSTRINFO_MEM_OPERAND_SIZE#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP#ifdef GET_INSTRINFO_MC_HELPER_DECLS#undef GET_INSTRINFO_MC_HELPER_DECLSclass MCInstclass FeatureBitsetvoid verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features)#endif // GET_INSTRINFO_MC_HELPER_DECLS#ifdef GET_INSTRINFO_MC_HELPERS#undef GET_INSTRINFO_MC_HELPERS#endif // GET_GENISTRINFO_MC_HELPERS#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\ defined(GET_AVAILABLE_OPCODE_CHECKER)#define GET_COMPUTE_FEATURES#endif#ifdef GET_COMPUTE_FEATURES#undef GET_COMPUTE_FEATURES#endif // GET_COMPUTE_FEATURES#ifdef GET_AVAILABLE_OPCODE_CHECKER#undef GET_AVAILABLE_OPCODE_CHECKER#endif // GET_AVAILABLE_OPCODE_CHECKER#ifdef ENABLE_INSTR_PREDICATE_VERIFIER#undef ENABLE_INSTR_PREDICATE_VERIFIER#include <sstream>#ifndef NDEBUG#endif // NDEBUG#ifndef NDEBUG#endif // NDEBUG#endif // ENABLE_INSTR_PREDICATE_VERIFIER
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