/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Global Instruction Selector for the ARM target *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_GLOBALISEL_PREDICATE_BITSET const unsigned MAX_SUBTARGET_PREDICATES = …; PredicateBitset; #endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET #ifdef GET_GLOBALISEL_TEMPORARIES_DECL mutable MatcherState State; typedef ComplexRendererFns(ARMInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; typedef void(ARMInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const; const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo; static ARMInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; static ARMInstructionSelector::CustomRendererFn CustomRenderers[]; bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; const uint8_t *getMatchTable() const override; bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override; bool testSimplePredicate(unsigned PredicateID) const override; bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override; #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL #ifdef GET_GLOBALISEL_TEMPORARIES_INIT , State(0), ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers) #endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT #ifdef GET_GLOBALISEL_IMPL // LLT Objects. enum { GILLT_s16, GILLT_s32, GILLT_s64, GILLT_v2s1, GILLT_v2s32, GILLT_v2s64, GILLT_v4s1, GILLT_v4s16, GILLT_v4s32, GILLT_v4s64, GILLT_v8s1, GILLT_v8s8, GILLT_v8s16, GILLT_v8s64, GILLT_v16s1, GILLT_v16s8, }; const static size_t NumTypeObjects = 16; const static LLT TypeObjects[] = { LLT::scalar(16), LLT::scalar(32), LLT::scalar(64), LLT::vector(ElementCount::getFixed(2), 1), LLT::vector(ElementCount::getFixed(2), 32), LLT::vector(ElementCount::getFixed(2), 64), LLT::vector(ElementCount::getFixed(4), 1), LLT::vector(ElementCount::getFixed(4), 16), LLT::vector(ElementCount::getFixed(4), 32), LLT::vector(ElementCount::getFixed(4), 64), LLT::vector(ElementCount::getFixed(8), 1), LLT::vector(ElementCount::getFixed(8), 8), LLT::vector(ElementCount::getFixed(8), 16), LLT::vector(ElementCount::getFixed(8), 64), LLT::vector(ElementCount::getFixed(16), 1), LLT::vector(ElementCount::getFixed(16), 8), }; // Bits for subtarget features that participate in instruction matching. enum SubtargetFeatureBits : uint8_t { Feature_NoHonorSignDependentRoundingBit = 78, Feature_HasV4TBit = 6, Feature_NoV4TBit = 7, Feature_HasV5TBit = 13, Feature_NoV5TBit = 67, Feature_HasV5TEBit = 11, Feature_HasV6Bit = 0, Feature_NoV6Bit = 9, Feature_HasV6MBit = 28, Feature_HasV8MBaselineBit = 35, Feature_HasV8_1MMainlineBit = 41, Feature_HasMVEIntBit = 65, Feature_HasMVEFloatBit = 66, Feature_HasCDEBit = 86, Feature_HasFPRegsBit = 42, Feature_HasFPRegs16Bit = 43, Feature_HasNoFPRegs16Bit = 77, Feature_HasFPRegs64Bit = 52, Feature_HasV6T2Bit = 8, Feature_HasV6KBit = 18, Feature_HasV7Bit = 3, Feature_HasV8Bit = 56, Feature_PreV8Bit = 19, Feature_HasV8_1aBit = 80, Feature_HasV8_3aBit = 81, Feature_NoVFPBit = 22, Feature_HasVFP2Bit = 21, Feature_HasVFP3Bit = 53, Feature_HasVFP4Bit = 50, Feature_HasDPVFPBit = 44, Feature_HasFPARMv8Bit = 47, Feature_HasNEONBit = 54, Feature_HasSHA2Bit = 63, Feature_HasAESBit = 55, Feature_HasDotProdBit = 57, Feature_HasCRCBit = 14, Feature_HasLOBBit = 40, Feature_HasFP16Bit = 62, Feature_HasFullFP16Bit = 46, Feature_HasBF16Bit = 64, Feature_HasMatMulInt8Bit = 58, Feature_HasDivideInThumbBit = 37, Feature_HasDivideInARMBit = 12, Feature_HasDSPBit = 36, Feature_HasDBBit = 15, Feature_HasV7ClrexBit = 17, Feature_HasAcquireReleaseBit = 16, Feature_HasMPBit = 2, Feature_Has8MSecExtBit = 29, Feature_HasZCZBit = 59, Feature_UseNEONForFPBit = 84, Feature_DontUseNEONForFPBit = 45, Feature_IsThumbBit = 26, Feature_IsThumb1OnlyBit = 27, Feature_IsThumb2Bit = 34, Feature_IsNotMClassBit = 38, Feature_IsARMBit = 1, Feature_IsWindowsBit = 30, Feature_IsNotWindowsBit = 31, Feature_IsReadTPTPIDRURWBit = 70, Feature_IsReadTPTPIDRUROBit = 71, Feature_IsReadTPTPIDRPRWBit = 72, Feature_IsReadTPSoftBit = 20, Feature_UseNaClTrapBit = 4, Feature_DontUseNaClTrapBit = 5, Feature_UseMovtBit = 39, Feature_DontUseMovtBit = 23, Feature_UseMovtInPicBit = 24, Feature_DontUseMovtInPicBit = 25, Feature_UseFPVMLxBit = 49, Feature_SLSBLRMitigationBit = 69, Feature_NoSLSBLRMitigationBit = 68, Feature_UseMulOpsBit = 10, Feature_UseFusedMACBit = 51, Feature_HasFastVGETLNi32Bit = 60, Feature_HasSlowVGETLNi32Bit = 82, Feature_HasFastVDUP32Bit = 61, Feature_HasSlowVDUP32Bit = 83, Feature_UseVMOVSRBit = 48, Feature_DontUseVMOVSRBit = 85, Feature_IsLEBit = 76, Feature_IsBEBit = 79, Feature_GenExecuteOnlyBit = 33, Feature_DontGenExecuteOnlyBit = 32, Feature_GenT1ExecuteOnlyBit = 75, Feature_SignRetAddrBit = 74, Feature_NoSignRetAddrBit = 73, }; PredicateBitset ARMInstructionSelector:: computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const { PredicateBitset Features{}; if (!TM.Options.HonorSignDependentRoundingFPMath()) Features.set(Feature_NoHonorSignDependentRoundingBit); if (Subtarget->hasV4TOps()) Features.set(Feature_HasV4TBit); if (!Subtarget->hasV4TOps()) Features.set(Feature_NoV4TBit); if (Subtarget->hasV5TOps()) Features.set(Feature_HasV5TBit); if (!Subtarget->hasV5TOps()) Features.set(Feature_NoV5TBit); if (Subtarget->hasV5TEOps()) Features.set(Feature_HasV5TEBit); if (Subtarget->hasV6Ops()) Features.set(Feature_HasV6Bit); if (!Subtarget->hasV6Ops()) Features.set(Feature_NoV6Bit); if (Subtarget->hasV6MOps()) Features.set(Feature_HasV6MBit); if (Subtarget->hasV8MBaselineOps()) Features.set(Feature_HasV8MBaselineBit); if (Subtarget->hasV8_1MMainlineOps()) Features.set(Feature_HasV8_1MMainlineBit); if (Subtarget->hasMVEIntegerOps()) Features.set(Feature_HasMVEIntBit); if (Subtarget->hasMVEFloatOps()) Features.set(Feature_HasMVEFloatBit); if (Subtarget->hasCDEOps()) Features.set(Feature_HasCDEBit); if (Subtarget->hasFPRegs()) Features.set(Feature_HasFPRegsBit); if (Subtarget->hasFPRegs16()) Features.set(Feature_HasFPRegs16Bit); if (!Subtarget->hasFPRegs16()) Features.set(Feature_HasNoFPRegs16Bit); if (Subtarget->hasFPRegs64()) Features.set(Feature_HasFPRegs64Bit); if (Subtarget->hasV6T2Ops()) Features.set(Feature_HasV6T2Bit); if (Subtarget->hasV6KOps()) Features.set(Feature_HasV6KBit); if (Subtarget->hasV7Ops()) Features.set(Feature_HasV7Bit); if (Subtarget->hasV8Ops()) Features.set(Feature_HasV8Bit); if (!Subtarget->hasV8Ops()) Features.set(Feature_PreV8Bit); if (Subtarget->hasV8_1aOps()) Features.set(Feature_HasV8_1aBit); if (Subtarget->hasV8_3aOps()) Features.set(Feature_HasV8_3aBit); if (!Subtarget->hasVFP2Base()) Features.set(Feature_NoVFPBit); if (Subtarget->hasVFP2Base()) Features.set(Feature_HasVFP2Bit); if (Subtarget->hasVFP3Base()) Features.set(Feature_HasVFP3Bit); if (Subtarget->hasVFP4Base()) Features.set(Feature_HasVFP4Bit); if (Subtarget->hasFP64()) Features.set(Feature_HasDPVFPBit); if (Subtarget->hasFPARMv8Base()) Features.set(Feature_HasFPARMv8Bit); if (Subtarget->hasNEON()) Features.set(Feature_HasNEONBit); if (Subtarget->hasSHA2()) Features.set(Feature_HasSHA2Bit); if (Subtarget->hasAES()) Features.set(Feature_HasAESBit); if (Subtarget->hasDotProd()) Features.set(Feature_HasDotProdBit); if (Subtarget->hasCRC()) Features.set(Feature_HasCRCBit); if (Subtarget->hasLOB()) Features.set(Feature_HasLOBBit); if (Subtarget->hasFP16()) Features.set(Feature_HasFP16Bit); if (Subtarget->hasFullFP16()) Features.set(Feature_HasFullFP16Bit); if (Subtarget->hasBF16()) Features.set(Feature_HasBF16Bit); if (Subtarget->hasMatMulInt8()) Features.set(Feature_HasMatMulInt8Bit); if (Subtarget->hasDivideInThumbMode()) Features.set(Feature_HasDivideInThumbBit); if (Subtarget->hasDivideInARMMode()) Features.set(Feature_HasDivideInARMBit); if (Subtarget->hasDSP()) Features.set(Feature_HasDSPBit); if (Subtarget->hasDataBarrier()) Features.set(Feature_HasDBBit); if (Subtarget->hasV7Clrex()) Features.set(Feature_HasV7ClrexBit); if (Subtarget->hasAcquireRelease()) Features.set(Feature_HasAcquireReleaseBit); if (Subtarget->hasMPExtension()) Features.set(Feature_HasMPBit); if (Subtarget->has8MSecExt()) Features.set(Feature_Has8MSecExtBit); if (Subtarget->hasZeroCycleZeroing()) Features.set(Feature_HasZCZBit); if (Subtarget->useNEONForSinglePrecisionFP()) Features.set(Feature_UseNEONForFPBit); if (!Subtarget->useNEONForSinglePrecisionFP()) Features.set(Feature_DontUseNEONForFPBit); if (Subtarget->isThumb()) Features.set(Feature_IsThumbBit); if (Subtarget->isThumb1Only()) Features.set(Feature_IsThumb1OnlyBit); if (Subtarget->isThumb2()) Features.set(Feature_IsThumb2Bit); if (!Subtarget->isMClass()) Features.set(Feature_IsNotMClassBit); if (!Subtarget->isThumb()) Features.set(Feature_IsARMBit); if (Subtarget->isTargetWindows()) Features.set(Feature_IsWindowsBit); if (!Subtarget->isTargetWindows()) Features.set(Feature_IsNotWindowsBit); if (Subtarget->isReadTPTPIDRURW()) Features.set(Feature_IsReadTPTPIDRURWBit); if (Subtarget->isReadTPTPIDRURO()) Features.set(Feature_IsReadTPTPIDRUROBit); if (Subtarget->isReadTPTPIDRPRW()) Features.set(Feature_IsReadTPTPIDRPRWBit); if (Subtarget->isReadTPSoft()) Features.set(Feature_IsReadTPSoftBit); if (Subtarget->useNaClTrap()) Features.set(Feature_UseNaClTrapBit); if (!Subtarget->useNaClTrap()) Features.set(Feature_DontUseNaClTrapBit); if (Subtarget->useMulOps()) Features.set(Feature_UseMulOpsBit); if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast && Subtarget->useFPVFMx()) Features.set(Feature_UseFusedMACBit); if (!Subtarget->hasSlowVGETLNi32()) Features.set(Feature_HasFastVGETLNi32Bit); if (Subtarget->hasSlowVGETLNi32()) Features.set(Feature_HasSlowVGETLNi32Bit); if (!Subtarget->hasSlowVDUP32()) Features.set(Feature_HasFastVDUP32Bit); if (Subtarget->hasSlowVDUP32()) Features.set(Feature_HasSlowVDUP32Bit); if (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP()) Features.set(Feature_UseVMOVSRBit); if (!Subtarget->preferVMOVSR() &&Subtarget->useNEONForSinglePrecisionFP()) Features.set(Feature_DontUseVMOVSRBit); if (Subtarget->genExecuteOnly()) Features.set(Feature_GenExecuteOnlyBit); if (!Subtarget->genExecuteOnly()) Features.set(Feature_DontGenExecuteOnlyBit); if (Subtarget->genExecuteOnly() && Subtarget->isThumb1Only() && !Subtarget->hasV8MBaselineOps()) Features.set(Feature_GenT1ExecuteOnlyBit); return Features; } void ARMInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) { AvailableFunctionFeatures = computeAvailableFunctionFeatures((const ARMSubtarget *)&MF.getSubtarget(), &MF); } PredicateBitset ARMInstructionSelector:: computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, const MachineFunction *MF) const { PredicateBitset Features{}; if (Subtarget->useMovt()) Features.set(Feature_UseMovtBit); if (!Subtarget->useMovt()) Features.set(Feature_DontUseMovtBit); if (Subtarget->useMovt() && Subtarget->allowPositionIndependentMovt()) Features.set(Feature_UseMovtInPicBit); if (!Subtarget->useMovt() || !Subtarget->allowPositionIndependentMovt()) Features.set(Feature_DontUseMovtInPicBit); if (((Subtarget->useFPVMLx() && TM.Options.AllowFPOpFusion != FPOpFusion::Fast) ||Subtarget->hasMinSize())) Features.set(Feature_UseFPVMLxBit); if ( MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() ) Features.set(Feature_SLSBLRMitigationBit); if ( !MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() ) Features.set(Feature_NoSLSBLRMitigationBit); if (MF->getDataLayout().isLittleEndian()) Features.set(Feature_IsLEBit); if (MF->getDataLayout().isBigEndian()) Features.set(Feature_IsBEBit); if ( MF->getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true) ) Features.set(Feature_SignRetAddrBit); if ( !MF->getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true) ) Features.set(Feature_NoSignRetAddrBit); return Features; } // Feature bitsets. enum { GIFBS_Invalid, GIFBS_HasDotProd, GIFBS_HasFP16, GIFBS_HasFPARMv8, GIFBS_HasFPRegs, GIFBS_HasFullFP16, GIFBS_HasMVEFloat, GIFBS_HasMVEInt, GIFBS_HasMatMulInt8, GIFBS_HasNEON, GIFBS_HasVFP2, GIFBS_HasVFP3, GIFBS_HasVFP4, GIFBS_IsARM, GIFBS_IsThumb, GIFBS_IsThumb2, GIFBS_NoHonorSignDependentRounding, GIFBS_DontUseNEONForFP_HasVFP2, GIFBS_DontUseNaClTrap_IsARM, GIFBS_DontUseVMOVSR_HasNEON, GIFBS_Has8MSecExt_IsThumb, GIFBS_HasAES_HasV8, GIFBS_HasBF16_HasNEON, GIFBS_HasCRC_IsARM, GIFBS_HasCRC_IsThumb2, GIFBS_HasDB_IsARM, GIFBS_HasDB_IsThumb, GIFBS_HasDPVFP_HasFPARMv8, GIFBS_HasDPVFP_HasVFP2, GIFBS_HasDPVFP_HasVFP3, GIFBS_HasDPVFP_HasVFP4, GIFBS_HasDPVFP_NoHonorSignDependentRounding, GIFBS_HasDSP_IsThumb2, GIFBS_HasDivideInARM_IsARM, GIFBS_HasFP16_HasNEON, GIFBS_HasFPARMv8_HasNEON, GIFBS_HasFPRegs_HasFastVGETLNi32, GIFBS_HasFPRegs_UseVMOVSR, GIFBS_HasFullFP16_HasNEON, GIFBS_HasMVEInt_HasV8_1MMainline, GIFBS_HasMVEInt_IsBE, GIFBS_HasMVEInt_IsLE, GIFBS_HasNEON_HasV8, GIFBS_HasNEON_HasV8_1a, GIFBS_HasNEON_HasV8_3a, GIFBS_HasNEON_HasVFP4, GIFBS_HasNEON_IsBE, GIFBS_HasNEON_IsLE, GIFBS_HasNEON_UseNEONForFP, GIFBS_HasSHA2_HasV8, GIFBS_HasV5T_IsARM, GIFBS_HasV5T_IsThumb, GIFBS_HasV5TE_IsARM, GIFBS_HasV6_IsARM, GIFBS_HasV6K_IsARM, GIFBS_HasV6M_IsThumb, GIFBS_HasV6T2_IsARM, GIFBS_HasV7_IsARM, GIFBS_HasV7Clrex_IsThumb, GIFBS_HasV8MBaseline_IsThumb, GIFBS_IsARM_NoV5T, GIFBS_IsARM_NoV6, GIFBS_IsARM_PreV8, GIFBS_IsARM_UseNaClTrap, GIFBS_IsThumb_IsThumb1Only, GIFBS_IsThumb_IsWindows, GIFBS_IsThumb_NoV5T, GIFBS_IsThumb_UseMovt, GIFBS_IsThumb2_PreV8, GIFBS_IsThumb2_UseMulOps, GIFBS_DontUseMovt_GenExecuteOnly_IsThumb1Only, GIFBS_HasDSP_IsThumb2_UseMulOps, GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb, GIFBS_HasFPARMv8_HasFullFP16_HasNEON, GIFBS_HasFullFP16_HasNEON_HasV8, GIFBS_HasFullFP16_HasNEON_HasV8_3a, GIFBS_HasFullFP16_HasNEON_UseFPVMLx, GIFBS_HasFullFP16_HasNEON_UseFusedMAC, GIFBS_HasLOB_HasV8_1MMainline_IsThumb2, GIFBS_HasNEON_UseFPVMLx_UseNEONForFP, GIFBS_HasV5TE_IsARM_UseMulOps, GIFBS_HasV6_IsARM_UseMulOps, GIFBS_HasV6_IsThumb_IsThumb1Only, GIFBS_HasV6T2_IsARM_UseMulOps, GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP, GIFBS_IsARM_NoV6_UseMulOps, }; constexpr static PredicateBitset FeatureBitsets[] { {}, // GIFBS_Invalid {Feature_HasDotProdBit, }, {Feature_HasFP16Bit, }, {Feature_HasFPARMv8Bit, }, {Feature_HasFPRegsBit, }, {Feature_HasFullFP16Bit, }, {Feature_HasMVEFloatBit, }, {Feature_HasMVEIntBit, }, {Feature_HasMatMulInt8Bit, }, {Feature_HasNEONBit, }, {Feature_HasVFP2Bit, }, {Feature_HasVFP3Bit, }, {Feature_HasVFP4Bit, }, {Feature_IsARMBit, }, {Feature_IsThumbBit, }, {Feature_IsThumb2Bit, }, {Feature_NoHonorSignDependentRoundingBit, }, {Feature_DontUseNEONForFPBit, Feature_HasVFP2Bit, }, {Feature_DontUseNaClTrapBit, Feature_IsARMBit, }, {Feature_DontUseVMOVSRBit, Feature_HasNEONBit, }, {Feature_Has8MSecExtBit, Feature_IsThumbBit, }, {Feature_HasAESBit, Feature_HasV8Bit, }, {Feature_HasBF16Bit, Feature_HasNEONBit, }, {Feature_HasCRCBit, Feature_IsARMBit, }, {Feature_HasCRCBit, Feature_IsThumb2Bit, }, {Feature_HasDBBit, Feature_IsARMBit, }, {Feature_HasDBBit, Feature_IsThumbBit, }, {Feature_HasDPVFPBit, Feature_HasFPARMv8Bit, }, {Feature_HasDPVFPBit, Feature_HasVFP2Bit, }, {Feature_HasDPVFPBit, Feature_HasVFP3Bit, }, {Feature_HasDPVFPBit, Feature_HasVFP4Bit, }, {Feature_HasDPVFPBit, Feature_NoHonorSignDependentRoundingBit, }, {Feature_HasDSPBit, Feature_IsThumb2Bit, }, {Feature_HasDivideInARMBit, Feature_IsARMBit, }, {Feature_HasFP16Bit, Feature_HasNEONBit, }, {Feature_HasFPARMv8Bit, Feature_HasNEONBit, }, {Feature_HasFPRegsBit, Feature_HasFastVGETLNi32Bit, }, {Feature_HasFPRegsBit, Feature_UseVMOVSRBit, }, {Feature_HasFullFP16Bit, Feature_HasNEONBit, }, {Feature_HasMVEIntBit, Feature_HasV8_1MMainlineBit, }, {Feature_HasMVEIntBit, Feature_IsBEBit, }, {Feature_HasMVEIntBit, Feature_IsLEBit, }, {Feature_HasNEONBit, Feature_HasV8Bit, }, {Feature_HasNEONBit, Feature_HasV8_1aBit, }, {Feature_HasNEONBit, Feature_HasV8_3aBit, }, {Feature_HasNEONBit, Feature_HasVFP4Bit, }, {Feature_HasNEONBit, Feature_IsBEBit, }, {Feature_HasNEONBit, Feature_IsLEBit, }, {Feature_HasNEONBit, Feature_UseNEONForFPBit, }, {Feature_HasSHA2Bit, Feature_HasV8Bit, }, {Feature_HasV5TBit, Feature_IsARMBit, }, {Feature_HasV5TBit, Feature_IsThumbBit, }, {Feature_HasV5TEBit, Feature_IsARMBit, }, {Feature_HasV6Bit, Feature_IsARMBit, }, {Feature_HasV6KBit, Feature_IsARMBit, }, {Feature_HasV6MBit, Feature_IsThumbBit, }, {Feature_HasV6T2Bit, Feature_IsARMBit, }, {Feature_HasV7Bit, Feature_IsARMBit, }, {Feature_HasV7ClrexBit, Feature_IsThumbBit, }, {Feature_HasV8MBaselineBit, Feature_IsThumbBit, }, {Feature_IsARMBit, Feature_NoV5TBit, }, {Feature_IsARMBit, Feature_NoV6Bit, }, {Feature_IsARMBit, Feature_PreV8Bit, }, {Feature_IsARMBit, Feature_UseNaClTrapBit, }, {Feature_IsThumbBit, Feature_IsThumb1OnlyBit, }, {Feature_IsThumbBit, Feature_IsWindowsBit, }, {Feature_IsThumbBit, Feature_NoV5TBit, }, {Feature_IsThumbBit, Feature_UseMovtBit, }, {Feature_IsThumb2Bit, Feature_PreV8Bit, }, {Feature_IsThumb2Bit, Feature_UseMulOpsBit, }, {Feature_DontUseMovtBit, Feature_GenExecuteOnlyBit, Feature_IsThumb1OnlyBit, }, {Feature_HasDSPBit, Feature_IsThumb2Bit, Feature_UseMulOpsBit, }, {Feature_HasDivideInThumbBit, Feature_HasV8MBaselineBit, Feature_IsThumbBit, }, {Feature_HasFPARMv8Bit, Feature_HasFullFP16Bit, Feature_HasNEONBit, }, {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8Bit, }, {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8_3aBit, }, {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFPVMLxBit, }, {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFusedMACBit, }, {Feature_HasLOBBit, Feature_HasV8_1MMainlineBit, Feature_IsThumb2Bit, }, {Feature_HasNEONBit, Feature_UseFPVMLxBit, Feature_UseNEONForFPBit, }, {Feature_HasV5TEBit, Feature_IsARMBit, Feature_UseMulOpsBit, }, {Feature_HasV6Bit, Feature_IsARMBit, Feature_UseMulOpsBit, }, {Feature_HasV6Bit, Feature_IsThumbBit, Feature_IsThumb1OnlyBit, }, {Feature_HasV6T2Bit, Feature_IsARMBit, Feature_UseMulOpsBit, }, {Feature_HasVFP4Bit, Feature_UseFusedMACBit, Feature_UseNEONForFPBit, }, {Feature_IsARMBit, Feature_NoV6Bit, Feature_UseMulOpsBit, }, }; // ComplexPattern predicates. enum { GICP_Invalid, }; // See constructor for table contents ARMInstructionSelector::ComplexMatcherMemFn ARMInstructionSelector::ComplexPredicateFns[] = { nullptr, // GICP_Invalid }; // PatFrag predicates. enum { GICXXPred_MI_Predicate_bf_inv_mask_imm = GICXXPred_Invalid + 1, GICXXPred_MI_Predicate_vfp_f32imm, GICXXPred_MI_Predicate_vfp_f64imm, }; bool ARMInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const { const MachineFunction &MF = *MI.getParent()->getParent(); const MachineRegisterInfo &MRI = MF.getRegInfo(); const auto &Operands = State.RecordedOperands; (void)Operands; (void)MRI; switch (PredicateID) { case GICXXPred_MI_Predicate_bf_inv_mask_imm: { // There's better methods of implementing this check. IntImmLeaf<> would be // equivalent and have less boilerplate but we need a test for C++ // predicates and this one causes new rules to be imported into GlobalISel // without requiring additional features first. const auto &MO = MI.getOperand(1); if (!MO.isCImm()) return false; return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue()); llvm_unreachable("bf_inv_mask_imm should have returned"); } case GICXXPred_MI_Predicate_vfp_f32imm: { const auto &MO = MI.getOperand(1); if (!MO.isFPImm()) return false; return ARM_AM::getFP32Imm(MO.getFPImm()->getValueAPF()) != -1; llvm_unreachable("vfp_f32imm should have returned"); } case GICXXPred_MI_Predicate_vfp_f64imm: { const auto &MO = MI.getOperand(1); if (!MO.isFPImm()) return false; return ARM_AM::getFP64Imm(MO.getFPImm()->getValueAPF()) != -1; llvm_unreachable("vfp_f64imm should have returned"); } } llvm_unreachable("Unknown predicate"); return false; } // PatFrag predicates. enum { GICXXPred_I64_Predicate_VectorIndex8 = GICXXPred_Invalid + 1, GICXXPred_I64_Predicate_VectorIndex16, GICXXPred_I64_Predicate_VectorIndex32, GICXXPred_I64_Predicate_VectorIndex64, GICXXPred_I64_Predicate_asr_imm, GICXXPred_I64_Predicate_imm0_7, GICXXPred_I64_Predicate_imm0_15, GICXXPred_I64_Predicate_imm0_31, GICXXPred_I64_Predicate_imm0_32, GICXXPred_I64_Predicate_imm0_63, GICXXPred_I64_Predicate_imm0_239, GICXXPred_I64_Predicate_imm0_255, GICXXPred_I64_Predicate_imm0_255_expr, GICXXPred_I64_Predicate_imm0_4095, GICXXPred_I64_Predicate_imm0_65535, GICXXPred_I64_Predicate_imm0_65535_expr, GICXXPred_I64_Predicate_imm0_65535_neg, GICXXPred_I64_Predicate_imm1_7, GICXXPred_I64_Predicate_imm1_15, GICXXPred_I64_Predicate_imm1_16, GICXXPred_I64_Predicate_imm1_31, GICXXPred_I64_Predicate_imm8, GICXXPred_I64_Predicate_imm8_255, GICXXPred_I64_Predicate_imm8_or_16, GICXXPred_I64_Predicate_imm16, GICXXPred_I64_Predicate_imm16_31, GICXXPred_I64_Predicate_imm24b, GICXXPred_I64_Predicate_imm32, GICXXPred_I64_Predicate_imm256_510, GICXXPred_I64_Predicate_imm_3b, GICXXPred_I64_Predicate_imm_4b, GICXXPred_I64_Predicate_imm_6b, GICXXPred_I64_Predicate_imm_7b, GICXXPred_I64_Predicate_imm_9b, GICXXPred_I64_Predicate_imm_11b, GICXXPred_I64_Predicate_imm_12b, GICXXPred_I64_Predicate_imm_13b, GICXXPred_I64_Predicate_imm_even, GICXXPred_I64_Predicate_imm_odd, GICXXPred_I64_Predicate_long_shift, GICXXPred_I64_Predicate_mod_imm, GICXXPred_I64_Predicate_mod_imm_not, GICXXPred_I64_Predicate_pkh_asr_amt, GICXXPred_I64_Predicate_pkh_lsl_amt, GICXXPred_I64_Predicate_shr_imm8, GICXXPred_I64_Predicate_shr_imm16, GICXXPred_I64_Predicate_shr_imm32, GICXXPred_I64_Predicate_shr_imm64, GICXXPred_I64_Predicate_t2_so_imm, GICXXPred_I64_Predicate_t2_so_imm_neg, }; bool ARMInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const { switch (PredicateID) { case GICXXPred_I64_Predicate_VectorIndex8: { return ((uint64_t)Imm) < 8; } case GICXXPred_I64_Predicate_VectorIndex16: { return ((uint64_t)Imm) < 4; } case GICXXPred_I64_Predicate_VectorIndex32: { return ((uint64_t)Imm) < 2; } case GICXXPred_I64_Predicate_VectorIndex64: { return ((uint64_t)Imm) < 1; } case GICXXPred_I64_Predicate_asr_imm: { return Imm > 0 && Imm <= 32; } case GICXXPred_I64_Predicate_imm0_7: { return Imm >= 0 && Imm < 8; } case GICXXPred_I64_Predicate_imm0_15: { return Imm >= 0 && Imm < 16; } case GICXXPred_I64_Predicate_imm0_31: { return Imm >= 0 && Imm < 32; } case GICXXPred_I64_Predicate_imm0_32: { return Imm >= 0 && Imm < 33; } case GICXXPred_I64_Predicate_imm0_63: { return Imm >= 0 && Imm < 64; } case GICXXPred_I64_Predicate_imm0_239: { return Imm >= 0 && Imm < 240; } case GICXXPred_I64_Predicate_imm0_255: { return Imm >= 0 && Imm < 256; } case GICXXPred_I64_Predicate_imm0_255_expr: { return Imm >= 0 && Imm < 256; } case GICXXPred_I64_Predicate_imm0_4095: { return Imm >= 0 && Imm < 4096; } case GICXXPred_I64_Predicate_imm0_65535: { return Imm >= 0 && Imm < 65536; } case GICXXPred_I64_Predicate_imm0_65535_expr: { return Imm >= 0 && Imm < 65536; } case GICXXPred_I64_Predicate_imm0_65535_neg: { return -Imm >= 0 && -Imm < 65536; } case GICXXPred_I64_Predicate_imm1_7: { return Imm > 0 && Imm < 8; } case GICXXPred_I64_Predicate_imm1_15: { return Imm > 0 && Imm < 16; } case GICXXPred_I64_Predicate_imm1_16: { return Imm > 0 && Imm <= 16; } case GICXXPred_I64_Predicate_imm1_31: { return Imm > 0 && Imm < 32; } case GICXXPred_I64_Predicate_imm8: { return Imm == 8; } case GICXXPred_I64_Predicate_imm8_255: { return Imm >= 8 && Imm < 256; } case GICXXPred_I64_Predicate_imm8_or_16: { return Imm == 8 || Imm == 16; } case GICXXPred_I64_Predicate_imm16: { return Imm == 16; } case GICXXPred_I64_Predicate_imm16_31: { return (int32_t)Imm >= 16 && (int32_t)Imm < 32; } case GICXXPred_I64_Predicate_imm24b: { return Imm >= 0 && Imm <= 0xffffff; } case GICXXPred_I64_Predicate_imm32: { return Imm == 32; } case GICXXPred_I64_Predicate_imm256_510: { return Imm >= 256 && Imm < 511; } case GICXXPred_I64_Predicate_imm_3b: { { return Imm >= 0 && Imm < (1 << 3); } llvm_unreachable("imm_3b should have returned"); } case GICXXPred_I64_Predicate_imm_4b: { { return Imm >= 0 && Imm < (1 << 4); } llvm_unreachable("imm_4b should have returned"); } case GICXXPred_I64_Predicate_imm_6b: { { return Imm >= 0 && Imm < (1 << 6); } llvm_unreachable("imm_6b should have returned"); } case GICXXPred_I64_Predicate_imm_7b: { { return Imm >= 0 && Imm < (1 << 7); } llvm_unreachable("imm_7b should have returned"); } case GICXXPred_I64_Predicate_imm_9b: { { return Imm >= 0 && Imm < (1 << 9); } llvm_unreachable("imm_9b should have returned"); } case GICXXPred_I64_Predicate_imm_11b: { { return Imm >= 0 && Imm < (1 << 11); } llvm_unreachable("imm_11b should have returned"); } case GICXXPred_I64_Predicate_imm_12b: { { return Imm >= 0 && Imm < (1 << 12); } llvm_unreachable("imm_12b should have returned"); } case GICXXPred_I64_Predicate_imm_13b: { { return Imm >= 0 && Imm < (1 << 13); } llvm_unreachable("imm_13b should have returned"); } case GICXXPred_I64_Predicate_imm_even: { return (Imm & 1) == 0; } case GICXXPred_I64_Predicate_imm_odd: { return (Imm & 1) == 1; } case GICXXPred_I64_Predicate_long_shift: { return Imm > 0 && Imm <= 32; } case GICXXPred_I64_Predicate_mod_imm: { return ARM_AM::getSOImmVal(Imm) != -1; } case GICXXPred_I64_Predicate_mod_imm_not: { return ARM_AM::getSOImmVal(~(uint32_t)Imm) != -1; } case GICXXPred_I64_Predicate_pkh_asr_amt: { return Imm > 0 && Imm <= 32; } case GICXXPred_I64_Predicate_pkh_lsl_amt: { return Imm >= 0 && Imm < 32; } case GICXXPred_I64_Predicate_shr_imm8: { return Imm > 0 && Imm <= 8; } case GICXXPred_I64_Predicate_shr_imm16: { return Imm > 0 && Imm <= 16; } case GICXXPred_I64_Predicate_shr_imm32: { return Imm > 0 && Imm <= 32; } case GICXXPred_I64_Predicate_shr_imm64: { return Imm > 0 && Imm <= 64; } case GICXXPred_I64_Predicate_t2_so_imm: { return ARM_AM::getT2SOImmVal(Imm) != -1; } case GICXXPred_I64_Predicate_t2_so_imm_neg: { return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1; } } llvm_unreachable("Unknown predicate"); return false; } // PatFrag predicates. bool ARMInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const { llvm_unreachable("Unknown predicate"); return false; } // PatFrag predicates. enum { GICXXPred_APInt_Predicate_arm_i32imm = GICXXPred_Invalid + 1, }; bool ARMInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const { switch (PredicateID) { case GICXXPred_APInt_Predicate_arm_i32imm: { if (Subtarget->useMovt()) return true; if (ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue())) return true; return ARM_AM::isSOImmTwoPartValNeg(Imm.getZExtValue()); llvm_unreachable("arm_i32imm should have returned"); } } llvm_unreachable("Unknown predicate"); return false; } bool ARMInstructionSelector::testSimplePredicate(unsigned) const { llvm_unreachable("ARMInstructionSelector does not support simple predicates!"); return false; } // Custom renderers. enum { GICR_Invalid, GICR_renderInvertedImm, GICR_renderVFPF32Imm, GICR_renderVFPF64Imm, }; ARMInstructionSelector::CustomRendererFn ARMInstructionSelector::CustomRenderers[] = { nullptr, // GICR_Invalid &ARMInstructionSelector::renderInvertedImm, &ARMInstructionSelector::renderVFPF32Imm, &ARMInstructionSelector::renderVFPF64Imm, }; bool ARMInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { const PredicateBitset AvailableFeatures = getAvailableFeatures(); MachineIRBuilder B(I); State.MIs.clear(); State.MIs.push_back(&I); if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) { return true; } return false; } bool ARMInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const { llvm_unreachable("ARMInstructionSelector does not support custom C++ actions!"); } #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ #define GIMT_Encode2 … #define GIMT_Encode4 … #define GIMT_Encode8 … #else #define GIMT_Encode2 … #define GIMT_Encode4 … #define GIMT_Encode8 … #endif const uint8_t *ARMInstructionSelector::getMatchTable() const { constexpr static uint8_t MatchTable0[] = { GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(53), GIMT_Encode2(300), /*)*//*default:*//*Label 76*/ GIMT_Encode4(125459), /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(998), /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(6623), /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(9771), /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(10641), /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(10737), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_AND*//*Label 5*/ GIMT_Encode4(10833), /*TargetOpcode::G_OR*//*Label 6*/ GIMT_Encode4(13793), /*TargetOpcode::G_XOR*//*Label 7*/ GIMT_Encode4(19524), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_CONCAT_VECTORS*//*Label 8*/ GIMT_Encode4(21097), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_BITCAST*//*Label 9*/ GIMT_Encode4(21523), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 10*/ GIMT_Encode4(31971), /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 11*/ GIMT_Encode4(32263), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_FENCE*//*Label 12*/ GIMT_Encode4(32522), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_INTRINSIC*//*Label 13*/ GIMT_Encode4(32543), /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 14*/ GIMT_Encode4(87635), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_ANYEXT*//*Label 15*/ GIMT_Encode4(95297), /*TargetOpcode::G_TRUNC*//*Label 16*/ GIMT_Encode4(95455), /*TargetOpcode::G_CONSTANT*//*Label 17*/ GIMT_Encode4(95613), /*TargetOpcode::G_FCONSTANT*//*Label 18*/ GIMT_Encode4(95893), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_SEXT*//*Label 19*/ GIMT_Encode4(95989), GIMT_Encode4(0), /*TargetOpcode::G_ZEXT*//*Label 20*/ GIMT_Encode4(96147), /*TargetOpcode::G_SHL*//*Label 21*/ GIMT_Encode4(96305), /*TargetOpcode::G_LSHR*//*Label 22*/ GIMT_Encode4(96416), /*TargetOpcode::G_ASHR*//*Label 23*/ GIMT_Encode4(96472), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_ROTR*//*Label 24*/ GIMT_Encode4(96701), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_UMULH*//*Label 25*/ GIMT_Encode4(96983), /*TargetOpcode::G_SMULH*//*Label 26*/ GIMT_Encode4(97225), /*TargetOpcode::G_UADDSAT*//*Label 27*/ GIMT_Encode4(97588), /*TargetOpcode::G_SADDSAT*//*Label 28*/ GIMT_Encode4(98227), /*TargetOpcode::G_USUBSAT*//*Label 29*/ GIMT_Encode4(99521), /*TargetOpcode::G_SSUBSAT*//*Label 30*/ GIMT_Encode4(100160), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_FADD*//*Label 31*/ GIMT_Encode4(101174), /*TargetOpcode::G_FSUB*//*Label 32*/ GIMT_Encode4(103486), /*TargetOpcode::G_FMUL*//*Label 33*/ GIMT_Encode4(105150), /*TargetOpcode::G_FMA*//*Label 34*/ GIMT_Encode4(106130), GIMT_Encode4(0), /*TargetOpcode::G_FDIV*//*Label 35*/ GIMT_Encode4(107945), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_FNEG*//*Label 36*/ GIMT_Encode4(108110), /*TargetOpcode::G_FPEXT*//*Label 37*/ GIMT_Encode4(109651), /*TargetOpcode::G_FPTRUNC*//*Label 38*/ GIMT_Encode4(109881), /*TargetOpcode::G_FPTOSI*//*Label 39*/ GIMT_Encode4(110153), /*TargetOpcode::G_FPTOUI*//*Label 40*/ GIMT_Encode4(111483), /*TargetOpcode::G_SITOFP*//*Label 41*/ GIMT_Encode4(112813), /*TargetOpcode::G_UITOFP*//*Label 42*/ GIMT_Encode4(113457), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_FABS*//*Label 43*/ GIMT_Encode4(114101), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_FMINNUM*//*Label 44*/ GIMT_Encode4(114871), /*TargetOpcode::G_FMAXNUM*//*Label 45*/ GIMT_Encode4(115459), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_FMINIMUM*//*Label 46*/ GIMT_Encode4(116047), /*TargetOpcode::G_FMAXIMUM*//*Label 47*/ GIMT_Encode4(116763), /*TargetOpcode::G_GET_FPENV*//*Label 48*/ GIMT_Encode4(117479), /*TargetOpcode::G_SET_FPENV*//*Label 49*/ GIMT_Encode4(117512), /*TargetOpcode::G_RESET_FPENV*//*Label 50*/ GIMT_Encode4(117548), /*TargetOpcode::G_GET_FPMODE*//*Label 51*/ GIMT_Encode4(117613), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_SMIN*//*Label 52*/ GIMT_Encode4(117646), /*TargetOpcode::G_SMAX*//*Label 53*/ GIMT_Encode4(118183), /*TargetOpcode::G_UMIN*//*Label 54*/ GIMT_Encode4(118720), /*TargetOpcode::G_UMAX*//*Label 55*/ GIMT_Encode4(119635), /*TargetOpcode::G_ABS*//*Label 56*/ GIMT_Encode4(120550), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_BR*//*Label 57*/ GIMT_Encode4(121015), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 58*/ GIMT_Encode4(121088), /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 59*/ GIMT_Encode4(121388), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_CTLZ*//*Label 60*/ GIMT_Encode4(121543), GIMT_Encode4(0), /*TargetOpcode::G_CTPOP*//*Label 61*/ GIMT_Encode4(122098), /*TargetOpcode::G_BSWAP*//*Label 62*/ GIMT_Encode4(122206), /*TargetOpcode::G_BITREVERSE*//*Label 63*/ GIMT_Encode4(122492), /*TargetOpcode::G_FCEIL*//*Label 64*/ GIMT_Encode4(122918), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_FSQRT*//*Label 65*/ GIMT_Encode4(123177), /*TargetOpcode::G_FFLOOR*//*Label 66*/ GIMT_Encode4(123315), /*TargetOpcode::G_FRINT*//*Label 67*/ GIMT_Encode4(123574), /*TargetOpcode::G_FNEARBYINT*//*Label 68*/ GIMT_Encode4(123866), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_TRAP*//*Label 69*/ GIMT_Encode4(124004), /*TargetOpcode::G_DEBUGTRAP*//*Label 70*/ GIMT_Encode4(124050), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_VECREDUCE_ADD*//*Label 71*/ GIMT_Encode4(124137), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_VECREDUCE_SMAX*//*Label 72*/ GIMT_Encode4(124313), /*TargetOpcode::G_VECREDUCE_SMIN*//*Label 73*/ GIMT_Encode4(124593), /*TargetOpcode::G_VECREDUCE_UMAX*//*Label 74*/ GIMT_Encode4(124882), /*TargetOpcode::G_VECREDUCE_UMIN*//*Label 75*/ GIMT_Encode4(125163), // Label 0: @998 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 86*/ GIMT_Encode4(6622), /*GILLT_s32*//*Label 77*/ GIMT_Encode4(1069), /*GILLT_s64*//*Label 78*/ GIMT_Encode4(3149), GIMT_Encode4(0), /*GILLT_v2s32*//*Label 79*/ GIMT_Encode4(3196), /*GILLT_v2s64*//*Label 80*/ GIMT_Encode4(3381), GIMT_Encode4(0), /*GILLT_v4s16*//*Label 81*/ GIMT_Encode4(4092), /*GILLT_v4s32*//*Label 82*/ GIMT_Encode4(4277), GIMT_Encode4(0), GIMT_Encode4(0), /*GILLT_v8s8*//*Label 83*/ GIMT_Encode4(5231), /*GILLT_v8s16*//*Label 84*/ GIMT_Encode4(5416), GIMT_Encode4(0), GIMT_Encode4(0), /*GILLT_v16s8*//*Label 85*/ GIMT_Encode4(6370), // Label 77: @1069 GIM_Try, /*On fail goto*//*Label 87*/ GIMT_Encode4(3148), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 88*/ GIMT_Encode4(1155), // Rule ID 5785 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5785, GIR_EraseRootFromParent_Done, // Label 88: @1155 GIM_Try, /*On fail goto*//*Label 89*/ GIMT_Encode4(1230), // Rule ID 5786 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5786, GIR_EraseRootFromParent_Done, // Label 89: @1230 GIM_Try, /*On fail goto*//*Label 90*/ GIMT_Encode4(1305), // Rule ID 5820 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5820, GIR_EraseRootFromParent_Done, // Label 90: @1305 GIM_Try, /*On fail goto*//*Label 91*/ GIMT_Encode4(1380), // Rule ID 5821 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5821, GIR_EraseRootFromParent_Done, // Label 91: @1380 GIM_Try, /*On fail goto*//*Label 92*/ GIMT_Encode4(1455), // Rule ID 2013 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2013, GIR_EraseRootFromParent_Done, // Label 92: @1455 GIM_Try, /*On fail goto*//*Label 93*/ GIMT_Encode4(1530), // Rule ID 2014 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2014, GIR_EraseRootFromParent_Done, // Label 93: @1530 GIM_Try, /*On fail goto*//*Label 94*/ GIMT_Encode4(1605), // Rule ID 2235 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2235, GIR_EraseRootFromParent_Done, // Label 94: @1605 GIM_Try, /*On fail goto*//*Label 95*/ GIMT_Encode4(1680), // Rule ID 2236 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2236, GIR_EraseRootFromParent_Done, // Label 95: @1680 GIM_Try, /*On fail goto*//*Label 96*/ GIMT_Encode4(1790), // Rule ID 5564 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/3, // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_RootToRootCopy, /*OpIdx*/2, // Ra GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5564, GIR_EraseRootFromParent_Done, // Label 96: @1790 GIM_Try, /*On fail goto*//*Label 97*/ GIMT_Encode4(1900), // Rule ID 5601 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/3, // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_RootToRootCopy, /*OpIdx*/2, // Ra GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5601, GIR_EraseRootFromParent_Done, // Label 97: @1900 GIM_Try, /*On fail goto*//*Label 98*/ GIMT_Encode4(2010), // Rule ID 192 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, GIM_CheckIsSafeToFold, /*NumInsns*/3, // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_RootToRootCopy, /*OpIdx*/1, // Ra GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 192, GIR_EraseRootFromParent_Done, // Label 98: @2010 GIM_Try, /*On fail goto*//*Label 99*/ GIMT_Encode4(2120), // Rule ID 529 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, GIM_CheckIsSafeToFold, /*NumInsns*/3, // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_RootToRootCopy, /*OpIdx*/1, // Ra GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 529, GIR_EraseRootFromParent_Done, // Label 99: @2120 GIM_Try, /*On fail goto*//*Label 100*/ GIMT_Encode4(2177), // Rule ID 72 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ADDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ADDri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 72, GIR_EraseRootFromParent_Done, // Label 100: @2177 GIM_Try, /*On fail goto*//*Label 101*/ GIMT_Encode4(2234), // Rule ID 415 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ADDri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 415, GIR_EraseRootFromParent_Done, // Label 101: @2234 GIM_Try, /*On fail goto*//*Label 102*/ GIMT_Encode4(2285), // Rule ID 416 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_4095), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm) => (t2ADDri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDri12), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 416, GIR_EraseRootFromParent_Done, // Label 102: @2285 GIM_Try, /*On fail goto*//*Label 103*/ GIMT_Encode4(2361), // Rule ID 171 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLA), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_RootToRootCopy, /*OpIdx*/2, // Ra GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 171, GIR_EraseRootFromParent_Done, // Label 103: @2361 GIM_Try, /*On fail goto*//*Label 104*/ GIMT_Encode4(2437), // Rule ID 172 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV6), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLAv5), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_RootToRootCopy, /*OpIdx*/2, // Ra GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 172, GIR_EraseRootFromParent_Done, // Label 104: @2437 GIM_Try, /*On fail goto*//*Label 105*/ GIMT_Encode4(2507), // Rule ID 511 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm), rGPR:{ *:[i32] }:$Ra) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLA), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_RootToRootCopy, /*OpIdx*/2, // Ra GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 511, GIR_EraseRootFromParent_Done, // Label 105: @2507 GIM_Try, /*On fail goto*//*Label 106*/ GIMT_Encode4(2577), // Rule ID 180 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm), GPR:{ *:[i32] }:$Ra) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMLA), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_RootToRootCopy, /*OpIdx*/2, // Ra GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 180, GIR_EraseRootFromParent_Done, // Label 106: @2577 GIM_Try, /*On fail goto*//*Label 107*/ GIMT_Encode4(2647), // Rule ID 517 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Ra) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMLA), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_RootToRootCopy, /*OpIdx*/2, // Ra GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 517, GIR_EraseRootFromParent_Done, // Label 107: @2647 GIM_Try, /*On fail goto*//*Label 108*/ GIMT_Encode4(2723), // Rule ID 5558 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLA), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_RootToRootCopy, /*OpIdx*/1, // Ra GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5558, GIR_EraseRootFromParent_Done, // Label 108: @2723 GIM_Try, /*On fail goto*//*Label 109*/ GIMT_Encode4(2799), // Rule ID 5559 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV6), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLAv5), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_RootToRootCopy, /*OpIdx*/1, // Ra GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5559, GIR_EraseRootFromParent_Done, // Label 109: @2799 GIM_Try, /*On fail goto*//*Label 110*/ GIMT_Encode4(2869), // Rule ID 5596 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLA), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_RootToRootCopy, /*OpIdx*/1, // Ra GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5596, GIR_EraseRootFromParent_Done, // Label 110: @2869 GIM_Try, /*On fail goto*//*Label 111*/ GIMT_Encode4(2939), // Rule ID 5560 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMLA), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_RootToRootCopy, /*OpIdx*/1, // Ra GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5560, GIR_EraseRootFromParent_Done, // Label 111: @2939 GIM_Try, /*On fail goto*//*Label 112*/ GIMT_Encode4(3009), // Rule ID 5597 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMLA), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_RootToRootCopy, /*OpIdx*/1, // Ra GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5597, GIR_EraseRootFromParent_Done, // Label 112: @3009 GIM_Try, /*On fail goto*//*Label 113*/ GIMT_Encode4(3055), // Rule ID 73 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ADDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ADDrr), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_RootToRootCopy, /*OpIdx*/2, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73, GIR_EraseRootFromParent_Done, // Label 113: @3055 GIM_Try, /*On fail goto*//*Label 114*/ GIMT_Encode4(3101), // Rule ID 417 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDrr), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_RootToRootCopy, /*OpIdx*/2, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 417, GIR_EraseRootFromParent_Done, // Label 114: @3101 GIM_Try, /*On fail goto*//*Label 115*/ GIMT_Encode4(3147), // Rule ID 5578 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDrr), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/2, // Rn GIR_RootToRootCopy, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5578, GIR_EraseRootFromParent_Done, // Label 115: @3147 GIM_Reject, // Label 87: @3148 GIM_Reject, // Label 78: @3149 GIM_Try, /*On fail goto*//*Label 116*/ GIMT_Encode4(3195), // Rule ID 779 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (add:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VADDv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv1i64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 779, GIR_EraseRootFromParent_Done, // Label 116: @3195 GIM_Reject, // Label 79: @3196 GIM_Try, /*On fail goto*//*Label 117*/ GIMT_Encode4(3380), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_Try, /*On fail goto*//*Label 118*/ GIMT_Encode4(3277), // Rule ID 5647 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv2i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5647, GIR_EraseRootFromParent_Done, // Label 118: @3277 GIM_Try, /*On fail goto*//*Label 119*/ GIMT_Encode4(3343), // Rule ID 906 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv2i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 906, GIR_EraseRootFromParent_Done, // Label 119: @3343 GIM_Try, /*On fail goto*//*Label 120*/ GIMT_Encode4(3379), // Rule ID 775 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VADDv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv2i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 775, GIR_EraseRootFromParent_Done, // Label 120: @3379 GIM_Reject, // Label 117: @3380 GIM_Reject, // Label 80: @3381 GIM_Try, /*On fail goto*//*Label 121*/ GIMT_Encode4(4091), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_Try, /*On fail goto*//*Label 122*/ GIMT_Encode4(3464), // Rule ID 799 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 799, GIR_EraseRootFromParent_Done, // Label 122: @3464 GIM_Try, /*On fail goto*//*Label 123*/ GIMT_Encode4(3532), // Rule ID 798 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 798, GIR_EraseRootFromParent_Done, // Label 123: @3532 GIM_Try, /*On fail goto*//*Label 124*/ GIMT_Encode4(3600), // Rule ID 787 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv2i64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 787, GIR_EraseRootFromParent_Done, // Label 124: @3600 GIM_Try, /*On fail goto*//*Label 125*/ GIMT_Encode4(3668), // Rule ID 797 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 797, GIR_EraseRootFromParent_Done, // Label 125: @3668 GIM_Try, /*On fail goto*//*Label 126*/ GIMT_Encode4(3736), // Rule ID 796 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 796, GIR_EraseRootFromParent_Done, // Label 126: @3736 GIM_Try, /*On fail goto*//*Label 127*/ GIMT_Encode4(3789), // Rule ID 5626 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5626, GIR_EraseRootFromParent_Done, // Label 127: @3789 GIM_Try, /*On fail goto*//*Label 128*/ GIMT_Encode4(3842), // Rule ID 5620 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv2i64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5620, GIR_EraseRootFromParent_Done, // Label 128: @3842 GIM_Try, /*On fail goto*//*Label 129*/ GIMT_Encode4(3895), // Rule ID 5625 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5625, GIR_EraseRootFromParent_Done, // Label 129: @3895 GIM_Try, /*On fail goto*//*Label 130*/ GIMT_Encode4(3948), // Rule ID 808 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 808, GIR_EraseRootFromParent_Done, // Label 130: @3948 GIM_Try, /*On fail goto*//*Label 131*/ GIMT_Encode4(4001), // Rule ID 802 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv2i64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 802, GIR_EraseRootFromParent_Done, // Label 131: @4001 GIM_Try, /*On fail goto*//*Label 132*/ GIMT_Encode4(4054), // Rule ID 807 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 807, GIR_EraseRootFromParent_Done, // Label 132: @4054 GIM_Try, /*On fail goto*//*Label 133*/ GIMT_Encode4(4090), // Rule ID 780 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VADDv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv2i64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 780, GIR_EraseRootFromParent_Done, // Label 133: @4090 GIM_Reject, // Label 121: @4091 GIM_Reject, // Label 81: @4092 GIM_Try, /*On fail goto*//*Label 134*/ GIMT_Encode4(4276), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_Try, /*On fail goto*//*Label 135*/ GIMT_Encode4(4173), // Rule ID 5646 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5646, GIR_EraseRootFromParent_Done, // Label 135: @4173 GIM_Try, /*On fail goto*//*Label 136*/ GIMT_Encode4(4239), // Rule ID 905 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 905, GIR_EraseRootFromParent_Done, // Label 136: @4239 GIM_Try, /*On fail goto*//*Label 137*/ GIMT_Encode4(4275), // Rule ID 774 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VADDv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv4i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 774, GIR_EraseRootFromParent_Done, // Label 137: @4275 GIM_Reject, // Label 134: @4276 GIM_Reject, // Label 82: @4277 GIM_Try, /*On fail goto*//*Label 138*/ GIMT_Encode4(5230), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 139*/ GIMT_Encode4(4360), // Rule ID 795 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 795, GIR_EraseRootFromParent_Done, // Label 139: @4360 GIM_Try, /*On fail goto*//*Label 140*/ GIMT_Encode4(4432), // Rule ID 794 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 794, GIR_EraseRootFromParent_Done, // Label 140: @4432 GIM_Try, /*On fail goto*//*Label 141*/ GIMT_Encode4(4504), // Rule ID 786 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 786, GIR_EraseRootFromParent_Done, // Label 141: @4504 GIM_Try, /*On fail goto*//*Label 142*/ GIMT_Encode4(4576), // Rule ID 793 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 793, GIR_EraseRootFromParent_Done, // Label 142: @4576 GIM_Try, /*On fail goto*//*Label 143*/ GIMT_Encode4(4648), // Rule ID 792 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 792, GIR_EraseRootFromParent_Done, // Label 143: @4648 GIM_Try, /*On fail goto*//*Label 144*/ GIMT_Encode4(4718), // Rule ID 5650 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5650, GIR_EraseRootFromParent_Done, // Label 144: @4718 GIM_Try, /*On fail goto*//*Label 145*/ GIMT_Encode4(4775), // Rule ID 5624 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5624, GIR_EraseRootFromParent_Done, // Label 145: @4775 GIM_Try, /*On fail goto*//*Label 146*/ GIMT_Encode4(4832), // Rule ID 5619 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5619, GIR_EraseRootFromParent_Done, // Label 146: @4832 GIM_Try, /*On fail goto*//*Label 147*/ GIMT_Encode4(4889), // Rule ID 5623 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5623, GIR_EraseRootFromParent_Done, // Label 147: @4889 GIM_Try, /*On fail goto*//*Label 148*/ GIMT_Encode4(4959), // Rule ID 909 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 909, GIR_EraseRootFromParent_Done, // Label 148: @4959 GIM_Try, /*On fail goto*//*Label 149*/ GIMT_Encode4(5016), // Rule ID 806 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 806, GIR_EraseRootFromParent_Done, // Label 149: @5016 GIM_Try, /*On fail goto*//*Label 150*/ GIMT_Encode4(5073), // Rule ID 801 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 801, GIR_EraseRootFromParent_Done, // Label 150: @5073 GIM_Try, /*On fail goto*//*Label 151*/ GIMT_Encode4(5130), // Rule ID 805 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 805, GIR_EraseRootFromParent_Done, // Label 151: @5130 GIM_Try, /*On fail goto*//*Label 152*/ GIMT_Encode4(5170), // Rule ID 778 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VADDv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 778, GIR_EraseRootFromParent_Done, // Label 152: @5170 GIM_Try, /*On fail goto*//*Label 153*/ GIMT_Encode4(5229), // Rule ID 3591 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (add:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // Qm GIR_RootToRootCopy, /*OpIdx*/2, // Qn GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3591, GIR_EraseRootFromParent_Done, // Label 153: @5229 GIM_Reject, // Label 138: @5230 GIM_Reject, // Label 83: @5231 GIM_Try, /*On fail goto*//*Label 154*/ GIMT_Encode4(5415), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_Try, /*On fail goto*//*Label 155*/ GIMT_Encode4(5312), // Rule ID 5645 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5645, GIR_EraseRootFromParent_Done, // Label 155: @5312 GIM_Try, /*On fail goto*//*Label 156*/ GIMT_Encode4(5378), // Rule ID 904 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 904, GIR_EraseRootFromParent_Done, // Label 156: @5378 GIM_Try, /*On fail goto*//*Label 157*/ GIMT_Encode4(5414), // Rule ID 773 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VADDv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv8i8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 773, GIR_EraseRootFromParent_Done, // Label 157: @5414 GIM_Reject, // Label 154: @5415 GIM_Reject, // Label 84: @5416 GIM_Try, /*On fail goto*//*Label 158*/ GIMT_Encode4(6369), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 159*/ GIMT_Encode4(5499), // Rule ID 791 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 791, GIR_EraseRootFromParent_Done, // Label 159: @5499 GIM_Try, /*On fail goto*//*Label 160*/ GIMT_Encode4(5571), // Rule ID 790 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 790, GIR_EraseRootFromParent_Done, // Label 160: @5571 GIM_Try, /*On fail goto*//*Label 161*/ GIMT_Encode4(5643), // Rule ID 785 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 785, GIR_EraseRootFromParent_Done, // Label 161: @5643 GIM_Try, /*On fail goto*//*Label 162*/ GIMT_Encode4(5715), // Rule ID 789 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 789, GIR_EraseRootFromParent_Done, // Label 162: @5715 GIM_Try, /*On fail goto*//*Label 163*/ GIMT_Encode4(5787), // Rule ID 788 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 788, GIR_EraseRootFromParent_Done, // Label 163: @5787 GIM_Try, /*On fail goto*//*Label 164*/ GIMT_Encode4(5857), // Rule ID 5649 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5649, GIR_EraseRootFromParent_Done, // Label 164: @5857 GIM_Try, /*On fail goto*//*Label 165*/ GIMT_Encode4(5914), // Rule ID 5622 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5622, GIR_EraseRootFromParent_Done, // Label 165: @5914 GIM_Try, /*On fail goto*//*Label 166*/ GIMT_Encode4(5971), // Rule ID 5618 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5618, GIR_EraseRootFromParent_Done, // Label 166: @5971 GIM_Try, /*On fail goto*//*Label 167*/ GIMT_Encode4(6028), // Rule ID 5621 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5621, GIR_EraseRootFromParent_Done, // Label 167: @6028 GIM_Try, /*On fail goto*//*Label 168*/ GIMT_Encode4(6098), // Rule ID 908 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 908, GIR_EraseRootFromParent_Done, // Label 168: @6098 GIM_Try, /*On fail goto*//*Label 169*/ GIMT_Encode4(6155), // Rule ID 804 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 804, GIR_EraseRootFromParent_Done, // Label 169: @6155 GIM_Try, /*On fail goto*//*Label 170*/ GIMT_Encode4(6212), // Rule ID 800 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 800, GIR_EraseRootFromParent_Done, // Label 170: @6212 GIM_Try, /*On fail goto*//*Label 171*/ GIMT_Encode4(6269), // Rule ID 803 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 803, GIR_EraseRootFromParent_Done, // Label 171: @6269 GIM_Try, /*On fail goto*//*Label 172*/ GIMT_Encode4(6309), // Rule ID 777 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VADDv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 777, GIR_EraseRootFromParent_Done, // Label 172: @6309 GIM_Try, /*On fail goto*//*Label 173*/ GIMT_Encode4(6368), // Rule ID 3587 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (add:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // Qm GIR_RootToRootCopy, /*OpIdx*/2, // Qn GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3587, GIR_EraseRootFromParent_Done, // Label 173: @6368 GIM_Reject, // Label 158: @6369 GIM_Reject, // Label 85: @6370 GIM_Try, /*On fail goto*//*Label 174*/ GIMT_Encode4(6621), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_Try, /*On fail goto*//*Label 175*/ GIMT_Encode4(6451), // Rule ID 5648 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv16i8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5648, GIR_EraseRootFromParent_Done, // Label 175: @6451 GIM_Try, /*On fail goto*//*Label 176*/ GIMT_Encode4(6521), // Rule ID 907 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv16i8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 907, GIR_EraseRootFromParent_Done, // Label 176: @6521 GIM_Try, /*On fail goto*//*Label 177*/ GIMT_Encode4(6561), // Rule ID 776 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VADDv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv16i8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 776, GIR_EraseRootFromParent_Done, // Label 177: @6561 GIM_Try, /*On fail goto*//*Label 178*/ GIMT_Encode4(6620), // Rule ID 3583 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (add:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // Qm GIR_RootToRootCopy, /*OpIdx*/2, // Qn GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3583, GIR_EraseRootFromParent_Done, // Label 178: @6620 GIM_Reject, // Label 174: @6621 GIM_Reject, // Label 86: @6622 GIM_Reject, // Label 1: @6623 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 188*/ GIMT_Encode4(9770), /*GILLT_s32*//*Label 179*/ GIMT_Encode4(6694), /*GILLT_s64*//*Label 180*/ GIMT_Encode4(7218), GIMT_Encode4(0), /*GILLT_v2s32*//*Label 181*/ GIMT_Encode4(7265), /*GILLT_v2s64*//*Label 182*/ GIMT_Encode4(7380), GIMT_Encode4(0), /*GILLT_v4s16*//*Label 183*/ GIMT_Encode4(7932), /*GILLT_v4s32*//*Label 184*/ GIMT_Encode4(8047), GIMT_Encode4(0), GIMT_Encode4(0), /*GILLT_v8s8*//*Label 185*/ GIMT_Encode4(8760), /*GILLT_v8s16*//*Label 186*/ GIMT_Encode4(8875), GIMT_Encode4(0), GIMT_Encode4(0), /*GILLT_v16s8*//*Label 187*/ GIMT_Encode4(9588), // Label 179: @6694 GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(7217), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 190*/ GIMT_Encode4(6762), // Rule ID 96 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), // MIs[1] Operand 1 // No operand predicates GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, GPR:{ *:[i32] }:$Rn) => (RSBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::RSBri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 96, GIR_EraseRootFromParent_Done, // Label 190: @6762 GIM_Try, /*On fail goto*//*Label 191*/ GIMT_Encode4(6819), // Rule ID 435 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), // MIs[1] Operand 1 // No operand predicates GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, rGPR:{ *:[i32] }:$Rn) => (t2RSBri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RSBri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 435, GIR_EraseRootFromParent_Done, // Label 191: @6819 GIM_Try, /*On fail goto*//*Label 192*/ GIMT_Encode4(6876), // Rule ID 76 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (SUBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SUBri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 76, GIR_EraseRootFromParent_Done, // Label 192: @6876 GIM_Try, /*On fail goto*//*Label 193*/ GIMT_Encode4(6933), // Rule ID 419 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2SUBri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 419, GIR_EraseRootFromParent_Done, // Label 193: @6933 GIM_Try, /*On fail goto*//*Label 194*/ GIMT_Encode4(6984), // Rule ID 420 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_4095), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm) => (t2SUBri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBri12), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 420, GIR_EraseRootFromParent_Done, // Label 194: @6984 GIM_Try, /*On fail goto*//*Label 195*/ GIMT_Encode4(7054), // Rule ID 173 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM_UseMulOps), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (MLS:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_RootToRootCopy, /*OpIdx*/1, // Ra GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 173, GIR_EraseRootFromParent_Done, // Label 195: @7054 GIM_Try, /*On fail goto*//*Label 196*/ GIMT_Encode4(7124), // Rule ID 512 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLS:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_RootToRootCopy, /*OpIdx*/1, // Ra GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 512, GIR_EraseRootFromParent_Done, // Label 196: @7124 GIM_Try, /*On fail goto*//*Label 197*/ GIMT_Encode4(7170), // Rule ID 77 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SUBrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SUBrr), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_RootToRootCopy, /*OpIdx*/2, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 77, GIR_EraseRootFromParent_Done, // Label 197: @7170 GIM_Try, /*On fail goto*//*Label 198*/ GIMT_Encode4(7216), // Rule ID 421 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SUBrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBrr), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_RootToRootCopy, /*OpIdx*/2, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 421, GIR_EraseRootFromParent_Done, // Label 198: @7216 GIM_Reject, // Label 189: @7217 GIM_Reject, // Label 180: @7218 GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(7264), // Rule ID 983 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (sub:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VSUBv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv1i64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 983, GIR_EraseRootFromParent_Done, // Label 199: @7264 GIM_Reject, // Label 181: @7265 GIM_Try, /*On fail goto*//*Label 200*/ GIMT_Encode4(7379), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_Try, /*On fail goto*//*Label 201*/ GIMT_Encode4(7346), // Rule ID 934 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv2i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 934, GIR_EraseRootFromParent_Done, // Label 201: @7346 GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(7378), // Rule ID 979 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VSUBv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv2i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 979, GIR_EraseRootFromParent_Done, // Label 202: @7378 GIM_Reject, // Label 200: @7379 GIM_Reject, // Label 182: @7380 GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(7931), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(7463), // Rule ID 1003 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1003, GIR_EraseRootFromParent_Done, // Label 204: @7463 GIM_Try, /*On fail goto*//*Label 205*/ GIMT_Encode4(7531), // Rule ID 1002 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1002, GIR_EraseRootFromParent_Done, // Label 205: @7531 GIM_Try, /*On fail goto*//*Label 206*/ GIMT_Encode4(7599), // Rule ID 991 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv2i64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 991, GIR_EraseRootFromParent_Done, // Label 206: @7599 GIM_Try, /*On fail goto*//*Label 207*/ GIMT_Encode4(7667), // Rule ID 1001 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1001, GIR_EraseRootFromParent_Done, // Label 207: @7667 GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(7735), // Rule ID 1000 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1000, GIR_EraseRootFromParent_Done, // Label 208: @7735 GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(7788), // Rule ID 1012 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv2i64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1012, GIR_EraseRootFromParent_Done, // Label 209: @7788 GIM_Try, /*On fail goto*//*Label 210*/ GIMT_Encode4(7841), // Rule ID 1006 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv2i64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1006, GIR_EraseRootFromParent_Done, // Label 210: @7841 GIM_Try, /*On fail goto*//*Label 211*/ GIMT_Encode4(7894), // Rule ID 1011 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv2i64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1011, GIR_EraseRootFromParent_Done, // Label 211: @7894 GIM_Try, /*On fail goto*//*Label 212*/ GIMT_Encode4(7930), // Rule ID 984 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VSUBv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv2i64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 984, GIR_EraseRootFromParent_Done, // Label 212: @7930 GIM_Reject, // Label 203: @7931 GIM_Reject, // Label 183: @7932 GIM_Try, /*On fail goto*//*Label 213*/ GIMT_Encode4(8046), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_Try, /*On fail goto*//*Label 214*/ GIMT_Encode4(8013), // Rule ID 933 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv4i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 933, GIR_EraseRootFromParent_Done, // Label 214: @8013 GIM_Try, /*On fail goto*//*Label 215*/ GIMT_Encode4(8045), // Rule ID 978 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VSUBv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv4i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 978, GIR_EraseRootFromParent_Done, // Label 215: @8045 GIM_Reject, // Label 213: @8046 GIM_Reject, // Label 184: @8047 GIM_Try, /*On fail goto*//*Label 216*/ GIMT_Encode4(8759), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 217*/ GIMT_Encode4(8130), // Rule ID 999 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 999, GIR_EraseRootFromParent_Done, // Label 217: @8130 GIM_Try, /*On fail goto*//*Label 218*/ GIMT_Encode4(8202), // Rule ID 998 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 998, GIR_EraseRootFromParent_Done, // Label 218: @8202 GIM_Try, /*On fail goto*//*Label 219*/ GIMT_Encode4(8274), // Rule ID 990 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 990, GIR_EraseRootFromParent_Done, // Label 219: @8274 GIM_Try, /*On fail goto*//*Label 220*/ GIMT_Encode4(8346), // Rule ID 997 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 997, GIR_EraseRootFromParent_Done, // Label 220: @8346 GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(8418), // Rule ID 996 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 996, GIR_EraseRootFromParent_Done, // Label 221: @8418 GIM_Try, /*On fail goto*//*Label 222*/ GIMT_Encode4(8488), // Rule ID 937 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 937, GIR_EraseRootFromParent_Done, // Label 222: @8488 GIM_Try, /*On fail goto*//*Label 223*/ GIMT_Encode4(8545), // Rule ID 1010 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1010, GIR_EraseRootFromParent_Done, // Label 223: @8545 GIM_Try, /*On fail goto*//*Label 224*/ GIMT_Encode4(8602), // Rule ID 1005 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1005, GIR_EraseRootFromParent_Done, // Label 224: @8602 GIM_Try, /*On fail goto*//*Label 225*/ GIMT_Encode4(8659), // Rule ID 1009 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1009, GIR_EraseRootFromParent_Done, // Label 225: @8659 GIM_Try, /*On fail goto*//*Label 226*/ GIMT_Encode4(8699), // Rule ID 982 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VSUBv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 982, GIR_EraseRootFromParent_Done, // Label 226: @8699 GIM_Try, /*On fail goto*//*Label 227*/ GIMT_Encode4(8758), // Rule ID 3603 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (sub:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VSUBi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // Qm GIR_RootToRootCopy, /*OpIdx*/2, // Qn GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3603, GIR_EraseRootFromParent_Done, // Label 227: @8758 GIM_Reject, // Label 216: @8759 GIM_Reject, // Label 185: @8760 GIM_Try, /*On fail goto*//*Label 228*/ GIMT_Encode4(8874), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_Try, /*On fail goto*//*Label 229*/ GIMT_Encode4(8841), // Rule ID 932 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv8i8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 932, GIR_EraseRootFromParent_Done, // Label 229: @8841 GIM_Try, /*On fail goto*//*Label 230*/ GIMT_Encode4(8873), // Rule ID 977 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VSUBv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv8i8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 977, GIR_EraseRootFromParent_Done, // Label 230: @8873 GIM_Reject, // Label 228: @8874 GIM_Reject, // Label 186: @8875 GIM_Try, /*On fail goto*//*Label 231*/ GIMT_Encode4(9587), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 232*/ GIMT_Encode4(8958), // Rule ID 995 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 995, GIR_EraseRootFromParent_Done, // Label 232: @8958 GIM_Try, /*On fail goto*//*Label 233*/ GIMT_Encode4(9030), // Rule ID 994 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 994, GIR_EraseRootFromParent_Done, // Label 233: @9030 GIM_Try, /*On fail goto*//*Label 234*/ GIMT_Encode4(9102), // Rule ID 989 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 989, GIR_EraseRootFromParent_Done, // Label 234: @9102 GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(9174), // Rule ID 993 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 993, GIR_EraseRootFromParent_Done, // Label 235: @9174 GIM_Try, /*On fail goto*//*Label 236*/ GIMT_Encode4(9246), // Rule ID 992 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 992, GIR_EraseRootFromParent_Done, // Label 236: @9246 GIM_Try, /*On fail goto*//*Label 237*/ GIMT_Encode4(9316), // Rule ID 936 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 936, GIR_EraseRootFromParent_Done, // Label 237: @9316 GIM_Try, /*On fail goto*//*Label 238*/ GIMT_Encode4(9373), // Rule ID 1008 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1008, GIR_EraseRootFromParent_Done, // Label 238: @9373 GIM_Try, /*On fail goto*//*Label 239*/ GIMT_Encode4(9430), // Rule ID 1004 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1004, GIR_EraseRootFromParent_Done, // Label 239: @9430 GIM_Try, /*On fail goto*//*Label 240*/ GIMT_Encode4(9487), // Rule ID 1007 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1007, GIR_EraseRootFromParent_Done, // Label 240: @9487 GIM_Try, /*On fail goto*//*Label 241*/ GIMT_Encode4(9527), // Rule ID 981 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VSUBv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 981, GIR_EraseRootFromParent_Done, // Label 241: @9527 GIM_Try, /*On fail goto*//*Label 242*/ GIMT_Encode4(9586), // Rule ID 3599 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (sub:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VSUBi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // Qm GIR_RootToRootCopy, /*OpIdx*/2, // Qn GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3599, GIR_EraseRootFromParent_Done, // Label 242: @9586 GIM_Reject, // Label 231: @9587 GIM_Reject, // Label 187: @9588 GIM_Try, /*On fail goto*//*Label 243*/ GIMT_Encode4(9769), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_Try, /*On fail goto*//*Label 244*/ GIMT_Encode4(9669), // Rule ID 935 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv16i8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 935, GIR_EraseRootFromParent_Done, // Label 244: @9669 GIM_Try, /*On fail goto*//*Label 245*/ GIMT_Encode4(9709), // Rule ID 980 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSUBv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv16i8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 980, GIR_EraseRootFromParent_Done, // Label 245: @9709 GIM_Try, /*On fail goto*//*Label 246*/ GIMT_Encode4(9768), // Rule ID 3595 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (sub:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VSUBi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // Qm GIR_RootToRootCopy, /*OpIdx*/2, // Qn GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3595, GIR_EraseRootFromParent_Done, // Label 246: @9768 GIM_Reject, // Label 243: @9769 GIM_Reject, // Label 188: @9770 GIM_Reject, // Label 2: @9771 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 254*/ GIMT_Encode4(10640), /*GILLT_s32*//*Label 247*/ GIMT_Encode4(9842), GIMT_Encode4(0), GIMT_Encode4(0), /*GILLT_v2s32*//*Label 248*/ GIMT_Encode4(10163), GIMT_Encode4(0), GIMT_Encode4(0), /*GILLT_v4s16*//*Label 249*/ GIMT_Encode4(10210), /*GILLT_v4s32*//*Label 250*/ GIMT_Encode4(10257), GIMT_Encode4(0), GIMT_Encode4(0), /*GILLT_v8s8*//*Label 251*/ GIMT_Encode4(10369), /*GILLT_v8s16*//*Label 252*/ GIMT_Encode4(10416), GIMT_Encode4(0), GIMT_Encode4(0), /*GILLT_v16s8*//*Label 253*/ GIMT_Encode4(10528), // Label 247: @9842 GIM_Try, /*On fail goto*//*Label 255*/ GIMT_Encode4(10162), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(9941), // Rule ID 186 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 186, GIR_EraseRootFromParent_Done, // Label 256: @9941 GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(10029), // Rule ID 523 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 523, GIR_EraseRootFromParent_Done, // Label 257: @10029 GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(10075), // Rule ID 169 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MUL:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MUL), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_RootToRootCopy, /*OpIdx*/2, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 169, GIR_EraseRootFromParent_Done, // Label 258: @10075 GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(10121), // Rule ID 170 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV6_UseMulOps), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MULv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MULv5), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_RootToRootCopy, /*OpIdx*/2, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 170, GIR_EraseRootFromParent_Done, // Label 259: @10121 GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(10161), // Rule ID 510 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), // (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2MUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MUL), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_RootToRootCopy, /*OpIdx*/2, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 510, GIR_EraseRootFromParent_Done, // Label 260: @10161 GIM_Reject, // Label 255: @10162 GIM_Reject, // Label 248: @10163 GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(10209), // Rule ID 854 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMULv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv2i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 854, GIR_EraseRootFromParent_Done, // Label 261: @10209 GIM_Reject, // Label 249: @10210 GIM_Try, /*On fail goto*//*Label 262*/ GIMT_Encode4(10256), // Rule ID 853 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMULv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv4i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 853, GIR_EraseRootFromParent_Done, // Label 262: @10256 GIM_Reject, // Label 250: @10257 GIM_Try, /*On fail goto*//*Label 263*/ GIMT_Encode4(10368), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 264*/ GIMT_Encode4(10308), // Rule ID 857 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMULv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 857, GIR_EraseRootFromParent_Done, // Label 264: @10308 GIM_Try, /*On fail goto*//*Label 265*/ GIMT_Encode4(10367), // Rule ID 3561 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // Qm GIR_RootToRootCopy, /*OpIdx*/2, // Qn GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3561, GIR_EraseRootFromParent_Done, // Label 265: @10367 GIM_Reject, // Label 263: @10368 GIM_Reject, // Label 251: @10369 GIM_Try, /*On fail goto*//*Label 266*/ GIMT_Encode4(10415), // Rule ID 852 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv8i8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 852, GIR_EraseRootFromParent_Done, // Label 266: @10415 GIM_Reject, // Label 252: @10416 GIM_Try, /*On fail goto*//*Label 267*/ GIMT_Encode4(10527), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 268*/ GIMT_Encode4(10467), // Rule ID 856 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMULv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 856, GIR_EraseRootFromParent_Done, // Label 268: @10467 GIM_Try, /*On fail goto*//*Label 269*/ GIMT_Encode4(10526), // Rule ID 3557 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // Qm GIR_RootToRootCopy, /*OpIdx*/2, // Qn GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3557, GIR_EraseRootFromParent_Done, // Label 269: @10526 GIM_Reject, // Label 267: @10527 GIM_Reject, // Label 253: @10528 GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(10639), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_Try, /*On fail goto*//*Label 271*/ GIMT_Encode4(10579), // Rule ID 855 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMULv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv16i8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 855, GIR_EraseRootFromParent_Done, // Label 271: @10579 GIM_Try, /*On fail goto*//*Label 272*/ GIMT_Encode4(10638), // Rule ID 3553 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // Qm GIR_RootToRootCopy, /*OpIdx*/2, // Qn GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3553, GIR_EraseRootFromParent_Done, // Label 272: @10638 GIM_Reject, // Label 270: @10639 GIM_Reject, // Label 254: @10640 GIM_Reject, // Label 3: @10641 GIM_Try, /*On fail goto*//*Label 273*/ GIMT_Encode4(10736), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(10695), // Rule ID 195 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInARM_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SDIV), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_RootToRootCopy, /*OpIdx*/2, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 195, GIR_EraseRootFromParent_Done, // Label 274: @10695 GIM_Try, /*On fail goto*//*Label 275*/ GIMT_Encode4(10735), // Rule ID 540 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), // (sdiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SDIV), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_RootToRootCopy, /*OpIdx*/2, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 540, GIR_EraseRootFromParent_Done, // Label 275: @10735 GIM_Reject, // Label 273: @10736 GIM_Reject, // Label 4: @10737 GIM_Try, /*On fail goto*//*Label 276*/ GIMT_Encode4(10832), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 277*/ GIMT_Encode4(10791), // Rule ID 196 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInARM_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (UDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDIV), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_RootToRootCopy, /*OpIdx*/2, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 196, GIR_EraseRootFromParent_Done, // Label 277: @10791 GIM_Try, /*On fail goto*//*Label 278*/ GIMT_Encode4(10831), // Rule ID 541 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), // (udiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UDIV), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_RootToRootCopy, /*OpIdx*/2, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 541, GIR_EraseRootFromParent_Done, // Label 278: @10831 GIM_Reject, // Label 276: @10832 GIM_Reject, // Label 5: @10833 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 292*/ GIMT_Encode4(13792), /*GILLT_s32*//*Label 279*/ GIMT_Encode4(10904), /*GILLT_s64*//*Label 280*/ GIMT_Encode4(12708), /*GILLT_v2s1*//*Label 281*/ GIMT_Encode4(12755), /*GILLT_v2s32*//*Label 282*/ GIMT_Encode4(12867), /*GILLT_v2s64*//*Label 283*/ GIMT_Encode4(12914), /*GILLT_v4s1*//*Label 284*/ GIMT_Encode4(13026), /*GILLT_v4s16*//*Label 285*/ GIMT_Encode4(13138), /*GILLT_v4s32*//*Label 286*/ GIMT_Encode4(13185), GIMT_Encode4(0), /*GILLT_v8s1*//*Label 287*/ GIMT_Encode4(13297), /*GILLT_v8s8*//*Label 288*/ GIMT_Encode4(13409), /*GILLT_v8s16*//*Label 289*/ GIMT_Encode4(13456), GIMT_Encode4(0), /*GILLT_v16s1*//*Label 290*/ GIMT_Encode4(13568), /*GILLT_v16s8*//*Label 291*/ GIMT_Encode4(13680), // Label 279: @10904 GIM_Try, /*On fail goto*//*Label 293*/ GIMT_Encode4(12707), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 294*/ GIMT_Encode4(10988), // Rule ID 1877 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 1:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src GIR_AddImm8, /*InsnID*/0, /*Imm*/1, GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1877, GIR_EraseRootFromParent_Done, // Label 294: @10988 GIM_Try, /*On fail goto*//*Label 295*/ GIMT_Encode4(11061), // Rule ID 2117 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 1:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src GIR_AddImm8, /*InsnID*/0, /*Imm*/1, GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2117, GIR_EraseRootFromParent_Done, // Label 295: @11061 GIM_Try, /*On fail goto*//*Label 296*/ GIMT_Encode4(11109), // Rule ID 2010 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255), // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 255:{ *:[i32] }) => (UXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2010, GIR_EraseRootFromParent_Done, // Label 296: @11109 GIM_Try, /*On fail goto*//*Label 297*/ GIMT_Encode4(11157), // Rule ID 2011 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 65535:{ *:[i32] }) => (UXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2011, GIR_EraseRootFromParent_Done, // Label 297: @11157 GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(11205), // Rule ID 2012 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2012, GIR_EraseRootFromParent_Done, // Label 298: @11205 GIM_Try, /*On fail goto*//*Label 299*/ GIMT_Encode4(11253), // Rule ID 2232 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255), // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (t2UXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2232, GIR_EraseRootFromParent_Done, // Label 299: @11253 GIM_Try, /*On fail goto*//*Label 300*/ GIMT_Encode4(11301), // Rule ID 2233 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (t2UXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2233, GIR_EraseRootFromParent_Done, // Label 300: @11301 GIM_Try, /*On fail goto*//*Label 301*/ GIMT_Encode4(11349), // Rule ID 2234 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2234, GIR_EraseRootFromParent_Done, // Label 301: @11349 GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(11426), // Rule ID 5554 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), // MIs[2] Operand 1 // No operand predicates GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5554, GIR_EraseRootFromParent_Done, // Label 302: @11426 GIM_Try, /*On fail goto*//*Label 303*/ GIMT_Encode4(11503), // Rule ID 5587 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), // MIs[2] Operand 1 // No operand predicates GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5587, GIR_EraseRootFromParent_Done, // Label 303: @11503 GIM_Try, /*On fail goto*//*Label 304*/ GIMT_Encode4(11580), // Rule ID 5553 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5553, GIR_EraseRootFromParent_Done, // Label 304: @11580 GIM_Try, /*On fail goto*//*Label 305*/ GIMT_Encode4(11657), // Rule ID 5586 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5586, GIR_EraseRootFromParent_Done, // Label 305: @11657 GIM_Try, /*On fail goto*//*Label 306*/ GIMT_Encode4(11734), // Rule ID 5552 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5552, GIR_EraseRootFromParent_Done, // Label 306: @11734 GIM_Try, /*On fail goto*//*Label 307*/ GIMT_Encode4(11811), // Rule ID 5585 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5585, GIR_EraseRootFromParent_Done, // Label 307: @11811 GIM_Try, /*On fail goto*//*Label 308*/ GIMT_Encode4(11888), // Rule ID 159 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] })) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 159, GIR_EraseRootFromParent_Done, // Label 308: @11888 GIM_Try, /*On fail goto*//*Label 309*/ GIMT_Encode4(11965), // Rule ID 498 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 498, GIR_EraseRootFromParent_Done, // Label 309: @11965 GIM_Try, /*On fail goto*//*Label 310*/ GIMT_Encode4(12036), // Rule ID 5555 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICrr), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5555, GIR_EraseRootFromParent_Done, // Label 310: @12036 GIM_Try, /*On fail goto*//*Label 311*/ GIMT_Encode4(12107), // Rule ID 5588 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICrr), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5588, GIR_EraseRootFromParent_Done, // Label 311: @12107 GIM_Try, /*On fail goto*//*Label 312*/ GIMT_Encode4(12178), // Rule ID 160 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICrr), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 160, GIR_EraseRootFromParent_Done, // Label 312: @12178 GIM_Try, /*On fail goto*//*Label 313*/ GIMT_Encode4(12249), // Rule ID 499 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICrr), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 499, GIR_EraseRootFromParent_Done, // Label 313: @12249 GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(12294), // Rule ID 352 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255), // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (tUXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUXTB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 352, GIR_EraseRootFromParent_Done, // Label 314: @12294 GIM_Try, /*On fail goto*//*Label 315*/ GIMT_Encode4(12339), // Rule ID 353 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (tUXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUXTH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 353, GIR_EraseRootFromParent_Done, // Label 315: @12339 GIM_Try, /*On fail goto*//*Label 316*/ GIMT_Encode4(12398), // Rule ID 1916 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm_not), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>><<X:imm_not_XFORM>>:$imm) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm_not_XFORM:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>>:$imm)) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderInvertedImm), // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1916, GIR_EraseRootFromParent_Done, // Label 316: @12398 GIM_Try, /*On fail goto*//*Label 317*/ GIMT_Encode4(12455), // Rule ID 147 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ANDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ANDri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 147, GIR_EraseRootFromParent_Done, // Label 317: @12455 GIM_Try, /*On fail goto*//*Label 318*/ GIMT_Encode4(12512), // Rule ID 489 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ANDri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ANDri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 489, GIR_EraseRootFromParent_Done, // Label 318: @12512 GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(12563), // Rule ID 163 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), // MIs[1] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_bf_inv_mask_imm), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm) => (BFC:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BFC), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 163, GIR_EraseRootFromParent_Done, // Label 319: @12563 GIM_Try, /*On fail goto*//*Label 320*/ GIMT_Encode4(12614), // Rule ID 501 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), // MIs[1] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_bf_inv_mask_imm), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm) => (t2BFC:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BFC), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 501, GIR_EraseRootFromParent_Done, // Label 320: @12614 GIM_Try, /*On fail goto*//*Label 321*/ GIMT_Encode4(12660), // Rule ID 148 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ANDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ANDrr), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_RootToRootCopy, /*OpIdx*/2, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 148, GIR_EraseRootFromParent_Done, // Label 321: @12660 GIM_Try, /*On fail goto*//*Label 322*/ GIMT_Encode4(12706), // Rule ID 490 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ANDrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_RootToRootCopy, /*OpIdx*/2, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 490, GIR_EraseRootFromParent_Done, // Label 322: @12706 GIM_Reject, // Label 293: @12707 GIM_Reject, // Label 280: @12708 GIM_Try, /*On fail goto*//*Label 323*/ GIMT_Encode4(12754), // Rule ID 2521 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (and:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VANDd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // LHS GIR_RootToRootCopy, /*OpIdx*/2, // RHS GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2521, GIR_EraseRootFromParent_Done, // Label 323: @12754 GIM_Reject, // Label 281: @12755 GIM_Try, /*On fail goto*//*Label 324*/ GIMT_Encode4(12866), // Rule ID 1848 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), // (and:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, GIR_AddImm8, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), // GIR_Coverage, 1848, GIR_EraseRootFromParent_Done, // Label 324: @12866 GIM_Reject, // Label 282: @12867 GIM_Try, /*On fail goto*//*Label 325*/ GIMT_Encode4(12913), // Rule ID 1150 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (and:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VANDd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1150, GIR_EraseRootFromParent_Done, // Label 325: @12913 GIM_Reject, // Label 283: @12914 GIM_Try, /*On fail goto*//*Label 326*/ GIMT_Encode4(13025), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_Try, /*On fail goto*//*Label 327*/ GIMT_Encode4(12965), // Rule ID 2524 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (and:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VANDq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // LHS GIR_RootToRootCopy, /*OpIdx*/2, // RHS GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2524, GIR_EraseRootFromParent_Done, // Label 327: @12965 GIM_Try, /*On fail goto*//*Label 328*/ GIMT_Encode4(13024), // Rule ID 3465 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (and:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VAND:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // Qm GIR_RootToRootCopy, /*OpIdx*/2, // Qn GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3465, GIR_EraseRootFromParent_Done, // Label 328: @13024 GIM_Reject, // Label 326: @13025 GIM_Reject, // Label 284: @13026 GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(13137), // Rule ID 1849 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), // (and:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, GIR_AddImm8, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), // GIR_Coverage, 1849, GIR_EraseRootFromParent_Done, // Label 329: @13137 GIM_Reject, // Label 285: @13138 GIM_Try, /*On fail goto*//*Label 330*/ GIMT_Encode4(13184), // Rule ID 2520 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (and:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VANDd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // LHS GIR_RootToRootCopy, /*OpIdx*/2, // RHS GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2520, GIR_EraseRootFromParent_Done, // Label 330: @13184 GIM_Reject, // Label 286: @13185 GIM_Try, /*On fail goto*//*Label 331*/ GIMT_Encode4(13296), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 332*/ GIMT_Encode4(13236), // Rule ID 1151 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VANDq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1151, GIR_EraseRootFromParent_Done, // Label 332: @13236 GIM_Try, /*On fail goto*//*Label 333*/ GIMT_Encode4(13295), // Rule ID 3461 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (and:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VAND:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // Qm GIR_RootToRootCopy, /*OpIdx*/2, // Qn GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3461, GIR_EraseRootFromParent_Done, // Label 333: @13295 GIM_Reject, // Label 331: @13296 GIM_Reject, // Label 287: @13297 GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(13408), // Rule ID 1850 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), // (and:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, GIR_AddImm8, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), // GIR_Coverage, 1850, GIR_EraseRootFromParent_Done, // Label 334: @13408 GIM_Reject, // Label 288: @13409 GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(13455), // Rule ID 2519 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (and:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VANDd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // LHS GIR_RootToRootCopy, /*OpIdx*/2, // RHS GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2519, GIR_EraseRootFromParent_Done, // Label 335: @13455 GIM_Reject, // Label 289: @13456 GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(13567), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 337*/ GIMT_Encode4(13507), // Rule ID 2523 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (and:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VANDq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // LHS GIR_RootToRootCopy, /*OpIdx*/2, // RHS GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2523, GIR_EraseRootFromParent_Done, // Label 337: @13507 GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(13566), // Rule ID 3457 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (and:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VAND:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // Qm GIR_RootToRootCopy, /*OpIdx*/2, // Qn GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3457, GIR_EraseRootFromParent_Done, // Label 338: @13566 GIM_Reject, // Label 336: @13567 GIM_Reject, // Label 290: @13568 GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(13679), // Rule ID 1851 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), // (and:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, GIR_AddImm8, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), // GIR_Coverage, 1851, GIR_EraseRootFromParent_Done, // Label 339: @13679 GIM_Reject, // Label 291: @13680 GIM_Try, /*On fail goto*//*Label 340*/ GIMT_Encode4(13791), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_Try, /*On fail goto*//*Label 341*/ GIMT_Encode4(13731), // Rule ID 2522 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (and:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VANDq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // LHS GIR_RootToRootCopy, /*OpIdx*/2, // RHS GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2522, GIR_EraseRootFromParent_Done, // Label 341: @13731 GIM_Try, /*On fail goto*//*Label 342*/ GIMT_Encode4(13790), // Rule ID 3453 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (and:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VAND:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // Qm GIR_RootToRootCopy, /*OpIdx*/2, // Qn GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3453, GIR_EraseRootFromParent_Done, // Label 342: @13790 GIM_Reject, // Label 340: @13791 GIM_Reject, // Label 292: @13792 GIM_Reject, // Label 6: @13793 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 356*/ GIMT_Encode4(19523), /*GILLT_s32*//*Label 343*/ GIMT_Encode4(13864), /*GILLT_s64*//*Label 344*/ GIMT_Encode4(18439), /*GILLT_v2s1*//*Label 345*/ GIMT_Encode4(18486), /*GILLT_v2s32*//*Label 346*/ GIMT_Encode4(18598), /*GILLT_v2s64*//*Label 347*/ GIMT_Encode4(18645), /*GILLT_v4s1*//*Label 348*/ GIMT_Encode4(18757), /*GILLT_v4s16*//*Label 349*/ GIMT_Encode4(18869), /*GILLT_v4s32*//*Label 350*/ GIMT_Encode4(18916), GIMT_Encode4(0), /*GILLT_v8s1*//*Label 351*/ GIMT_Encode4(19028), /*GILLT_v8s8*//*Label 352*/ GIMT_Encode4(19140), /*GILLT_v8s16*//*Label 353*/ GIMT_Encode4(19187), GIMT_Encode4(0), /*GILLT_v16s1*//*Label 354*/ GIMT_Encode4(19299), /*GILLT_v16s8*//*Label 355*/ GIMT_Encode4(19411), // Label 343: @13864 GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(18438), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(14002), // Rule ID 5770 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, // MIs[4] Rm GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24, GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, GIM_CheckIsSafeToFold, /*NumInsns*/4, // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5770, GIR_EraseRootFromParent_Done, // Label 358: @14002 GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(14129), // Rule ID 5812 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, // MIs[4] Rm GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24, GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, GIM_CheckIsSafeToFold, /*NumInsns*/4, // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5812, GIR_EraseRootFromParent_Done, // Label 359: @14129 GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(14256), // Rule ID 1936 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, // MIs[4] Rm GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8, GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255), GIM_CheckIsSafeToFold, /*NumInsns*/4, // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1936, GIR_EraseRootFromParent_Done, // Label 360: @14256 GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(14383), // Rule ID 2201 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, // MIs[4] Rm GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8, GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255), GIM_CheckIsSafeToFold, /*NumInsns*/4, // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2201, GIR_EraseRootFromParent_Done, // Label 361: @14383 GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(14516), // Rule ID 5568 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), // MIs[3] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), GIM_CheckIsSafeToFold, /*NumInsns*/4, // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5568, GIR_EraseRootFromParent_Done, // Label 362: @14516 GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(14649), // Rule ID 5605 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), // MIs[3] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), GIM_CheckIsSafeToFold, /*NumInsns*/4, // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5605, GIR_EraseRootFromParent_Done, // Label 363: @14649 GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(14782), // Rule ID 5775 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), // MIs[3] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), GIM_CheckIsSafeToFold, /*NumInsns*/4, // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5775, GIR_EraseRootFromParent_Done, // Label 364: @14782 GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(14915), // Rule ID 5817 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), // MIs[3] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), GIM_CheckIsSafeToFold, /*NumInsns*/4, // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5817, GIR_EraseRootFromParent_Done, // Label 365: @14915 GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(15048), // Rule ID 5567 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), // MIs[3] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(65535), GIM_CheckIsSafeToFold, /*NumInsns*/4, // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5567, GIR_EraseRootFromParent_Done, // Label 366: @15048 GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(15181), // Rule ID 5604 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), // MIs[3] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(65535), GIM_CheckIsSafeToFold, /*NumInsns*/4, // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5604, GIR_EraseRootFromParent_Done, // Label 367: @15181 GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(15314), // Rule ID 203 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), // MIs[4] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), GIM_CheckIsSafeToFold, /*NumInsns*/4, // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 203, GIR_EraseRootFromParent_Done, // Label 368: @15314 GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(15447), // Rule ID 548 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), // MIs[4] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), GIM_CheckIsSafeToFold, /*NumInsns*/4, // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 548, GIR_EraseRootFromParent_Done, // Label 369: @15447 GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(15580), // Rule ID 1941 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), // MIs[4] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), GIM_CheckIsSafeToFold, /*NumInsns*/4, // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1941, GIR_EraseRootFromParent_Done, // Label 370: @15580 GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(15713), // Rule ID 2206 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), // MIs[4] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), GIM_CheckIsSafeToFold, /*NumInsns*/4, // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2206, GIR_EraseRootFromParent_Done, // Label 371: @15713 GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(15846), // Rule ID 202 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), // MIs[4] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), GIM_CheckIsSafeToFold, /*NumInsns*/4, // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 202, GIR_EraseRootFromParent_Done, // Label 372: @15846 GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(15979), // Rule ID 547 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), // MIs[4] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), GIM_CheckIsSafeToFold, /*NumInsns*/4, // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 547, GIR_EraseRootFromParent_Done, // Label 373: @15979 GIM_Try, /*On fail goto*//*Label 374*/ GIMT_Encode4(16084), // Rule ID 1937 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1937, GIR_EraseRootFromParent_Done, // Label 374: @16084 GIM_Try, /*On fail goto*//*Label 375*/ GIMT_Encode4(16189), // Rule ID 2202 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2202, GIR_EraseRootFromParent_Done, // Label 375: @16189 GIM_Try, /*On fail goto*//*Label 376*/ GIMT_Encode4(16294), // Rule ID 5771 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5771, GIR_EraseRootFromParent_Done, // Label 376: @16294 GIM_Try, /*On fail goto*//*Label 377*/ GIMT_Encode4(16399), // Rule ID 5813 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5813, GIR_EraseRootFromParent_Done, // Label 377: @16399 GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(16505), // Rule ID 1940 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1940, GIR_EraseRootFromParent_Done, // Label 378: @16505 GIM_Try, /*On fail goto*//*Label 379*/ GIMT_Encode4(16611), // Rule ID 2205 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2205, GIR_EraseRootFromParent_Done, // Label 379: @16611 GIM_Try, /*On fail goto*//*Label 380*/ GIMT_Encode4(16717), // Rule ID 1939 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1939, GIR_EraseRootFromParent_Done, // Label 380: @16717 GIM_Try, /*On fail goto*//*Label 381*/ GIMT_Encode4(16823), // Rule ID 2204 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2204, GIR_EraseRootFromParent_Done, // Label 381: @16823 GIM_Try, /*On fail goto*//*Label 382*/ GIMT_Encode4(16929), // Rule ID 1938 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1938, GIR_EraseRootFromParent_Done, // Label 382: @16929 GIM_Try, /*On fail goto*//*Label 383*/ GIMT_Encode4(17035), // Rule ID 2203 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2203, GIR_EraseRootFromParent_Done, // Label 383: @17035 GIM_Try, /*On fail goto*//*Label 384*/ GIMT_Encode4(17141), // Rule ID 5774 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), GIM_CheckIsSafeToFold, /*NumInsns*/3, // (or:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5774, GIR_EraseRootFromParent_Done, // Label 384: @17141 GIM_Try, /*On fail goto*//*Label 385*/ GIMT_Encode4(17247), // Rule ID 5816 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), GIM_CheckIsSafeToFold, /*NumInsns*/3, // (or:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5816, GIR_EraseRootFromParent_Done, // Label 385: @17247 GIM_Try, /*On fail goto*//*Label 386*/ GIMT_Encode4(17353), // Rule ID 5773 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), GIM_CheckIsSafeToFold, /*NumInsns*/3, // (or:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5773, GIR_EraseRootFromParent_Done, // Label 386: @17353 GIM_Try, /*On fail goto*//*Label 387*/ GIMT_Encode4(17459), // Rule ID 5815 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), GIM_CheckIsSafeToFold, /*NumInsns*/3, // (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5815, GIR_EraseRootFromParent_Done, // Label 387: @17459 GIM_Try, /*On fail goto*//*Label 388*/ GIMT_Encode4(17565), // Rule ID 5772 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535), GIM_CheckIsSafeToFold, /*NumInsns*/3, // (or:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5772, GIR_EraseRootFromParent_Done, // Label 388: @17565 GIM_Try, /*On fail goto*//*Label 389*/ GIMT_Encode4(17671), // Rule ID 5814 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535), GIM_CheckIsSafeToFold, /*NumInsns*/3, // (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5814, GIR_EraseRootFromParent_Done, // Label 389: @17671 GIM_Try, /*On fail goto*//*Label 390*/ GIMT_Encode4(17748), // Rule ID 5592 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), // MIs[2] Operand 1 // No operand predicates GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (or:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5592, GIR_EraseRootFromParent_Done, // Label 390: @17748 GIM_Try, /*On fail goto*//*Label 391*/ GIMT_Encode4(17825), // Rule ID 5591 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (or:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5591, GIR_EraseRootFromParent_Done, // Label 391: @17825 GIM_Try, /*On fail goto*//*Label 392*/ GIMT_Encode4(17902), // Rule ID 5590 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5590, GIR_EraseRootFromParent_Done, // Label 392: @17902 GIM_Try, /*On fail goto*//*Label 393*/ GIMT_Encode4(17979), // Rule ID 504 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 504, GIR_EraseRootFromParent_Done, // Label 393: @17979 GIM_Try, /*On fail goto*//*Label 394*/ GIMT_Encode4(18050), // Rule ID 5593 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (or:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNrr), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5593, GIR_EraseRootFromParent_Done, // Label 394: @18050 GIM_Try, /*On fail goto*//*Label 395*/ GIMT_Encode4(18121), // Rule ID 505 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNrr), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 505, GIR_EraseRootFromParent_Done, // Label 395: @18121 GIM_Try, /*On fail goto*//*Label 396*/ GIMT_Encode4(18176), // Rule ID 1870 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294901760), // (or:{ *:[i32] } GPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (MOVTi16:{ *:[i32] } GPR:{ *:[i32] }:$src, 65535:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVTi16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(65535), GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1870, GIR_EraseRootFromParent_Done, // Label 396: @18176 GIM_Try, /*On fail goto*//*Label 397*/ GIMT_Encode4(18231), // Rule ID 2099 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294901760), // (or:{ *:[i32] } rGPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (t2MOVTi16:{ *:[i32] } rGPR:{ *:[i32] }:$src, 65535:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVTi16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(65535), GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2099, GIR_EraseRootFromParent_Done, // Label 397: @18231 GIM_Try, /*On fail goto*//*Label 398*/ GIMT_Encode4(18288), // Rule ID 151 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ORRri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ORRri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 151, GIR_EraseRootFromParent_Done, // Label 398: @18288 GIM_Try, /*On fail goto*//*Label 399*/ GIMT_Encode4(18345), // Rule ID 492 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ORRri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORRri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 492, GIR_EraseRootFromParent_Done, // Label 399: @18345 GIM_Try, /*On fail goto*//*Label 400*/ GIMT_Encode4(18391), // Rule ID 152 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ORRrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ORRrr), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_RootToRootCopy, /*OpIdx*/2, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 152, GIR_EraseRootFromParent_Done, // Label 400: @18391 GIM_Try, /*On fail goto*//*Label 401*/ GIMT_Encode4(18437), // Rule ID 493 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ORRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_RootToRootCopy, /*OpIdx*/2, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 493, GIR_EraseRootFromParent_Done, // Label 401: @18437 GIM_Reject, // Label 357: @18438 GIM_Reject, // Label 344: @18439 GIM_Try, /*On fail goto*//*Label 402*/ GIMT_Encode4(18485), // Rule ID 2527 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (or:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VORRd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // LHS GIR_RootToRootCopy, /*OpIdx*/2, // RHS GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2527, GIR_EraseRootFromParent_Done, // Label 402: @18485 GIM_Reject, // Label 345: @18486 GIM_Try, /*On fail goto*//*Label 403*/ GIMT_Encode4(18597), // Rule ID 1856 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), // (or:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, GIR_AddImm8, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), // GIR_Coverage, 1856, GIR_EraseRootFromParent_Done, // Label 403: @18597 GIM_Reject, // Label 346: @18598 GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(18644), // Rule ID 1154 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (or:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VORRd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1154, GIR_EraseRootFromParent_Done, // Label 404: @18644 GIM_Reject, // Label 347: @18645 GIM_Try, /*On fail goto*//*Label 405*/ GIMT_Encode4(18756), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_Try, /*On fail goto*//*Label 406*/ GIMT_Encode4(18696), // Rule ID 2530 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (or:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VORRq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // LHS GIR_RootToRootCopy, /*OpIdx*/2, // RHS GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2530, GIR_EraseRootFromParent_Done, // Label 406: @18696 GIM_Try, /*On fail goto*//*Label 407*/ GIMT_Encode4(18755), // Rule ID 3479 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (or:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VORR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // Qm GIR_RootToRootCopy, /*OpIdx*/2, // Qn GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3479, GIR_EraseRootFromParent_Done, // Label 407: @18755 GIM_Reject, // Label 405: @18756 GIM_Reject, // Label 348: @18757 GIM_Try, /*On fail goto*//*Label 408*/ GIMT_Encode4(18868), // Rule ID 1857 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), // (or:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, GIR_AddImm8, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), // GIR_Coverage, 1857, GIR_EraseRootFromParent_Done, // Label 408: @18868 GIM_Reject, // Label 349: @18869 GIM_Try, /*On fail goto*//*Label 409*/ GIMT_Encode4(18915), // Rule ID 2526 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (or:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VORRd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // LHS GIR_RootToRootCopy, /*OpIdx*/2, // RHS GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2526, GIR_EraseRootFromParent_Done, // Label 409: @18915 GIM_Reject, // Label 350: @18916 GIM_Try, /*On fail goto*//*Label 410*/ GIMT_Encode4(19027), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 411*/ GIMT_Encode4(18967), // Rule ID 1155 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (or:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VORRq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1155, GIR_EraseRootFromParent_Done, // Label 411: @18967 GIM_Try, /*On fail goto*//*Label 412*/ GIMT_Encode4(19026), // Rule ID 3475 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (or:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VORR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // Qm GIR_RootToRootCopy, /*OpIdx*/2, // Qn GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3475, GIR_EraseRootFromParent_Done, // Label 412: @19026 GIM_Reject, // Label 410: @19027 GIM_Reject, // Label 351: @19028 GIM_Try, /*On fail goto*//*Label 413*/ GIMT_Encode4(19139), // Rule ID 1858 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), // (or:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, GIR_AddImm8, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), // GIR_Coverage, 1858, GIR_EraseRootFromParent_Done, // Label 413: @19139 GIM_Reject, // Label 352: @19140 GIM_Try, /*On fail goto*//*Label 414*/ GIMT_Encode4(19186), // Rule ID 2525 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (or:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VORRd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // LHS GIR_RootToRootCopy, /*OpIdx*/2, // RHS GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2525, GIR_EraseRootFromParent_Done, // Label 414: @19186 GIM_Reject, // Label 353: @19187 GIM_Try, /*On fail goto*//*Label 415*/ GIMT_Encode4(19298), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 416*/ GIMT_Encode4(19238), // Rule ID 2529 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (or:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VORRq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // LHS GIR_RootToRootCopy, /*OpIdx*/2, // RHS GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2529, GIR_EraseRootFromParent_Done, // Label 416: @19238 GIM_Try, /*On fail goto*//*Label 417*/ GIMT_Encode4(19297), // Rule ID 3471 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (or:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VORR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // Qm GIR_RootToRootCopy, /*OpIdx*/2, // Qn GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3471, GIR_EraseRootFromParent_Done, // Label 417: @19297 GIM_Reject, // Label 415: @19298 GIM_Reject, // Label 354: @19299 GIM_Try, /*On fail goto*//*Label 418*/ GIMT_Encode4(19410), // Rule ID 1859 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), // (or:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, GIR_AddImm8, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), // GIR_Coverage, 1859, GIR_EraseRootFromParent_Done, // Label 418: @19410 GIM_Reject, // Label 355: @19411 GIM_Try, /*On fail goto*//*Label 419*/ GIMT_Encode4(19522), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_Try, /*On fail goto*//*Label 420*/ GIMT_Encode4(19462), // Rule ID 2528 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (or:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VORRq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // LHS GIR_RootToRootCopy, /*OpIdx*/2, // RHS GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2528, GIR_EraseRootFromParent_Done, // Label 420: @19462 GIM_Try, /*On fail goto*//*Label 421*/ GIMT_Encode4(19521), // Rule ID 3467 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (or:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VORR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // Qm GIR_RootToRootCopy, /*OpIdx*/2, // Qn GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3467, GIR_EraseRootFromParent_Done, // Label 421: @19521 GIM_Reject, // Label 419: @19522 GIM_Reject, // Label 356: @19523 GIM_Reject, // Label 7: @19524 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 435*/ GIMT_Encode4(21096), /*GILLT_s32*//*Label 422*/ GIMT_Encode4(19595), /*GILLT_s64*//*Label 423*/ GIMT_Encode4(20012), /*GILLT_v2s1*//*Label 424*/ GIMT_Encode4(20059), /*GILLT_v2s32*//*Label 425*/ GIMT_Encode4(20171), /*GILLT_v2s64*//*Label 426*/ GIMT_Encode4(20218), /*GILLT_v4s1*//*Label 427*/ GIMT_Encode4(20330), /*GILLT_v4s16*//*Label 428*/ GIMT_Encode4(20442), /*GILLT_v4s32*//*Label 429*/ GIMT_Encode4(20489), GIMT_Encode4(0), /*GILLT_v8s1*//*Label 430*/ GIMT_Encode4(20601), /*GILLT_v8s8*//*Label 431*/ GIMT_Encode4(20713), /*GILLT_v8s16*//*Label 432*/ GIMT_Encode4(20760), GIMT_Encode4(0), /*GILLT_v16s1*//*Label 433*/ GIMT_Encode4(20872), /*GILLT_v16s8*//*Label 434*/ GIMT_Encode4(20984), // Label 422: @19595 GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(20011), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 437*/ GIMT_Encode4(19661), // Rule ID 5595 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, uint8_t(-1), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNi), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5595, GIR_EraseRootFromParent_Done, // Label 437: @19661 GIM_Try, /*On fail goto*//*Label 438*/ GIMT_Encode4(19716), // Rule ID 507 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNi), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 507, GIR_EraseRootFromParent_Done, // Label 438: @19716 GIM_Try, /*On fail goto*//*Label 439*/ GIMT_Encode4(19760), // Rule ID 508 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (t2MVNr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNr), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 508, GIR_EraseRootFromParent_Done, // Label 439: @19760 GIM_Try, /*On fail goto*//*Label 440*/ GIMT_Encode4(19804), // Rule ID 165 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (MVNr:{ *:[i32] } GPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVNr), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 165, GIR_EraseRootFromParent_Done, // Label 440: @19804 GIM_Try, /*On fail goto*//*Label 441*/ GIMT_Encode4(19861), // Rule ID 155 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (EORri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::EORri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 155, GIR_EraseRootFromParent_Done, // Label 441: @19861 GIM_Try, /*On fail goto*//*Label 442*/ GIMT_Encode4(19918), // Rule ID 495 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2EORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2EORri), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 495, GIR_EraseRootFromParent_Done, // Label 442: @19918 GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(19964), // Rule ID 156 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (EORrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::EORrr), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_RootToRootCopy, /*OpIdx*/2, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 156, GIR_EraseRootFromParent_Done, // Label 443: @19964 GIM_Try, /*On fail goto*//*Label 444*/ GIMT_Encode4(20010), // Rule ID 496 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2EORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/1, // Rn GIR_RootToRootCopy, /*OpIdx*/2, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 496, GIR_EraseRootFromParent_Done, // Label 444: @20010 GIM_Reject, // Label 436: @20011 GIM_Reject, // Label 423: @20012 GIM_Try, /*On fail goto*//*Label 445*/ GIMT_Encode4(20058), // Rule ID 2533 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (xor:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VEORd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // LHS GIR_RootToRootCopy, /*OpIdx*/2, // RHS GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2533, GIR_EraseRootFromParent_Done, // Label 445: @20058 GIM_Reject, // Label 424: @20059 GIM_Try, /*On fail goto*//*Label 446*/ GIMT_Encode4(20170), // Rule ID 1852 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), // (xor:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, GIR_AddImm8, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), // GIR_Coverage, 1852, GIR_EraseRootFromParent_Done, // Label 446: @20170 GIM_Reject, // Label 425: @20171 GIM_Try, /*On fail goto*//*Label 447*/ GIMT_Encode4(20217), // Rule ID 1152 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (xor:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VEORd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1152, GIR_EraseRootFromParent_Done, // Label 447: @20217 GIM_Reject, // Label 426: @20218 GIM_Try, /*On fail goto*//*Label 448*/ GIMT_Encode4(20329), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_Try, /*On fail goto*//*Label 449*/ GIMT_Encode4(20269), // Rule ID 2536 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (xor:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VEORq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // LHS GIR_RootToRootCopy, /*OpIdx*/2, // RHS GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2536, GIR_EraseRootFromParent_Done, // Label 449: @20269 GIM_Try, /*On fail goto*//*Label 450*/ GIMT_Encode4(20328), // Rule ID 3493 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (xor:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VEOR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // Qm GIR_RootToRootCopy, /*OpIdx*/2, // Qn GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3493, GIR_EraseRootFromParent_Done, // Label 450: @20328 GIM_Reject, // Label 448: @20329 GIM_Reject, // Label 427: @20330 GIM_Try, /*On fail goto*//*Label 451*/ GIMT_Encode4(20441), // Rule ID 1853 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), // (xor:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, GIR_AddImm8, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), // GIR_Coverage, 1853, GIR_EraseRootFromParent_Done, // Label 451: @20441 GIM_Reject, // Label 428: @20442 GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(20488), // Rule ID 2532 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (xor:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VEORd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // LHS GIR_RootToRootCopy, /*OpIdx*/2, // RHS GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2532, GIR_EraseRootFromParent_Done, // Label 452: @20488 GIM_Reject, // Label 429: @20489 GIM_Try, /*On fail goto*//*Label 453*/ GIMT_Encode4(20600), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 454*/ GIMT_Encode4(20540), // Rule ID 1153 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (xor:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VEORq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // Vn GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1153, GIR_EraseRootFromParent_Done, // Label 454: @20540 GIM_Try, /*On fail goto*//*Label 455*/ GIMT_Encode4(20599), // Rule ID 3489 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (xor:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VEOR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // Qm GIR_RootToRootCopy, /*OpIdx*/2, // Qn GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3489, GIR_EraseRootFromParent_Done, // Label 455: @20599 GIM_Reject, // Label 453: @20600 GIM_Reject, // Label 430: @20601 GIM_Try, /*On fail goto*//*Label 456*/ GIMT_Encode4(20712), // Rule ID 1854 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), // (xor:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, GIR_AddImm8, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), // GIR_Coverage, 1854, GIR_EraseRootFromParent_Done, // Label 456: @20712 GIM_Reject, // Label 431: @20713 GIM_Try, /*On fail goto*//*Label 457*/ GIMT_Encode4(20759), // Rule ID 2531 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (xor:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VEORd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // LHS GIR_RootToRootCopy, /*OpIdx*/2, // RHS GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2531, GIR_EraseRootFromParent_Done, // Label 457: @20759 GIM_Reject, // Label 432: @20760 GIM_Try, /*On fail goto*//*Label 458*/ GIMT_Encode4(20871), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 459*/ GIMT_Encode4(20811), // Rule ID 2535 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (xor:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VEORq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // LHS GIR_RootToRootCopy, /*OpIdx*/2, // RHS GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2535, GIR_EraseRootFromParent_Done, // Label 459: @20811 GIM_Try, /*On fail goto*//*Label 460*/ GIMT_Encode4(20870), // Rule ID 3485 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (xor:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VEOR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // Qm GIR_RootToRootCopy, /*OpIdx*/2, // Qn GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3485, GIR_EraseRootFromParent_Done, // Label 460: @20870 GIM_Reject, // Label 458: @20871 GIM_Reject, // Label 433: @20872 GIM_Try, /*On fail goto*//*Label 461*/ GIMT_Encode4(20983), // Rule ID 1855 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), // (xor:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, GIR_AddImm8, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), // GIR_Coverage, 1855, GIR_EraseRootFromParent_Done, // Label 461: @20983 GIM_Reject, // Label 434: @20984 GIM_Try, /*On fail goto*//*Label 462*/ GIMT_Encode4(21095), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_Try, /*On fail goto*//*Label 463*/ GIMT_Encode4(21035), // Rule ID 2534 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (xor:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VEORq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // LHS GIR_RootToRootCopy, /*OpIdx*/2, // RHS GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2534, GIR_EraseRootFromParent_Done, // Label 463: @21035 GIM_Try, /*On fail goto*//*Label 464*/ GIMT_Encode4(21094), // Rule ID 3481 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (xor:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VEOR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // Qm GIR_RootToRootCopy, /*OpIdx*/2, // Qn GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3481, GIR_EraseRootFromParent_Done, // Label 464: @21094 GIM_Reject, // Label 462: @21095 GIM_Reject, // Label 435: @21096 GIM_Reject, // Label 8: @21097 GIM_Try, /*On fail goto*//*Label 465*/ GIMT_Encode4(21522), GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(16), /*)*//*default:*//*Label 470*/ GIMT_Encode4(21521), /*GILLT_v2s64*//*Label 466*/ GIMT_Encode4(21160), GIMT_Encode4(0), GIMT_Encode4(0), /*GILLT_v4s32*//*Label 467*/ GIMT_Encode4(21218), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*GILLT_v8s16*//*Label 468*/ GIMT_Encode4(21321), GIMT_Encode4(0), GIMT_Encode4(0), /*GILLT_v16s8*//*Label 469*/ GIMT_Encode4(21463), // Label 466: @21160 GIM_Try, /*On fail goto*//*Label 471*/ GIMT_Encode4(21217), // Rule ID 3114 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (concat_vectors:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Dn, DPR:{ *:[v1i64] }:$Dm) => (REG_SEQUENCE:{ *:[v2i64] } QPR:{ *:[i32] }, DPR:{ *:[v1i64] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v1i64] }:$Dm, dsub_1:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_RootToRootCopy, /*OpIdx*/1, // Dn GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, GIR_RootToRootCopy, /*OpIdx*/2, // Dm GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 3114, GIR_EraseRootFromParent_Done, // Label 471: @21217 GIM_Reject, // Label 467: @21218 GIM_Try, /*On fail goto*//*Label 472*/ GIMT_Encode4(21320), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_Try, /*On fail goto*//*Label 473*/ GIMT_Encode4(21280), // Rule ID 3115 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), // (concat_vectors:{ *:[v4i32] } DPR:{ *:[v2i32] }:$Dn, DPR:{ *:[v2i32] }:$Dm) => (REG_SEQUENCE:{ *:[v4i32] } QPR:{ *:[i32] }, DPR:{ *:[v2i32] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v2i32] }:$Dm, dsub_1:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_RootToRootCopy, /*OpIdx*/1, // Dn GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, GIR_RootToRootCopy, /*OpIdx*/2, // Dm GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 3115, GIR_EraseRootFromParent_Done, // Label 473: @21280 GIM_Try, /*On fail goto*//*Label 474*/ GIMT_Encode4(21319), // Rule ID 3118 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), // (concat_vectors:{ *:[v4f32] } DPR:{ *:[v2f32] }:$Dn, DPR:{ *:[v2f32] }:$Dm) => (REG_SEQUENCE:{ *:[v4f32] } QPR:{ *:[i32] }, DPR:{ *:[v2f32] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v2f32] }:$Dm, dsub_1:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_RootToRootCopy, /*OpIdx*/1, // Dn GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, GIR_RootToRootCopy, /*OpIdx*/2, // Dm GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 3118, GIR_EraseRootFromParent_Done, // Label 474: @21319 GIM_Reject, // Label 472: @21320 GIM_Reject, // Label 468: @21321 GIM_Try, /*On fail goto*//*Label 475*/ GIMT_Encode4(21462), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_Try, /*On fail goto*//*Label 476*/ GIMT_Encode4(21383), // Rule ID 3116 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), // (concat_vectors:{ *:[v8i16] } DPR:{ *:[v4i16] }:$Dn, DPR:{ *:[v4i16] }:$Dm) => (REG_SEQUENCE:{ *:[v8i16] } QPR:{ *:[i32] }, DPR:{ *:[v4i16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4i16] }:$Dm, dsub_1:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_RootToRootCopy, /*OpIdx*/1, // Dn GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, GIR_RootToRootCopy, /*OpIdx*/2, // Dm GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 3116, GIR_EraseRootFromParent_Done, // Label 476: @21383 GIM_Try, /*On fail goto*//*Label 477*/ GIMT_Encode4(21422), // Rule ID 3119 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), // (concat_vectors:{ *:[v8f16] } DPR:{ *:[v4f16] }:$Dn, DPR:{ *:[v4f16] }:$Dm) => (REG_SEQUENCE:{ *:[v8f16] } QPR:{ *:[i32] }, DPR:{ *:[v4f16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4f16] }:$Dm, dsub_1:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_RootToRootCopy, /*OpIdx*/1, // Dn GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, GIR_RootToRootCopy, /*OpIdx*/2, // Dm GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 3119, GIR_EraseRootFromParent_Done, // Label 477: @21422 GIM_Try, /*On fail goto*//*Label 478*/ GIMT_Encode4(21461), // Rule ID 3120 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), // (concat_vectors:{ *:[v8bf16] } DPR:{ *:[v4bf16] }:$Dn, DPR:{ *:[v4bf16] }:$Dm) => (REG_SEQUENCE:{ *:[v8bf16] } QPR:{ *:[i32] }, DPR:{ *:[v4bf16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4bf16] }:$Dm, dsub_1:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_RootToRootCopy, /*OpIdx*/1, // Dn GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, GIR_RootToRootCopy, /*OpIdx*/2, // Dm GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 3120, GIR_EraseRootFromParent_Done, // Label 478: @21461 GIM_Reject, // Label 475: @21462 GIM_Reject, // Label 469: @21463 GIM_Try, /*On fail goto*//*Label 479*/ GIMT_Encode4(21520), // Rule ID 3117 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (concat_vectors:{ *:[v16i8] } DPR:{ *:[v8i8] }:$Dn, DPR:{ *:[v8i8] }:$Dm) => (REG_SEQUENCE:{ *:[v16i8] } QPR:{ *:[i32] }, DPR:{ *:[v8i8] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v8i8] }:$Dm, dsub_1:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_RootToRootCopy, /*OpIdx*/1, // Dn GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, GIR_RootToRootCopy, /*OpIdx*/2, // Dm GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 3117, GIR_EraseRootFromParent_Done, // Label 479: @21520 GIM_Reject, // Label 470: @21521 GIM_Reject, // Label 465: @21522 GIM_Reject, // Label 9: @21523 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 489*/ GIMT_Encode4(31970), /*GILLT_s32*//*Label 480*/ GIMT_Encode4(21594), /*GILLT_s64*//*Label 481*/ GIMT_Encode4(21742), GIMT_Encode4(0), /*GILLT_v2s32*//*Label 482*/ GIMT_Encode4(22635), /*GILLT_v2s64*//*Label 483*/ GIMT_Encode4(23528), GIMT_Encode4(0), /*GILLT_v4s16*//*Label 484*/ GIMT_Encode4(25365), /*GILLT_v4s32*//*Label 485*/ GIMT_Encode4(26529), GIMT_Encode4(0), GIMT_Encode4(0), /*GILLT_v8s8*//*Label 486*/ GIMT_Encode4(28366), /*GILLT_v8s16*//*Label 487*/ GIMT_Encode4(28850), GIMT_Encode4(0), GIMT_Encode4(0), /*GILLT_v16s8*//*Label 488*/ GIMT_Encode4(30958), // Label 480: @21594 GIM_Try, /*On fail goto*//*Label 490*/ GIMT_Encode4(21741), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 491*/ GIMT_Encode4(21636), // Rule ID 706 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), // (bitconvert:{ *:[i32] } SPR:{ *:[f32] }:$Sn) => (VMOVRS:{ *:[i32] } SPR:{ *:[f32] }:$Sn) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVRS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] GIR_RootToRootCopy, /*OpIdx*/1, // Sn GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 706, GIR_EraseRootFromParent_Done, // Label 491: @21636 GIM_Try, /*On fail goto*//*Label 492*/ GIMT_Encode4(21670), // Rule ID 707 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs_UseVMOVSR), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$Rt) => (VMOVSR:{ *:[f32] } GPR:{ *:[i32] }:$Rt) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVSR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sn] GIR_RootToRootCopy, /*OpIdx*/1, // Rt GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 707, GIR_EraseRootFromParent_Done, // Label 492: @21670 GIM_Try, /*On fail goto*//*Label 493*/ GIMT_Encode4(21740), // Rule ID 2734 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseVMOVSR_HasNEON), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VMOVDRR:{ *:[f64] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$a), ssub_0:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VMOVDRR), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a GIR_AddImm8, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), // GIR_Coverage, 2734, GIR_EraseRootFromParent_Done, // Label 493: @21740 GIM_Reject, // Label 490: @21741 GIM_Reject, // Label 481: @21742 GIM_Try, /*On fail goto*//*Label 494*/ GIMT_Encode4(21774), // Rule ID 2736 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[f64] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[f64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2736, GIR_EraseRootFromParent_Done, // Label 494: @21774 GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(21806), // Rule ID 2737 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v1i64] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v1i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2737, GIR_EraseRootFromParent_Done, // Label 495: @21806 GIM_Try, /*On fail goto*//*Label 496*/ GIMT_Encode4(21838), // Rule ID 2752 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[f64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2752, GIR_EraseRootFromParent_Done, // Label 496: @21838 GIM_Try, /*On fail goto*//*Label 497*/ GIMT_Encode4(21870), // Rule ID 2753 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[f64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2753, GIR_EraseRootFromParent_Done, // Label 497: @21870 GIM_Try, /*On fail goto*//*Label 498*/ GIMT_Encode4(21902), // Rule ID 2754 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[f64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2754, GIR_EraseRootFromParent_Done, // Label 498: @21902 GIM_Try, /*On fail goto*//*Label 499*/ GIMT_Encode4(21934), // Rule ID 2755 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[f64] } DPR:{ *:[v4bf16] }:$src) => DPR:{ *:[f64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2755, GIR_EraseRootFromParent_Done, // Label 499: @21934 GIM_Try, /*On fail goto*//*Label 500*/ GIMT_Encode4(21966), // Rule ID 2756 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[f64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2756, GIR_EraseRootFromParent_Done, // Label 500: @21966 GIM_Try, /*On fail goto*//*Label 501*/ GIMT_Encode4(21998), // Rule ID 2757 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[f64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2757, GIR_EraseRootFromParent_Done, // Label 501: @21998 GIM_Try, /*On fail goto*//*Label 502*/ GIMT_Encode4(22030), // Rule ID 2758 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v1i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2758, GIR_EraseRootFromParent_Done, // Label 502: @22030 GIM_Try, /*On fail goto*//*Label 503*/ GIMT_Encode4(22062), // Rule ID 2759 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v1i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2759, GIR_EraseRootFromParent_Done, // Label 503: @22062 GIM_Try, /*On fail goto*//*Label 504*/ GIMT_Encode4(22094), // Rule ID 2760 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v1i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2760, GIR_EraseRootFromParent_Done, // Label 504: @22094 GIM_Try, /*On fail goto*//*Label 505*/ GIMT_Encode4(22126), // Rule ID 2761 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4bf16] }:$src) => DPR:{ *:[v1i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2761, GIR_EraseRootFromParent_Done, // Label 505: @22126 GIM_Try, /*On fail goto*//*Label 506*/ GIMT_Encode4(22158), // Rule ID 2762 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v1i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2762, GIR_EraseRootFromParent_Done, // Label 506: @22158 GIM_Try, /*On fail goto*//*Label 507*/ GIMT_Encode4(22190), // Rule ID 2763 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v1i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2763, GIR_EraseRootFromParent_Done, // Label 507: @22190 GIM_Try, /*On fail goto*//*Label 508*/ GIMT_Encode4(22227), // Rule ID 2844 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2f32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2844, GIR_EraseRootFromParent_Done, // Label 508: @22227 GIM_Try, /*On fail goto*//*Label 509*/ GIMT_Encode4(22264), // Rule ID 2845 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2i32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2845, GIR_EraseRootFromParent_Done, // Label 509: @22264 GIM_Try, /*On fail goto*//*Label 510*/ GIMT_Encode4(22301), // Rule ID 2846 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4f16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2846, GIR_EraseRootFromParent_Done, // Label 510: @22301 GIM_Try, /*On fail goto*//*Label 511*/ GIMT_Encode4(22338), // Rule ID 2847 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[f64] } DPR:{ *:[v4bf16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4bf16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2847, GIR_EraseRootFromParent_Done, // Label 511: @22338 GIM_Try, /*On fail goto*//*Label 512*/ GIMT_Encode4(22375), // Rule ID 2848 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4i16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2848, GIR_EraseRootFromParent_Done, // Label 512: @22375 GIM_Try, /*On fail goto*//*Label 513*/ GIMT_Encode4(22412), // Rule ID 2849 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[f64] } DPR:{ *:[v8i8] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2849, GIR_EraseRootFromParent_Done, // Label 513: @22412 GIM_Try, /*On fail goto*//*Label 514*/ GIMT_Encode4(22449), // Rule ID 2850 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2850, GIR_EraseRootFromParent_Done, // Label 514: @22449 GIM_Try, /*On fail goto*//*Label 515*/ GIMT_Encode4(22486), // Rule ID 2851 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2851, GIR_EraseRootFromParent_Done, // Label 515: @22486 GIM_Try, /*On fail goto*//*Label 516*/ GIMT_Encode4(22523), // Rule ID 2852 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2852, GIR_EraseRootFromParent_Done, // Label 516: @22523 GIM_Try, /*On fail goto*//*Label 517*/ GIMT_Encode4(22560), // Rule ID 2853 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4bf16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4bf16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2853, GIR_EraseRootFromParent_Done, // Label 517: @22560 GIM_Try, /*On fail goto*//*Label 518*/ GIMT_Encode4(22597), // Rule ID 2854 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2854, GIR_EraseRootFromParent_Done, // Label 518: @22597 GIM_Try, /*On fail goto*//*Label 519*/ GIMT_Encode4(22634), // Rule ID 2855 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2855, GIR_EraseRootFromParent_Done, // Label 519: @22634 GIM_Reject, // Label 482: @22635 GIM_Try, /*On fail goto*//*Label 520*/ GIMT_Encode4(22667), // Rule ID 2738 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2f32] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v2f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2738, GIR_EraseRootFromParent_Done, // Label 520: @22667 GIM_Try, /*On fail goto*//*Label 521*/ GIMT_Encode4(22699), // Rule ID 2739 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2i32] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v2i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2739, GIR_EraseRootFromParent_Done, // Label 521: @22699 GIM_Try, /*On fail goto*//*Label 522*/ GIMT_Encode4(22731), // Rule ID 2764 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2764, GIR_EraseRootFromParent_Done, // Label 522: @22731 GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(22763), // Rule ID 2765 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2765, GIR_EraseRootFromParent_Done, // Label 523: @22763 GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(22795), // Rule ID 2766 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2766, GIR_EraseRootFromParent_Done, // Label 524: @22795 GIM_Try, /*On fail goto*//*Label 525*/ GIMT_Encode4(22827), // Rule ID 2767 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4bf16] }:$src) => DPR:{ *:[v2f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2767, GIR_EraseRootFromParent_Done, // Label 525: @22827 GIM_Try, /*On fail goto*//*Label 526*/ GIMT_Encode4(22859), // Rule ID 2768 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2768, GIR_EraseRootFromParent_Done, // Label 526: @22859 GIM_Try, /*On fail goto*//*Label 527*/ GIMT_Encode4(22891), // Rule ID 2769 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2769, GIR_EraseRootFromParent_Done, // Label 527: @22891 GIM_Try, /*On fail goto*//*Label 528*/ GIMT_Encode4(22923), // Rule ID 2770 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2770, GIR_EraseRootFromParent_Done, // Label 528: @22923 GIM_Try, /*On fail goto*//*Label 529*/ GIMT_Encode4(22955), // Rule ID 2771 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2771, GIR_EraseRootFromParent_Done, // Label 529: @22955 GIM_Try, /*On fail goto*//*Label 530*/ GIMT_Encode4(22987), // Rule ID 2772 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2772, GIR_EraseRootFromParent_Done, // Label 530: @22987 GIM_Try, /*On fail goto*//*Label 531*/ GIMT_Encode4(23019), // Rule ID 2773 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4bf16] }:$src) => DPR:{ *:[v2i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2773, GIR_EraseRootFromParent_Done, // Label 531: @23019 GIM_Try, /*On fail goto*//*Label 532*/ GIMT_Encode4(23051), // Rule ID 2774 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2774, GIR_EraseRootFromParent_Done, // Label 532: @23051 GIM_Try, /*On fail goto*//*Label 533*/ GIMT_Encode4(23083), // Rule ID 2775 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2775, GIR_EraseRootFromParent_Done, // Label 533: @23083 GIM_Try, /*On fail goto*//*Label 534*/ GIMT_Encode4(23120), // Rule ID 2856 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[f64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2856, GIR_EraseRootFromParent_Done, // Label 534: @23120 GIM_Try, /*On fail goto*//*Label 535*/ GIMT_Encode4(23157), // Rule ID 2857 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2857, GIR_EraseRootFromParent_Done, // Label 535: @23157 GIM_Try, /*On fail goto*//*Label 536*/ GIMT_Encode4(23194), // Rule ID 2858 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2858, GIR_EraseRootFromParent_Done, // Label 536: @23194 GIM_Try, /*On fail goto*//*Label 537*/ GIMT_Encode4(23231), // Rule ID 2859 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4bf16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4bf16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2859, GIR_EraseRootFromParent_Done, // Label 537: @23231 GIM_Try, /*On fail goto*//*Label 538*/ GIMT_Encode4(23268), // Rule ID 2860 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2860, GIR_EraseRootFromParent_Done, // Label 538: @23268 GIM_Try, /*On fail goto*//*Label 539*/ GIMT_Encode4(23305), // Rule ID 2861 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2861, GIR_EraseRootFromParent_Done, // Label 539: @23305 GIM_Try, /*On fail goto*//*Label 540*/ GIMT_Encode4(23342), // Rule ID 2862 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[f64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2862, GIR_EraseRootFromParent_Done, // Label 540: @23342 GIM_Try, /*On fail goto*//*Label 541*/ GIMT_Encode4(23379), // Rule ID 2863 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2863, GIR_EraseRootFromParent_Done, // Label 541: @23379 GIM_Try, /*On fail goto*//*Label 542*/ GIMT_Encode4(23416), // Rule ID 2864 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2864, GIR_EraseRootFromParent_Done, // Label 542: @23416 GIM_Try, /*On fail goto*//*Label 543*/ GIMT_Encode4(23453), // Rule ID 2865 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4bf16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4bf16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2865, GIR_EraseRootFromParent_Done, // Label 543: @23453 GIM_Try, /*On fail goto*//*Label 544*/ GIMT_Encode4(23490), // Rule ID 2866 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2866, GIR_EraseRootFromParent_Done, // Label 544: @23490 GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(23527), // Rule ID 2867 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2867, GIR_EraseRootFromParent_Done, // Label 545: @23527 GIM_Reject, // Label 483: @23528 GIM_Try, /*On fail goto*//*Label 546*/ GIMT_Encode4(23560), // Rule ID 2744 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2f64] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v2f64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2744, GIR_EraseRootFromParent_Done, // Label 546: @23560 GIM_Try, /*On fail goto*//*Label 547*/ GIMT_Encode4(23592), // Rule ID 2745 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2i64] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v2i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2745, GIR_EraseRootFromParent_Done, // Label 547: @23592 GIM_Try, /*On fail goto*//*Label 548*/ GIMT_Encode4(23624), // Rule ID 2798 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2f64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2798, GIR_EraseRootFromParent_Done, // Label 548: @23624 GIM_Try, /*On fail goto*//*Label 549*/ GIMT_Encode4(23656), // Rule ID 2799 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2f64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2799, GIR_EraseRootFromParent_Done, // Label 549: @23656 GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(23688), // Rule ID 2800 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2f64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2800, GIR_EraseRootFromParent_Done, // Label 550: @23688 GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(23720), // Rule ID 2801 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8bf16] }:$src) => QPR:{ *:[v2f64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2801, GIR_EraseRootFromParent_Done, // Label 551: @23720 GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(23752), // Rule ID 2802 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2f64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2802, GIR_EraseRootFromParent_Done, // Label 552: @23752 GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(23784), // Rule ID 2803 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2f64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2803, GIR_EraseRootFromParent_Done, // Label 553: @23784 GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(23816), // Rule ID 2804 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2804, GIR_EraseRootFromParent_Done, // Label 554: @23816 GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(23848), // Rule ID 2805 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2805, GIR_EraseRootFromParent_Done, // Label 555: @23848 GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(23880), // Rule ID 2806 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2806, GIR_EraseRootFromParent_Done, // Label 556: @23880 GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(23912), // Rule ID 2807 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8bf16] }:$src) => QPR:{ *:[v2i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2807, GIR_EraseRootFromParent_Done, // Label 557: @23912 GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(23944), // Rule ID 2808 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2808, GIR_EraseRootFromParent_Done, // Label 558: @23944 GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(23976), // Rule ID 2809 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2809, GIR_EraseRootFromParent_Done, // Label 559: @23976 GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(24013), // Rule ID 2890 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2890, GIR_EraseRootFromParent_Done, // Label 560: @24013 GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(24050), // Rule ID 2891 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2891, GIR_EraseRootFromParent_Done, // Label 561: @24050 GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(24087), // Rule ID 2892 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2892, GIR_EraseRootFromParent_Done, // Label 562: @24087 GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(24124), // Rule ID 2893 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8bf16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8bf16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2893, GIR_EraseRootFromParent_Done, // Label 563: @24124 GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(24161), // Rule ID 2894 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2894, GIR_EraseRootFromParent_Done, // Label 564: @24161 GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(24198), // Rule ID 2895 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2895, GIR_EraseRootFromParent_Done, // Label 565: @24198 GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(24235), // Rule ID 2896 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2896, GIR_EraseRootFromParent_Done, // Label 566: @24235 GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(24272), // Rule ID 2897 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2897, GIR_EraseRootFromParent_Done, // Label 567: @24272 GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(24309), // Rule ID 2898 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2898, GIR_EraseRootFromParent_Done, // Label 568: @24309 GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(24346), // Rule ID 2899 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8bf16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8bf16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2899, GIR_EraseRootFromParent_Done, // Label 569: @24346 GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(24383), // Rule ID 2900 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2900, GIR_EraseRootFromParent_Done, // Label 570: @24383 GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(24420), // Rule ID 2901 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2901, GIR_EraseRootFromParent_Done, // Label 571: @24420 GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(24452), // Rule ID 5398 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v2f64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5398, GIR_EraseRootFromParent_Done, // Label 572: @24452 GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(24484), // Rule ID 5399 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v2i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5399, GIR_EraseRootFromParent_Done, // Label 573: @24484 GIM_Try, /*On fail goto*//*Label 574*/ GIMT_Encode4(24516), // Rule ID 5404 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2f64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5404, GIR_EraseRootFromParent_Done, // Label 574: @24516 GIM_Try, /*On fail goto*//*Label 575*/ GIMT_Encode4(24548), // Rule ID 5405 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2f64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5405, GIR_EraseRootFromParent_Done, // Label 575: @24548 GIM_Try, /*On fail goto*//*Label 576*/ GIMT_Encode4(24580), // Rule ID 5406 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2f64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5406, GIR_EraseRootFromParent_Done, // Label 576: @24580 GIM_Try, /*On fail goto*//*Label 577*/ GIMT_Encode4(24612), // Rule ID 5407 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2f64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5407, GIR_EraseRootFromParent_Done, // Label 577: @24612 GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(24644), // Rule ID 5408 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2f64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5408, GIR_EraseRootFromParent_Done, // Label 578: @24644 GIM_Try, /*On fail goto*//*Label 579*/ GIMT_Encode4(24676), // Rule ID 5409 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5409, GIR_EraseRootFromParent_Done, // Label 579: @24676 GIM_Try, /*On fail goto*//*Label 580*/ GIMT_Encode4(24708), // Rule ID 5410 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5410, GIR_EraseRootFromParent_Done, // Label 580: @24708 GIM_Try, /*On fail goto*//*Label 581*/ GIMT_Encode4(24740), // Rule ID 5411 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5411, GIR_EraseRootFromParent_Done, // Label 581: @24740 GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(24772), // Rule ID 5412 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5412, GIR_EraseRootFromParent_Done, // Label 582: @24772 GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(24804), // Rule ID 5413 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5413, GIR_EraseRootFromParent_Done, // Label 583: @24804 GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(24860), // Rule ID 5440 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5440, GIR_EraseRootFromParent_Done, // Label 584: @24860 GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(24916), // Rule ID 5441 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5441, GIR_EraseRootFromParent_Done, // Label 585: @24916 GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(24972), // Rule ID 5442 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5442, GIR_EraseRootFromParent_Done, // Label 586: @24972 GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(25028), // Rule ID 5443 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5443, GIR_EraseRootFromParent_Done, // Label 587: @25028 GIM_Try, /*On fail goto*//*Label 588*/ GIMT_Encode4(25084), // Rule ID 5444 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5444, GIR_EraseRootFromParent_Done, // Label 588: @25084 GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(25140), // Rule ID 5445 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5445, GIR_EraseRootFromParent_Done, // Label 589: @25140 GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(25196), // Rule ID 5446 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5446, GIR_EraseRootFromParent_Done, // Label 590: @25196 GIM_Try, /*On fail goto*//*Label 591*/ GIMT_Encode4(25252), // Rule ID 5447 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5447, GIR_EraseRootFromParent_Done, // Label 591: @25252 GIM_Try, /*On fail goto*//*Label 592*/ GIMT_Encode4(25308), // Rule ID 5448 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5448, GIR_EraseRootFromParent_Done, // Label 592: @25308 GIM_Try, /*On fail goto*//*Label 593*/ GIMT_Encode4(25364), // Rule ID 5449 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5449, GIR_EraseRootFromParent_Done, // Label 593: @25364 GIM_Reject, // Label 484: @25365 GIM_Try, /*On fail goto*//*Label 594*/ GIMT_Encode4(25397), // Rule ID 2740 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4i16] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v4i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2740, GIR_EraseRootFromParent_Done, // Label 594: @25397 GIM_Try, /*On fail goto*//*Label 595*/ GIMT_Encode4(25429), // Rule ID 2741 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4f16] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v4f16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2741, GIR_EraseRootFromParent_Done, // Label 595: @25429 GIM_Try, /*On fail goto*//*Label 596*/ GIMT_Encode4(25461), // Rule ID 2742 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4i16] } DPR:{ *:[v4bf16] }:$src) => DPR:{ *:[v4i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2742, GIR_EraseRootFromParent_Done, // Label 596: @25461 GIM_Try, /*On fail goto*//*Label 597*/ GIMT_Encode4(25493), // Rule ID 2743 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v4bf16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2743, GIR_EraseRootFromParent_Done, // Label 597: @25493 GIM_Try, /*On fail goto*//*Label 598*/ GIMT_Encode4(25525), // Rule ID 2776 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4f16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2776, GIR_EraseRootFromParent_Done, // Label 598: @25525 GIM_Try, /*On fail goto*//*Label 599*/ GIMT_Encode4(25557), // Rule ID 2777 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4f16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2777, GIR_EraseRootFromParent_Done, // Label 599: @25557 GIM_Try, /*On fail goto*//*Label 600*/ GIMT_Encode4(25589), // Rule ID 2778 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4f16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2778, GIR_EraseRootFromParent_Done, // Label 600: @25589 GIM_Try, /*On fail goto*//*Label 601*/ GIMT_Encode4(25621), // Rule ID 2779 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4f16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2779, GIR_EraseRootFromParent_Done, // Label 601: @25621 GIM_Try, /*On fail goto*//*Label 602*/ GIMT_Encode4(25653), // Rule ID 2780 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4f16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2780, GIR_EraseRootFromParent_Done, // Label 602: @25653 GIM_Try, /*On fail goto*//*Label 603*/ GIMT_Encode4(25685), // Rule ID 2781 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4bf16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4bf16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2781, GIR_EraseRootFromParent_Done, // Label 603: @25685 GIM_Try, /*On fail goto*//*Label 604*/ GIMT_Encode4(25717), // Rule ID 2782 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4bf16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2782, GIR_EraseRootFromParent_Done, // Label 604: @25717 GIM_Try, /*On fail goto*//*Label 605*/ GIMT_Encode4(25749), // Rule ID 2783 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4bf16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2783, GIR_EraseRootFromParent_Done, // Label 605: @25749 GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(25781), // Rule ID 2784 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4bf16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2784, GIR_EraseRootFromParent_Done, // Label 606: @25781 GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(25813), // Rule ID 2785 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4bf16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2785, GIR_EraseRootFromParent_Done, // Label 607: @25813 GIM_Try, /*On fail goto*//*Label 608*/ GIMT_Encode4(25845), // Rule ID 2786 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2786, GIR_EraseRootFromParent_Done, // Label 608: @25845 GIM_Try, /*On fail goto*//*Label 609*/ GIMT_Encode4(25877), // Rule ID 2787 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2787, GIR_EraseRootFromParent_Done, // Label 609: @25877 GIM_Try, /*On fail goto*//*Label 610*/ GIMT_Encode4(25909), // Rule ID 2788 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2788, GIR_EraseRootFromParent_Done, // Label 610: @25909 GIM_Try, /*On fail goto*//*Label 611*/ GIMT_Encode4(25941), // Rule ID 2789 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2789, GIR_EraseRootFromParent_Done, // Label 611: @25941 GIM_Try, /*On fail goto*//*Label 612*/ GIMT_Encode4(25973), // Rule ID 2790 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2790, GIR_EraseRootFromParent_Done, // Label 612: @25973 GIM_Try, /*On fail goto*//*Label 613*/ GIMT_Encode4(26010), // Rule ID 2868 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[f64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2868, GIR_EraseRootFromParent_Done, // Label 613: @26010 GIM_Try, /*On fail goto*//*Label 614*/ GIMT_Encode4(26047), // Rule ID 2869 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2869, GIR_EraseRootFromParent_Done, // Label 614: @26047 GIM_Try, /*On fail goto*//*Label 615*/ GIMT_Encode4(26084), // Rule ID 2870 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2870, GIR_EraseRootFromParent_Done, // Label 615: @26084 GIM_Try, /*On fail goto*//*Label 616*/ GIMT_Encode4(26121), // Rule ID 2871 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2871, GIR_EraseRootFromParent_Done, // Label 616: @26121 GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(26158), // Rule ID 2872 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2872, GIR_EraseRootFromParent_Done, // Label 617: @26158 GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(26195), // Rule ID 2873 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4bf16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4bf16] } DPR:{ *:[f64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2873, GIR_EraseRootFromParent_Done, // Label 618: @26195 GIM_Try, /*On fail goto*//*Label 619*/ GIMT_Encode4(26232), // Rule ID 2874 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4bf16] } DPR:{ *:[v1i64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2874, GIR_EraseRootFromParent_Done, // Label 619: @26232 GIM_Try, /*On fail goto*//*Label 620*/ GIMT_Encode4(26269), // Rule ID 2875 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4bf16] } DPR:{ *:[v2f32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2875, GIR_EraseRootFromParent_Done, // Label 620: @26269 GIM_Try, /*On fail goto*//*Label 621*/ GIMT_Encode4(26306), // Rule ID 2876 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4bf16] } DPR:{ *:[v2i32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2876, GIR_EraseRootFromParent_Done, // Label 621: @26306 GIM_Try, /*On fail goto*//*Label 622*/ GIMT_Encode4(26343), // Rule ID 2877 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4bf16] } DPR:{ *:[v8i8] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2877, GIR_EraseRootFromParent_Done, // Label 622: @26343 GIM_Try, /*On fail goto*//*Label 623*/ GIMT_Encode4(26380), // Rule ID 2878 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[f64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2878, GIR_EraseRootFromParent_Done, // Label 623: @26380 GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(26417), // Rule ID 2879 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2879, GIR_EraseRootFromParent_Done, // Label 624: @26417 GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(26454), // Rule ID 2880 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2880, GIR_EraseRootFromParent_Done, // Label 625: @26454 GIM_Try, /*On fail goto*//*Label 626*/ GIMT_Encode4(26491), // Rule ID 2881 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2881, GIR_EraseRootFromParent_Done, // Label 626: @26491 GIM_Try, /*On fail goto*//*Label 627*/ GIMT_Encode4(26528), // Rule ID 2882 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2882, GIR_EraseRootFromParent_Done, // Label 627: @26528 GIM_Reject, // Label 485: @26529 GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(26561), // Rule ID 2746 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4i32] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v4i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2746, GIR_EraseRootFromParent_Done, // Label 628: @26561 GIM_Try, /*On fail goto*//*Label 629*/ GIMT_Encode4(26593), // Rule ID 2747 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4f32] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v4f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2747, GIR_EraseRootFromParent_Done, // Label 629: @26593 GIM_Try, /*On fail goto*//*Label 630*/ GIMT_Encode4(26625), // Rule ID 2810 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2810, GIR_EraseRootFromParent_Done, // Label 630: @26625 GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(26657), // Rule ID 2811 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2811, GIR_EraseRootFromParent_Done, // Label 631: @26657 GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(26689), // Rule ID 2812 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2812, GIR_EraseRootFromParent_Done, // Label 632: @26689 GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(26721), // Rule ID 2813 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8bf16] }:$src) => QPR:{ *:[v4f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2813, GIR_EraseRootFromParent_Done, // Label 633: @26721 GIM_Try, /*On fail goto*//*Label 634*/ GIMT_Encode4(26753), // Rule ID 2814 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2814, GIR_EraseRootFromParent_Done, // Label 634: @26753 GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(26785), // Rule ID 2815 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2815, GIR_EraseRootFromParent_Done, // Label 635: @26785 GIM_Try, /*On fail goto*//*Label 636*/ GIMT_Encode4(26817), // Rule ID 2816 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2816, GIR_EraseRootFromParent_Done, // Label 636: @26817 GIM_Try, /*On fail goto*//*Label 637*/ GIMT_Encode4(26849), // Rule ID 2817 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2817, GIR_EraseRootFromParent_Done, // Label 637: @26849 GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(26881), // Rule ID 2818 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2818, GIR_EraseRootFromParent_Done, // Label 638: @26881 GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(26913), // Rule ID 2819 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8bf16] }:$src) => QPR:{ *:[v4i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2819, GIR_EraseRootFromParent_Done, // Label 639: @26913 GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(26945), // Rule ID 2820 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2820, GIR_EraseRootFromParent_Done, // Label 640: @26945 GIM_Try, /*On fail goto*//*Label 641*/ GIMT_Encode4(26977), // Rule ID 2821 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2821, GIR_EraseRootFromParent_Done, // Label 641: @26977 GIM_Try, /*On fail goto*//*Label 642*/ GIMT_Encode4(27014), // Rule ID 2902 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2902, GIR_EraseRootFromParent_Done, // Label 642: @27014 GIM_Try, /*On fail goto*//*Label 643*/ GIMT_Encode4(27051), // Rule ID 2903 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2903, GIR_EraseRootFromParent_Done, // Label 643: @27051 GIM_Try, /*On fail goto*//*Label 644*/ GIMT_Encode4(27088), // Rule ID 2904 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2904, GIR_EraseRootFromParent_Done, // Label 644: @27088 GIM_Try, /*On fail goto*//*Label 645*/ GIMT_Encode4(27125), // Rule ID 2905 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8bf16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8bf16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2905, GIR_EraseRootFromParent_Done, // Label 645: @27125 GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(27162), // Rule ID 2906 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2906, GIR_EraseRootFromParent_Done, // Label 646: @27162 GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(27199), // Rule ID 2907 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2907, GIR_EraseRootFromParent_Done, // Label 647: @27199 GIM_Try, /*On fail goto*//*Label 648*/ GIMT_Encode4(27236), // Rule ID 2908 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2908, GIR_EraseRootFromParent_Done, // Label 648: @27236 GIM_Try, /*On fail goto*//*Label 649*/ GIMT_Encode4(27273), // Rule ID 2909 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2909, GIR_EraseRootFromParent_Done, // Label 649: @27273 GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(27310), // Rule ID 2910 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2910, GIR_EraseRootFromParent_Done, // Label 650: @27310 GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(27347), // Rule ID 2911 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8bf16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8bf16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2911, GIR_EraseRootFromParent_Done, // Label 651: @27347 GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(27384), // Rule ID 2912 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2912, GIR_EraseRootFromParent_Done, // Label 652: @27384 GIM_Try, /*On fail goto*//*Label 653*/ GIMT_Encode4(27421), // Rule ID 2913 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2913, GIR_EraseRootFromParent_Done, // Label 653: @27421 GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(27453), // Rule ID 5400 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v4i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5400, GIR_EraseRootFromParent_Done, // Label 654: @27453 GIM_Try, /*On fail goto*//*Label 655*/ GIMT_Encode4(27485), // Rule ID 5401 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v4f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5401, GIR_EraseRootFromParent_Done, // Label 655: @27485 GIM_Try, /*On fail goto*//*Label 656*/ GIMT_Encode4(27517), // Rule ID 5414 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5414, GIR_EraseRootFromParent_Done, // Label 656: @27517 GIM_Try, /*On fail goto*//*Label 657*/ GIMT_Encode4(27549), // Rule ID 5415 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5415, GIR_EraseRootFromParent_Done, // Label 657: @27549 GIM_Try, /*On fail goto*//*Label 658*/ GIMT_Encode4(27581), // Rule ID 5416 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5416, GIR_EraseRootFromParent_Done, // Label 658: @27581 GIM_Try, /*On fail goto*//*Label 659*/ GIMT_Encode4(27613), // Rule ID 5417 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5417, GIR_EraseRootFromParent_Done, // Label 659: @27613 GIM_Try, /*On fail goto*//*Label 660*/ GIMT_Encode4(27645), // Rule ID 5418 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5418, GIR_EraseRootFromParent_Done, // Label 660: @27645 GIM_Try, /*On fail goto*//*Label 661*/ GIMT_Encode4(27677), // Rule ID 5419 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5419, GIR_EraseRootFromParent_Done, // Label 661: @27677 GIM_Try, /*On fail goto*//*Label 662*/ GIMT_Encode4(27709), // Rule ID 5420 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5420, GIR_EraseRootFromParent_Done, // Label 662: @27709 GIM_Try, /*On fail goto*//*Label 663*/ GIMT_Encode4(27741), // Rule ID 5421 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5421, GIR_EraseRootFromParent_Done, // Label 663: @27741 GIM_Try, /*On fail goto*//*Label 664*/ GIMT_Encode4(27773), // Rule ID 5422 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5422, GIR_EraseRootFromParent_Done, // Label 664: @27773 GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(27805), // Rule ID 5423 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5423, GIR_EraseRootFromParent_Done, // Label 665: @27805 GIM_Try, /*On fail goto*//*Label 666*/ GIMT_Encode4(27861), // Rule ID 5450 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5450, GIR_EraseRootFromParent_Done, // Label 666: @27861 GIM_Try, /*On fail goto*//*Label 667*/ GIMT_Encode4(27917), // Rule ID 5451 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5451, GIR_EraseRootFromParent_Done, // Label 667: @27917 GIM_Try, /*On fail goto*//*Label 668*/ GIMT_Encode4(27973), // Rule ID 5452 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5452, GIR_EraseRootFromParent_Done, // Label 668: @27973 GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(28029), // Rule ID 5453 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5453, GIR_EraseRootFromParent_Done, // Label 669: @28029 GIM_Try, /*On fail goto*//*Label 670*/ GIMT_Encode4(28085), // Rule ID 5454 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5454, GIR_EraseRootFromParent_Done, // Label 670: @28085 GIM_Try, /*On fail goto*//*Label 671*/ GIMT_Encode4(28141), // Rule ID 5455 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5455, GIR_EraseRootFromParent_Done, // Label 671: @28141 GIM_Try, /*On fail goto*//*Label 672*/ GIMT_Encode4(28197), // Rule ID 5456 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5456, GIR_EraseRootFromParent_Done, // Label 672: @28197 GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(28253), // Rule ID 5457 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5457, GIR_EraseRootFromParent_Done, // Label 673: @28253 GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(28309), // Rule ID 5458 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5458, GIR_EraseRootFromParent_Done, // Label 674: @28309 GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(28365), // Rule ID 5459 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5459, GIR_EraseRootFromParent_Done, // Label 675: @28365 GIM_Reject, // Label 486: @28366 GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(28398), // Rule ID 2791 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v8i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2791, GIR_EraseRootFromParent_Done, // Label 676: @28398 GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(28430), // Rule ID 2792 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v8i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2792, GIR_EraseRootFromParent_Done, // Label 677: @28430 GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(28462), // Rule ID 2793 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v8i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2793, GIR_EraseRootFromParent_Done, // Label 678: @28462 GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(28494), // Rule ID 2794 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v8i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2794, GIR_EraseRootFromParent_Done, // Label 679: @28494 GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(28526), // Rule ID 2795 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v8i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2795, GIR_EraseRootFromParent_Done, // Label 680: @28526 GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(28558), // Rule ID 2796 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4bf16] }:$src) => DPR:{ *:[v8i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2796, GIR_EraseRootFromParent_Done, // Label 681: @28558 GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(28590), // Rule ID 2797 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v8i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), // GIR_Coverage, 2797, GIR_EraseRootFromParent_Done, // Label 682: @28590 GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(28627), // Rule ID 2883 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[f64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2883, GIR_EraseRootFromParent_Done, // Label 683: @28627 GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(28664), // Rule ID 2884 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2884, GIR_EraseRootFromParent_Done, // Label 684: @28664 GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(28701), // Rule ID 2885 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2885, GIR_EraseRootFromParent_Done, // Label 685: @28701 GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(28738), // Rule ID 2886 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2886, GIR_EraseRootFromParent_Done, // Label 686: @28738 GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(28775), // Rule ID 2887 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2887, GIR_EraseRootFromParent_Done, // Label 687: @28775 GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(28812), // Rule ID 2888 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4bf16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4bf16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2888, GIR_EraseRootFromParent_Done, // Label 688: @28812 GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(28849), // Rule ID 2889 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2889, GIR_EraseRootFromParent_Done, // Label 689: @28849 GIM_Reject, // Label 487: @28850 GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(28882), // Rule ID 2748 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8i16] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v8i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2748, GIR_EraseRootFromParent_Done, // Label 690: @28882 GIM_Try, /*On fail goto*//*Label 691*/ GIMT_Encode4(28914), // Rule ID 2749 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8f16] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v8f16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2749, GIR_EraseRootFromParent_Done, // Label 691: @28914 GIM_Try, /*On fail goto*//*Label 692*/ GIMT_Encode4(28946), // Rule ID 2750 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8i16] } QPR:{ *:[v8bf16] }:$src) => QPR:{ *:[v8i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2750, GIR_EraseRootFromParent_Done, // Label 692: @28946 GIM_Try, /*On fail goto*//*Label 693*/ GIMT_Encode4(28978), // Rule ID 2751 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v8bf16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2751, GIR_EraseRootFromParent_Done, // Label 693: @28978 GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(29010), // Rule ID 2822 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8f16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2822, GIR_EraseRootFromParent_Done, // Label 694: @29010 GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(29042), // Rule ID 2823 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8f16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2823, GIR_EraseRootFromParent_Done, // Label 695: @29042 GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(29074), // Rule ID 2824 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8f16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2824, GIR_EraseRootFromParent_Done, // Label 696: @29074 GIM_Try, /*On fail goto*//*Label 697*/ GIMT_Encode4(29106), // Rule ID 2825 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8f16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2825, GIR_EraseRootFromParent_Done, // Label 697: @29106 GIM_Try, /*On fail goto*//*Label 698*/ GIMT_Encode4(29138), // Rule ID 2826 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8f16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2826, GIR_EraseRootFromParent_Done, // Label 698: @29138 GIM_Try, /*On fail goto*//*Label 699*/ GIMT_Encode4(29170), // Rule ID 2827 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8bf16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2827, GIR_EraseRootFromParent_Done, // Label 699: @29170 GIM_Try, /*On fail goto*//*Label 700*/ GIMT_Encode4(29202), // Rule ID 2828 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8bf16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2828, GIR_EraseRootFromParent_Done, // Label 700: @29202 GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(29234), // Rule ID 2829 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8bf16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2829, GIR_EraseRootFromParent_Done, // Label 701: @29234 GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(29266), // Rule ID 2830 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8bf16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2830, GIR_EraseRootFromParent_Done, // Label 702: @29266 GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(29298), // Rule ID 2831 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8bf16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2831, GIR_EraseRootFromParent_Done, // Label 703: @29298 GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(29330), // Rule ID 2832 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2832, GIR_EraseRootFromParent_Done, // Label 704: @29330 GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(29362), // Rule ID 2833 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2833, GIR_EraseRootFromParent_Done, // Label 705: @29362 GIM_Try, /*On fail goto*//*Label 706*/ GIMT_Encode4(29394), // Rule ID 2834 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2834, GIR_EraseRootFromParent_Done, // Label 706: @29394 GIM_Try, /*On fail goto*//*Label 707*/ GIMT_Encode4(29426), // Rule ID 2835 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2835, GIR_EraseRootFromParent_Done, // Label 707: @29426 GIM_Try, /*On fail goto*//*Label 708*/ GIMT_Encode4(29458), // Rule ID 2836 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2836, GIR_EraseRootFromParent_Done, // Label 708: @29458 GIM_Try, /*On fail goto*//*Label 709*/ GIMT_Encode4(29495), // Rule ID 2914 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2914, GIR_EraseRootFromParent_Done, // Label 709: @29495 GIM_Try, /*On fail goto*//*Label 710*/ GIMT_Encode4(29532), // Rule ID 2915 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2915, GIR_EraseRootFromParent_Done, // Label 710: @29532 GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(29569), // Rule ID 2916 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2916, GIR_EraseRootFromParent_Done, // Label 711: @29569 GIM_Try, /*On fail goto*//*Label 712*/ GIMT_Encode4(29606), // Rule ID 2917 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2917, GIR_EraseRootFromParent_Done, // Label 712: @29606 GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(29643), // Rule ID 2918 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2918, GIR_EraseRootFromParent_Done, // Label 713: @29643 GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(29680), // Rule ID 2919 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8bf16] } QPR:{ *:[v2f64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2919, GIR_EraseRootFromParent_Done, // Label 714: @29680 GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(29717), // Rule ID 2920 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8bf16] } QPR:{ *:[v2i64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2920, GIR_EraseRootFromParent_Done, // Label 715: @29717 GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(29754), // Rule ID 2921 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8bf16] } QPR:{ *:[v4f32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2921, GIR_EraseRootFromParent_Done, // Label 716: @29754 GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(29791), // Rule ID 2922 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8bf16] } QPR:{ *:[v4i32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2922, GIR_EraseRootFromParent_Done, // Label 717: @29791 GIM_Try, /*On fail goto*//*Label 718*/ GIMT_Encode4(29828), // Rule ID 2923 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8bf16] } QPR:{ *:[v16i8] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2923, GIR_EraseRootFromParent_Done, // Label 718: @29828 GIM_Try, /*On fail goto*//*Label 719*/ GIMT_Encode4(29865), // Rule ID 2924 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2924, GIR_EraseRootFromParent_Done, // Label 719: @29865 GIM_Try, /*On fail goto*//*Label 720*/ GIMT_Encode4(29902), // Rule ID 2925 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2925, GIR_EraseRootFromParent_Done, // Label 720: @29902 GIM_Try, /*On fail goto*//*Label 721*/ GIMT_Encode4(29939), // Rule ID 2926 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2926, GIR_EraseRootFromParent_Done, // Label 721: @29939 GIM_Try, /*On fail goto*//*Label 722*/ GIMT_Encode4(29976), // Rule ID 2927 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2927, GIR_EraseRootFromParent_Done, // Label 722: @29976 GIM_Try, /*On fail goto*//*Label 723*/ GIMT_Encode4(30013), // Rule ID 2928 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2928, GIR_EraseRootFromParent_Done, // Label 723: @30013 GIM_Try, /*On fail goto*//*Label 724*/ GIMT_Encode4(30045), // Rule ID 5402 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v8i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5402, GIR_EraseRootFromParent_Done, // Label 724: @30045 GIM_Try, /*On fail goto*//*Label 725*/ GIMT_Encode4(30077), // Rule ID 5403 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v8f16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5403, GIR_EraseRootFromParent_Done, // Label 725: @30077 GIM_Try, /*On fail goto*//*Label 726*/ GIMT_Encode4(30109), // Rule ID 5424 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8f16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5424, GIR_EraseRootFromParent_Done, // Label 726: @30109 GIM_Try, /*On fail goto*//*Label 727*/ GIMT_Encode4(30141), // Rule ID 5425 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8f16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5425, GIR_EraseRootFromParent_Done, // Label 727: @30141 GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(30173), // Rule ID 5426 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8f16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5426, GIR_EraseRootFromParent_Done, // Label 728: @30173 GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(30205), // Rule ID 5427 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8f16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5427, GIR_EraseRootFromParent_Done, // Label 729: @30205 GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(30237), // Rule ID 5428 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8f16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5428, GIR_EraseRootFromParent_Done, // Label 730: @30237 GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(30269), // Rule ID 5429 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5429, GIR_EraseRootFromParent_Done, // Label 731: @30269 GIM_Try, /*On fail goto*//*Label 732*/ GIMT_Encode4(30301), // Rule ID 5430 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5430, GIR_EraseRootFromParent_Done, // Label 732: @30301 GIM_Try, /*On fail goto*//*Label 733*/ GIMT_Encode4(30333), // Rule ID 5431 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5431, GIR_EraseRootFromParent_Done, // Label 733: @30333 GIM_Try, /*On fail goto*//*Label 734*/ GIMT_Encode4(30365), // Rule ID 5432 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5432, GIR_EraseRootFromParent_Done, // Label 734: @30365 GIM_Try, /*On fail goto*//*Label 735*/ GIMT_Encode4(30397), // Rule ID 5433 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5433, GIR_EraseRootFromParent_Done, // Label 735: @30397 GIM_Try, /*On fail goto*//*Label 736*/ GIMT_Encode4(30453), // Rule ID 5460 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5460, GIR_EraseRootFromParent_Done, // Label 736: @30453 GIM_Try, /*On fail goto*//*Label 737*/ GIMT_Encode4(30509), // Rule ID 5461 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5461, GIR_EraseRootFromParent_Done, // Label 737: @30509 GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(30565), // Rule ID 5462 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5462, GIR_EraseRootFromParent_Done, // Label 738: @30565 GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(30621), // Rule ID 5463 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5463, GIR_EraseRootFromParent_Done, // Label 739: @30621 GIM_Try, /*On fail goto*//*Label 740*/ GIMT_Encode4(30677), // Rule ID 5464 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5464, GIR_EraseRootFromParent_Done, // Label 740: @30677 GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(30733), // Rule ID 5465 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5465, GIR_EraseRootFromParent_Done, // Label 741: @30733 GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(30789), // Rule ID 5466 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5466, GIR_EraseRootFromParent_Done, // Label 742: @30789 GIM_Try, /*On fail goto*//*Label 743*/ GIMT_Encode4(30845), // Rule ID 5467 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5467, GIR_EraseRootFromParent_Done, // Label 743: @30845 GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(30901), // Rule ID 5468 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5468, GIR_EraseRootFromParent_Done, // Label 744: @30901 GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(30957), // Rule ID 5469 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5469, GIR_EraseRootFromParent_Done, // Label 745: @30957 GIM_Reject, // Label 488: @30958 GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(30990), // Rule ID 2837 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v16i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2837, GIR_EraseRootFromParent_Done, // Label 746: @30990 GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(31022), // Rule ID 2838 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v16i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2838, GIR_EraseRootFromParent_Done, // Label 747: @31022 GIM_Try, /*On fail goto*//*Label 748*/ GIMT_Encode4(31054), // Rule ID 2839 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v16i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2839, GIR_EraseRootFromParent_Done, // Label 748: @31054 GIM_Try, /*On fail goto*//*Label 749*/ GIMT_Encode4(31086), // Rule ID 2840 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v16i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2840, GIR_EraseRootFromParent_Done, // Label 749: @31086 GIM_Try, /*On fail goto*//*Label 750*/ GIMT_Encode4(31118), // Rule ID 2841 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v16i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2841, GIR_EraseRootFromParent_Done, // Label 750: @31118 GIM_Try, /*On fail goto*//*Label 751*/ GIMT_Encode4(31150), // Rule ID 2842 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8bf16] }:$src) => QPR:{ *:[v16i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2842, GIR_EraseRootFromParent_Done, // Label 751: @31150 GIM_Try, /*On fail goto*//*Label 752*/ GIMT_Encode4(31182), // Rule ID 2843 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v16i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), // GIR_Coverage, 2843, GIR_EraseRootFromParent_Done, // Label 752: @31182 GIM_Try, /*On fail goto*//*Label 753*/ GIMT_Encode4(31219), // Rule ID 2929 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2929, GIR_EraseRootFromParent_Done, // Label 753: @31219 GIM_Try, /*On fail goto*//*Label 754*/ GIMT_Encode4(31256), // Rule ID 2930 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2930, GIR_EraseRootFromParent_Done, // Label 754: @31256 GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(31293), // Rule ID 2931 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2931, GIR_EraseRootFromParent_Done, // Label 755: @31293 GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(31330), // Rule ID 2932 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2932, GIR_EraseRootFromParent_Done, // Label 756: @31330 GIM_Try, /*On fail goto*//*Label 757*/ GIMT_Encode4(31367), // Rule ID 2933 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2933, GIR_EraseRootFromParent_Done, // Label 757: @31367 GIM_Try, /*On fail goto*//*Label 758*/ GIMT_Encode4(31404), // Rule ID 2934 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8bf16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8bf16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2934, GIR_EraseRootFromParent_Done, // Label 758: @31404 GIM_Try, /*On fail goto*//*Label 759*/ GIMT_Encode4(31441), // Rule ID 2935 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2935, GIR_EraseRootFromParent_Done, // Label 759: @31441 GIM_Try, /*On fail goto*//*Label 760*/ GIMT_Encode4(31473), // Rule ID 5434 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v16i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5434, GIR_EraseRootFromParent_Done, // Label 760: @31473 GIM_Try, /*On fail goto*//*Label 761*/ GIMT_Encode4(31505), // Rule ID 5435 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v16i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5435, GIR_EraseRootFromParent_Done, // Label 761: @31505 GIM_Try, /*On fail goto*//*Label 762*/ GIMT_Encode4(31537), // Rule ID 5436 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v16i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5436, GIR_EraseRootFromParent_Done, // Label 762: @31537 GIM_Try, /*On fail goto*//*Label 763*/ GIMT_Encode4(31569), // Rule ID 5437 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v16i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5437, GIR_EraseRootFromParent_Done, // Label 763: @31569 GIM_Try, /*On fail goto*//*Label 764*/ GIMT_Encode4(31601), // Rule ID 5438 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v16i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5438, GIR_EraseRootFromParent_Done, // Label 764: @31601 GIM_Try, /*On fail goto*//*Label 765*/ GIMT_Encode4(31633), // Rule ID 5439 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v16i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), // GIR_Coverage, 5439, GIR_EraseRootFromParent_Done, // Label 765: @31633 GIM_Try, /*On fail goto*//*Label 766*/ GIMT_Encode4(31689), // Rule ID 5470 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5470, GIR_EraseRootFromParent_Done, // Label 766: @31689 GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(31745), // Rule ID 5471 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5471, GIR_EraseRootFromParent_Done, // Label 767: @31745 GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(31801), // Rule ID 5472 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5472, GIR_EraseRootFromParent_Done, // Label 768: @31801 GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(31857), // Rule ID 5473 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5473, GIR_EraseRootFromParent_Done, // Label 769: @31857 GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(31913), // Rule ID 5474 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5474, GIR_EraseRootFromParent_Done, // Label 770: @31913 GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(31969), // Rule ID 5475 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5475, GIR_EraseRootFromParent_Done, // Label 771: @31969 GIM_Reject, // Label 489: @31970 GIM_Reject, // Label 10: @31971 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 777*/ GIMT_Encode4(32262), /*GILLT_s16*//*Label 772*/ GIMT_Encode4(32034), /*GILLT_s32*//*Label 773*/ GIMT_Encode4(32072), /*GILLT_s64*//*Label 774*/ GIMT_Encode4(32110), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*GILLT_v4s32*//*Label 775*/ GIMT_Encode4(32148), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*GILLT_v8s16*//*Label 776*/ GIMT_Encode4(32205), // Label 772: @32034 GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(32071), // Rule ID 682 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), // (ftrunc:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTZH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] GIR_RootToRootCopy, /*OpIdx*/1, // Sm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 682, GIR_EraseRootFromParent_Done, // Label 778: @32071 GIM_Reject, // Label 773: @32072 GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(32109), // Rule ID 683 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), // (ftrunc:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTZS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] GIR_RootToRootCopy, /*OpIdx*/1, // Sm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 683, GIR_EraseRootFromParent_Done, // Label 779: @32109 GIM_Reject, // Label 774: @32110 GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(32147), // Rule ID 684 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (ftrunc:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTZD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] GIR_RootToRootCopy, /*OpIdx*/1, // Dm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 684, GIR_EraseRootFromParent_Done, // Label 780: @32147 GIM_Reject, // Label 775: @32148 GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(32204), // Rule ID 4095 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (ftrunc:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32Z:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32Z), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // val GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4095, GIR_EraseRootFromParent_Done, // Label 781: @32204 GIM_Reject, // Label 776: @32205 GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(32261), // Rule ID 4083 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (ftrunc:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16Z:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16Z), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // val GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4083, GIR_EraseRootFromParent_Done, // Label 782: @32261 GIM_Reject, // Label 777: @32262 GIM_Reject, // Label 11: @32263 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 788*/ GIMT_Encode4(32521), /*GILLT_s16*//*Label 783*/ GIMT_Encode4(32326), /*GILLT_s32*//*Label 784*/ GIMT_Encode4(32353), /*GILLT_s64*//*Label 785*/ GIMT_Encode4(32380), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*GILLT_v4s32*//*Label 786*/ GIMT_Encode4(32407), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*GILLT_v8s16*//*Label 787*/ GIMT_Encode4(32464), // Label 783: @32326 GIM_Try, /*On fail goto*//*Label 789*/ GIMT_Encode4(32352), // Rule ID 691 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), // (fround:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTAH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAH), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 691, GIR_Done, // Label 789: @32352 GIM_Reject, // Label 784: @32353 GIM_Try, /*On fail goto*//*Label 790*/ GIMT_Encode4(32379), // Rule ID 692 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), // (fround:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTAS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAS), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 692, GIR_Done, // Label 790: @32379 GIM_Reject, // Label 785: @32380 GIM_Try, /*On fail goto*//*Label 791*/ GIMT_Encode4(32406), // Rule ID 693 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (fround:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTAD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAD), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 693, GIR_Done, // Label 791: @32406 GIM_Reject, // Label 786: @32407 GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(32463), // Rule ID 4093 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (fround:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32A:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32A), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // val GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4093, GIR_EraseRootFromParent_Done, // Label 792: @32463 GIM_Reject, // Label 787: @32464 GIM_Try, /*On fail goto*//*Label 793*/ GIMT_Encode4(32520), // Rule ID 4081 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), // (fround:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16A:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16A), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] GIR_RootToRootCopy, /*OpIdx*/1, // val GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4081, GIR_EraseRootFromParent_Done, // Label 793: @32520 GIM_Reject, // Label 788: @32521 GIM_Reject, // Label 12: @32522 GIM_Try, /*On fail goto*//*Label 794*/ GIMT_Encode4(32542), // Rule ID 5536 // GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // MIs[0] Operand 0 GIM_CheckIsImm, /*MI*/0, /*Op*/0, GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0, // (atomic_fence (timm:{ *:[i32] }), 0:{ *:[i32] }) => (MEMBARRIER) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::MEMBARRIER), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 5536, GIR_EraseRootFromParent_Done, // Label 794: @32542 GIM_Reject, // Label 13: @32543 GIM_Try, /*On fail goto*//*Label 795*/ GIMT_Encode4(38345), GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, GIM_Try, /*On fail goto*//*Label 796*/ GIMT_Encode4(32599), // Rule ID 1878 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtb16), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 3643:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/2, // Src GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1878, GIR_EraseRootFromParent_Done, // Label 796: @32599 GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(32647), // Rule ID 2115 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtb16), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 3643:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] GIR_RootToRootCopy, /*OpIdx*/2, // Rm GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2115, GIR_EraseRootFromParent_Done, // Label 797: @32647 GIM_Try, /*On fail goto*//*Label 798*/ GIMT_Encode4(32683), // Rule ID 694 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), // (intrinsic_wo_chain:{ *:[f16] } 3529:{ *:[iPTR] }, HPR:{ *:[f16] }:$Sm) => (VRINTNH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTNH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] GIR_RootToRootCopy, /*OpIdx*/2, // Sm GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 694, GIR_EraseRootFromParent_Done, // Label 798: @32683 GIM_Try, /*On fail goto*//*Label 799*/ GIMT_Encode4(32719), // Rule ID 695 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), // (intrinsic_wo_chain:{ *:[f32] } 3529:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VRINTNS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTNS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] GIR_RootToRootCopy, /*OpIdx*/2, // Sm GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 695, GIR_EraseRootFromParent_Done, // Label 799: @32719 GIM_Try, /*On fail goto*//*Label 800*/ GIMT_Encode4(32755), // Rule ID 696 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 3529:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VRINTND:{ *:[f64] } DPR:{ *:[f64] }:$Dm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTND), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] GIR_RootToRootCopy, /*OpIdx*/2, // Dm GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 696, GIR_EraseRootFromParent_Done, // Label 800: @32755 GIM_Try, /*On fail goto*//*Label 801*/ GIMT_Encode4(32800), // Rule ID 710 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtr), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (intrinsic_wo_chain:{ *:[f32] } 3644:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOSIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOSIRD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] GIR_RootToRootCopy, /*OpIdx*/2, // Dm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 710, GIR_EraseRootFromParent_Done, // Label 801: @32800 GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(32845), // Rule ID 711 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtr), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), // (intrinsic_wo_chain:{ *:[f32] } 3644:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOSIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOSIRS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] GIR_RootToRootCopy, /*OpIdx*/2, // Sm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 711, GIR_EraseRootFromParent_Done, // Label 802: @32845 GIM_Try, /*On fail goto*//*Label 803*/ GIMT_Encode4(32890), // Rule ID 712 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtru), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (intrinsic_wo_chain:{ *:[f32] } 3645:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOUIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOUIRD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] GIR_RootToRootCopy, /*OpIdx*/2, // Dm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 712, GIR_EraseRootFromParent_Done, // Label 803: @32890 GIM_Try, /*On fail goto*//*Label 804*/ GIMT_Encode4(32935), // Rule ID 713 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtru), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), // (intrinsic_wo_chain:{ *:[f32] } 3645:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOUIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOUIRS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] GIR_RootToRootCopy, /*OpIdx*/2, // Sm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 713, GIR_EraseRootFromParent_Done, // Label 804: @32935 GIM_Try, /*On fail goto*//*Label 805*/ GIMT_Encode4(32980), // Rule ID 1259 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (intrinsic_wo_chain:{ *:[v4i16] } 3495:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLsv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv8i8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1259, GIR_EraseRootFromParent_Done, // Label 805: @32980 GIM_Try, /*On fail goto*//*Label 806*/ GIMT_Encode4(33025), // Rule ID 1260 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (intrinsic_wo_chain:{ *:[v2i32] } 3495:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLsv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv4i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1260, GIR_EraseRootFromParent_Done, // Label 806: @33025 GIM_Try, /*On fail goto*//*Label 807*/ GIMT_Encode4(33070), // Rule ID 1261 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (intrinsic_wo_chain:{ *:[v1i64] } 3495:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLsv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv2i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1261, GIR_EraseRootFromParent_Done, // Label 807: @33070 GIM_Try, /*On fail goto*//*Label 808*/ GIMT_Encode4(33115), // Rule ID 1262 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 3495:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLsv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv16i8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1262, GIR_EraseRootFromParent_Done, // Label 808: @33115 GIM_Try, /*On fail goto*//*Label 809*/ GIMT_Encode4(33160), // Rule ID 1263 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 3495:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLsv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1263, GIR_EraseRootFromParent_Done, // Label 809: @33160 GIM_Try, /*On fail goto*//*Label 810*/ GIMT_Encode4(33205), // Rule ID 1264 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 3495:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLsv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1264, GIR_EraseRootFromParent_Done, // Label 810: @33205 GIM_Try, /*On fail goto*//*Label 811*/ GIMT_Encode4(33250), // Rule ID 1265 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (intrinsic_wo_chain:{ *:[v4i16] } 3496:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLuv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv8i8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1265, GIR_EraseRootFromParent_Done, // Label 811: @33250 GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(33295), // Rule ID 1266 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (intrinsic_wo_chain:{ *:[v2i32] } 3496:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLuv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv4i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1266, GIR_EraseRootFromParent_Done, // Label 812: @33295 GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(33340), // Rule ID 1267 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (intrinsic_wo_chain:{ *:[v1i64] } 3496:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLuv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv2i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1267, GIR_EraseRootFromParent_Done, // Label 813: @33340 GIM_Try, /*On fail goto*//*Label 814*/ GIMT_Encode4(33385), // Rule ID 1268 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 3496:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLuv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv16i8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1268, GIR_EraseRootFromParent_Done, // Label 814: @33385 GIM_Try, /*On fail goto*//*Label 815*/ GIMT_Encode4(33430), // Rule ID 1269 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 3496:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLuv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv8i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1269, GIR_EraseRootFromParent_Done, // Label 815: @33430 GIM_Try, /*On fail goto*//*Label 816*/ GIMT_Encode4(33475), // Rule ID 1270 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 3496:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLuv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv4i32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1270, GIR_EraseRootFromParent_Done, // Label 816: @33475 GIM_Try, /*On fail goto*//*Label 817*/ GIMT_Encode4(33520), // Rule ID 1299 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (intrinsic_wo_chain:{ *:[v2i32] } 3523:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRECPEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEd), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1299, GIR_EraseRootFromParent_Done, // Label 817: @33520 GIM_Try, /*On fail goto*//*Label 818*/ GIMT_Encode4(33565), // Rule ID 1300 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 3523:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRECPEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEq), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1300, GIR_EraseRootFromParent_Done, // Label 818: @33565 GIM_Try, /*On fail goto*//*Label 819*/ GIMT_Encode4(33610), // Rule ID 1301 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (intrinsic_wo_chain:{ *:[v2f32] } 3523:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRECPEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEfd), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1301, GIR_EraseRootFromParent_Done, // Label 819: @33610 GIM_Try, /*On fail goto*//*Label 820*/ GIMT_Encode4(33655), // Rule ID 1302 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 3523:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRECPEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEfq), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1302, GIR_EraseRootFromParent_Done, // Label 820: @33655 GIM_Try, /*On fail goto*//*Label 821*/ GIMT_Encode4(33700), // Rule ID 1303 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (intrinsic_wo_chain:{ *:[v4f16] } 3523:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRECPEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEhd), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1303, GIR_EraseRootFromParent_Done, // Label 821: @33700 GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(33745), // Rule ID 1304 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (intrinsic_wo_chain:{ *:[v8f16] } 3523:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRECPEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEhq), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1304, GIR_EraseRootFromParent_Done, // Label 822: @33745 GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(33790), // Rule ID 1309 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (intrinsic_wo_chain:{ *:[v2i32] } 3536:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRSQRTEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEd), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1309, GIR_EraseRootFromParent_Done, // Label 823: @33790 GIM_Try, /*On fail goto*//*Label 824*/ GIMT_Encode4(33835), // Rule ID 1310 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 3536:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRSQRTEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEq), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1310, GIR_EraseRootFromParent_Done, // Label 824: @33835 GIM_Try, /*On fail goto*//*Label 825*/ GIMT_Encode4(33880), // Rule ID 1311 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (intrinsic_wo_chain:{ *:[v2f32] } 3536:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRSQRTEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEfd), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1311, GIR_EraseRootFromParent_Done, // Label 825: @33880 GIM_Try, /*On fail goto*//*Label 826*/ GIMT_Encode4(33925), // Rule ID 1312 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 3536:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRSQRTEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEfq), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1312, GIR_EraseRootFromParent_Done, // Label 826: @33925 GIM_Try, /*On fail goto*//*Label 827*/ GIMT_Encode4(33970), // Rule ID 1313 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (intrinsic_wo_chain:{ *:[v4f16] } 3536:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRSQRTEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEhd), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1313, GIR_EraseRootFromParent_Done, // Label 827: @33970 GIM_Try, /*On fail goto*//*Label 828*/ GIMT_Encode4(34015), // Rule ID 1314 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), // (intrinsic_wo_chain:{ *:[v8f16] } 3536:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRSQRTEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEhq), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1314, GIR_EraseRootFromParent_Done, // Label 828: @34015 GIM_Try, /*On fail goto*//*Label 829*/ GIMT_Encode4(34060), // Rule ID 1535 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (intrinsic_wo_chain:{ *:[v8i8] } 3501:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VQABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv8i8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] GIR_RootToRootCopy, /*OpIdx*/2, // Vm GIR_AddImm8, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1535, GIR_EraseRootFromParent_Done, // Label 829: @34060 GIM_Try, /*On fail goto*//*Label 830*/ GIMT_Encode4(34105), // Rule ID 1536 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), // (intrinsic_wo_chain:{ *:[v4i16] } 3501:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VQABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv4i16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]<TRUNCATED>#undef GIMT_Encode2#undef GIMT_Encode4#undef GIMT_Encode8#endif // ifdef GET_GLOBALISEL_IMPL#ifdef GET_GLOBALISEL_PREDICATES_DECL#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL#ifdef GET_GLOBALISEL_PREDICATES_INIT#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT
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