/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM namespace llvm { namespace PPC { enum { … }; } // end namespace PPC } // end namespace llvm #endif // GET_INSTRINFO_ENUM #ifdef GET_INSTRINFO_SCHED_ENUM #undef GET_INSTRINFO_SCHED_ENUM namespace llvm { namespace PPC { namespace Sched { enum { … }; } // end namespace Sched } // end namespace PPC } // end namespace llvm #endif // GET_INSTRINFO_SCHED_ENUM #if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) namespace llvm { struct PPCInstrTable { MCInstrDesc Insts[2874]; static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo"); MCOperandInfo OperandInfo[1287]; static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps"); MCPhysReg ImplicitOps[222]; }; } // end namespace llvm #endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) #ifdef GET_INSTRINFO_MC_DESC #undef GET_INSTRINFO_MC_DESC namespace llvm { static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0); static constexpr unsigned PPCImpOpBase = sizeof PPCInstrTable::OperandInfo / (sizeof(MCPhysReg)); extern const PPCInstrTable PPCDescs = { { { 2873, 4, 0, 4, 102, 2, 1, PPCImpOpBase + 109, 1283, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2873 = gBCat { 2872, 4, 0, 4, 102, 2, 2, PPCImpOpBase + 218, 1283, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2872 = gBCLat { 2871, 3, 0, 4, 445, 3, 2, PPCImpOpBase + 213, 1280, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2871 = gBCLRL { 2870, 3, 0, 4, 445, 3, 1, PPCImpOpBase + 112, 1280, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2870 = gBCLR { 2869, 4, 0, 4, 102, 2, 2, PPCImpOpBase + 218, 1276, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2869 = gBCLAat { 2868, 3, 0, 4, 102, 2, 2, PPCImpOpBase + 218, 1273, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2868 = gBCLA { 2867, 3, 0, 4, 102, 2, 2, PPCImpOpBase + 218, 1270, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2867 = gBCL { 2866, 3, 0, 4, 445, 3, 2, PPCImpOpBase + 213, 1280, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2866 = gBCCTRL { 2865, 3, 0, 4, 445, 3, 1, PPCImpOpBase + 112, 1280, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2865 = gBCCTR { 2864, 4, 0, 4, 102, 2, 1, PPCImpOpBase + 109, 1276, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2864 = gBCAat { 2863, 3, 0, 4, 102, 2, 1, PPCImpOpBase + 109, 1273, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2863 = gBCA { 2862, 3, 0, 4, 102, 2, 1, PPCImpOpBase + 109, 1270, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2862 = gBC { 2861, 3, 1, 4, 580, 0, 0, PPCImpOpBase + 0, 1258, 0, 0x0ULL }, // Inst #2861 = XXSPLTWs { 2860, 3, 1, 4, 580, 0, 0, PPCImpOpBase + 0, 1267, 0, 0x0ULL }, // Inst #2860 = XXSPLTW { 2859, 2, 1, 8, 591, 0, 0, PPCImpOpBase + 0, 630, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x80ULL }, // Inst #2859 = XXSPLTIW { 2858, 2, 1, 8, 591, 0, 0, PPCImpOpBase + 0, 630, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x80ULL }, // Inst #2858 = XXSPLTIDP { 2857, 2, 1, 4, 576, 0, 0, PPCImpOpBase + 0, 630, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2857 = XXSPLTIB { 2856, 4, 1, 8, 592, 0, 0, PPCImpOpBase + 0, 1263, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x80ULL }, // Inst #2856 = XXSPLTI32DX { 2855, 3, 1, 4, 165, 0, 0, PPCImpOpBase + 0, 1258, 0, 0x0ULL }, // Inst #2855 = XXSLDWIs { 2854, 4, 1, 4, 165, 0, 0, PPCImpOpBase + 0, 1254, 0, 0x0ULL }, // Inst #2854 = XXSLDWI { 2853, 1, 1, 4, 23, 0, 0, PPCImpOpBase + 0, 1262, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #2853 = XXSETACCZW { 2852, 1, 1, 4, 563, 0, 0, PPCImpOpBase + 0, 1261, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #2852 = XXSETACCZ { 2851, 4, 1, 4, 270, 0, 0, PPCImpOpBase + 0, 1224, 0, 0x0ULL }, // Inst #2851 = XXSEL { 2850, 5, 1, 8, 594, 0, 0, PPCImpOpBase + 0, 1228, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #2850 = XXPERMX { 2849, 4, 1, 4, 325, 0, 0, PPCImpOpBase + 0, 1250, 0, 0x0ULL }, // Inst #2849 = XXPERMR { 2848, 3, 1, 4, 165, 0, 0, PPCImpOpBase + 0, 1258, 0, 0x0ULL }, // Inst #2848 = XXPERMDIs { 2847, 4, 1, 4, 165, 0, 0, PPCImpOpBase + 0, 1254, 0, 0x0ULL }, // Inst #2847 = XXPERMDI { 2846, 4, 1, 4, 325, 0, 0, PPCImpOpBase + 0, 1250, 0, 0x0ULL }, // Inst #2846 = XXPERM { 2845, 2, 1, 4, 23, 0, 0, PPCImpOpBase + 0, 1248, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2845 = XXMTACCW { 2844, 2, 1, 4, 570, 0, 0, PPCImpOpBase + 0, 1246, 0, 0x0ULL }, // Inst #2844 = XXMTACC { 2843, 3, 1, 4, 165, 0, 0, PPCImpOpBase + 0, 1181, 0, 0x0ULL }, // Inst #2843 = XXMRGLW { 2842, 3, 1, 4, 165, 0, 0, PPCImpOpBase + 0, 1181, 0, 0x0ULL }, // Inst #2842 = XXMRGHW { 2841, 2, 1, 4, 23, 0, 0, PPCImpOpBase + 0, 1248, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2841 = XXMFACCW { 2840, 2, 1, 4, 571, 0, 0, PPCImpOpBase + 0, 1246, 0, 0x0ULL }, // Inst #2840 = XXMFACC { 2839, 1, 1, 4, 167, 0, 0, PPCImpOpBase + 0, 1243, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #2839 = XXLXORz { 2838, 1, 1, 4, 167, 0, 0, PPCImpOpBase + 0, 1245, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #2838 = XXLXORspz { 2837, 1, 1, 4, 167, 0, 0, PPCImpOpBase + 0, 1244, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #2837 = XXLXORdpz { 2836, 3, 1, 4, 167, 0, 0, PPCImpOpBase + 0, 1181, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2836 = XXLXOR { 2835, 3, 1, 4, 167, 0, 0, PPCImpOpBase + 0, 1122, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2835 = XXLORf { 2834, 3, 1, 4, 260, 0, 0, PPCImpOpBase + 0, 1181, 0, 0x0ULL }, // Inst #2834 = XXLORC { 2833, 3, 1, 4, 167, 0, 0, PPCImpOpBase + 0, 1181, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2833 = XXLOR { 2832, 3, 1, 4, 167, 0, 0, PPCImpOpBase + 0, 1181, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2832 = XXLNOR { 2831, 3, 1, 4, 260, 0, 0, PPCImpOpBase + 0, 1181, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2831 = XXLNAND { 2830, 1, 1, 4, 528, 0, 0, PPCImpOpBase + 0, 1243, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #2830 = XXLEQVOnes { 2829, 3, 1, 4, 260, 0, 0, PPCImpOpBase + 0, 1181, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2829 = XXLEQV { 2828, 3, 1, 4, 167, 0, 0, PPCImpOpBase + 0, 1181, 0, 0x0ULL }, // Inst #2828 = XXLANDC { 2827, 3, 1, 4, 167, 0, 0, PPCImpOpBase + 0, 1181, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2827 = XXLAND { 2826, 4, 1, 4, 588, 0, 0, PPCImpOpBase + 0, 1239, 0, 0x0ULL }, // Inst #2826 = XXINSERTW { 2825, 3, 1, 4, 581, 0, 0, PPCImpOpBase + 0, 1236, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2825 = XXGENPCVWM { 2824, 3, 1, 4, 581, 0, 0, PPCImpOpBase + 0, 1236, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2824 = XXGENPCVHM { 2823, 3, 1, 4, 581, 0, 0, PPCImpOpBase + 0, 1236, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2823 = XXGENPCVDM { 2822, 3, 1, 4, 464, 0, 0, PPCImpOpBase + 0, 1236, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2822 = XXGENPCVBM { 2821, 3, 1, 4, 584, 0, 0, PPCImpOpBase + 0, 1233, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2821 = XXEXTRACTUW { 2820, 5, 1, 8, 593, 0, 0, PPCImpOpBase + 0, 1228, 0, 0x80ULL }, // Inst #2820 = XXEVAL { 2819, 2, 1, 4, 584, 0, 0, PPCImpOpBase + 0, 1179, 0, 0x0ULL }, // Inst #2819 = XXBRW { 2818, 2, 1, 4, 584, 0, 0, PPCImpOpBase + 0, 1179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2818 = XXBRQ { 2817, 2, 1, 4, 584, 0, 0, PPCImpOpBase + 0, 1179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2817 = XXBRH { 2816, 2, 1, 4, 584, 0, 0, PPCImpOpBase + 0, 1179, 0, 0x0ULL }, // Inst #2816 = XXBRD { 2815, 4, 1, 8, 593, 0, 0, PPCImpOpBase + 0, 1224, 0, 0x80ULL }, // Inst #2815 = XXBLENDVW { 2814, 4, 1, 8, 593, 0, 0, PPCImpOpBase + 0, 1224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #2814 = XXBLENDVH { 2813, 4, 1, 8, 593, 0, 0, PPCImpOpBase + 0, 1224, 0, 0x80ULL }, // Inst #2813 = XXBLENDVD { 2812, 4, 1, 8, 593, 0, 0, PPCImpOpBase + 0, 1224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #2812 = XXBLENDVB { 2811, 2, 1, 4, 520, 0, 0, PPCImpOpBase + 0, 1179, 0, 0x0ULL }, // Inst #2811 = XVXSIGSP { 2810, 2, 1, 4, 520, 0, 0, PPCImpOpBase + 0, 1179, 0, 0x0ULL }, // Inst #2810 = XVXSIGDP { 2809, 2, 1, 4, 518, 0, 0, PPCImpOpBase + 0, 1179, 0, 0x0ULL }, // Inst #2809 = XVXEXPSP { 2808, 2, 1, 4, 518, 0, 0, PPCImpOpBase + 0, 1179, 0, 0x0ULL }, // Inst #2808 = XVXEXPDP { 2807, 3, 1, 4, 481, 0, 0, PPCImpOpBase + 0, 1221, 0, 0x0ULL }, // Inst #2807 = XVTSTDCSP { 2806, 3, 1, 4, 481, 0, 0, PPCImpOpBase + 0, 1221, 0, 0x0ULL }, // Inst #2806 = XVTSTDCDP { 2805, 2, 1, 4, 480, 1, 0, PPCImpOpBase + 134, 1219, 0, 0x0ULL }, // Inst #2805 = XVTSQRTSP { 2804, 2, 1, 4, 479, 1, 0, PPCImpOpBase + 134, 1219, 0, 0x0ULL }, // Inst #2804 = XVTSQRTDP { 2803, 2, 1, 4, 471, 0, 0, PPCImpOpBase + 0, 1219, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2803 = XVTLSBB { 2802, 3, 1, 4, 168, 1, 0, PPCImpOpBase + 134, 1216, 0, 0x0ULL }, // Inst #2802 = XVTDIVSP { 2801, 3, 1, 4, 163, 1, 0, PPCImpOpBase + 134, 1216, 0, 0x0ULL }, // Inst #2801 = XVTDIVDP { 2800, 3, 1, 4, 440, 1, 0, PPCImpOpBase + 134, 1181, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2800 = XVSUBSP { 2799, 3, 1, 4, 439, 1, 0, PPCImpOpBase + 134, 1181, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2799 = XVSUBDP { 2798, 2, 1, 4, 178, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2798 = XVSQRTSP { 2797, 2, 1, 4, 180, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2797 = XVSQRTDP { 2796, 2, 1, 4, 430, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2796 = XVRSQRTESP { 2795, 2, 1, 4, 433, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2795 = XVRSQRTEDP { 2794, 2, 1, 4, 433, 0, 0, PPCImpOpBase + 0, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2794 = XVRSPIZ { 2793, 2, 1, 4, 433, 0, 0, PPCImpOpBase + 0, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2793 = XVRSPIP { 2792, 2, 1, 4, 433, 0, 0, PPCImpOpBase + 0, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2792 = XVRSPIM { 2791, 2, 1, 4, 433, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2791 = XVRSPIC { 2790, 2, 1, 4, 433, 0, 0, PPCImpOpBase + 0, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2790 = XVRSPI { 2789, 2, 1, 4, 430, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2789 = XVRESP { 2788, 2, 1, 4, 433, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2788 = XVREDP { 2787, 2, 1, 4, 433, 0, 0, PPCImpOpBase + 0, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2787 = XVRDPIZ { 2786, 2, 1, 4, 433, 0, 0, PPCImpOpBase + 0, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2786 = XVRDPIP { 2785, 2, 1, 4, 433, 0, 0, PPCImpOpBase + 0, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2785 = XVRDPIM { 2784, 2, 1, 4, 433, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2784 = XVRDPIC { 2783, 2, 1, 4, 433, 0, 0, PPCImpOpBase + 0, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2783 = XVRDPI { 2782, 4, 1, 4, 189, 1, 0, PPCImpOpBase + 134, 1212, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2782 = XVNMSUBMSP { 2781, 4, 1, 4, 192, 1, 0, PPCImpOpBase + 134, 1212, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2781 = XVNMSUBMDP { 2780, 4, 1, 4, 189, 1, 0, PPCImpOpBase + 134, 1212, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2780 = XVNMSUBASP { 2779, 4, 1, 4, 192, 1, 0, PPCImpOpBase + 134, 1212, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2779 = XVNMSUBADP { 2778, 4, 1, 4, 189, 1, 0, PPCImpOpBase + 134, 1212, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2778 = XVNMADDMSP { 2777, 4, 1, 4, 192, 1, 0, PPCImpOpBase + 134, 1212, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2777 = XVNMADDMDP { 2776, 4, 1, 4, 189, 1, 0, PPCImpOpBase + 134, 1212, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2776 = XVNMADDASP { 2775, 4, 1, 4, 192, 1, 0, PPCImpOpBase + 134, 1212, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2775 = XVNMADDADP { 2774, 2, 1, 4, 266, 1, 0, PPCImpOpBase + 134, 1179, 0, 0x0ULL }, // Inst #2774 = XVNEGSP { 2773, 2, 1, 4, 519, 1, 0, PPCImpOpBase + 134, 1179, 0, 0x0ULL }, // Inst #2773 = XVNEGDP { 2772, 2, 1, 4, 266, 1, 0, PPCImpOpBase + 134, 1179, 0, 0x0ULL }, // Inst #2772 = XVNABSSP { 2771, 2, 1, 4, 519, 1, 0, PPCImpOpBase + 134, 1179, 0, 0x0ULL }, // Inst #2771 = XVNABSDP { 2770, 3, 1, 4, 440, 1, 0, PPCImpOpBase + 134, 1181, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2770 = XVMULSP { 2769, 3, 1, 4, 439, 1, 0, PPCImpOpBase + 134, 1181, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2769 = XVMULDP { 2768, 4, 1, 4, 189, 1, 0, PPCImpOpBase + 134, 1212, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2768 = XVMSUBMSP { 2767, 4, 1, 4, 192, 1, 0, PPCImpOpBase + 134, 1212, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2767 = XVMSUBMDP { 2766, 4, 1, 4, 189, 1, 0, PPCImpOpBase + 134, 1212, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2766 = XVMSUBASP { 2765, 4, 1, 4, 192, 1, 0, PPCImpOpBase + 134, 1212, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2765 = XVMSUBADP { 2764, 3, 1, 4, 161, 1, 0, PPCImpOpBase + 134, 1181, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2764 = XVMINSP { 2763, 3, 1, 4, 161, 1, 0, PPCImpOpBase + 134, 1181, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2763 = XVMINDP { 2762, 3, 1, 4, 161, 1, 0, PPCImpOpBase + 134, 1181, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2762 = XVMAXSP { 2761, 3, 1, 4, 161, 1, 0, PPCImpOpBase + 134, 1181, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2761 = XVMAXDP { 2760, 4, 1, 4, 189, 1, 0, PPCImpOpBase + 134, 1212, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2760 = XVMADDMSP { 2759, 4, 1, 4, 192, 1, 0, PPCImpOpBase + 134, 1212, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2759 = XVMADDMDP { 2758, 4, 1, 4, 189, 1, 0, PPCImpOpBase + 134, 1212, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2758 = XVMADDASP { 2757, 4, 1, 4, 192, 1, 0, PPCImpOpBase + 134, 1212, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2757 = XVMADDADP { 2756, 3, 1, 4, 527, 0, 0, PPCImpOpBase + 0, 1181, 0, 0x0ULL }, // Inst #2756 = XVIEXPSP { 2755, 3, 1, 4, 527, 0, 0, PPCImpOpBase + 0, 1181, 0, 0x0ULL }, // Inst #2755 = XVIEXPDP { 2754, 4, 1, 4, 23, 0, 0, PPCImpOpBase + 0, 1194, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2754 = XVI8GER4WSPP { 2753, 4, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1194, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2753 = XVI8GER4WPP { 2752, 3, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1191, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2752 = XVI8GER4W { 2751, 4, 1, 4, 566, 0, 0, PPCImpOpBase + 0, 1187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2751 = XVI8GER4SPP { 2750, 4, 1, 4, 565, 0, 0, PPCImpOpBase + 0, 1187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2750 = XVI8GER4PP { 2749, 3, 1, 4, 564, 0, 0, PPCImpOpBase + 0, 1184, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2749 = XVI8GER4 { 2748, 4, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1194, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2748 = XVI4GER8WPP { 2747, 3, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1191, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2747 = XVI4GER8W { 2746, 4, 1, 4, 565, 0, 0, PPCImpOpBase + 0, 1187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2746 = XVI4GER8PP { 2745, 3, 1, 4, 564, 0, 0, PPCImpOpBase + 0, 1184, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2745 = XVI4GER8 { 2744, 4, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1194, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2744 = XVI16GER2WPP { 2743, 3, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1191, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2743 = XVI16GER2W { 2742, 4, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1194, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2742 = XVI16GER2SWPP { 2741, 3, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1191, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2741 = XVI16GER2SW { 2740, 4, 1, 4, 565, 0, 0, PPCImpOpBase + 0, 1187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2740 = XVI16GER2SPP { 2739, 3, 1, 4, 564, 0, 0, PPCImpOpBase + 0, 1184, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2739 = XVI16GER2S { 2738, 4, 1, 4, 565, 0, 0, PPCImpOpBase + 0, 1187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2738 = XVI16GER2PP { 2737, 3, 1, 4, 564, 0, 0, PPCImpOpBase + 0, 1184, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2737 = XVI16GER2 { 2736, 4, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1208, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2736 = XVF64GERWPP { 2735, 4, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1208, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2735 = XVF64GERWPN { 2734, 4, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1208, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2734 = XVF64GERWNP { 2733, 4, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1208, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2733 = XVF64GERWNN { 2732, 3, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1205, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2732 = XVF64GERW { 2731, 4, 1, 4, 565, 0, 0, PPCImpOpBase + 0, 1201, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2731 = XVF64GERPP { 2730, 4, 1, 4, 565, 0, 0, PPCImpOpBase + 0, 1201, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2730 = XVF64GERPN { 2729, 4, 1, 4, 565, 0, 0, PPCImpOpBase + 0, 1201, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2729 = XVF64GERNP { 2728, 4, 1, 4, 565, 0, 0, PPCImpOpBase + 0, 1201, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2728 = XVF64GERNN { 2727, 3, 1, 4, 564, 0, 0, PPCImpOpBase + 0, 1198, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2727 = XVF64GER { 2726, 4, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1194, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2726 = XVF32GERWPP { 2725, 4, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1194, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2725 = XVF32GERWPN { 2724, 4, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1194, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2724 = XVF32GERWNP { 2723, 4, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1194, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2723 = XVF32GERWNN { 2722, 3, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1191, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2722 = XVF32GERW { 2721, 4, 1, 4, 565, 0, 0, PPCImpOpBase + 0, 1187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2721 = XVF32GERPP { 2720, 4, 1, 4, 565, 0, 0, PPCImpOpBase + 0, 1187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2720 = XVF32GERPN { 2719, 4, 1, 4, 565, 0, 0, PPCImpOpBase + 0, 1187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2719 = XVF32GERNP { 2718, 4, 1, 4, 565, 0, 0, PPCImpOpBase + 0, 1187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2718 = XVF32GERNN { 2717, 3, 1, 4, 564, 0, 0, PPCImpOpBase + 0, 1184, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2717 = XVF32GER { 2716, 4, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1194, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2716 = XVF16GER2WPP { 2715, 4, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1194, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2715 = XVF16GER2WPN { 2714, 4, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1194, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2714 = XVF16GER2WNP { 2713, 4, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1194, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2713 = XVF16GER2WNN { 2712, 3, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1191, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2712 = XVF16GER2W { 2711, 4, 1, 4, 565, 0, 0, PPCImpOpBase + 0, 1187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2711 = XVF16GER2PP { 2710, 4, 1, 4, 565, 0, 0, PPCImpOpBase + 0, 1187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2710 = XVF16GER2PN { 2709, 4, 1, 4, 565, 0, 0, PPCImpOpBase + 0, 1187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2709 = XVF16GER2NP { 2708, 4, 1, 4, 565, 0, 0, PPCImpOpBase + 0, 1187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2708 = XVF16GER2NN { 2707, 3, 1, 4, 564, 0, 0, PPCImpOpBase + 0, 1184, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2707 = XVF16GER2 { 2706, 3, 1, 4, 177, 1, 0, PPCImpOpBase + 134, 1181, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2706 = XVDIVSP { 2705, 3, 1, 4, 179, 1, 0, PPCImpOpBase + 134, 1181, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2705 = XVDIVDP { 2704, 2, 1, 4, 430, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2704 = XVCVUXWSP { 2703, 2, 1, 4, 433, 1, 0, PPCImpOpBase + 134, 1179, 0, 0x0ULL }, // Inst #2703 = XVCVUXWDP { 2702, 2, 1, 4, 430, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2702 = XVCVUXDSP { 2701, 2, 1, 4, 433, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2701 = XVCVUXDDP { 2700, 2, 1, 4, 430, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2700 = XVCVSXWSP { 2699, 2, 1, 4, 433, 1, 0, PPCImpOpBase + 134, 1179, 0, 0x0ULL }, // Inst #2699 = XVCVSXWDP { 2698, 2, 1, 4, 430, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2698 = XVCVSXDSP { 2697, 2, 1, 4, 433, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2697 = XVCVSXDDP { 2696, 2, 1, 4, 433, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2696 = XVCVSPUXWS { 2695, 2, 1, 4, 433, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2695 = XVCVSPUXDS { 2694, 2, 1, 4, 433, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2694 = XVCVSPSXWS { 2693, 2, 1, 4, 433, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2693 = XVCVSPSXDS { 2692, 2, 1, 4, 429, 0, 0, PPCImpOpBase + 0, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2692 = XVCVSPHP { 2691, 2, 1, 4, 193, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2691 = XVCVSPDP { 2690, 2, 1, 4, 434, 0, 0, PPCImpOpBase + 0, 1179, 0, 0x0ULL }, // Inst #2690 = XVCVSPBF16 { 2689, 2, 1, 4, 310, 0, 0, PPCImpOpBase + 0, 1179, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2689 = XVCVHPSP { 2688, 2, 1, 4, 433, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2688 = XVCVDPUXWS { 2687, 2, 1, 4, 433, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2687 = XVCVDPUXDS { 2686, 2, 1, 4, 433, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2686 = XVCVDPSXWS { 2685, 2, 1, 4, 433, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2685 = XVCVDPSXDS { 2684, 2, 1, 4, 430, 1, 0, PPCImpOpBase + 134, 1179, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2684 = XVCVDPSP { 2683, 2, 1, 4, 583, 0, 0, PPCImpOpBase + 0, 1179, 0, 0x0ULL }, // Inst #2683 = XVCVBF16SPN { 2682, 3, 1, 4, 267, 1, 0, PPCImpOpBase + 134, 1181, 0, 0x0ULL }, // Inst #2682 = XVCPSGNSP { 2681, 3, 1, 4, 265, 1, 0, PPCImpOpBase + 134, 1181, 0, 0x0ULL }, // Inst #2681 = XVCPSGNDP { 2680, 3, 1, 4, 486, 1, 1, PPCImpOpBase + 211, 1181, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2680 = XVCMPGTSP_rec { 2679, 3, 1, 4, 486, 1, 0, PPCImpOpBase + 134, 1181, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2679 = XVCMPGTSP { 2678, 3, 1, 4, 162, 1, 1, PPCImpOpBase + 211, 1181, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2678 = XVCMPGTDP_rec { 2677, 3, 1, 4, 162, 1, 0, PPCImpOpBase + 134, 1181, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2677 = XVCMPGTDP { 2676, 3, 1, 4, 486, 1, 1, PPCImpOpBase + 211, 1181, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2676 = XVCMPGESP_rec { 2675, 3, 1, 4, 486, 1, 0, PPCImpOpBase + 134, 1181, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2675 = XVCMPGESP { 2674, 3, 1, 4, 162, 1, 1, PPCImpOpBase + 211, 1181, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2674 = XVCMPGEDP_rec { 2673, 3, 1, 4, 162, 1, 0, PPCImpOpBase + 134, 1181, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2673 = XVCMPGEDP { 2672, 3, 1, 4, 486, 1, 1, PPCImpOpBase + 211, 1181, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2672 = XVCMPEQSP_rec { 2671, 3, 1, 4, 486, 1, 0, PPCImpOpBase + 134, 1181, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2671 = XVCMPEQSP { 2670, 3, 1, 4, 162, 1, 1, PPCImpOpBase + 211, 1181, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2670 = XVCMPEQDP_rec { 2669, 3, 1, 4, 162, 1, 0, PPCImpOpBase + 134, 1181, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2669 = XVCMPEQDP { 2668, 4, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1194, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2668 = XVBF16GER2WPP { 2667, 4, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1194, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2667 = XVBF16GER2WPN { 2666, 4, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1194, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2666 = XVBF16GER2WNP { 2665, 4, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1194, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2665 = XVBF16GER2WNN { 2664, 3, 1, 4, 5, 0, 0, PPCImpOpBase + 0, 1191, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2664 = XVBF16GER2W { 2663, 4, 1, 4, 565, 0, 0, PPCImpOpBase + 0, 1187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2663 = XVBF16GER2PP { 2662, 4, 1, 4, 565, 0, 0, PPCImpOpBase + 0, 1187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2662 = XVBF16GER2PN { 2661, 4, 1, 4, 565, 0, 0, PPCImpOpBase + 0, 1187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2661 = XVBF16GER2NP { 2660, 4, 1, 4, 565, 0, 0, PPCImpOpBase + 0, 1187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2660 = XVBF16GER2NN { 2659, 3, 1, 4, 564, 0, 0, PPCImpOpBase + 0, 1184, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2659 = XVBF16GER2 { 2658, 3, 1, 4, 440, 1, 0, PPCImpOpBase + 134, 1181, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2658 = XVADDSP { 2657, 3, 1, 4, 439, 1, 0, PPCImpOpBase + 134, 1181, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2657 = XVADDDP { 2656, 2, 1, 4, 266, 1, 0, PPCImpOpBase + 134, 1179, 0, 0x0ULL }, // Inst #2656 = XVABSSP { 2655, 2, 1, 4, 519, 1, 0, PPCImpOpBase + 134, 1179, 0, 0x0ULL }, // Inst #2655 = XVABSDP { 2654, 2, 1, 4, 463, 0, 0, PPCImpOpBase + 0, 307, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2654 = XSXSIGQP { 2653, 2, 1, 4, 277, 0, 0, PPCImpOpBase + 0, 672, 0, 0x0ULL }, // Inst #2653 = XSXSIGDP { 2652, 2, 1, 4, 518, 0, 0, PPCImpOpBase + 0, 307, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2652 = XSXEXPQP { 2651, 2, 1, 4, 293, 0, 0, PPCImpOpBase + 0, 672, 0, 0x0ULL }, // Inst #2651 = XSXEXPDP { 2650, 3, 1, 4, 275, 0, 0, PPCImpOpBase + 0, 1176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2650 = XSTSTDCSP { 2649, 3, 1, 4, 463, 0, 0, PPCImpOpBase + 0, 1173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2649 = XSTSTDCQP { 2648, 3, 1, 4, 275, 0, 0, PPCImpOpBase + 0, 1170, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2648 = XSTSTDCDP { 2647, 2, 1, 4, 478, 1, 0, PPCImpOpBase + 134, 1168, 0, 0x0ULL }, // Inst #2647 = XSTSQRTDP { 2646, 3, 1, 4, 160, 1, 0, PPCImpOpBase + 134, 1131, 0, 0x0ULL }, // Inst #2646 = XSTDIVDP { 2645, 3, 1, 4, 187, 0, 0, PPCImpOpBase + 0, 1125, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2645 = XSSUBSP { 2644, 3, 1, 4, 327, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2644 = XSSUBQPO { 2643, 3, 1, 4, 327, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2643 = XSSUBQP { 2642, 3, 1, 4, 187, 1, 0, PPCImpOpBase + 134, 1122, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2642 = XSSUBDP { 2641, 2, 1, 4, 173, 0, 0, PPCImpOpBase + 0, 1138, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2641 = XSSQRTSP { 2640, 2, 1, 4, 332, 0, 0, PPCImpOpBase + 0, 307, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2640 = XSSQRTQPO { 2639, 2, 1, 4, 332, 0, 0, PPCImpOpBase + 0, 307, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2639 = XSSQRTQP { 2638, 2, 1, 4, 175, 1, 0, PPCImpOpBase + 134, 1120, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2638 = XSSQRTDP { 2637, 2, 1, 4, 188, 0, 0, PPCImpOpBase + 0, 1138, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2637 = XSRSQRTESP { 2636, 2, 1, 4, 432, 1, 0, PPCImpOpBase + 134, 1120, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2636 = XSRSQRTEDP { 2635, 2, 1, 4, 188, 0, 0, PPCImpOpBase + 0, 1144, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2635 = XSRSP { 2634, 4, 1, 4, 451, 0, 0, PPCImpOpBase + 0, 1164, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2634 = XSRQPXP { 2633, 4, 1, 4, 451, 0, 0, PPCImpOpBase + 0, 1164, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2633 = XSRQPIX { 2632, 4, 1, 4, 451, 0, 0, PPCImpOpBase + 0, 1164, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2632 = XSRQPI { 2631, 2, 1, 4, 188, 0, 0, PPCImpOpBase + 0, 1138, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2631 = XSRESP { 2630, 2, 1, 4, 432, 1, 0, PPCImpOpBase + 134, 1120, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2630 = XSREDP { 2629, 2, 1, 4, 432, 0, 0, PPCImpOpBase + 0, 1120, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2629 = XSRDPIZ { 2628, 2, 1, 4, 432, 0, 0, PPCImpOpBase + 0, 1120, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2628 = XSRDPIP { 2627, 2, 1, 4, 432, 0, 0, PPCImpOpBase + 0, 1120, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2627 = XSRDPIM { 2626, 2, 1, 4, 432, 1, 0, PPCImpOpBase + 134, 1120, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2626 = XSRDPIC { 2625, 2, 1, 4, 432, 0, 0, PPCImpOpBase + 0, 1120, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2625 = XSRDPI { 2624, 4, 1, 4, 329, 0, 0, PPCImpOpBase + 0, 1160, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2624 = XSNMSUBQPO { 2623, 4, 1, 4, 329, 0, 0, PPCImpOpBase + 0, 1160, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2623 = XSNMSUBQP { 2622, 4, 1, 4, 318, 0, 0, PPCImpOpBase + 0, 1156, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2622 = XSNMSUBMSP { 2621, 4, 1, 4, 318, 1, 0, PPCImpOpBase + 134, 1152, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2621 = XSNMSUBMDP { 2620, 4, 1, 4, 318, 0, 0, PPCImpOpBase + 0, 1156, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2620 = XSNMSUBASP { 2619, 4, 1, 4, 318, 1, 0, PPCImpOpBase + 134, 1152, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2619 = XSNMSUBADP { 2618, 4, 1, 4, 329, 0, 0, PPCImpOpBase + 0, 1160, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2618 = XSNMADDQPO { 2617, 4, 1, 4, 329, 0, 0, PPCImpOpBase + 0, 1160, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2617 = XSNMADDQP { 2616, 4, 1, 4, 318, 0, 0, PPCImpOpBase + 0, 1156, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2616 = XSNMADDMSP { 2615, 4, 1, 4, 318, 1, 0, PPCImpOpBase + 134, 1152, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2615 = XSNMADDMDP { 2614, 4, 1, 4, 318, 0, 0, PPCImpOpBase + 0, 1156, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2614 = XSNMADDASP { 2613, 4, 1, 4, 318, 1, 0, PPCImpOpBase + 134, 1152, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2613 = XSNMADDADP { 2612, 2, 1, 4, 518, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2612 = XSNEGQP { 2611, 2, 1, 4, 517, 1, 0, PPCImpOpBase + 134, 1120, 0, 0x0ULL }, // Inst #2611 = XSNEGDP { 2610, 2, 1, 4, 518, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2610 = XSNABSQP { 2609, 2, 1, 4, 517, 1, 0, PPCImpOpBase + 134, 1138, 0, 0x0ULL }, // Inst #2609 = XSNABSDPs { 2608, 2, 1, 4, 517, 1, 0, PPCImpOpBase + 134, 1120, 0, 0x0ULL }, // Inst #2608 = XSNABSDP { 2607, 3, 1, 4, 438, 0, 0, PPCImpOpBase + 0, 1125, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2607 = XSMULSP { 2606, 3, 1, 4, 454, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2606 = XSMULQPO { 2605, 3, 1, 4, 454, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2605 = XSMULQP { 2604, 3, 1, 4, 438, 1, 0, PPCImpOpBase + 134, 1122, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2604 = XSMULDP { 2603, 4, 1, 4, 329, 0, 0, PPCImpOpBase + 0, 1160, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2603 = XSMSUBQPO { 2602, 4, 1, 4, 329, 0, 0, PPCImpOpBase + 0, 1160, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2602 = XSMSUBQP { 2601, 4, 1, 4, 318, 0, 0, PPCImpOpBase + 0, 1156, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2601 = XSMSUBMSP { 2600, 4, 1, 4, 318, 1, 0, PPCImpOpBase + 134, 1152, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2600 = XSMSUBMDP { 2599, 4, 1, 4, 318, 0, 0, PPCImpOpBase + 0, 1156, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2599 = XSMSUBASP { 2598, 4, 1, 4, 318, 1, 0, PPCImpOpBase + 134, 1152, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2598 = XSMSUBADP { 2597, 3, 1, 4, 491, 0, 0, PPCImpOpBase + 0, 1128, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2597 = XSMINJDP { 2596, 3, 1, 4, 159, 1, 0, PPCImpOpBase + 134, 1122, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2596 = XSMINDP { 2595, 3, 1, 4, 467, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2595 = XSMINCQP { 2594, 3, 1, 4, 491, 0, 0, PPCImpOpBase + 0, 1122, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2594 = XSMINCDP { 2593, 3, 1, 4, 491, 0, 0, PPCImpOpBase + 0, 1128, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2593 = XSMAXJDP { 2592, 3, 1, 4, 159, 1, 0, PPCImpOpBase + 134, 1122, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2592 = XSMAXDP { 2591, 3, 1, 4, 467, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2591 = XSMAXCQP { 2590, 3, 1, 4, 491, 0, 0, PPCImpOpBase + 0, 1122, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2590 = XSMAXCDP { 2589, 4, 1, 4, 329, 0, 0, PPCImpOpBase + 0, 1160, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2589 = XSMADDQPO { 2588, 4, 1, 4, 329, 0, 0, PPCImpOpBase + 0, 1160, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2588 = XSMADDQP { 2587, 4, 1, 4, 318, 0, 0, PPCImpOpBase + 0, 1156, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2587 = XSMADDMSP { 2586, 4, 1, 4, 318, 1, 0, PPCImpOpBase + 134, 1152, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2586 = XSMADDMDP { 2585, 4, 1, 4, 318, 0, 0, PPCImpOpBase + 0, 1156, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2585 = XSMADDASP { 2584, 4, 1, 4, 318, 1, 0, PPCImpOpBase + 134, 1152, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2584 = XSMADDADP { 2583, 3, 1, 4, 527, 0, 0, PPCImpOpBase + 0, 1149, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2583 = XSIEXPQP { 2582, 3, 1, 4, 303, 0, 0, PPCImpOpBase + 0, 1146, 0, 0x0ULL }, // Inst #2582 = XSIEXPDP { 2581, 3, 1, 4, 183, 0, 0, PPCImpOpBase + 0, 1125, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2581 = XSDIVSP { 2580, 3, 1, 4, 331, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2580 = XSDIVQPO { 2579, 3, 1, 4, 331, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2579 = XSDIVQP { 2578, 3, 1, 4, 172, 1, 0, PPCImpOpBase + 134, 1122, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2578 = XSDIVDP { 2577, 2, 1, 4, 188, 0, 0, PPCImpOpBase + 0, 1144, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2577 = XSCVUXDSP { 2576, 2, 1, 4, 432, 1, 0, PPCImpOpBase + 134, 1120, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2576 = XSCVUXDDP { 2575, 2, 1, 4, 452, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2575 = XSCVUQQP { 2574, 2, 1, 4, 451, 0, 0, PPCImpOpBase + 0, 1134, 0, 0x0ULL }, // Inst #2574 = XSCVUDQP { 2573, 2, 1, 4, 188, 0, 0, PPCImpOpBase + 0, 1144, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2573 = XSCVSXDSP { 2572, 2, 1, 4, 432, 1, 0, PPCImpOpBase + 134, 1120, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2572 = XSCVSXDDP { 2571, 2, 1, 4, 452, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2571 = XSCVSQQP { 2570, 2, 1, 4, 282, 0, 0, PPCImpOpBase + 0, 1142, 0, 0x0ULL }, // Inst #2570 = XSCVSPDPN { 2569, 2, 1, 4, 432, 1, 0, PPCImpOpBase + 134, 1120, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2569 = XSCVSPDP { 2568, 2, 1, 4, 451, 0, 0, PPCImpOpBase + 0, 1134, 0, 0x0ULL }, // Inst #2568 = XSCVSDQP { 2567, 2, 1, 4, 451, 0, 0, PPCImpOpBase + 0, 307, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2567 = XSCVQPUWZ { 2566, 2, 1, 4, 452, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2566 = XSCVQPUQZ { 2565, 2, 1, 4, 451, 0, 0, PPCImpOpBase + 0, 307, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2565 = XSCVQPUDZ { 2564, 2, 1, 4, 451, 0, 0, PPCImpOpBase + 0, 307, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2564 = XSCVQPSWZ { 2563, 2, 1, 4, 452, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2563 = XSCVQPSQZ { 2562, 2, 1, 4, 451, 0, 0, PPCImpOpBase + 0, 307, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2562 = XSCVQPSDZ { 2561, 2, 1, 4, 451, 0, 0, PPCImpOpBase + 0, 1140, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2561 = XSCVQPDPO { 2560, 2, 1, 4, 451, 0, 0, PPCImpOpBase + 0, 1140, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2560 = XSCVQPDP { 2559, 2, 1, 4, 321, 0, 0, PPCImpOpBase + 0, 1120, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2559 = XSCVHPDP { 2558, 2, 1, 4, 432, 1, 0, PPCImpOpBase + 134, 1138, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2558 = XSCVDPUXWSs { 2557, 2, 1, 4, 432, 1, 0, PPCImpOpBase + 134, 1120, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2557 = XSCVDPUXWS { 2556, 2, 1, 4, 432, 1, 0, PPCImpOpBase + 134, 1138, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2556 = XSCVDPUXDSs { 2555, 2, 1, 4, 432, 1, 0, PPCImpOpBase + 134, 1120, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2555 = XSCVDPUXDS { 2554, 2, 1, 4, 432, 1, 0, PPCImpOpBase + 134, 1138, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2554 = XSCVDPSXWSs { 2553, 2, 1, 4, 432, 1, 0, PPCImpOpBase + 134, 1120, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2553 = XSCVDPSXWS { 2552, 2, 1, 4, 432, 1, 0, PPCImpOpBase + 134, 1138, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2552 = XSCVDPSXDSs { 2551, 2, 1, 4, 432, 1, 0, PPCImpOpBase + 134, 1120, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2551 = XSCVDPSXDS { 2550, 2, 1, 4, 188, 0, 0, PPCImpOpBase + 0, 1136, 0, 0x0ULL }, // Inst #2550 = XSCVDPSPN { 2549, 2, 1, 4, 432, 1, 0, PPCImpOpBase + 134, 1120, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2549 = XSCVDPSP { 2548, 2, 1, 4, 451, 0, 0, PPCImpOpBase + 0, 1134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2548 = XSCVDPQP { 2547, 2, 1, 4, 431, 0, 0, PPCImpOpBase + 0, 1120, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2547 = XSCVDPHP { 2546, 3, 1, 4, 527, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2546 = XSCPSGNQP { 2545, 3, 1, 4, 292, 1, 0, PPCImpOpBase + 134, 1122, 0, 0x0ULL }, // Inst #2545 = XSCPSGNDP { 2544, 3, 1, 4, 326, 0, 0, PPCImpOpBase + 0, 1070, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2544 = XSCMPUQP { 2543, 3, 1, 4, 160, 1, 0, PPCImpOpBase + 134, 1131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2543 = XSCMPUDP { 2542, 3, 1, 4, 326, 0, 0, PPCImpOpBase + 0, 1070, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2542 = XSCMPOQP { 2541, 3, 1, 4, 160, 1, 0, PPCImpOpBase + 134, 1131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2541 = XSCMPODP { 2540, 3, 1, 4, 467, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2540 = XSCMPGTQP { 2539, 3, 1, 4, 278, 0, 0, PPCImpOpBase + 0, 1128, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2539 = XSCMPGTDP { 2538, 3, 1, 4, 467, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2538 = XSCMPGEQP { 2537, 3, 1, 4, 278, 0, 0, PPCImpOpBase + 0, 1128, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2537 = XSCMPGEDP { 2536, 3, 1, 4, 326, 0, 0, PPCImpOpBase + 0, 1070, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2536 = XSCMPEXPQP { 2535, 3, 1, 4, 278, 0, 0, PPCImpOpBase + 0, 1131, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2535 = XSCMPEXPDP { 2534, 3, 1, 4, 467, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2534 = XSCMPEQQP { 2533, 3, 1, 4, 278, 0, 0, PPCImpOpBase + 0, 1128, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2533 = XSCMPEQDP { 2532, 3, 1, 4, 187, 0, 0, PPCImpOpBase + 0, 1125, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2532 = XSADDSP { 2531, 3, 1, 4, 327, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2531 = XSADDQPO { 2530, 3, 1, 4, 327, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2530 = XSADDQP { 2529, 3, 1, 4, 187, 1, 0, PPCImpOpBase + 134, 1122, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2529 = XSADDDP { 2528, 2, 1, 4, 518, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2528 = XSABSQP { 2527, 2, 1, 4, 517, 1, 0, PPCImpOpBase + 134, 1120, 0, 0x0ULL }, // Inst #2527 = XSABSDP { 2526, 3, 1, 4, 198, 0, 1, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #2526 = XOR_rec { 2525, 3, 1, 4, 508, 0, 0, PPCImpOpBase + 0, 181, 0, 0x8ULL }, // Inst #2525 = XORIS8 { 2524, 3, 1, 4, 508, 0, 0, PPCImpOpBase + 0, 184, 0, 0x8ULL }, // Inst #2524 = XORIS { 2523, 3, 1, 4, 508, 0, 0, PPCImpOpBase + 0, 181, 0, 0x8ULL }, // Inst #2523 = XORI8 { 2522, 3, 1, 4, 508, 0, 0, PPCImpOpBase + 0, 184, 0, 0x8ULL }, // Inst #2522 = XORI { 2521, 3, 1, 4, 198, 0, 1, PPCImpOpBase + 0, 228, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #2521 = XOR8_rec { 2520, 3, 1, 4, 198, 0, 0, PPCImpOpBase + 0, 228, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #2520 = XOR8 { 2519, 3, 1, 4, 198, 0, 0, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #2519 = XOR { 2518, 1, 0, 4, 420, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2518 = WRTEEI { 2517, 1, 0, 4, 420, 0, 0, PPCImpOpBase + 0, 171, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2517 = WRTEE { 2516, 2, 0, 4, 497, 0, 0, PPCImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2516 = WAITP10 { 2515, 1, 0, 4, 296, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2515 = WAIT { 2514, 1, 1, 4, 575, 0, 0, PPCImpOpBase + 0, 671, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL }, // Inst #2514 = V_SETALLONESH { 2513, 1, 1, 4, 575, 0, 0, PPCImpOpBase + 0, 671, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL }, // Inst #2513 = V_SETALLONESB { 2512, 1, 1, 4, 575, 0, 0, PPCImpOpBase + 0, 671, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL }, // Inst #2512 = V_SETALLONES { 2511, 1, 1, 4, 527, 0, 0, PPCImpOpBase + 0, 671, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL }, // Inst #2511 = V_SET0H { 2510, 1, 1, 4, 527, 0, 0, PPCImpOpBase + 0, 671, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL }, // Inst #2510 = V_SET0B { 2509, 1, 1, 4, 527, 0, 0, PPCImpOpBase + 0, 671, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL }, // Inst #2509 = V_SET0 { 2508, 3, 1, 4, 261, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2508 = VXOR { 2507, 2, 1, 4, 579, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2507 = VUPKLSW { 2506, 2, 1, 4, 582, 0, 0, PPCImpOpBase + 0, 307, 0, 0x28ULL }, // Inst #2506 = VUPKLSH { 2505, 2, 1, 4, 582, 0, 0, PPCImpOpBase + 0, 307, 0, 0x28ULL }, // Inst #2505 = VUPKLSB { 2504, 2, 1, 4, 582, 0, 0, PPCImpOpBase + 0, 307, 0, 0x28ULL }, // Inst #2504 = VUPKLPX { 2503, 2, 1, 4, 579, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2503 = VUPKHSW { 2502, 2, 1, 4, 582, 0, 0, PPCImpOpBase + 0, 307, 0, 0x28ULL }, // Inst #2502 = VUPKHSH { 2501, 2, 1, 4, 582, 0, 0, PPCImpOpBase + 0, 307, 0, 0x28ULL }, // Inst #2501 = VUPKHSB { 2500, 2, 1, 4, 582, 0, 0, PPCImpOpBase + 0, 307, 0, 0x28ULL }, // Inst #2500 = VUPKHPX { 2499, 3, 1, 4, 590, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2499 = VSUMSWS { 2498, 3, 1, 4, 622, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2498 = VSUM4UBS { 2497, 3, 1, 4, 622, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2497 = VSUM4SHS { 2496, 3, 1, 4, 622, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2496 = VSUM4SBS { 2495, 3, 1, 4, 622, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2495 = VSUM2SWS { 2494, 3, 1, 4, 485, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2494 = VSUBUWS { 2493, 3, 1, 4, 167, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2493 = VSUBUWM { 2492, 3, 1, 4, 238, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2492 = VSUBUQM { 2491, 3, 1, 4, 485, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2491 = VSUBUHS { 2490, 3, 1, 4, 167, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2490 = VSUBUHM { 2489, 3, 1, 4, 260, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2489 = VSUBUDM { 2488, 3, 1, 4, 485, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2488 = VSUBUBS { 2487, 3, 1, 4, 167, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2487 = VSUBUBM { 2486, 3, 1, 4, 485, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2486 = VSUBSWS { 2485, 3, 1, 4, 485, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2485 = VSUBSHS { 2484, 3, 1, 4, 485, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2484 = VSUBSBS { 2483, 3, 1, 4, 191, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2483 = VSUBFP { 2482, 4, 1, 4, 237, 0, 0, PPCImpOpBase + 0, 1058, 0, 0x0ULL }, // Inst #2482 = VSUBEUQM { 2481, 4, 1, 4, 237, 0, 0, PPCImpOpBase + 0, 1058, 0, 0x0ULL }, // Inst #2481 = VSUBECUQ { 2480, 3, 1, 4, 485, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2480 = VSUBCUW { 2479, 3, 1, 4, 466, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2479 = VSUBCUQ { 2478, 2, 1, 4, 539, 0, 1, PPCImpOpBase + 78, 307, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2478 = VSTRIHR_rec { 2477, 2, 1, 4, 581, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2477 = VSTRIHR { 2476, 2, 1, 4, 539, 0, 1, PPCImpOpBase + 78, 307, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2476 = VSTRIHL_rec { 2475, 2, 1, 4, 581, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2475 = VSTRIHL { 2474, 2, 1, 4, 539, 0, 1, PPCImpOpBase + 78, 307, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2474 = VSTRIBR_rec { 2473, 2, 1, 4, 581, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2473 = VSTRIBR { 2472, 2, 1, 4, 539, 0, 1, PPCImpOpBase + 78, 307, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2472 = VSTRIBL_rec { 2471, 2, 1, 4, 581, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2471 = VSTRIBL { 2470, 3, 1, 4, 261, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2470 = VSRW { 2469, 3, 1, 4, 588, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2469 = VSRV { 2468, 3, 1, 4, 494, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2468 = VSRQ { 2467, 3, 1, 4, 230, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2467 = VSRO { 2466, 3, 1, 4, 261, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2466 = VSRH { 2465, 4, 1, 4, 586, 0, 0, PPCImpOpBase + 0, 297, 0, 0x0ULL }, // Inst #2465 = VSRDBI { 2464, 3, 1, 4, 260, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2464 = VSRD { 2463, 3, 1, 4, 261, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2463 = VSRB { 2462, 3, 1, 4, 261, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2462 = VSRAW { 2461, 3, 1, 4, 494, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2461 = VSRAQ { 2460, 3, 1, 4, 261, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2460 = VSRAH { 2459, 3, 1, 4, 260, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2459 = VSRAD { 2458, 3, 1, 4, 261, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2458 = VSRAB { 2457, 3, 1, 4, 230, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2457 = VSR { 2456, 3, 1, 4, 580, 0, 0, PPCImpOpBase + 0, 1062, 0, 0x28ULL }, // Inst #2456 = VSPLTW { 2455, 2, 1, 4, 574, 0, 0, PPCImpOpBase + 0, 701, 0, 0x28ULL }, // Inst #2455 = VSPLTISW { 2454, 2, 1, 4, 574, 0, 0, PPCImpOpBase + 0, 701, 0, 0x28ULL }, // Inst #2454 = VSPLTISH { 2453, 2, 1, 4, 574, 0, 0, PPCImpOpBase + 0, 701, 0, 0x28ULL }, // Inst #2453 = VSPLTISB { 2452, 3, 1, 4, 580, 0, 0, PPCImpOpBase + 0, 1117, 0, 0x28ULL }, // Inst #2452 = VSPLTHs { 2451, 3, 1, 4, 580, 0, 0, PPCImpOpBase + 0, 1062, 0, 0x28ULL }, // Inst #2451 = VSPLTH { 2450, 3, 1, 4, 580, 0, 0, PPCImpOpBase + 0, 1117, 0, 0x28ULL }, // Inst #2450 = VSPLTBs { 2449, 3, 1, 4, 580, 0, 0, PPCImpOpBase + 0, 1062, 0, 0x28ULL }, // Inst #2449 = VSPLTB { 2448, 3, 1, 4, 261, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2448 = VSLW { 2447, 3, 1, 4, 588, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2447 = VSLV { 2446, 3, 1, 4, 494, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2446 = VSLQ { 2445, 3, 1, 4, 230, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2445 = VSLO { 2444, 3, 1, 4, 261, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2444 = VSLH { 2443, 4, 1, 4, 230, 0, 0, PPCImpOpBase + 0, 297, 0, 0x28ULL }, // Inst #2443 = VSLDOI { 2442, 4, 1, 4, 586, 0, 0, PPCImpOpBase + 0, 297, 0, 0x0ULL }, // Inst #2442 = VSLDBI { 2441, 3, 1, 4, 260, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2441 = VSLD { 2440, 3, 1, 4, 261, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2440 = VSLB { 2439, 3, 1, 4, 230, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2439 = VSL { 2438, 4, 1, 4, 477, 0, 0, PPCImpOpBase + 0, 1113, 0, 0x0ULL }, // Inst #2438 = VSHASIGMAW { 2437, 4, 1, 4, 477, 0, 0, PPCImpOpBase + 0, 1113, 0, 0x0ULL }, // Inst #2437 = VSHASIGMAD { 2436, 4, 1, 4, 269, 0, 0, PPCImpOpBase + 0, 1058, 0, 0x28ULL }, // Inst #2436 = VSEL { 2435, 2, 1, 4, 448, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2435 = VSBOX { 2434, 2, 1, 4, 430, 0, 0, PPCImpOpBase + 0, 307, 0, 0x28ULL }, // Inst #2434 = VRSQRTEFP { 2433, 3, 1, 4, 527, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2433 = VRLWNM { 2432, 4, 1, 4, 263, 0, 0, PPCImpOpBase + 0, 1109, 0, 0x0ULL }, // Inst #2432 = VRLWMI { 2431, 3, 1, 4, 261, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2431 = VRLW { 2430, 3, 1, 4, 494, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2430 = VRLQNM { 2429, 4, 1, 4, 495, 0, 0, PPCImpOpBase + 0, 1109, 0, 0x0ULL }, // Inst #2429 = VRLQMI { 2428, 3, 1, 4, 494, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2428 = VRLQ { 2427, 3, 1, 4, 261, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2427 = VRLH { 2426, 3, 1, 4, 527, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2426 = VRLDNM { 2425, 4, 1, 4, 263, 0, 0, PPCImpOpBase + 0, 1109, 0, 0x0ULL }, // Inst #2425 = VRLDMI { 2424, 3, 1, 4, 264, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2424 = VRLD { 2423, 3, 1, 4, 261, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2423 = VRLB { 2422, 2, 1, 4, 430, 0, 0, PPCImpOpBase + 0, 307, 0, 0x28ULL }, // Inst #2422 = VRFIZ { 2421, 2, 1, 4, 430, 0, 0, PPCImpOpBase + 0, 307, 0, 0x28ULL }, // Inst #2421 = VRFIP { 2420, 2, 1, 4, 430, 0, 0, PPCImpOpBase + 0, 307, 0, 0x28ULL }, // Inst #2420 = VRFIN { 2419, 2, 1, 4, 430, 0, 0, PPCImpOpBase + 0, 307, 0, 0x28ULL }, // Inst #2419 = VRFIM { 2418, 2, 1, 4, 430, 0, 0, PPCImpOpBase + 0, 307, 0, 0x28ULL }, // Inst #2418 = VREFP { 2417, 2, 1, 4, 475, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2417 = VPRTYBW { 2416, 2, 1, 4, 578, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2416 = VPRTYBQ { 2415, 2, 1, 4, 475, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2415 = VPRTYBD { 2414, 2, 1, 4, 232, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2414 = VPOPCNTW { 2413, 2, 1, 4, 476, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2413 = VPOPCNTH { 2412, 2, 1, 4, 309, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2412 = VPOPCNTD { 2411, 2, 1, 4, 476, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2411 = VPOPCNTB { 2410, 3, 1, 4, 182, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2410 = VPMSUMW { 2409, 3, 1, 4, 182, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2409 = VPMSUMH { 2408, 3, 1, 4, 182, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2408 = VPMSUMD { 2407, 3, 1, 4, 182, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2407 = VPMSUMB { 2406, 3, 1, 4, 587, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2406 = VPKUWUS { 2405, 3, 1, 4, 587, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2405 = VPKUWUM { 2404, 3, 1, 4, 587, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2404 = VPKUHUS { 2403, 3, 1, 4, 587, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2403 = VPKUHUM { 2402, 3, 1, 4, 585, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2402 = VPKUDUS { 2401, 3, 1, 4, 585, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2401 = VPKUDUM { 2400, 3, 1, 4, 587, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2400 = VPKSWUS { 2399, 3, 1, 4, 587, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2399 = VPKSWSS { 2398, 3, 1, 4, 587, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2398 = VPKSHUS { 2397, 3, 1, 4, 587, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2397 = VPKSHSS { 2396, 3, 1, 4, 585, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2396 = VPKSDUS { 2395, 3, 1, 4, 585, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2395 = VPKSDSS { 2394, 3, 1, 4, 587, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2394 = VPKPX { 2393, 3, 1, 4, 450, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2393 = VPEXTD { 2392, 4, 1, 4, 229, 0, 0, PPCImpOpBase + 0, 1058, 0, 0x0ULL }, // Inst #2392 = VPERMXOR { 2391, 4, 1, 4, 323, 0, 0, PPCImpOpBase + 0, 1058, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2391 = VPERMR { 2390, 4, 1, 4, 164, 0, 0, PPCImpOpBase + 0, 1058, 0, 0x28ULL }, // Inst #2390 = VPERM { 2389, 3, 1, 4, 450, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2389 = VPDEPD { 2388, 3, 1, 4, 260, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2388 = VORC { 2387, 3, 1, 4, 261, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2387 = VOR { 2386, 3, 1, 4, 261, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2386 = VNOR { 2385, 4, 1, 4, 441, 0, 0, PPCImpOpBase + 0, 1058, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2385 = VNMSUBFP { 2384, 2, 1, 4, 515, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2384 = VNEGW { 2383, 2, 1, 4, 515, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2383 = VNEGD { 2382, 3, 1, 4, 182, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2382 = VNCIPHERLAST { 2381, 3, 1, 4, 182, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2381 = VNCIPHER { 2380, 3, 1, 4, 260, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2380 = VNAND { 2379, 3, 1, 4, 241, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2379 = VMULUWM { 2378, 3, 1, 4, 240, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2378 = VMULOUW { 2377, 3, 1, 4, 622, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2377 = VMULOUH { 2376, 3, 1, 4, 623, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2376 = VMULOUD { 2375, 3, 1, 4, 622, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2375 = VMULOUB { 2374, 3, 1, 4, 240, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2374 = VMULOSW { 2373, 3, 1, 4, 622, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2373 = VMULOSH { 2372, 3, 1, 4, 623, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2372 = VMULOSD { 2371, 3, 1, 4, 622, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2371 = VMULOSB { 2370, 3, 1, 4, 572, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2370 = VMULLD { 2369, 3, 1, 4, 623, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2369 = VMULHUW { 2368, 3, 1, 4, 572, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2368 = VMULHUD { 2367, 3, 1, 4, 623, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2367 = VMULHSW { 2366, 3, 1, 4, 572, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2366 = VMULHSD { 2365, 3, 1, 4, 240, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2365 = VMULEUW { 2364, 3, 1, 4, 622, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2364 = VMULEUH { 2363, 3, 1, 4, 623, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2363 = VMULEUD { 2362, 3, 1, 4, 622, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2362 = VMULEUB { 2361, 3, 1, 4, 240, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2361 = VMULESW { 2360, 3, 1, 4, 622, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2360 = VMULESH { 2359, 3, 1, 4, 623, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2359 = VMULESD { 2358, 3, 1, 4, 622, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2358 = VMULESB { 2357, 2, 1, 4, 463, 0, 0, PPCImpOpBase + 0, 307, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2357 = VMUL10UQ { 2356, 3, 1, 4, 465, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2356 = VMUL10EUQ { 2355, 3, 1, 4, 465, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2355 = VMUL10ECUQ { 2354, 2, 1, 4, 463, 0, 0, PPCImpOpBase + 0, 307, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2354 = VMUL10CUQ { 2353, 4, 1, 4, 239, 0, 0, PPCImpOpBase + 0, 1058, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2353 = VMSUMUHS { 2352, 4, 1, 4, 239, 0, 0, PPCImpOpBase + 0, 1058, 0, 0x28ULL }, // Inst #2352 = VMSUMUHM { 2351, 4, 1, 4, 166, 0, 0, PPCImpOpBase + 0, 1058, 0, 0x0ULL }, // Inst #2351 = VMSUMUDM { 2350, 4, 1, 4, 239, 0, 0, PPCImpOpBase + 0, 1058, 0, 0x28ULL }, // Inst #2350 = VMSUMUBM { 2349, 4, 1, 4, 239, 0, 0, PPCImpOpBase + 0, 1058, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2349 = VMSUMSHS { 2348, 4, 1, 4, 239, 0, 0, PPCImpOpBase + 0, 1058, 0, 0x28ULL }, // Inst #2348 = VMSUMSHM { 2347, 4, 1, 4, 239, 0, 0, PPCImpOpBase + 0, 1058, 0, 0x28ULL }, // Inst #2347 = VMSUMMBM { 2346, 4, 1, 4, 624, 0, 0, PPCImpOpBase + 0, 1058, 0, 0x0ULL }, // Inst #2346 = VMSUMCUD { 2345, 3, 1, 4, 268, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2345 = VMRGOW { 2344, 3, 1, 4, 230, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2344 = VMRGLW { 2343, 3, 1, 4, 230, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2343 = VMRGLH { 2342, 3, 1, 4, 230, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2342 = VMRGLB { 2341, 3, 1, 4, 230, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2341 = VMRGHW { 2340, 3, 1, 4, 230, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2340 = VMRGHH { 2339, 3, 1, 4, 230, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2339 = VMRGHB { 2338, 3, 1, 4, 268, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2338 = VMRGEW { 2337, 3, 1, 4, 460, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2337 = VMODUW { 2336, 3, 1, 4, 456, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2336 = VMODUQ { 2335, 3, 1, 4, 458, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2335 = VMODUD { 2334, 3, 1, 4, 460, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2334 = VMODSW { 2333, 3, 1, 4, 456, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2333 = VMODSQ { 2332, 3, 1, 4, 458, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2332 = VMODSD { 2331, 4, 1, 4, 239, 0, 0, PPCImpOpBase + 0, 1058, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2331 = VMLADDUHM { 2330, 3, 1, 4, 231, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2330 = VMINUW { 2329, 3, 1, 4, 231, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2329 = VMINUH { 2328, 3, 1, 4, 233, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2328 = VMINUD { 2327, 3, 1, 4, 231, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2327 = VMINUB { 2326, 3, 1, 4, 231, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2326 = VMINSW { 2325, 3, 1, 4, 231, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2325 = VMINSH { 2324, 3, 1, 4, 233, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2324 = VMINSD { 2323, 3, 1, 4, 231, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2323 = VMINSB { 2322, 3, 1, 4, 485, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2322 = VMINFP { 2321, 4, 1, 4, 239, 0, 0, PPCImpOpBase + 0, 1058, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2321 = VMHRADDSHS { 2320, 4, 1, 4, 239, 0, 0, PPCImpOpBase + 0, 1058, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2320 = VMHADDSHS { 2319, 3, 1, 4, 231, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2319 = VMAXUW { 2318, 3, 1, 4, 231, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2318 = VMAXUH { 2317, 3, 1, 4, 233, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2317 = VMAXUD { 2316, 3, 1, 4, 231, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2316 = VMAXUB { 2315, 3, 1, 4, 231, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2315 = VMAXSW { 2314, 3, 1, 4, 231, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2314 = VMAXSH { 2313, 3, 1, 4, 233, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2313 = VMAXSD { 2312, 3, 1, 4, 231, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2312 = VMAXSB { 2311, 3, 1, 4, 485, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2311 = VMAXFP { 2310, 4, 1, 4, 441, 0, 0, PPCImpOpBase + 0, 1058, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2310 = VMADDFP { 2309, 2, 1, 4, 430, 0, 0, PPCImpOpBase + 0, 307, 0, 0x28ULL }, // Inst #2309 = VLOGEFP { 2308, 4, 1, 4, 589, 0, 0, PPCImpOpBase + 0, 1089, 0, 0x0ULL }, // Inst #2308 = VINSWVRX { 2307, 4, 1, 4, 589, 0, 0, PPCImpOpBase + 0, 1089, 0, 0x0ULL }, // Inst #2307 = VINSWVLX { 2306, 4, 1, 4, 589, 0, 0, PPCImpOpBase + 0, 1085, 0, 0x0ULL }, // Inst #2306 = VINSWRX { 2305, 4, 1, 4, 589, 0, 0, PPCImpOpBase + 0, 1085, 0, 0x0ULL }, // Inst #2305 = VINSWLX { 2304, 4, 1, 4, 586, 0, 0, PPCImpOpBase + 0, 1105, 0, 0x0ULL }, // Inst #2304 = VINSW { 2303, 4, 1, 4, 589, 0, 0, PPCImpOpBase + 0, 1089, 0, 0x0ULL }, // Inst #2303 = VINSHVRX { 2302, 4, 1, 4, 589, 0, 0, PPCImpOpBase + 0, 1089, 0, 0x0ULL }, // Inst #2302 = VINSHVLX { 2301, 4, 1, 4, 589, 0, 0, PPCImpOpBase + 0, 1085, 0, 0x0ULL }, // Inst #2301 = VINSHRX { 2300, 4, 1, 4, 589, 0, 0, PPCImpOpBase + 0, 1085, 0, 0x0ULL }, // Inst #2300 = VINSHLX { 2299, 3, 1, 4, 578, 0, 0, PPCImpOpBase + 0, 1062, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2299 = VINSERTW { 2298, 4, 1, 4, 324, 0, 0, PPCImpOpBase + 0, 1101, 0, 0x0ULL }, // Inst #2298 = VINSERTH { 2297, 3, 1, 4, 578, 0, 0, PPCImpOpBase + 0, 1062, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2297 = VINSERTD { 2296, 4, 1, 4, 324, 0, 0, PPCImpOpBase + 0, 1101, 0, 0x0ULL }, // Inst #2296 = VINSERTB { 2295, 4, 1, 4, 589, 0, 0, PPCImpOpBase + 0, 1097, 0, 0x0ULL }, // Inst #2295 = VINSDRX { 2294, 4, 1, 4, 589, 0, 0, PPCImpOpBase + 0, 1097, 0, 0x0ULL }, // Inst #2294 = VINSDLX { 2293, 4, 1, 4, 586, 0, 0, PPCImpOpBase + 0, 1093, 0, 0x0ULL }, // Inst #2293 = VINSD { 2292, 4, 1, 4, 589, 0, 0, PPCImpOpBase + 0, 1089, 0, 0x0ULL }, // Inst #2292 = VINSBVRX { 2291, 4, 1, 4, 589, 0, 0, PPCImpOpBase + 0, 1089, 0, 0x0ULL }, // Inst #2291 = VINSBVLX { 2290, 4, 1, 4, 589, 0, 0, PPCImpOpBase + 0, 1085, 0, 0x0ULL }, // Inst #2290 = VINSBRX { 2289, 4, 1, 4, 589, 0, 0, PPCImpOpBase + 0, 1085, 0, 0x0ULL }, // Inst #2289 = VINSBLX { 2288, 3, 1, 4, 447, 0, 0, PPCImpOpBase + 0, 1073, 0, 0x0ULL }, // Inst #2288 = VGNB { 2287, 2, 1, 4, 579, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2287 = VGBBD { 2286, 3, 1, 4, 324, 0, 0, PPCImpOpBase + 0, 1082, 0, 0x200ULL }, // Inst #2286 = VEXTUWRX { 2285, 3, 1, 4, 324, 0, 0, PPCImpOpBase + 0, 1082, 0, 0x200ULL }, // Inst #2285 = VEXTUWLX { 2284, 3, 1, 4, 324, 0, 0, PPCImpOpBase + 0, 1082, 0, 0x200ULL }, // Inst #2284 = VEXTUHRX { 2283, 3, 1, 4, 324, 0, 0, PPCImpOpBase + 0, 1082, 0, 0x200ULL }, // Inst #2283 = VEXTUHLX { 2282, 3, 1, 4, 324, 0, 0, PPCImpOpBase + 0, 1082, 0, 0x200ULL }, // Inst #2282 = VEXTUBRX { 2281, 3, 1, 4, 324, 0, 0, PPCImpOpBase + 0, 1082, 0, 0x200ULL }, // Inst #2281 = VEXTUBLX { 2280, 2, 1, 4, 515, 0, 0, PPCImpOpBase + 0, 1080, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2280 = VEXTSW2Ds { 2279, 2, 1, 4, 515, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2279 = VEXTSW2D { 2278, 2, 1, 4, 515, 0, 0, PPCImpOpBase + 0, 1080, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2278 = VEXTSH2Ws { 2277, 2, 1, 4, 515, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2277 = VEXTSH2W { 2276, 2, 1, 4, 515, 0, 0, PPCImpOpBase + 0, 1080, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2276 = VEXTSH2Ds { 2275, 2, 1, 4, 515, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2275 = VEXTSH2D { 2274, 2, 1, 4, 516, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2274 = VEXTSD2Q { 2273, 2, 1, 4, 515, 0, 0, PPCImpOpBase + 0, 1080, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2273 = VEXTSB2Ws { 2272, 2, 1, 4, 515, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2272 = VEXTSB2W { 2271, 2, 1, 4, 515, 0, 0, PPCImpOpBase + 0, 1080, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2271 = VEXTSB2Ds { 2270, 2, 1, 4, 515, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2270 = VEXTSB2D { 2269, 2, 1, 4, 471, 0, 0, PPCImpOpBase + 0, 1068, 0, 0x200ULL }, // Inst #2269 = VEXTRACTWM { 2268, 3, 1, 4, 578, 0, 0, PPCImpOpBase + 0, 1062, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2268 = VEXTRACTUW { 2267, 3, 1, 4, 578, 0, 0, PPCImpOpBase + 0, 1062, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2267 = VEXTRACTUH { 2266, 3, 1, 4, 578, 0, 0, PPCImpOpBase + 0, 1062, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2266 = VEXTRACTUB { 2265, 2, 1, 4, 471, 0, 0, PPCImpOpBase + 0, 1068, 0, 0x0ULL }, // Inst #2265 = VEXTRACTQM { 2264, 2, 1, 4, 471, 0, 0, PPCImpOpBase + 0, 1068, 0, 0x200ULL }, // Inst #2264 = VEXTRACTHM { 2263, 2, 1, 4, 471, 0, 0, PPCImpOpBase + 0, 1068, 0, 0x200ULL }, // Inst #2263 = VEXTRACTDM { 2262, 3, 1, 4, 578, 0, 0, PPCImpOpBase + 0, 1062, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2262 = VEXTRACTD { 2261, 2, 1, 4, 471, 0, 0, PPCImpOpBase + 0, 1068, 0, 0x200ULL }, // Inst #2261 = VEXTRACTBM { 2260, 4, 1, 4, 589, 0, 0, PPCImpOpBase + 0, 1076, 0, 0x0ULL }, // Inst #2260 = VEXTDUWVRX { 2259, 4, 1, 4, 589, 0, 0, PPCImpOpBase + 0, 1076, 0, 0x0ULL }, // Inst #2259 = VEXTDUWVLX { 2258, 4, 1, 4, 589, 0, 0, PPCImpOpBase + 0, 1076, 0, 0x0ULL }, // Inst #2258 = VEXTDUHVRX { 2257, 4, 1, 4, 589, 0, 0, PPCImpOpBase + 0, 1076, 0, 0x0ULL }, // Inst #2257 = VEXTDUHVLX { 2256, 4, 1, 4, 589, 0, 0, PPCImpOpBase + 0, 1076, 0, 0x0ULL }, // Inst #2256 = VEXTDUBVRX { 2255, 4, 1, 4, 589, 0, 0, PPCImpOpBase + 0, 1076, 0, 0x0ULL }, // Inst #2255 = VEXTDUBVLX { 2254, 4, 1, 4, 589, 0, 0, PPCImpOpBase + 0, 1076, 0, 0x0ULL }, // Inst #2254 = VEXTDDVRX { 2253, 4, 1, 4, 589, 0, 0, PPCImpOpBase + 0, 1076, 0, 0x0ULL }, // Inst #2253 = VEXTDDVLX { 2252, 2, 1, 4, 190, 0, 0, PPCImpOpBase + 0, 307, 0, 0x28ULL }, // Inst #2252 = VEXPTEFP { 2251, 2, 1, 4, 471, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2251 = VEXPANDWM { 2250, 2, 1, 4, 471, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2250 = VEXPANDQM { 2249, 2, 1, 4, 471, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2249 = VEXPANDHM { 2248, 2, 1, 4, 471, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2248 = VEXPANDDM { 2247, 2, 1, 4, 471, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2247 = VEXPANDBM { 2246, 3, 1, 4, 260, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2246 = VEQV { 2245, 3, 1, 4, 459, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2245 = VDIVUW { 2244, 3, 1, 4, 455, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2244 = VDIVUQ { 2243, 3, 1, 4, 457, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2243 = VDIVUD { 2242, 3, 1, 4, 459, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2242 = VDIVSW { 2241, 3, 1, 4, 455, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2241 = VDIVSQ { 2240, 3, 1, 4, 457, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2240 = VDIVSD { 2239, 3, 1, 4, 462, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2239 = VDIVEUW { 2238, 3, 1, 4, 455, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2238 = VDIVEUQ { 2237, 3, 1, 4, 461, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2237 = VDIVEUD { 2236, 3, 1, 4, 462, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2236 = VDIVESW { 2235, 3, 1, 4, 455, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2235 = VDIVESQ { 2234, 3, 1, 4, 461, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2234 = VDIVESD { 2233, 2, 1, 4, 475, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2233 = VCTZW { 2232, 2, 1, 4, 578, 0, 0, PPCImpOpBase + 0, 1068, 0, 0x0ULL }, // Inst #2232 = VCTZLSBB { 2231, 2, 1, 4, 475, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2231 = VCTZH { 2230, 3, 1, 4, 450, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2230 = VCTZDM { 2229, 2, 1, 4, 475, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2229 = VCTZD { 2228, 2, 1, 4, 475, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2228 = VCTZB { 2227, 2, 1, 4, 429, 0, 0, PPCImpOpBase + 0, 307, 0, 0x28ULL }, // Inst #2227 = VCTUXS_0 { 2226, 3, 1, 4, 428, 0, 0, PPCImpOpBase + 0, 1062, 0, 0x28ULL }, // Inst #2226 = VCTUXS { 2225, 2, 1, 4, 429, 0, 0, PPCImpOpBase + 0, 307, 0, 0x28ULL }, // Inst #2225 = VCTSXS_0 { 2224, 3, 1, 4, 428, 0, 0, PPCImpOpBase + 0, 1062, 0, 0x28ULL }, // Inst #2224 = VCTSXS { 2223, 3, 1, 4, 471, 0, 0, PPCImpOpBase + 0, 1073, 0, 0x0ULL }, // Inst #2223 = VCNTMBW { 2222, 3, 1, 4, 471, 0, 0, PPCImpOpBase + 0, 1073, 0, 0x0ULL }, // Inst #2222 = VCNTMBH { 2221, 3, 1, 4, 471, 0, 0, PPCImpOpBase + 0, 1073, 0, 0x0ULL }, // Inst #2221 = VCNTMBD { 2220, 3, 1, 4, 471, 0, 0, PPCImpOpBase + 0, 1073, 0, 0x0ULL }, // Inst #2220 = VCNTMBB { 2219, 3, 1, 4, 490, 0, 0, PPCImpOpBase + 0, 1070, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2219 = VCMPUQ { 2218, 3, 1, 4, 490, 0, 0, PPCImpOpBase + 0, 1070, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2218 = VCMPSQ { 2217, 3, 1, 4, 489, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2217 = VCMPNEZW_rec { 2216, 3, 1, 4, 306, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2216 = VCMPNEZW { 2215, 3, 1, 4, 489, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2215 = VCMPNEZH_rec { 2214, 3, 1, 4, 306, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2214 = VCMPNEZH { 2213, 3, 1, 4, 489, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2213 = VCMPNEZB_rec { 2212, 3, 1, 4, 306, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2212 = VCMPNEZB { 2211, 3, 1, 4, 489, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2211 = VCMPNEW_rec { 2210, 3, 1, 4, 306, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2210 = VCMPNEW { 2209, 3, 1, 4, 489, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2209 = VCMPNEH_rec { 2208, 3, 1, 4, 306, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2208 = VCMPNEH { 2207, 3, 1, 4, 489, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2207 = VCMPNEB_rec { 2206, 3, 1, 4, 306, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2206 = VCMPNEB { 2205, 3, 1, 4, 486, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2205 = VCMPGTUW_rec { 2204, 3, 1, 4, 169, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2204 = VCMPGTUW { 2203, 3, 1, 4, 488, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2203 = VCMPGTUQ_rec { 2202, 3, 1, 4, 488, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2202 = VCMPGTUQ { 2201, 3, 1, 4, 486, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2201 = VCMPGTUH_rec { 2200, 3, 1, 4, 169, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2200 = VCMPGTUH { 2199, 3, 1, 4, 487, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2199 = VCMPGTUD_rec { 2198, 3, 1, 4, 234, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2198 = VCMPGTUD { 2197, 3, 1, 4, 486, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2197 = VCMPGTUB_rec { 2196, 3, 1, 4, 169, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2196 = VCMPGTUB { 2195, 3, 1, 4, 486, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2195 = VCMPGTSW_rec { 2194, 3, 1, 4, 169, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2194 = VCMPGTSW { 2193, 3, 1, 4, 488, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2193 = VCMPGTSQ_rec { 2192, 3, 1, 4, 488, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2192 = VCMPGTSQ { 2191, 3, 1, 4, 486, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2191 = VCMPGTSH_rec { 2190, 3, 1, 4, 169, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2190 = VCMPGTSH { 2189, 3, 1, 4, 487, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2189 = VCMPGTSD_rec { 2188, 3, 1, 4, 234, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2188 = VCMPGTSD { 2187, 3, 1, 4, 486, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2187 = VCMPGTSB_rec { 2186, 3, 1, 4, 169, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2186 = VCMPGTSB { 2185, 3, 1, 4, 486, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2185 = VCMPGTFP_rec { 2184, 3, 1, 4, 486, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2184 = VCMPGTFP { 2183, 3, 1, 4, 486, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2183 = VCMPGEFP_rec { 2182, 3, 1, 4, 486, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2182 = VCMPGEFP { 2181, 3, 1, 4, 486, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2181 = VCMPEQUW_rec { 2180, 3, 1, 4, 169, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2180 = VCMPEQUW { 2179, 3, 1, 4, 488, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2179 = VCMPEQUQ_rec { 2178, 3, 1, 4, 488, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2178 = VCMPEQUQ { 2177, 3, 1, 4, 486, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2177 = VCMPEQUH_rec { 2176, 3, 1, 4, 169, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2176 = VCMPEQUH { 2175, 3, 1, 4, 487, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2175 = VCMPEQUD_rec { 2174, 3, 1, 4, 234, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2174 = VCMPEQUD { 2173, 3, 1, 4, 486, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2173 = VCMPEQUB_rec { 2172, 3, 1, 4, 169, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2172 = VCMPEQUB { 2171, 3, 1, 4, 486, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2171 = VCMPEQFP_rec { 2170, 3, 1, 4, 486, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2170 = VCMPEQFP { 2169, 3, 1, 4, 486, 0, 1, PPCImpOpBase + 78, 304, 0, 0x28ULL }, // Inst #2169 = VCMPBFP_rec { 2168, 3, 1, 4, 486, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2168 = VCMPBFP { 2167, 2, 1, 4, 232, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2167 = VCLZW { 2166, 2, 1, 4, 578, 0, 0, PPCImpOpBase + 0, 1068, 0, 0x0ULL }, // Inst #2166 = VCLZLSBB { 2165, 2, 1, 4, 232, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2165 = VCLZH { 2164, 3, 1, 4, 450, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2164 = VCLZDM { 2163, 2, 1, 4, 232, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2163 = VCLZD { 2162, 2, 1, 4, 232, 0, 0, PPCImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #2162 = VCLZB { 2161, 3, 1, 4, 586, 0, 0, PPCImpOpBase + 0, 1065, 0, 0x0ULL }, // Inst #2161 = VCLRRB { 2160, 3, 1, 4, 586, 0, 0, PPCImpOpBase + 0, 1065, 0, 0x0ULL }, // Inst #2160 = VCLRLB { 2159, 3, 1, 4, 182, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2159 = VCIPHERLAST { 2158, 3, 1, 4, 182, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2158 = VCIPHER { 2157, 2, 1, 4, 429, 0, 0, PPCImpOpBase + 0, 307, 0, 0x28ULL }, // Inst #2157 = VCFUX_0 { 2156, 3, 1, 4, 428, 0, 0, PPCImpOpBase + 0, 1062, 0, 0x28ULL }, // Inst #2156 = VCFUX { 2155, 3, 1, 4, 450, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2155 = VCFUGED { 2154, 2, 1, 4, 429, 0, 0, PPCImpOpBase + 0, 307, 0, 0x28ULL }, // Inst #2154 = VCFSX_0 { 2153, 3, 1, 4, 428, 0, 0, PPCImpOpBase + 0, 1062, 0, 0x28ULL }, // Inst #2153 = VCFSX { 2152, 3, 1, 4, 585, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2152 = VBPERMQ { 2151, 3, 1, 4, 308, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2151 = VBPERMD { 2150, 3, 1, 4, 485, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2150 = VAVGUW { 2149, 3, 1, 4, 485, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2149 = VAVGUH { 2148, 3, 1, 4, 485, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2148 = VAVGUB { 2147, 3, 1, 4, 485, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2147 = VAVGSW { 2146, 3, 1, 4, 485, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2146 = VAVGSH { 2145, 3, 1, 4, 485, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2145 = VAVGSB { 2144, 3, 1, 4, 261, 0, 0, PPCImpOpBase + 0, 304, 0, 0x28ULL }, // Inst #2144 = VANDC { 2143, 3, 1, 4, 261, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2143 = VAND { 2142, 3, 1, 4, 485, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2142 = VADDUWS { 2141, 3, 1, 4, 167, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2141 = VADDUWM { 2140, 3, 1, 4, 238, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2140 = VADDUQM { 2139, 3, 1, 4, 485, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2139 = VADDUHS { 2138, 3, 1, 4, 167, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2138 = VADDUHM { 2137, 3, 1, 4, 260, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2137 = VADDUDM { 2136, 3, 1, 4, 485, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2136 = VADDUBS { 2135, 3, 1, 4, 167, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2135 = VADDUBM { 2134, 3, 1, 4, 485, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2134 = VADDSWS { 2133, 3, 1, 4, 485, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2133 = VADDSHS { 2132, 3, 1, 4, 485, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2132 = VADDSBS { 2131, 3, 1, 4, 437, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2131 = VADDFP { 2130, 4, 1, 4, 237, 0, 0, PPCImpOpBase + 0, 1058, 0, 0x0ULL }, // Inst #2130 = VADDEUQM { 2129, 4, 1, 4, 237, 0, 0, PPCImpOpBase + 0, 1058, 0, 0x0ULL }, // Inst #2129 = VADDECUQ { 2128, 3, 1, 4, 485, 0, 0, PPCImpOpBase + 0, 304, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2128 = VADDCUW { 2127, 3, 1, 4, 466, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2127 = VADDCUQ { 2126, 3, 1, 4, 307, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2126 = VABSDUW { 2125, 3, 1, 4, 307, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2125 = VABSDUH { 2124, 3, 1, 4, 307, 0, 0, PPCImpOpBase + 0, 304, 0, 0x0ULL }, // Inst #2124 = VABSDUB { 2123, 3, 2, 4, 0, 0, 0, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2123 = UpdateGBR { 2122, 0, 0, 4, 0, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2122 = UNENCODED_NOP { 2121, 3, 0, 4, 484, 0, 0, PPCImpOpBase + 0, 1041, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2121 = TWI { 2120, 3, 0, 4, 195, 0, 0, PPCImpOpBase + 0, 422, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2120 = TW { 2119, 1, 0, 4, 305, 0, 1, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2119 = TSR { 2118, 1, 0, 4, 305, 0, 1, PPCImpOpBase + 0, 171, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2118 = TRECLAIM { 2117, 0, 0, 4, 295, 0, 1, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2117 = TRECHKPT { 2116, 0, 0, 4, 492, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2116 = TRAP { 2115, 2, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 261, 0, 0x0ULL }, // Inst #2115 = TLSLDAIX8 { 2114, 2, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 259, 0, 0x0ULL }, // Inst #2114 = TLSLDAIX { 2113, 3, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 228, 0, 0x0ULL }, // Inst #2113 = TLSGDAIX8 { 2112, 3, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 222, 0, 0x0ULL }, // Inst #2112 = TLSGDAIX { 2111, 3, 0, 4, 618, 0, 0, PPCImpOpBase + 0, 184, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2111 = TLBWE2 { 2110, 0, 0, 4, 413, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2110 = TLBWE { 2109, 0, 0, 4, 345, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2109 = TLBSYNC { 2108, 3, 0, 4, 618, 0, 0, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2108 = TLBSX2D { 2107, 3, 0, 4, 618, 0, 0, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2107 = TLBSX2 { 2106, 2, 0, 4, 413, 0, 0, PPCImpOpBase + 0, 259, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2106 = TLBSX { 2105, 3, 1, 4, 618, 0, 0, PPCImpOpBase + 0, 184, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2105 = TLBRE2 { 2104, 0, 0, 4, 413, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2104 = TLBRE { 2103, 1, 0, 4, 618, 0, 0, PPCImpOpBase + 0, 171, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2103 = TLBLI { 2102, 1, 0, 4, 618, 0, 0, PPCImpOpBase + 0, 171, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2102 = TLBLD { 2101, 2, 0, 4, 413, 0, 0, PPCImpOpBase + 0, 259, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2101 = TLBIVAX { 2100, 3, 0, 4, 15, 0, 0, PPCImpOpBase + 0, 422, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2100 = TLBILX { 2099, 1, 0, 4, 354, 0, 0, PPCImpOpBase + 0, 171, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2099 = TLBIEL { 2098, 2, 0, 4, 372, 0, 0, PPCImpOpBase + 0, 259, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2098 = TLBIE { 2097, 0, 0, 4, 419, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2097 = TLBIA { 2096, 1, 0, 4, 357, 0, 1, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2096 = TEND { 2095, 3, 0, 4, 483, 0, 0, PPCImpOpBase + 0, 1055, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2095 = TDI { 2094, 3, 0, 4, 194, 0, 0, PPCImpOpBase + 0, 1052, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2094 = TD { 2093, 2, 0, 4, 0, 1, 0, PPCImpOpBase + 134, 1050, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #2093 = TCRETURNri8 { 2092, 2, 0, 4, 0, 1, 0, PPCImpOpBase + 134, 1048, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #2092 = TCRETURNri { 2091, 2, 0, 4, 0, 1, 0, PPCImpOpBase + 134, 1046, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #2091 = TCRETURNdi8 { 2090, 2, 0, 4, 0, 1, 0, PPCImpOpBase + 134, 1046, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #2090 = TCRETURNdi { 2089, 2, 0, 4, 0, 1, 0, PPCImpOpBase + 134, 1044, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #2089 = TCRETURNai8 { 2088, 2, 0, 4, 0, 1, 0, PPCImpOpBase + 134, 1044, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #2088 = TCRETURNai { 2087, 1, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 171, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2087 = TCHECK_RET { 2086, 1, 1, 4, 359, 0, 0, PPCImpOpBase + 0, 654, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2086 = TCHECK { 2085, 2, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 206, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2085 = TBEGIN_RET { 2084, 1, 0, 4, 295, 0, 1, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2084 = TBEGIN { 2083, 0, 0, 4, 402, 2, 0, PPCImpOpBase + 209, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #2083 = TAILBCTR8 { 2082, 0, 0, 4, 402, 2, 0, PPCImpOpBase + 207, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #2082 = TAILBCTR { 2081, 1, 0, 4, 446, 1, 0, PPCImpOpBase + 134, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #2081 = TAILBA8 { 2080, 1, 0, 4, 446, 1, 0, PPCImpOpBase + 134, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #2080 = TAILBA { 2079, 1, 0, 4, 446, 1, 0, PPCImpOpBase + 134, 285, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #2079 = TAILB8 { 2078, 1, 0, 4, 446, 1, 0, PPCImpOpBase + 134, 285, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #2078 = TAILB { 2077, 3, 0, 4, 271, 0, 1, PPCImpOpBase + 0, 1041, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2077 = TABORTWCI { 2076, 3, 0, 4, 271, 0, 1, PPCImpOpBase + 0, 422, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2076 = TABORTWC { 2075, 3, 0, 4, 271, 0, 1, PPCImpOpBase + 0, 1041, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2075 = TABORTDCI { 2074, 3, 0, 4, 271, 0, 1, PPCImpOpBase + 0, 422, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2074 = TABORTDC { 2073, 1, 0, 4, 305, 0, 1, PPCImpOpBase + 0, 171, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2073 = TABORT { 2072, 2, 0, 4, 612, 0, 0, PPCImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2072 = SYNCP10 { 2071, 1, 0, 4, 346, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2071 = SYNC { 2070, 3, 1, 4, 287, 0, 1, PPCImpOpBase + 0, 222, 0, 0x8ULL }, // Inst #2070 = SUBF_rec { 2069, 2, 1, 4, 532, 1, 2, PPCImpOpBase + 22, 259, 0, 0x8ULL }, // Inst #2069 = SUBFZE_rec { 2068, 2, 1, 4, 532, 1, 3, PPCImpOpBase + 18, 259, 0, 0x8ULL }, // Inst #2068 = SUBFZEO_rec { 2067, 2, 1, 4, 502, 1, 2, PPCImpOpBase + 15, 259, 0, 0x8ULL }, // Inst #2067 = SUBFZEO { 2066, 2, 1, 4, 532, 1, 2, PPCImpOpBase + 22, 261, 0, 0x8ULL }, // Inst #2066 = SUBFZE8_rec { 2065, 2, 1, 4, 532, 1, 3, PPCImpOpBase + 18, 261, 0, 0x8ULL }, // Inst #2065 = SUBFZE8O_rec { 2064, 2, 1, 4, 502, 1, 2, PPCImpOpBase + 15, 261, 0, 0x8ULL }, // Inst #2064 = SUBFZE8O { 2063, 2, 1, 4, 501, 1, 1, PPCImpOpBase + 13, 261, 0, 0x8ULL }, // Inst #2063 = SUBFZE8 { 2062, 2, 1, 4, 501, 1, 1, PPCImpOpBase + 13, 259, 0, 0x8ULL }, // Inst #2062 = SUBFZE { 2061, 4, 1, 4, 144, 0, 1, PPCImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2061 = SUBFUS_rec { 2060, 4, 1, 4, 144, 0, 0, PPCImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2060 = SUBFUS { 2059, 3, 1, 4, 534, 0, 2, PPCImpOpBase + 3, 222, 0, 0x8ULL }, // Inst #2059 = SUBFO_rec { 2058, 3, 1, 4, 521, 0, 1, PPCImpOpBase + 2, 222, 0, 0x8ULL }, // Inst #2058 = SUBFO { 2057, 2, 1, 4, 532, 1, 2, PPCImpOpBase + 22, 259, 0, 0x8ULL }, // Inst #2057 = SUBFME_rec { 2056, 2, 1, 4, 532, 1, 3, PPCImpOpBase + 18, 259, 0, 0x8ULL }, // Inst #2056 = SUBFMEO_rec { 2055, 2, 1, 4, 502, 1, 2, PPCImpOpBase + 15, 259, 0, 0x8ULL }, // Inst #2055 = SUBFMEO { 2054, 2, 1, 4, 532, 1, 2, PPCImpOpBase + 22, 261, 0, 0x8ULL }, // Inst #2054 = SUBFME8_rec { 2053, 2, 1, 4, 532, 1, 3, PPCImpOpBase + 18, 261, 0, 0x8ULL }, // Inst #2053 = SUBFME8O_rec { 2052, 2, 1, 4, 502, 1, 2, PPCImpOpBase + 15, 261, 0, 0x8ULL }, // Inst #2052 = SUBFME8O { 2051, 2, 1, 4, 501, 1, 1, PPCImpOpBase + 13, 261, 0, 0x8ULL }, // Inst #2051 = SUBFME8 { 2050, 2, 1, 4, 501, 1, 1, PPCImpOpBase + 13, 259, 0, 0x8ULL }, // Inst #2050 = SUBFME { 2049, 3, 1, 4, 501, 0, 1, PPCImpOpBase + 5, 181, 0, 0x8ULL }, // Inst #2049 = SUBFIC8 { 2048, 3, 1, 4, 501, 0, 1, PPCImpOpBase + 5, 184, 0, 0x8ULL }, // Inst #2048 = SUBFIC { 2047, 3, 1, 4, 534, 1, 2, PPCImpOpBase + 22, 222, 0, 0x8ULL }, // Inst #2047 = SUBFE_rec { 2046, 3, 1, 4, 534, 1, 3, PPCImpOpBase + 18, 222, 0, 0x8ULL }, // Inst #2046 = SUBFEO_rec { 2045, 3, 1, 4, 521, 1, 2, PPCImpOpBase + 15, 222, 0, 0x8ULL }, // Inst #2045 = SUBFEO { 2044, 3, 1, 4, 534, 1, 2, PPCImpOpBase + 22, 228, 0, 0x8ULL }, // Inst #2044 = SUBFE8_rec { 2043, 3, 1, 4, 534, 1, 3, PPCImpOpBase + 18, 228, 0, 0x8ULL }, // Inst #2043 = SUBFE8O_rec { 2042, 3, 1, 4, 521, 1, 2, PPCImpOpBase + 15, 228, 0, 0x8ULL }, // Inst #2042 = SUBFE8O { 2041, 3, 1, 4, 142, 1, 1, PPCImpOpBase + 13, 228, 0, 0x8ULL }, // Inst #2041 = SUBFE8 { 2040, 3, 1, 4, 142, 1, 1, PPCImpOpBase + 13, 222, 0, 0x8ULL }, // Inst #2040 = SUBFE { 2039, 3, 1, 4, 538, 0, 2, PPCImpOpBase + 11, 222, 0, 0xcULL }, // Inst #2039 = SUBFC_rec { 2038, 3, 1, 4, 390, 0, 3, PPCImpOpBase + 8, 222, 0, 0xcULL }, // Inst #2038 = SUBFCO_rec { 2037, 3, 1, 4, 286, 0, 2, PPCImpOpBase + 6, 222, 0, 0xcULL }, // Inst #2037 = SUBFCO { 2036, 3, 1, 4, 538, 0, 2, PPCImpOpBase + 11, 228, 0, 0xcULL }, // Inst #2036 = SUBFC8_rec { 2035, 3, 1, 4, 390, 0, 3, PPCImpOpBase + 8, 228, 0, 0xcULL }, // Inst #2035 = SUBFC8O_rec { 2034, 3, 1, 4, 286, 0, 2, PPCImpOpBase + 6, 228, 0, 0xcULL }, // Inst #2034 = SUBFC8O { 2033, 3, 1, 4, 286, 0, 1, PPCImpOpBase + 5, 228, 0, 0xcULL }, // Inst #2033 = SUBFC8 { 2032, 3, 1, 4, 286, 0, 1, PPCImpOpBase + 5, 222, 0, 0xcULL }, // Inst #2032 = SUBFC { 2031, 3, 1, 4, 200, 0, 1, PPCImpOpBase + 0, 228, 0, 0x8ULL }, // Inst #2031 = SUBF8_rec { 2030, 3, 1, 4, 534, 0, 2, PPCImpOpBase + 3, 228, 0, 0x8ULL }, // Inst #2030 = SUBF8O_rec { 2029, 3, 1, 4, 521, 0, 1, PPCImpOpBase + 2, 228, 0, 0x8ULL }, // Inst #2029 = SUBF8O { 2028, 3, 1, 4, 139, 0, 0, PPCImpOpBase + 0, 228, 0, 0x8ULL }, // Inst #2028 = SUBF8 { 2027, 3, 1, 4, 228, 0, 0, PPCImpOpBase + 0, 222, 0, 0x8ULL }, // Inst #2027 = SUBF { 2026, 3, 0, 4, 373, 0, 0, PPCImpOpBase + 0, 627, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2026 = STXVX { 2025, 3, 0, 4, 116, 0, 0, PPCImpOpBase + 0, 627, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2025 = STXVW4X { 2024, 3, 0, 4, 609, 0, 0, PPCImpOpBase + 0, 627, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2024 = STXVRWX { 2023, 3, 0, 4, 15, 0, 0, PPCImpOpBase + 0, 632, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #2023 = STXVRLL { 2022, 3, 0, 4, 15, 0, 0, PPCImpOpBase + 0, 632, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #2022 = STXVRL { 2021, 3, 0, 4, 609, 0, 0, PPCImpOpBase + 0, 627, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2021 = STXVRHX { 2020, 3, 0, 4, 609, 0, 0, PPCImpOpBase + 0, 627, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2020 = STXVRDX { 2019, 3, 0, 4, 609, 0, 0, PPCImpOpBase + 0, 627, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2019 = STXVRBX { 2018, 3, 0, 4, 615, 0, 0, PPCImpOpBase + 0, 641, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2018 = STXVPX { 2017, 3, 0, 4, 40, 0, 0, PPCImpOpBase + 0, 638, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #2017 = STXVPRLL { 2016, 3, 0, 4, 40, 0, 0, PPCImpOpBase + 0, 638, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #2016 = STXVPRL { 2015, 3, 0, 4, 614, 0, 0, PPCImpOpBase + 0, 635, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2015 = STXVP { 2014, 3, 0, 4, 374, 0, 0, PPCImpOpBase + 0, 632, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2014 = STXVLL { 2013, 3, 0, 4, 374, 0, 0, PPCImpOpBase + 0, 632, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2013 = STXVL { 2012, 3, 0, 4, 373, 0, 0, PPCImpOpBase + 0, 627, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2012 = STXVH8X { 2011, 3, 0, 4, 116, 0, 0, PPCImpOpBase + 0, 627, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2011 = STXVD2X { 2010, 3, 0, 4, 373, 0, 0, PPCImpOpBase + 0, 627, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2010 = STXVB16X { 2009, 3, 0, 4, 604, 0, 0, PPCImpOpBase + 0, 624, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2009 = STXV { 2008, 3, 0, 4, 366, 0, 0, PPCImpOpBase + 0, 219, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2008 = STXSSPX { 2007, 3, 0, 4, 603, 0, 0, PPCImpOpBase + 0, 621, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2007 = STXSSP { 2006, 3, 0, 4, 366, 0, 0, PPCImpOpBase + 0, 203, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2006 = STXSIWX { 2005, 3, 0, 4, 367, 0, 0, PPCImpOpBase + 0, 627, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2005 = STXSIHXv { 2004, 3, 0, 4, 367, 0, 0, PPCImpOpBase + 0, 203, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2004 = STXSIHX { 2003, 3, 0, 4, 367, 0, 0, PPCImpOpBase + 0, 627, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2003 = STXSIBXv { 2002, 3, 0, 4, 367, 0, 0, PPCImpOpBase + 0, 203, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2002 = STXSIBX { 2001, 3, 0, 4, 368, 0, 0, PPCImpOpBase + 0, 203, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2001 = STXSDX { 2000, 3, 0, 4, 602, 0, 0, PPCImpOpBase + 0, 621, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2000 = STXSD { 1999, 3, 0, 4, 370, 0, 0, PPCImpOpBase + 0, 557, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #1999 = STWXTLS_32 { 1998, 3, 0, 4, 370, 0, 0, PPCImpOpBase + 0, 554, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #1998 = STWXTLS_ { 1997, 3, 0, 4, 370, 0, 0, PPCImpOpBase + 0, 554, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #1997 = STWXTLS { 1996, 3, 0, 4, 127, 0, 0, PPCImpOpBase + 0, 551, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1996 = STWX8 { 1995, 3, 0, 4, 127, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1995 = STWX { 1994, 4, 1, 4, 133, 0, 0, PPCImpOpBase + 0, 1021, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1994 = STWUX8 { 1993, 4, 1, 4, 133, 0, 0, PPCImpOpBase + 0, 1017, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1993 = STWUX { 1992, 4, 1, 4, 132, 0, 0, PPCImpOpBase + 0, 1013, 0|(1ULL<<MCID::MayStore), 0x10ULL }, // Inst #1992 = STWU8 { 1991, 4, 1, 4, 132, 0, 0, PPCImpOpBase + 0, 1009, 0|(1ULL<<MCID::MayStore), 0x10ULL }, // Inst #1991 = STWU { 1990, 3, 0, 4, 217, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1990 = STWEPX { 1989, 3, 0, 4, 130, 0, 1, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #1989 = STWCX { 1988, 3, 0, 4, 611, 0, 0, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1988 = STWCIX { 1987, 3, 0, 4, 127, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1987 = STWBRX { 1986, 3, 0, 4, 404, 0, 0, PPCImpOpBase + 0, 184, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #1986 = STWAT { 1985, 3, 0, 4, 596, 0, 0, PPCImpOpBase + 0, 521, 0|(1ULL<<MCID::MayStore), 0x10ULL }, // Inst #1985 = STW8 { 1984, 3, 0, 4, 596, 0, 0, PPCImpOpBase + 0, 200, 0|(1ULL<<MCID::MayStore), 0x10ULL }, // Inst #1984 = STW { 1983, 3, 0, 4, 122, 0, 0, PPCImpOpBase + 0, 612, 0|(1ULL<<MCID::MayStore), 0x50ULL }, // Inst #1983 = STVXL { 1982, 3, 0, 4, 122, 0, 0, PPCImpOpBase + 0, 612, 0|(1ULL<<MCID::MayStore), 0x50ULL }, // Inst #1982 = STVX { 1981, 3, 0, 4, 122, 0, 0, PPCImpOpBase + 0, 612, 0|(1ULL<<MCID::MayStore), 0x50ULL }, // Inst #1981 = STVEWX { 1980, 3, 0, 4, 122, 0, 0, PPCImpOpBase + 0, 612, 0|(1ULL<<MCID::MayStore), 0x50ULL }, // Inst #1980 = STVEHX { 1979, 3, 0, 4, 122, 0, 0, PPCImpOpBase + 0, 612, 0|(1ULL<<MCID::MayStore), 0x50ULL }, // Inst #1979 = STVEBX { 1978, 3, 0, 4, 221, 0, 0, PPCImpOpBase + 0, 184, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1978 = STSWI { 1977, 3, 0, 4, 0, 0, 0, PPCImpOpBase + 0, 609, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #1977 = STQX_PSEUDO { 1976, 3, 0, 4, 92, 0, 1, PPCImpOpBase + 0, 609, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #1976 = STQCX { 1975, 3, 0, 4, 91, 0, 0, PPCImpOpBase + 0, 867, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #1975 = STQ { 1974, 0, 0, 4, 425, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1974 = STOP { 1973, 3, 0, 4, 129, 0, 0, PPCImpOpBase + 0, 200, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1973 = STMW { 1972, 3, 0, 4, 370, 0, 0, PPCImpOpBase + 0, 557, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #1972 = STHXTLS_32 { 1971, 3, 0, 4, 370, 0, 0, PPCImpOpBase + 0, 554, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #1971 = STHXTLS_ { 1970, 3, 0, 4, 370, 0, 0, PPCImpOpBase + 0, 554, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #1970 = STHXTLS { 1969, 3, 0, 4, 127, 0, 0, PPCImpOpBase + 0, 551, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1969 = STHX8 { 1968, 3, 0, 4, 127, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1968 = STHX { 1967, 4, 1, 4, 133, 0, 0, PPCImpOpBase + 0, 1021, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1967 = STHUX8 { 1966, 4, 1, 4, 133, 0, 0, PPCImpOpBase + 0, 1017, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1966 = STHUX { 1965, 4, 1, 4, 132, 0, 0, PPCImpOpBase + 0, 1013, 0|(1ULL<<MCID::MayStore), 0x10ULL }, // Inst #1965 = STHU8 { 1964, 4, 1, 4, 132, 0, 0, PPCImpOpBase + 0, 1009, 0|(1ULL<<MCID::MayStore), 0x10ULL }, // Inst #1964 = STHU { 1963, 3, 0, 4, 217, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1963 = STHEPX { 1962, 3, 0, 4, 220, 0, 1, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #1962 = STHCX { 1961, 3, 0, 4, 611, 0, 0, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1961 = STHCIX { 1960, 3, 0, 4, 127, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1960 = STHBRX { 1959, 3, 0, 4, 596, 0, 0, PPCImpOpBase + 0, 521, 0|(1ULL<<MCID::MayStore), 0x10ULL }, // Inst #1959 = STH8 { 1958, 3, 0, 4, 596, 0, 0, PPCImpOpBase + 0, 200, 0|(1ULL<<MCID::MayStore), 0x10ULL }, // Inst #1958 = STH { 1957, 3, 0, 4, 366, 0, 0, PPCImpOpBase + 0, 603, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #1957 = STFSXTLS_ { 1956, 3, 0, 4, 366, 0, 0, PPCImpOpBase + 0, 603, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #1956 = STFSXTLS { 1955, 3, 0, 4, 120, 0, 0, PPCImpOpBase + 0, 600, 0|(1ULL<<MCID::MayStore), 0x50ULL }, // Inst #1955 = STFSX { 1954, 4, 1, 4, 121, 0, 0, PPCImpOpBase + 0, 1037, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1954 = STFSUX { 1953, 4, 1, 4, 601, 0, 0, PPCImpOpBase + 0, 1033, 0|(1ULL<<MCID::MayStore), 0x10ULL }, // Inst #1953 = STFSU { 1952, 3, 0, 4, 600, 0, 0, PPCImpOpBase + 0, 589, 0|(1ULL<<MCID::MayStore), 0x10ULL }, // Inst #1952 = STFS { 1951, 3, 0, 4, 120, 0, 0, PPCImpOpBase + 0, 575, 0|(1ULL<<MCID::MayStore), 0x50ULL }, // Inst #1951 = STFIWX { 1950, 3, 0, 4, 366, 0, 0, PPCImpOpBase + 0, 586, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #1950 = STFDXTLS_ { 1949, 3, 0, 4, 366, 0, 0, PPCImpOpBase + 0, 586, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #1949 = STFDXTLS { 1948, 3, 0, 4, 120, 0, 0, PPCImpOpBase + 0, 575, 0|(1ULL<<MCID::MayStore), 0x50ULL }, // Inst #1948 = STFDX { 1947, 4, 1, 4, 121, 0, 0, PPCImpOpBase + 0, 1029, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1947 = STFDUX { 1946, 4, 1, 4, 601, 0, 0, PPCImpOpBase + 0, 1025, 0|(1ULL<<MCID::MayStore), 0x10ULL }, // Inst #1946 = STFDU { 1945, 3, 0, 4, 216, 0, 0, PPCImpOpBase + 0, 575, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1945 = STFDEPX { 1944, 3, 0, 4, 600, 0, 0, PPCImpOpBase + 0, 572, 0|(1ULL<<MCID::MayStore), 0x10ULL }, // Inst #1944 = STFD { 1943, 3, 0, 4, 218, 0, 0, PPCImpOpBase + 0, 554, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #1943 = STDXTLS_ { 1942, 3, 0, 4, 218, 0, 0, PPCImpOpBase + 0, 554, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #1942 = STDXTLS { 1941, 3, 0, 4, 128, 0, 0, PPCImpOpBase + 0, 551, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1941 = STDX { 1940, 4, 1, 4, 133, 0, 0, PPCImpOpBase + 0, 1021, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1940 = STDUX { 1939, 4, 1, 4, 132, 0, 0, PPCImpOpBase + 0, 1013, 0|(1ULL<<MCID::MayStore), 0x10ULL }, // Inst #1939 = STDU { 1938, 3, 0, 4, 131, 0, 1, PPCImpOpBase + 0, 551, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #1938 = STDCX { 1937, 3, 0, 4, 219, 0, 0, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1937 = STDCIX { 1936, 3, 0, 4, 370, 0, 0, PPCImpOpBase + 0, 551, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1936 = STDBRX { 1935, 3, 0, 4, 404, 0, 0, PPCImpOpBase + 0, 181, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #1935 = STDAT { 1934, 3, 0, 4, 598, 0, 0, PPCImpOpBase + 0, 521, 0|(1ULL<<MCID::MayStore), 0x10ULL }, // Inst #1934 = STD { 1933, 3, 0, 4, 370, 0, 0, PPCImpOpBase + 0, 557, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #1933 = STBXTLS_32 { 1932, 3, 0, 4, 370, 0, 0, PPCImpOpBase + 0, 554, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #1932 = STBXTLS_ { 1931, 3, 0, 4, 370, 0, 0, PPCImpOpBase + 0, 554, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #1931 = STBXTLS { 1930, 3, 0, 4, 127, 0, 0, PPCImpOpBase + 0, 551, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1930 = STBX8 { 1929, 3, 0, 4, 127, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1929 = STBX { 1928, 4, 1, 4, 133, 0, 0, PPCImpOpBase + 0, 1021, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1928 = STBUX8 { 1927, 4, 1, 4, 133, 0, 0, PPCImpOpBase + 0, 1017, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1927 = STBUX { 1926, 4, 1, 4, 132, 0, 0, PPCImpOpBase + 0, 1013, 0|(1ULL<<MCID::MayStore), 0x10ULL }, // Inst #1926 = STBU8 { 1925, 4, 1, 4, 132, 0, 0, PPCImpOpBase + 0, 1009, 0|(1ULL<<MCID::MayStore), 0x10ULL }, // Inst #1925 = STBU { 1924, 3, 0, 4, 217, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1924 = STBEPX { 1923, 3, 0, 4, 220, 0, 1, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #1923 = STBCX { 1922, 3, 0, 4, 219, 0, 0, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1922 = STBCIX { 1921, 3, 0, 4, 596, 0, 0, PPCImpOpBase + 0, 521, 0|(1ULL<<MCID::MayStore), 0x10ULL }, // Inst #1921 = STB8 { 1920, 3, 0, 4, 596, 0, 0, PPCImpOpBase + 0, 200, 0|(1ULL<<MCID::MayStore), 0x10ULL }, // Inst #1920 = STB { 1919, 3, 1, 4, 199, 0, 1, PPCImpOpBase + 0, 222, 0, 0x208ULL }, // Inst #1919 = SRW_rec { 1918, 3, 1, 4, 199, 0, 1, PPCImpOpBase + 0, 228, 0, 0x208ULL }, // Inst #1918 = SRW8_rec { 1917, 3, 1, 4, 300, 0, 0, PPCImpOpBase + 0, 228, 0, 0x208ULL }, // Inst #1917 = SRW8 { 1916, 3, 1, 4, 300, 0, 0, PPCImpOpBase + 0, 222, 0, 0x208ULL }, // Inst #1916 = SRW { 1915, 3, 1, 4, 482, 0, 1, PPCImpOpBase + 0, 1003, 0, 0x8ULL }, // Inst #1915 = SRD_rec { 1914, 3, 1, 4, 283, 0, 0, PPCImpOpBase + 0, 1003, 0, 0x8ULL }, // Inst #1914 = SRD { 1913, 3, 1, 4, 147, 0, 2, PPCImpOpBase + 11, 222, 0, 0x108ULL }, // Inst #1913 = SRAW_rec { 1912, 3, 1, 4, 493, 0, 2, PPCImpOpBase + 11, 184, 0, 0x108ULL }, // Inst #1912 = SRAWI_rec { 1911, 3, 1, 4, 514, 0, 1, PPCImpOpBase + 5, 184, 0, 0x108ULL }, // Inst #1911 = SRAWI { 1910, 3, 1, 4, 302, 0, 1, PPCImpOpBase + 5, 222, 0, 0x108ULL }, // Inst #1910 = SRAW { 1909, 3, 1, 4, 146, 0, 2, PPCImpOpBase + 11, 1003, 0, 0x8ULL }, // Inst #1909 = SRAD_rec { 1908, 3, 1, 4, 145, 0, 2, PPCImpOpBase + 11, 181, 0, 0x8ULL }, // Inst #1908 = SRADI_rec { 1907, 3, 1, 4, 284, 0, 1, PPCImpOpBase + 5, 184, 0, 0x8ULL }, // Inst #1907 = SRADI_32 { 1906, 3, 1, 4, 284, 0, 1, PPCImpOpBase + 5, 181, 0, 0x8ULL }, // Inst #1906 = SRADI { 1905, 3, 1, 4, 283, 0, 1, PPCImpOpBase + 5, 1003, 0, 0x8ULL }, // Inst #1905 = SRAD { 1904, 3, 2, 4, 0, 0, 0, PPCImpOpBase + 0, 1006, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1904 = SPLIT_QUADWORD { 1903, 3, 0, 4, 0, 0, 0, PPCImpOpBase + 0, 873, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1903 = SPILL_WACC { 1902, 3, 0, 4, 0, 0, 0, PPCImpOpBase + 0, 870, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1902 = SPILL_UACC { 1901, 3, 0, 4, 0, 0, 0, PPCImpOpBase + 0, 867, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #1901 = SPILL_QUADWORD { 1900, 3, 0, 4, 0, 0, 0, PPCImpOpBase + 0, 864, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1900 = SPILL_CRBIT { 1899, 3, 0, 4, 0, 0, 0, PPCImpOpBase + 0, 861, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1899 = SPILL_CR { 1898, 3, 0, 4, 0, 0, 0, PPCImpOpBase + 0, 858, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1898 = SPILL_ACC { 1897, 3, 0, 4, 25, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1897 = SPESTWX { 1896, 3, 0, 4, 25, 0, 0, PPCImpOpBase + 0, 200, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1896 = SPESTW { 1895, 3, 1, 4, 15, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1895 = SPELWZX { 1894, 3, 1, 4, 15, 0, 0, PPCImpOpBase + 0, 200, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1894 = SPELWZ { 1893, 3, 1, 4, 199, 0, 1, PPCImpOpBase + 0, 222, 0, 0x208ULL }, // Inst #1893 = SLW_rec { 1892, 3, 1, 4, 199, 0, 1, PPCImpOpBase + 0, 228, 0, 0x208ULL }, // Inst #1892 = SLW8_rec { 1891, 3, 1, 4, 300, 0, 0, PPCImpOpBase + 0, 228, 0, 0x208ULL }, // Inst #1891 = SLW8 { 1890, 3, 1, 4, 300, 0, 0, PPCImpOpBase + 0, 222, 0, 0x208ULL }, // Inst #1890 = SLW { 1889, 3, 1, 4, 482, 0, 1, PPCImpOpBase + 0, 1003, 0, 0x8ULL }, // Inst #1889 = SLD_rec { 1888, 3, 1, 4, 283, 0, 0, PPCImpOpBase + 0, 1003, 0, 0x8ULL }, // Inst #1888 = SLD { 1887, 0, 0, 4, 423, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1887 = SLBSYNC { 1886, 2, 0, 4, 353, 0, 0, PPCImpOpBase + 0, 259, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1886 = SLBMTE { 1885, 2, 1, 4, 352, 0, 0, PPCImpOpBase + 0, 259, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1885 = SLBMFEV { 1884, 2, 1, 4, 351, 0, 0, PPCImpOpBase + 0, 259, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1884 = SLBMFEE { 1883, 2, 0, 4, 371, 0, 0, PPCImpOpBase + 0, 259, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1883 = SLBIEG { 1882, 1, 0, 4, 350, 0, 0, PPCImpOpBase + 0, 171, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1882 = SLBIE { 1881, 0, 0, 4, 349, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1881 = SLBIA { 1880, 2, 1, 4, 424, 0, 1, PPCImpOpBase + 0, 259, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1880 = SLBFEE_rec { 1879, 2, 1, 4, 0, 1, 1, PPCImpOpBase + 205, 659, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1879 = SETRNDi { 1878, 2, 1, 4, 0, 1, 1, PPCImpOpBase + 205, 1001, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1878 = SETRND { 1877, 2, 1, 4, 513, 0, 0, PPCImpOpBase + 0, 999, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1877 = SETNBCR8 { 1876, 2, 1, 4, 513, 0, 0, PPCImpOpBase + 0, 997, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1876 = SETNBCR { 1875, 2, 1, 4, 513, 0, 0, PPCImpOpBase + 0, 999, 0, 0x100ULL }, // Inst #1875 = SETNBC8 { 1874, 2, 1, 4, 513, 0, 0, PPCImpOpBase + 0, 997, 0, 0x100ULL }, // Inst #1874 = SETNBC { 1873, 2, 1, 4, 0, 1, 1, PPCImpOpBase + 205, 345, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1873 = SETFLM { 1872, 2, 1, 4, 513, 0, 0, PPCImpOpBase + 0, 999, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL }, // Inst #1872 = SETBCR8 { 1871, 2, 1, 4, 513, 0, 0, PPCImpOpBase + 0, 997, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL }, // Inst #1871 = SETBCR { 1870, 2, 1, 4, 513, 0, 0, PPCImpOpBase + 0, 999, 0, 0x300ULL }, // Inst #1870 = SETBC8 { 1869, 2, 1, 4, 513, 0, 0, PPCImpOpBase + 0, 997, 0, 0x300ULL }, // Inst #1869 = SETBC { 1868, 2, 1, 4, 512, 0, 0, PPCImpOpBase + 0, 995, 0, 0x108ULL }, // Inst #1868 = SETB8 { 1867, 2, 1, 4, 512, 0, 0, PPCImpOpBase + 0, 993, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1867 = SETB { 1866, 4, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 965, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL }, // Inst #1866 = SELECT_VSSRC { 1865, 4, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 989, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL }, // Inst #1865 = SELECT_VSRC { 1864, 4, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 969, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL }, // Inst #1864 = SELECT_VSFRC { 1863, 4, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 961, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL }, // Inst #1863 = SELECT_VRRC { 1862, 4, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 985, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #1862 = SELECT_SPE4 { 1861, 4, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 981, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #1861 = SELECT_SPE { 1860, 4, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 977, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL }, // Inst #1860 = SELECT_I8 { 1859, 4, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 973, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL }, // Inst #1859 = SELECT_I4 { 1858, 4, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 969, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL }, // Inst #1858 = SELECT_F8 { 1857, 4, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 965, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL }, // Inst #1857 = SELECT_F4 { 1856, 4, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 961, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL }, // Inst #1856 = SELECT_F16 { 1855, 5, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 926, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1855 = SELECT_CC_VSSRC { 1854, 5, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 956, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1854 = SELECT_CC_VSRC { 1853, 5, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 931, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1853 = SELECT_CC_VSFRC { 1852, 5, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 921, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1852 = SELECT_CC_VRRC { 1851, 5, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 951, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1851 = SELECT_CC_SPE4 { 1850, 5, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 946, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1850 = SELECT_CC_SPE { 1849, 5, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 941, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1849 = SELECT_CC_I8 { 1848, 5, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 936, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1848 = SELECT_CC_I4 { 1847, 5, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 931, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1847 = SELECT_CC_F8 { 1846, 5, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 926, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1846 = SELECT_CC_F4 { 1845, 5, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 921, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1845 = SELECT_CC_F16 { 1844, 1, 0, 4, 4, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1844 = SCV { 1843, 1, 0, 4, 535, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #1843 = SC { 1842, 2, 2, 4, 0, 0, 0, PPCImpOpBase + 0, 259, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1842 = ReadTB { 1841, 5, 1, 4, 199, 0, 1, PPCImpOpBase + 0, 911, 0, 0x8ULL }, // Inst #1841 = RLWNM_rec { 1840, 5, 1, 4, 199, 0, 1, PPCImpOpBase + 0, 916, 0, 0x8ULL }, // Inst #1840 = RLWNM8_rec { 1839, 5, 1, 4, 300, 0, 0, PPCImpOpBase + 0, 916, 0, 0x8ULL }, // Inst #1839 = RLWNM8 { 1838, 5, 1, 4, 300, 0, 0, PPCImpOpBase + 0, 911, 0, 0x8ULL }, // Inst #1838 = RLWNM { 1837, 5, 1, 4, 474, 0, 1, PPCImpOpBase + 0, 901, 0, 0xcULL }, // Inst #1837 = RLWINM_rec { 1836, 5, 1, 4, 474, 0, 1, PPCImpOpBase + 0, 906, 0, 0x8ULL }, // Inst #1836 = RLWINM8_rec { 1835, 5, 1, 4, 511, 0, 0, PPCImpOpBase + 0, 906, 0, 0x8ULL }, // Inst #1835 = RLWINM8 { 1834, 5, 1, 4, 511, 0, 0, PPCImpOpBase + 0, 901, 0, 0x8ULL }, // Inst #1834 = RLWINM { 1833, 6, 1, 4, 204, 0, 1, PPCImpOpBase + 0, 889, 0|(1ULL<<MCID::Commutable), 0xcULL }, // Inst #1833 = RLWIMI_rec { 1832, 6, 1, 4, 204, 0, 1, PPCImpOpBase + 0, 895, 0, 0xcULL }, // Inst #1832 = RLWIMI8_rec { 1831, 6, 1, 4, 197, 0, 0, PPCImpOpBase + 0, 895, 0, 0xcULL }, // Inst #1831 = RLWIMI8 { 1830, 6, 1, 4, 197, 0, 0, PPCImpOpBase + 0, 889, 0|(1ULL<<MCID::Commutable), 0xcULL }, // Inst #1830 = RLWIMI { 1829, 5, 1, 4, 393, 0, 1, PPCImpOpBase + 0, 884, 0, 0x8ULL }, // Inst #1829 = RLDIMI_rec { 1828, 5, 1, 4, 298, 0, 0, PPCImpOpBase + 0, 884, 0, 0x8ULL }, // Inst #1828 = RLDIMI { 1827, 4, 1, 4, 472, 0, 1, PPCImpOpBase + 0, 173, 0, 0x8ULL }, // Inst #1827 = RLDIC_rec { 1826, 4, 1, 4, 473, 0, 1, PPCImpOpBase + 0, 173, 0, 0x8ULL }, // Inst #1826 = RLDICR_rec { 1825, 4, 1, 4, 510, 0, 0, PPCImpOpBase + 0, 177, 0, 0x8ULL }, // Inst #1825 = RLDICR_32 { 1824, 4, 1, 4, 510, 0, 0, PPCImpOpBase + 0, 173, 0, 0x8ULL }, // Inst #1824 = RLDICR { 1823, 4, 1, 4, 473, 0, 1, PPCImpOpBase + 0, 173, 0, 0x8ULL }, // Inst #1823 = RLDICL_rec { 1822, 4, 1, 4, 473, 0, 1, PPCImpOpBase + 0, 177, 0, 0x8ULL }, // Inst #1822 = RLDICL_32_rec { 1821, 4, 1, 4, 510, 0, 0, PPCImpOpBase + 0, 880, 0, 0x8ULL }, // Inst #1821 = RLDICL_32_64 { 1820, 4, 1, 4, 510, 0, 0, PPCImpOpBase + 0, 177, 0, 0x8ULL }, // Inst #1820 = RLDICL_32 { 1819, 4, 1, 4, 510, 0, 0, PPCImpOpBase + 0, 173, 0, 0x8ULL }, // Inst #1819 = RLDICL { 1818, 4, 1, 4, 284, 0, 0, PPCImpOpBase + 0, 173, 0, 0x8ULL }, // Inst #1818 = RLDIC { 1817, 4, 1, 4, 392, 0, 1, PPCImpOpBase + 0, 876, 0, 0x8ULL }, // Inst #1817 = RLDCR_rec { 1816, 4, 1, 4, 297, 0, 0, PPCImpOpBase + 0, 876, 0, 0x8ULL }, // Inst #1816 = RLDCR { 1815, 4, 1, 4, 392, 0, 1, PPCImpOpBase + 0, 876, 0, 0x8ULL }, // Inst #1815 = RLDCL_rec { 1814, 4, 1, 4, 297, 0, 0, PPCImpOpBase + 0, 876, 0, 0x8ULL }, // Inst #1814 = RLDCL { 1813, 0, 0, 4, 410, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1813 = RFMCI { 1812, 0, 0, 4, 412, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1812 = RFID { 1811, 0, 0, 4, 411, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1811 = RFI { 1810, 1, 0, 4, 294, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1810 = RFEBB { 1809, 0, 0, 4, 410, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1809 = RFDI { 1808, 0, 0, 4, 410, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1808 = RFCI { 1807, 3, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 873, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1807 = RESTORE_WACC { 1806, 3, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 870, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1806 = RESTORE_UACC { 1805, 3, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 867, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #1805 = RESTORE_QUADWORD { 1804, 3, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 864, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1804 = RESTORE_CRBIT { 1803, 3, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 861, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1803 = RESTORE_CR { 1802, 3, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 858, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1802 = RESTORE_ACC { 1801, 0, 0, 4, 0, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1801 = PseudoEIEIO { 1800, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 758, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #1800 = PSTXVpc { 1799, 2, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 630, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1799 = PSTXVonlypc { 1798, 3, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 747, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1798 = PSTXVnopc { 1797, 3, 0, 8, 595, 0, 0, PPCImpOpBase + 0, 755, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1797 = PSTXVPpc { 1796, 2, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 753, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1796 = PSTXVPonlypc { 1795, 3, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 750, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1795 = PSTXVPnopc { 1794, 3, 0, 8, 595, 0, 0, PPCImpOpBase + 0, 750, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #1794 = PSTXVP { 1793, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 747, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #1793 = PSTXV { 1792, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 744, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1792 = PSTXSSPpc { 1791, 2, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 742, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1791 = PSTXSSPonlypc { 1790, 3, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 739, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1790 = PSTXSSPnopc { 1789, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 739, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1789 = PSTXSSP { 1788, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 744, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #1788 = PSTXSDpc { 1787, 2, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 742, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1787 = PSTXSDonlypc { 1786, 3, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 739, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1786 = PSTXSDnopc { 1785, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 739, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #1785 = PSTXSD { 1784, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 722, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #1784 = PSTWpc { 1783, 2, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 206, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1783 = PSTWonlypc { 1782, 3, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 713, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1782 = PSTWnopc { 1781, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 719, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #1781 = PSTW8pc { 1780, 2, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 217, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1780 = PSTW8onlypc { 1779, 3, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 716, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1779 = PSTW8nopc { 1778, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 716, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #1778 = PSTW8 { 1777, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 713, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #1777 = PSTW { 1776, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 722, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #1776 = PSTHpc { 1775, 2, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 206, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1775 = PSTHonlypc { 1774, 3, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 713, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1774 = PSTHnopc { 1773, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 719, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #1773 = PSTH8pc { 1772, 2, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 217, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1772 = PSTH8onlypc { 1771, 3, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 716, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1771 = PSTH8nopc { 1770, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 716, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #1770 = PSTH8 { 1769, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 713, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #1769 = PSTH { 1768, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 736, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #1768 = PSTFSpc { 1767, 2, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 734, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1767 = PSTFSonlypc { 1766, 3, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 731, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1766 = PSTFSnopc { 1765, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 731, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #1765 = PSTFS { 1764, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 728, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #1764 = PSTFDpc { 1763, 2, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 659, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1763 = PSTFDonlypc { 1762, 3, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 725, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1762 = PSTFDnopc { 1761, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 725, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #1761 = PSTFD { 1760, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 719, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #1760 = PSTDpc { 1759, 2, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 217, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1759 = PSTDonlypc { 1758, 3, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 716, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1758 = PSTDnopc { 1757, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 716, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #1757 = PSTD { 1756, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 722, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #1756 = PSTBpc { 1755, 2, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 206, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1755 = PSTBonlypc { 1754, 3, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 713, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1754 = PSTBnopc { 1753, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 719, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #1753 = PSTB8pc { 1752, 2, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 217, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1752 = PSTB8onlypc { 1751, 3, 0, 8, 40, 0, 0, PPCImpOpBase + 0, 716, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1751 = PSTB8nopc { 1750, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 716, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #1750 = PSTB8 { 1749, 3, 0, 8, 613, 0, 0, PPCImpOpBase + 0, 713, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #1749 = PSTB { 1748, 3, 2, 4, 0, 1, 1, PPCImpOpBase + 132, 181, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1748 = PROBED_STACKALLOC_64 { 1747, 3, 2, 4, 0, 1, 1, PPCImpOpBase + 61, 184, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1747 = PROBED_STACKALLOC_32 { 1746, 4, 1, 4, 0, 1, 1, PPCImpOpBase + 132, 447, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #1746 = PROBED_ALLOCA_64 { 1745, 4, 1, 4, 0, 1, 1, PPCImpOpBase + 61, 443, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #1745 = PROBED_ALLOCA_32 { 1744, 5, 2, 4, 0, 1, 1, PPCImpOpBase + 132, 853, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1744 = PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 { 1743, 5, 2, 4, 0, 1, 1, PPCImpOpBase + 61, 848, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1743 = PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 { 1742, 5, 2, 4, 0, 1, 1, PPCImpOpBase + 132, 843, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1742 = PREPARE_PROBED_ALLOCA_64 { 1741, 5, 2, 4, 0, 1, 1, PPCImpOpBase + 61, 838, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1741 = PREPARE_PROBED_ALLOCA_32 { 1740, 2, 2, 4, 0, 0, 0, PPCImpOpBase + 0, 259, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1740 = PPC32PICGOT { 1739, 1, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 171, 0, 0x0ULL }, // Inst #1739 = PPC32GOT { 1738, 2, 1, 4, 280, 0, 0, PPCImpOpBase + 0, 259, 0, 0x8ULL }, // Inst #1738 = POPCNTW { 1737, 2, 1, 4, 280, 0, 0, PPCImpOpBase + 0, 261, 0, 0x308ULL }, // Inst #1737 = POPCNTD { 1736, 2, 1, 4, 206, 0, 0, PPCImpOpBase + 0, 261, 0, 0x8ULL }, // Inst #1736 = POPCNTB8 { 1735, 2, 1, 4, 206, 0, 0, PPCImpOpBase + 0, 259, 0, 0x0ULL }, // Inst #1735 = POPCNTB { 1734, 7, 1, 8, 23, 0, 0, PPCImpOpBase + 0, 780, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1734 = PMXVI8GER4WSPP { 1733, 7, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 780, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1733 = PMXVI8GER4WPP { 1732, 6, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 774, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1732 = PMXVI8GER4W { 1731, 7, 1, 8, 569, 0, 0, PPCImpOpBase + 0, 767, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1731 = PMXVI8GER4SPP { 1730, 7, 1, 8, 568, 0, 0, PPCImpOpBase + 0, 767, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1730 = PMXVI8GER4PP { 1729, 6, 1, 8, 567, 0, 0, PPCImpOpBase + 0, 761, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1729 = PMXVI8GER4 { 1728, 7, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 780, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1728 = PMXVI4GER8WPP { 1727, 6, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 774, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1727 = PMXVI4GER8W { 1726, 7, 1, 8, 568, 0, 0, PPCImpOpBase + 0, 767, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1726 = PMXVI4GER8PP { 1725, 6, 1, 8, 567, 0, 0, PPCImpOpBase + 0, 761, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1725 = PMXVI4GER8 { 1724, 7, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 831, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1724 = PMXVI16GER2WPP { 1723, 6, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 774, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1723 = PMXVI16GER2W { 1722, 7, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 780, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1722 = PMXVI16GER2SWPP { 1721, 6, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 774, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1721 = PMXVI16GER2SW { 1720, 7, 1, 8, 568, 0, 0, PPCImpOpBase + 0, 767, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1720 = PMXVI16GER2SPP { 1719, 6, 1, 8, 567, 0, 0, PPCImpOpBase + 0, 761, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1719 = PMXVI16GER2S { 1718, 7, 1, 8, 568, 0, 0, PPCImpOpBase + 0, 767, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1718 = PMXVI16GER2PP { 1717, 6, 1, 8, 567, 0, 0, PPCImpOpBase + 0, 761, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1717 = PMXVI16GER2 { 1716, 6, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 825, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1716 = PMXVF64GERWPP { 1715, 6, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 825, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1715 = PMXVF64GERWPN { 1714, 6, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 825, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1714 = PMXVF64GERWNP { 1713, 6, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 825, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1713 = PMXVF64GERWNN { 1712, 5, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 820, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1712 = PMXVF64GERW { 1711, 6, 1, 8, 568, 0, 0, PPCImpOpBase + 0, 814, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1711 = PMXVF64GERPP { 1710, 6, 1, 8, 568, 0, 0, PPCImpOpBase + 0, 814, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1710 = PMXVF64GERPN { 1709, 6, 1, 8, 568, 0, 0, PPCImpOpBase + 0, 814, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1709 = PMXVF64GERNP { 1708, 6, 1, 8, 568, 0, 0, PPCImpOpBase + 0, 814, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1708 = PMXVF64GERNN { 1707, 5, 1, 8, 567, 0, 0, PPCImpOpBase + 0, 809, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1707 = PMXVF64GER { 1706, 6, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 803, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1706 = PMXVF32GERWPP { 1705, 6, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 803, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1705 = PMXVF32GERWPN { 1704, 6, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 803, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1704 = PMXVF32GERWNP { 1703, 6, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 803, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1703 = PMXVF32GERWNN { 1702, 5, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 798, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1702 = PMXVF32GERW { 1701, 6, 1, 8, 568, 0, 0, PPCImpOpBase + 0, 792, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1701 = PMXVF32GERPP { 1700, 6, 1, 8, 568, 0, 0, PPCImpOpBase + 0, 792, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1700 = PMXVF32GERPN { 1699, 6, 1, 8, 568, 0, 0, PPCImpOpBase + 0, 792, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1699 = PMXVF32GERNP { 1698, 6, 1, 8, 568, 0, 0, PPCImpOpBase + 0, 792, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1698 = PMXVF32GERNN { 1697, 5, 1, 8, 567, 0, 0, PPCImpOpBase + 0, 787, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1697 = PMXVF32GER { 1696, 7, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 780, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1696 = PMXVF16GER2WPP { 1695, 7, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 780, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1695 = PMXVF16GER2WPN { 1694, 7, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 780, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1694 = PMXVF16GER2WNP { 1693, 7, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 780, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1693 = PMXVF16GER2WNN { 1692, 6, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 774, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1692 = PMXVF16GER2W { 1691, 7, 1, 8, 568, 0, 0, PPCImpOpBase + 0, 767, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1691 = PMXVF16GER2PP { 1690, 7, 1, 8, 568, 0, 0, PPCImpOpBase + 0, 767, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1690 = PMXVF16GER2PN { 1689, 7, 1, 8, 568, 0, 0, PPCImpOpBase + 0, 767, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1689 = PMXVF16GER2NP { 1688, 7, 1, 8, 568, 0, 0, PPCImpOpBase + 0, 767, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1688 = PMXVF16GER2NN { 1687, 6, 1, 8, 567, 0, 0, PPCImpOpBase + 0, 761, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1687 = PMXVF16GER2 { 1686, 7, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 780, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1686 = PMXVBF16GER2WPP { 1685, 7, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 780, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1685 = PMXVBF16GER2WPN { 1684, 7, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 780, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1684 = PMXVBF16GER2WNP { 1683, 7, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 780, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1683 = PMXVBF16GER2WNN { 1682, 6, 1, 8, 5, 0, 0, PPCImpOpBase + 0, 774, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1682 = PMXVBF16GER2W { 1681, 7, 1, 8, 568, 0, 0, PPCImpOpBase + 0, 767, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1681 = PMXVBF16GER2PP { 1680, 7, 1, 8, 568, 0, 0, PPCImpOpBase + 0, 767, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1680 = PMXVBF16GER2PN { 1679, 7, 1, 8, 568, 0, 0, PPCImpOpBase + 0, 767, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1679 = PMXVBF16GER2NP { 1678, 7, 1, 8, 568, 0, 0, PPCImpOpBase + 0, 767, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1678 = PMXVBF16GER2NN { 1677, 6, 1, 8, 567, 0, 0, PPCImpOpBase + 0, 761, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1677 = PMXVBF16GER2 { 1676, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 758, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1676 = PLXVpc { 1675, 2, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 630, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1675 = PLXVonlypc { 1674, 3, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 747, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1674 = PLXVnopc { 1673, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 755, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1673 = PLXVPpc { 1672, 2, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 753, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1672 = PLXVPonlypc { 1671, 3, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 750, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1671 = PLXVPnopc { 1670, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 750, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1670 = PLXVP { 1669, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 747, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1669 = PLXV { 1668, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 744, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1668 = PLXSSPpc { 1667, 2, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 742, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1667 = PLXSSPonlypc { 1666, 3, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 739, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1666 = PLXSSPnopc { 1665, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 739, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1665 = PLXSSP { 1664, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 744, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1664 = PLXSDpc { 1663, 2, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 742, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1663 = PLXSDonlypc { 1662, 3, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 739, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1662 = PLXSDnopc { 1661, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 739, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1661 = PLXSD { 1660, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 722, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1660 = PLWZpc { 1659, 2, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1659 = PLWZonlypc { 1658, 3, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 713, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1658 = PLWZnopc { 1657, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 719, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1657 = PLWZ8pc { 1656, 2, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 217, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1656 = PLWZ8onlypc { 1655, 3, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 716, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1655 = PLWZ8nopc { 1654, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 716, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1654 = PLWZ8 { 1653, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 713, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1653 = PLWZ { 1652, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 722, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1652 = PLWApc { 1651, 2, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1651 = PLWAonlypc { 1650, 3, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 713, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1650 = PLWAnopc { 1649, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 719, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1649 = PLWA8pc { 1648, 2, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 217, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1648 = PLWA8onlypc { 1647, 3, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 716, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1647 = PLWA8nopc { 1646, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 716, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1646 = PLWA8 { 1645, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 713, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1645 = PLWA { 1644, 2, 1, 8, 621, 0, 0, PPCImpOpBase + 0, 217, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x80ULL }, // Inst #1644 = PLI8 { 1643, 2, 1, 8, 621, 0, 0, PPCImpOpBase + 0, 206, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x80ULL }, // Inst #1643 = PLI { 1642, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 722, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1642 = PLHZpc { 1641, 2, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1641 = PLHZonlypc { 1640, 3, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 713, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1640 = PLHZnopc { 1639, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 719, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1639 = PLHZ8pc { 1638, 2, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 217, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1638 = PLHZ8onlypc { 1637, 3, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 716, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1637 = PLHZ8nopc { 1636, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 716, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1636 = PLHZ8 { 1635, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 713, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1635 = PLHZ { 1634, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 722, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1634 = PLHApc { 1633, 2, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1633 = PLHAonlypc { 1632, 3, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 713, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1632 = PLHAnopc { 1631, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 719, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1631 = PLHA8pc { 1630, 2, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 217, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1630 = PLHA8onlypc { 1629, 3, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 716, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1629 = PLHA8nopc { 1628, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 716, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1628 = PLHA8 { 1627, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 713, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1627 = PLHA { 1626, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 736, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1626 = PLFSpc { 1625, 2, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 734, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1625 = PLFSonlypc { 1624, 3, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 731, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1624 = PLFSnopc { 1623, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 731, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1623 = PLFS { 1622, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 728, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1622 = PLFDpc { 1621, 2, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 659, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1621 = PLFDonlypc { 1620, 3, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 725, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1620 = PLFDnopc { 1619, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 725, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1619 = PLFD { 1618, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 719, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1618 = PLDpc { 1617, 2, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 217, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1617 = PLDonlypc { 1616, 3, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 716, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1616 = PLDnopc { 1615, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 716, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1615 = PLD { 1614, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 722, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1614 = PLBZpc { 1613, 2, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1613 = PLBZonlypc { 1612, 3, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 713, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1612 = PLBZnopc { 1611, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 719, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1611 = PLBZ8pc { 1610, 2, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 217, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1610 = PLBZ8onlypc { 1609, 3, 1, 8, 40, 0, 0, PPCImpOpBase + 0, 716, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1609 = PLBZ8nopc { 1608, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 716, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1608 = PLBZ8 { 1607, 3, 1, 8, 556, 0, 0, PPCImpOpBase + 0, 713, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #1607 = PLBZ { 1606, 2, 1, 8, 2, 0, 0, PPCImpOpBase + 0, 206, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1606 = PLApc { 1605, 2, 1, 8, 2, 0, 0, PPCImpOpBase + 0, 217, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1605 = PLA8pc { 1604, 3, 1, 8, 2, 0, 0, PPCImpOpBase + 0, 208, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1604 = PLA8 { 1603, 3, 1, 8, 2, 0, 0, PPCImpOpBase + 0, 245, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1603 = PLA { 1602, 3, 1, 4, 449, 0, 0, PPCImpOpBase + 0, 228, 0, 0x0ULL }, // Inst #1602 = PEXTD { 1601, 3, 1, 4, 449, 0, 0, PPCImpOpBase + 0, 228, 0, 0x0ULL }, // Inst #1601 = PDEPD { 1600, 3, 1, 8, 620, 0, 0, PPCImpOpBase + 0, 655, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1600 = PADDIpc { 1599, 3, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 208, 0, 0x0ULL }, // Inst #1599 = PADDIdtprel { 1598, 3, 1, 8, 620, 0, 0, PPCImpOpBase + 0, 710, 0, 0x80ULL }, // Inst #1598 = PADDI8pc { 1597, 3, 1, 8, 620, 0, 0, PPCImpOpBase + 0, 208, 0, 0x80ULL }, // Inst #1597 = PADDI8 { 1596, 3, 1, 8, 620, 0, 0, PPCImpOpBase + 0, 245, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1596 = PADDI { 1595, 3, 1, 4, 201, 0, 1, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1595 = OR_rec { 1594, 3, 1, 4, 508, 0, 0, PPCImpOpBase + 0, 181, 0, 0x8ULL }, // Inst #1594 = ORIS8 { 1593, 3, 1, 4, 508, 0, 0, PPCImpOpBase + 0, 184, 0, 0x8ULL }, // Inst #1593 = ORIS { 1592, 3, 1, 4, 508, 0, 0, PPCImpOpBase + 0, 181, 0, 0x8ULL }, // Inst #1592 = ORI8 { 1591, 3, 1, 4, 508, 0, 0, PPCImpOpBase + 0, 184, 0, 0x8ULL }, // Inst #1591 = ORI { 1590, 3, 1, 4, 198, 0, 1, PPCImpOpBase + 0, 222, 0, 0x8ULL }, // Inst #1590 = ORC_rec { 1589, 3, 1, 4, 198, 0, 1, PPCImpOpBase + 0, 228, 0, 0x8ULL }, // Inst #1589 = ORC8_rec { 1588, 3, 1, 4, 198, 0, 0, PPCImpOpBase + 0, 228, 0, 0x8ULL }, // Inst #1588 = ORC8 { 1587, 3, 1, 4, 198, 0, 0, PPCImpOpBase + 0, 222, 0, 0x8ULL }, // Inst #1587 = ORC { 1586, 3, 1, 4, 201, 0, 1, PPCImpOpBase + 0, 228, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1586 = OR8_rec { 1585, 3, 1, 4, 201, 0, 0, PPCImpOpBase + 0, 228, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1585 = OR8 { 1584, 3, 1, 4, 201, 0, 0, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1584 = OR { 1583, 3, 1, 4, 198, 0, 1, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1583 = NOR_rec { 1582, 3, 1, 4, 198, 0, 1, PPCImpOpBase + 0, 228, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1582 = NOR8_rec { 1581, 3, 1, 4, 198, 0, 0, PPCImpOpBase + 0, 228, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1581 = NOR8 { 1580, 3, 1, 4, 198, 0, 0, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1580 = NOR { 1579, 0, 0, 4, 418, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL }, // Inst #1579 = NOP_GT_PWR7 { 1578, 0, 0, 4, 418, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL }, // Inst #1578 = NOP_GT_PWR6 { 1577, 0, 0, 4, 509, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL }, // Inst #1577 = NOP { 1576, 2, 1, 4, 508, 0, 1, PPCImpOpBase + 0, 259, 0, 0x8ULL }, // Inst #1576 = NEG_rec { 1575, 2, 1, 4, 533, 0, 2, PPCImpOpBase + 3, 259, 0, 0x8ULL }, // Inst #1575 = NEGO_rec { 1574, 2, 1, 4, 498, 0, 1, PPCImpOpBase + 2, 259, 0, 0x8ULL }, // Inst #1574 = NEGO { 1573, 2, 1, 4, 508, 0, 1, PPCImpOpBase + 0, 261, 0, 0x8ULL }, // Inst #1573 = NEG8_rec { 1572, 2, 1, 4, 533, 0, 2, PPCImpOpBase + 3, 261, 0, 0x8ULL }, // Inst #1572 = NEG8O_rec { 1571, 2, 1, 4, 498, 0, 1, PPCImpOpBase + 2, 261, 0, 0x8ULL }, // Inst #1571 = NEG8O { 1570, 2, 1, 4, 498, 0, 0, PPCImpOpBase + 0, 261, 0, 0x8ULL }, // Inst #1570 = NEG8 { 1569, 2, 1, 4, 498, 0, 0, PPCImpOpBase + 0, 259, 0, 0x8ULL }, // Inst #1569 = NEG { 1568, 0, 0, 4, 616, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1568 = NAP { 1567, 3, 1, 4, 198, 0, 1, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1567 = NAND_rec { 1566, 3, 1, 4, 198, 0, 1, PPCImpOpBase + 0, 228, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1566 = NAND8_rec { 1565, 3, 1, 4, 198, 0, 0, PPCImpOpBase + 0, 228, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1565 = NAND8 { 1564, 3, 1, 4, 198, 0, 0, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1564 = NAND { 1563, 0, 0, 4, 0, 0, 1, PPCImpOpBase + 204, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #1563 = MovePCtoLR8 { 1562, 0, 0, 4, 0, 0, 1, PPCImpOpBase + 203, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #1562 = MovePCtoLR { 1561, 0, 0, 4, 0, 0, 1, PPCImpOpBase + 203, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #1561 = MoveGOTtoLR { 1560, 3, 1, 4, 150, 0, 1, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1560 = MULLW_rec { 1559, 3, 1, 4, 150, 0, 2, PPCImpOpBase + 3, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1559 = MULLWO_rec { 1558, 3, 1, 4, 312, 0, 1, PPCImpOpBase + 2, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1558 = MULLWO { 1557, 3, 1, 4, 312, 0, 0, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1557 = MULLW { 1556, 3, 1, 4, 149, 0, 0, PPCImpOpBase + 0, 181, 0, 0x8ULL }, // Inst #1556 = MULLI8 { 1555, 3, 1, 4, 149, 0, 0, PPCImpOpBase + 0, 184, 0, 0x8ULL }, // Inst #1555 = MULLI { 1554, 3, 1, 4, 152, 0, 1, PPCImpOpBase + 0, 228, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1554 = MULLD_rec { 1553, 3, 1, 4, 152, 0, 2, PPCImpOpBase + 3, 228, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1553 = MULLDO_rec { 1552, 3, 1, 4, 314, 0, 1, PPCImpOpBase + 2, 228, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1552 = MULLDO { 1551, 3, 1, 4, 314, 0, 0, PPCImpOpBase + 0, 228, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1551 = MULLD { 1550, 3, 1, 4, 150, 0, 1, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1550 = MULHW_rec { 1549, 3, 1, 4, 151, 0, 1, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1549 = MULHWU_rec { 1548, 3, 1, 4, 313, 0, 0, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1548 = MULHWU { 1547, 3, 1, 4, 312, 0, 0, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1547 = MULHW { 1546, 3, 1, 4, 150, 0, 1, PPCImpOpBase + 0, 228, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1546 = MULHD_rec { 1545, 3, 1, 4, 151, 0, 1, PPCImpOpBase + 0, 228, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1545 = MULHDU_rec { 1544, 3, 1, 4, 313, 0, 0, PPCImpOpBase + 0, 228, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1544 = MULHDU { 1543, 3, 1, 4, 312, 0, 0, PPCImpOpBase + 0, 228, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1543 = MULHD { 1542, 2, 1, 4, 259, 0, 0, PPCImpOpBase + 0, 708, 0, 0x0ULL }, // Inst #1542 = MTVSRWZ { 1541, 2, 1, 4, 578, 0, 0, PPCImpOpBase + 0, 697, 0, 0x0ULL }, // Inst #1541 = MTVSRWS { 1540, 2, 1, 4, 471, 0, 0, PPCImpOpBase + 0, 699, 0, 0x0ULL }, // Inst #1540 = MTVSRWM { 1539, 2, 1, 4, 259, 0, 0, PPCImpOpBase + 0, 708, 0, 0x0ULL }, // Inst #1539 = MTVSRWA { 1538, 2, 1, 4, 471, 0, 0, PPCImpOpBase + 0, 699, 0, 0x0ULL }, // Inst #1538 = MTVSRQM { 1537, 2, 1, 4, 471, 0, 0, PPCImpOpBase + 0, 699, 0, 0x0ULL }, // Inst #1537 = MTVSRHM { 1536, 2, 1, 4, 471, 0, 0, PPCImpOpBase + 0, 699, 0, 0x0ULL }, // Inst #1536 = MTVSRDM { 1535, 3, 1, 4, 262, 0, 0, PPCImpOpBase + 0, 705, 0, 0x0ULL }, // Inst #1535 = MTVSRDD { 1534, 2, 1, 4, 259, 0, 0, PPCImpOpBase + 0, 703, 0, 0x0ULL }, // Inst #1534 = MTVSRD { 1533, 2, 1, 4, 468, 0, 0, PPCImpOpBase + 0, 701, 0, 0x0ULL }, // Inst #1533 = MTVSRBMI { 1532, 2, 1, 4, 471, 0, 0, PPCImpOpBase + 0, 699, 0, 0x0ULL }, // Inst #1532 = MTVSRBM { 1531, 1, 0, 4, 236, 0, 0, PPCImpOpBase + 0, 671, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1531 = MTVSCR { 1530, 2, 1, 4, 259, 0, 0, PPCImpOpBase + 0, 697, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1530 = MTVRWZ { 1529, 2, 1, 4, 259, 0, 0, PPCImpOpBase + 0, 697, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1529 = MTVRWA { 1528, 2, 1, 4, 554, 0, 0, PPCImpOpBase + 0, 695, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xaULL }, // Inst #1528 = MTVRSAVEv { 1527, 1, 0, 4, 554, 0, 0, PPCImpOpBase + 0, 171, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xaULL }, // Inst #1527 = MTVRSAVE { 1526, 2, 1, 4, 259, 0, 0, PPCImpOpBase + 0, 693, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1526 = MTVRD { 1525, 1, 0, 4, 382, 0, 0, PPCImpOpBase + 0, 171, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xaULL }, // Inst #1525 = MTUDSCR { 1524, 2, 0, 4, 415, 0, 0, PPCImpOpBase + 0, 259, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1524 = MTSRIN { 1523, 2, 0, 4, 553, 0, 0, PPCImpOpBase + 0, 206, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1523 = MTSR { 1522, 2, 0, 4, 382, 0, 0, PPCImpOpBase + 0, 678, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1522 = MTSPR8 { 1521, 2, 0, 4, 382, 0, 0, PPCImpOpBase + 0, 676, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1521 = MTSPR { 1520, 2, 0, 4, 377, 0, 0, PPCImpOpBase + 0, 676, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1520 = MTPMR { 1519, 2, 1, 4, 299, 0, 0, PPCImpOpBase + 0, 691, 0|(1ULL<<MCID::ExtraDefRegAllocReq), 0x21ULL }, // Inst #1519 = MTOCRF8 { 1518, 2, 1, 4, 299, 0, 0, PPCImpOpBase + 0, 689, 0|(1ULL<<MCID::ExtraDefRegAllocReq), 0x21ULL }, // Inst #1518 = MTOCRF { 1517, 2, 0, 4, 381, 0, 0, PPCImpOpBase + 0, 206, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1517 = MTMSRD { 1516, 2, 0, 4, 380, 0, 0, PPCImpOpBase + 0, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1516 = MTMSR { 1515, 1, 0, 4, 104, 0, 1, PPCImpOpBase + 204, 172, 0, 0x9ULL }, // Inst #1515 = MTLR8 { 1514, 1, 0, 4, 104, 0, 1, PPCImpOpBase + 203, 171, 0, 0x9ULL }, // Inst #1514 = MTLR { 1513, 2, 0, 4, 186, 0, 1, PPCImpOpBase + 134, 687, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL }, // Inst #1513 = MTFSFb { 1512, 4, 0, 4, 185, 0, 1, PPCImpOpBase + 131, 680, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1512 = MTFSF_rec { 1511, 2, 0, 4, 536, 0, 1, PPCImpOpBase + 134, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1511 = MTFSFIb { 1510, 3, 0, 4, 536, 0, 1, PPCImpOpBase + 131, 684, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1510 = MTFSFI_rec { 1509, 3, 0, 4, 536, 0, 1, PPCImpOpBase + 134, 684, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1509 = MTFSFI { 1508, 4, 0, 4, 185, 0, 1, PPCImpOpBase + 134, 680, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1508 = MTFSF { 1507, 1, 0, 4, 272, 0, 1, PPCImpOpBase + 134, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL }, // Inst #1507 = MTFSB1 { 1506, 1, 0, 4, 531, 0, 1, PPCImpOpBase + 134, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL }, // Inst #1506 = MTFSB0 { 1505, 2, 0, 4, 417, 0, 0, PPCImpOpBase + 0, 206, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1505 = MTDCR { 1504, 1, 0, 4, 104, 0, 1, PPCImpOpBase + 63, 171, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL }, // Inst #1504 = MTCTRloop { 1503, 1, 0, 4, 104, 0, 1, PPCImpOpBase + 64, 172, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL }, // Inst #1503 = MTCTR8loop { 1502, 1, 0, 4, 104, 0, 1, PPCImpOpBase + 64, 172, 0, 0x9ULL }, // Inst #1502 = MTCTR8 { 1501, 1, 0, 4, 104, 0, 1, PPCImpOpBase + 63, 171, 0, 0x9ULL }, // Inst #1501 = MTCTR { 1500, 2, 0, 4, 196, 0, 0, PPCImpOpBase + 0, 678, 0|(1ULL<<MCID::ExtraDefRegAllocReq), 0x20ULL }, // Inst #1500 = MTCRF8 { 1499, 2, 0, 4, 196, 0, 0, PPCImpOpBase + 0, 676, 0|(1ULL<<MCID::ExtraDefRegAllocReq), 0x20ULL }, // Inst #1499 = MTCRF { 1498, 0, 0, 4, 422, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1498 = MSYNC { 1497, 0, 0, 4, 344, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1497 = MSGSYNC { 1496, 3, 1, 4, 387, 0, 0, PPCImpOpBase + 0, 222, 0, 0x0ULL }, // Inst #1496 = MODUW { 1495, 3, 1, 4, 387, 0, 0, PPCImpOpBase + 0, 228, 0, 0x8ULL }, // Inst #1495 = MODUD { 1494, 3, 1, 4, 384, 0, 0, PPCImpOpBase + 0, 222, 0, 0x0ULL }, // Inst #1494 = MODSW { 1493, 3, 1, 4, 387, 0, 0, PPCImpOpBase + 0, 228, 0, 0x8ULL }, // Inst #1493 = MODSD { 1492, 2, 1, 4, 259, 0, 0, PPCImpOpBase + 0, 674, 0, 0x200ULL }, // Inst #1492 = MFVSRWZ { 1491, 2, 1, 4, 578, 0, 0, PPCImpOpBase + 0, 665, 0, 0x0ULL }, // Inst #1491 = MFVSRLD { 1490, 2, 1, 4, 259, 0, 0, PPCImpOpBase + 0, 672, 0, 0x0ULL }, // Inst #1490 = MFVSRD { 1489, 1, 1, 4, 235, 0, 0, PPCImpOpBase + 0, 671, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1489 = MFVSCR { 1488, 2, 1, 4, 259, 0, 0, PPCImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1488 = MFVRWZ { 1487, 2, 1, 4, 375, 0, 0, PPCImpOpBase + 0, 667, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL }, // Inst #1487 = MFVRSAVEv { 1486, 1, 1, 4, 375, 0, 0, PPCImpOpBase + 0, 171, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL }, // Inst #1486 = MFVRSAVE { 1485, 2, 1, 4, 259, 0, 0, PPCImpOpBase + 0, 665, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1485 = MFVRD { 1484, 1, 1, 4, 378, 0, 0, PPCImpOpBase + 0, 171, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL }, // Inst #1484 = MFUDSCR { 1483, 1, 1, 4, 562, 0, 0, PPCImpOpBase + 0, 172, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL }, // Inst #1483 = MFTB8 { 1482, 2, 1, 4, 208, 0, 0, PPCImpOpBase + 0, 206, 0, 0x0ULL }, // Inst #1482 = MFTB { 1481, 2, 1, 4, 112, 0, 0, PPCImpOpBase + 0, 259, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1481 = MFSRIN { 1480, 2, 1, 4, 561, 0, 0, PPCImpOpBase + 0, 206, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1480 = MFSR { 1479, 2, 1, 4, 378, 0, 0, PPCImpOpBase + 0, 217, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1479 = MFSPR8 { 1478, 2, 1, 4, 378, 0, 0, PPCImpOpBase + 0, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1478 = MFSPR { 1477, 2, 1, 4, 376, 0, 0, PPCImpOpBase + 0, 206, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1477 = MFPMR { 1476, 2, 1, 4, 181, 0, 0, PPCImpOpBase + 0, 663, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x21ULL }, // Inst #1476 = MFOCRF8 { 1475, 2, 1, 4, 181, 0, 0, PPCImpOpBase + 0, 661, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x21ULL }, // Inst #1475 = MFOCRF { 1474, 1, 1, 4, 379, 0, 0, PPCImpOpBase + 0, 171, 0, 0x0ULL }, // Inst #1474 = MFMSR { 1473, 1, 1, 4, 103, 1, 0, PPCImpOpBase + 204, 172, 0, 0x9ULL }, // Inst #1473 = MFLR8 { 1472, 1, 1, 4, 103, 1, 0, PPCImpOpBase + 203, 171, 0, 0x9ULL }, // Inst #1472 = MFLR { 1471, 1, 1, 4, 529, 1, 1, PPCImpOpBase + 135, 658, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1471 = MFFS_rec { 1470, 1, 1, 4, 529, 1, 0, PPCImpOpBase + 134, 658, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL }, // Inst #1470 = MFFSL { 1469, 2, 1, 4, 530, 1, 0, PPCImpOpBase + 134, 659, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL }, // Inst #1469 = MFFSCRNI { 1468, 2, 1, 4, 273, 1, 0, PPCImpOpBase + 134, 345, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL }, // Inst #1468 = MFFSCRN { 1467, 1, 1, 4, 394, 1, 0, PPCImpOpBase + 134, 658, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL }, // Inst #1467 = MFFSCE { 1466, 2, 1, 4, 530, 1, 0, PPCImpOpBase + 134, 659, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL }, // Inst #1466 = MFFSCDRNI { 1465, 2, 1, 4, 273, 1, 0, PPCImpOpBase + 134, 345, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL }, // Inst #1465 = MFFSCDRN { 1464, 1, 1, 4, 529, 1, 0, PPCImpOpBase + 134, 658, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL }, // Inst #1464 = MFFS { 1463, 2, 1, 4, 416, 0, 0, PPCImpOpBase + 0, 206, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1463 = MFDCR { 1462, 1, 1, 4, 103, 1, 0, PPCImpOpBase + 64, 172, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL }, // Inst #1462 = MFCTR8 { 1461, 1, 1, 4, 103, 1, 0, PPCImpOpBase + 63, 171, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL }, // Inst #1461 = MFCTR { 1460, 1, 1, 4, 105, 0, 0, PPCImpOpBase + 0, 172, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x20ULL }, // Inst #1460 = MFCR8 { 1459, 1, 1, 4, 105, 0, 0, PPCImpOpBase + 0, 171, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x20ULL }, // Inst #1459 = MFCR { 1458, 3, 1, 4, 619, 0, 0, PPCImpOpBase + 0, 655, 0, 0x1ULL }, // Inst #1458 = MFBHRBE { 1457, 1, 1, 4, 291, 0, 0, PPCImpOpBase + 0, 654, 0, 0x0ULL }, // Inst #1457 = MCRXRX { 1456, 2, 1, 4, 391, 0, 0, PPCImpOpBase + 0, 652, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1456 = MCRFS { 1455, 2, 1, 4, 106, 0, 0, PPCImpOpBase + 0, 652, 0, 0x21ULL }, // Inst #1455 = MCRF { 1454, 1, 0, 4, 413, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1454 = MBAR { 1453, 4, 1, 4, 311, 0, 0, PPCImpOpBase + 0, 644, 0, 0x8ULL }, // Inst #1453 = MADDLD8 { 1452, 4, 1, 4, 311, 0, 0, PPCImpOpBase + 0, 648, 0, 0x8ULL }, // Inst #1452 = MADDLD { 1451, 4, 1, 4, 311, 0, 0, PPCImpOpBase + 0, 644, 0, 0x8ULL }, // Inst #1451 = MADDHDU { 1450, 4, 1, 4, 311, 0, 0, PPCImpOpBase + 0, 644, 0, 0x8ULL }, // Inst #1450 = MADDHD { 1449, 3, 1, 4, 334, 0, 0, PPCImpOpBase + 0, 627, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1449 = LXVX { 1448, 3, 1, 4, 334, 0, 0, PPCImpOpBase + 0, 627, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1448 = LXVWSX { 1447, 3, 1, 4, 113, 0, 0, PPCImpOpBase + 0, 627, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1447 = LXVW4X { 1446, 3, 1, 4, 552, 0, 0, PPCImpOpBase + 0, 627, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1446 = LXVRWX { 1445, 3, 1, 4, 15, 0, 0, PPCImpOpBase + 0, 632, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1445 = LXVRLL { 1444, 3, 1, 4, 15, 0, 0, PPCImpOpBase + 0, 632, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1444 = LXVRL { 1443, 3, 1, 4, 552, 0, 0, PPCImpOpBase + 0, 627, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1443 = LXVRHX { 1442, 3, 1, 4, 552, 0, 0, PPCImpOpBase + 0, 627, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1442 = LXVRDX { 1441, 3, 1, 4, 552, 0, 0, PPCImpOpBase + 0, 627, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1441 = LXVRBX { 1440, 3, 1, 4, 560, 0, 0, PPCImpOpBase + 0, 641, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1440 = LXVPX { 1439, 3, 1, 4, 40, 0, 0, PPCImpOpBase + 0, 638, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1439 = LXVPRLL { 1438, 3, 1, 4, 40, 0, 0, PPCImpOpBase + 0, 638, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1438 = LXVPRL { 1437, 3, 1, 4, 559, 0, 0, PPCImpOpBase + 0, 635, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1437 = LXVP { 1436, 3, 1, 4, 333, 0, 0, PPCImpOpBase + 0, 632, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1436 = LXVLL { 1435, 3, 1, 4, 333, 0, 0, PPCImpOpBase + 0, 632, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1435 = LXVL { 1434, 2, 1, 4, 573, 0, 0, PPCImpOpBase + 0, 630, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1434 = LXVKQ { 1433, 3, 1, 4, 365, 0, 0, PPCImpOpBase + 0, 627, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1433 = LXVH8X { 1432, 3, 1, 4, 113, 0, 0, PPCImpOpBase + 0, 627, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1432 = LXVDSX { 1431, 3, 1, 4, 335, 0, 0, PPCImpOpBase + 0, 627, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1431 = LXVD2X { 1430, 3, 1, 4, 213, 0, 0, PPCImpOpBase + 0, 627, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1430 = LXVB16X { 1429, 3, 1, 4, 547, 0, 0, PPCImpOpBase + 0, 624, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1429 = LXV { 1428, 3, 1, 4, 363, 0, 0, PPCImpOpBase + 0, 219, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1428 = LXSSPX { 1427, 3, 1, 4, 558, 0, 0, PPCImpOpBase + 0, 621, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1427 = LXSSP { 1426, 3, 1, 4, 213, 0, 0, PPCImpOpBase + 0, 203, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1426 = LXSIWZX { 1425, 3, 1, 4, 360, 0, 0, PPCImpOpBase + 0, 203, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1425 = LXSIWAX { 1424, 3, 1, 4, 334, 0, 0, PPCImpOpBase + 0, 203, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1424 = LXSIHZX { 1423, 3, 1, 4, 334, 0, 0, PPCImpOpBase + 0, 203, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1423 = LXSIBZX { 1422, 3, 1, 4, 335, 0, 0, PPCImpOpBase + 0, 203, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1422 = LXSDX { 1421, 3, 1, 4, 547, 0, 0, PPCImpOpBase + 0, 621, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1421 = LXSD { 1420, 3, 1, 4, 542, 0, 0, PPCImpOpBase + 0, 618, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1420 = LWZtocL { 1419, 3, 1, 4, 542, 0, 0, PPCImpOpBase + 0, 615, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1419 = LWZtoc { 1418, 3, 1, 4, 340, 0, 0, PPCImpOpBase + 0, 557, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1418 = LWZXTLS_32 { 1417, 3, 1, 4, 340, 0, 0, PPCImpOpBase + 0, 554, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1417 = LWZXTLS_ { 1416, 3, 1, 4, 340, 0, 0, PPCImpOpBase + 0, 554, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1416 = LWZXTLS { 1415, 3, 1, 4, 340, 0, 0, PPCImpOpBase + 0, 551, 0|(1ULL<<MCID::MayLoad), 0x250ULL }, // Inst #1415 = LWZX8 { 1414, 3, 1, 4, 340, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::MayLoad), 0x250ULL }, // Inst #1414 = LWZX { 1413, 4, 2, 4, 356, 0, 0, PPCImpOpBase + 0, 547, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1413 = LWZUX8 { 1412, 4, 2, 4, 356, 0, 0, PPCImpOpBase + 0, 543, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1412 = LWZUX { 1411, 4, 2, 4, 355, 0, 0, PPCImpOpBase + 0, 539, 0|(1ULL<<MCID::MayLoad), 0x10ULL }, // Inst #1411 = LWZU8 { 1410, 4, 2, 4, 355, 0, 0, PPCImpOpBase + 0, 535, 0|(1ULL<<MCID::MayLoad), 0x10ULL }, // Inst #1410 = LWZU { 1409, 3, 1, 4, 555, 0, 0, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1409 = LWZCIX { 1408, 3, 1, 4, 540, 0, 0, PPCImpOpBase + 0, 521, 0|(1ULL<<MCID::MayLoad), 0x210ULL }, // Inst #1408 = LWZ8 { 1407, 3, 1, 4, 540, 0, 0, PPCImpOpBase + 0, 200, 0|(1ULL<<MCID::MayLoad), 0x210ULL }, // Inst #1407 = LWZ { 1406, 3, 1, 4, 225, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1406 = LWEPX { 1405, 3, 1, 4, 111, 0, 0, PPCImpOpBase + 0, 551, 0|(1ULL<<MCID::MayLoad), 0x250ULL }, // Inst #1405 = LWBRX8 { 1404, 3, 1, 4, 111, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::MayLoad), 0x250ULL }, // Inst #1404 = LWBRX { 1403, 3, 1, 4, 124, 0, 0, PPCImpOpBase + 0, 200, 0|(1ULL<<MCID::MayLoad), 0x114ULL }, // Inst #1403 = LWA_32 { 1402, 3, 1, 4, 123, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::MayLoad), 0x154ULL }, // Inst #1402 = LWAX_32 { 1401, 3, 1, 4, 222, 0, 0, PPCImpOpBase + 0, 557, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1401 = LWAXTLS_32 { 1400, 3, 1, 4, 222, 0, 0, PPCImpOpBase + 0, 554, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1400 = LWAXTLS_ { 1399, 3, 1, 4, 222, 0, 0, PPCImpOpBase + 0, 554, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1399 = LWAXTLS { 1398, 3, 1, 4, 123, 0, 0, PPCImpOpBase + 0, 551, 0|(1ULL<<MCID::MayLoad), 0x154ULL }, // Inst #1398 = LWAX { 1397, 4, 2, 4, 126, 0, 0, PPCImpOpBase + 0, 547, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1397 = LWAUX { 1396, 3, 1, 4, 403, 0, 0, PPCImpOpBase + 0, 184, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x40ULL }, // Inst #1396 = LWAT { 1395, 3, 1, 4, 109, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1395 = LWARXL { 1394, 3, 1, 4, 109, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1394 = LWARX { 1393, 3, 1, 4, 124, 0, 0, PPCImpOpBase + 0, 521, 0|(1ULL<<MCID::MayLoad), 0x114ULL }, // Inst #1393 = LWA { 1392, 3, 1, 4, 212, 0, 0, PPCImpOpBase + 0, 612, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1392 = LVXL { 1391, 3, 1, 4, 212, 0, 0, PPCImpOpBase + 0, 612, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1391 = LVX { 1390, 3, 1, 4, 322, 0, 0, PPCImpOpBase + 0, 612, 0, 0x50ULL }, // Inst #1390 = LVSR { 1389, 3, 1, 4, 322, 0, 0, PPCImpOpBase + 0, 612, 0, 0x50ULL }, // Inst #1389 = LVSL { 1388, 3, 1, 4, 212, 0, 0, PPCImpOpBase + 0, 612, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1388 = LVEWX { 1387, 3, 1, 4, 212, 0, 0, PPCImpOpBase + 0, 612, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1387 = LVEHX { 1386, 3, 1, 4, 212, 0, 0, PPCImpOpBase + 0, 612, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1386 = LVEBX { 1385, 3, 1, 4, 118, 0, 0, PPCImpOpBase + 0, 184, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1385 = LSWI { 1384, 3, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 609, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #1384 = LQX_PSEUDO { 1383, 3, 1, 4, 48, 0, 0, PPCImpOpBase + 0, 609, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1383 = LQARXL { 1382, 3, 1, 4, 48, 0, 0, PPCImpOpBase + 0, 609, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1382 = LQARX { 1381, 3, 1, 4, 215, 0, 0, PPCImpOpBase + 0, 606, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #1381 = LQ { 1380, 3, 1, 4, 108, 0, 0, PPCImpOpBase + 0, 200, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1380 = LMW { 1379, 2, 1, 4, 498, 0, 0, PPCImpOpBase + 0, 217, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x108ULL }, // Inst #1379 = LIS8 { 1378, 2, 1, 4, 498, 0, 0, PPCImpOpBase + 0, 206, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x108ULL }, // Inst #1378 = LIS { 1377, 2, 1, 4, 498, 0, 0, PPCImpOpBase + 0, 217, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x108ULL }, // Inst #1377 = LI8 { 1376, 2, 1, 4, 498, 0, 0, PPCImpOpBase + 0, 206, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x108ULL }, // Inst #1376 = LI { 1375, 3, 1, 4, 340, 0, 0, PPCImpOpBase + 0, 557, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1375 = LHZXTLS_32 { 1374, 3, 1, 4, 340, 0, 0, PPCImpOpBase + 0, 554, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1374 = LHZXTLS_ { 1373, 3, 1, 4, 340, 0, 0, PPCImpOpBase + 0, 554, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1373 = LHZXTLS { 1372, 3, 1, 4, 340, 0, 0, PPCImpOpBase + 0, 551, 0|(1ULL<<MCID::MayLoad), 0x350ULL }, // Inst #1372 = LHZX8 { 1371, 3, 1, 4, 340, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::MayLoad), 0x350ULL }, // Inst #1371 = LHZX { 1370, 4, 2, 4, 356, 0, 0, PPCImpOpBase + 0, 547, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1370 = LHZUX8 { 1369, 4, 2, 4, 356, 0, 0, PPCImpOpBase + 0, 543, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1369 = LHZUX { 1368, 4, 2, 4, 355, 0, 0, PPCImpOpBase + 0, 539, 0|(1ULL<<MCID::MayLoad), 0x10ULL }, // Inst #1368 = LHZU8 { 1367, 4, 2, 4, 355, 0, 0, PPCImpOpBase + 0, 535, 0|(1ULL<<MCID::MayLoad), 0x10ULL }, // Inst #1367 = LHZU { 1366, 3, 1, 4, 555, 0, 0, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1366 = LHZCIX { 1365, 3, 1, 4, 540, 0, 0, PPCImpOpBase + 0, 521, 0|(1ULL<<MCID::MayLoad), 0x310ULL }, // Inst #1365 = LHZ8 { 1364, 3, 1, 4, 540, 0, 0, PPCImpOpBase + 0, 200, 0|(1ULL<<MCID::MayLoad), 0x310ULL }, // Inst #1364 = LHZ { 1363, 3, 1, 4, 225, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1363 = LHEPX { 1362, 3, 1, 4, 111, 0, 0, PPCImpOpBase + 0, 551, 0|(1ULL<<MCID::MayLoad), 0x250ULL }, // Inst #1362 = LHBRX8 { 1361, 3, 1, 4, 111, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::MayLoad), 0x250ULL }, // Inst #1361 = LHBRX { 1360, 3, 1, 4, 222, 0, 0, PPCImpOpBase + 0, 557, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1360 = LHAXTLS_32 { 1359, 3, 1, 4, 222, 0, 0, PPCImpOpBase + 0, 554, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1359 = LHAXTLS_ { 1358, 3, 1, 4, 222, 0, 0, PPCImpOpBase + 0, 554, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1358 = LHAXTLS { 1357, 3, 1, 4, 123, 0, 0, PPCImpOpBase + 0, 551, 0|(1ULL<<MCID::MayLoad), 0x154ULL }, // Inst #1357 = LHAX8 { 1356, 3, 1, 4, 123, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::MayLoad), 0x154ULL }, // Inst #1356 = LHAX { 1355, 4, 2, 4, 126, 0, 0, PPCImpOpBase + 0, 547, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1355 = LHAUX8 { 1354, 4, 2, 4, 126, 0, 0, PPCImpOpBase + 0, 543, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1354 = LHAUX { 1353, 4, 2, 4, 125, 0, 0, PPCImpOpBase + 0, 539, 0|(1ULL<<MCID::MayLoad), 0x10ULL }, // Inst #1353 = LHAU8 { 1352, 4, 2, 4, 125, 0, 0, PPCImpOpBase + 0, 535, 0|(1ULL<<MCID::MayLoad), 0x10ULL }, // Inst #1352 = LHAU { 1351, 3, 1, 4, 224, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1351 = LHARXL { 1350, 3, 1, 4, 117, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1350 = LHARX { 1349, 3, 1, 4, 546, 0, 0, PPCImpOpBase + 0, 521, 0|(1ULL<<MCID::MayLoad), 0x114ULL }, // Inst #1349 = LHA8 { 1348, 3, 1, 4, 546, 0, 0, PPCImpOpBase + 0, 200, 0|(1ULL<<MCID::MayLoad), 0x114ULL }, // Inst #1348 = LHA { 1347, 3, 1, 4, 362, 0, 0, PPCImpOpBase + 0, 603, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1347 = LFSXTLS_ { 1346, 3, 1, 4, 362, 0, 0, PPCImpOpBase + 0, 603, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1346 = LFSXTLS { 1345, 3, 1, 4, 362, 0, 0, PPCImpOpBase + 0, 600, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1345 = LFSX { 1344, 4, 2, 4, 401, 0, 0, PPCImpOpBase + 0, 596, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1344 = LFSUX { 1343, 4, 2, 4, 400, 0, 0, PPCImpOpBase + 0, 592, 0|(1ULL<<MCID::MayLoad), 0x10ULL }, // Inst #1343 = LFSU { 1342, 3, 1, 4, 557, 0, 0, PPCImpOpBase + 0, 589, 0|(1ULL<<MCID::MayLoad), 0x10ULL }, // Inst #1342 = LFS { 1341, 3, 1, 4, 347, 0, 0, PPCImpOpBase + 0, 575, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1341 = LFIWZX { 1340, 3, 1, 4, 119, 0, 0, PPCImpOpBase + 0, 575, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1340 = LFIWAX { 1339, 3, 1, 4, 348, 0, 0, PPCImpOpBase + 0, 586, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1339 = LFDXTLS_ { 1338, 3, 1, 4, 348, 0, 0, PPCImpOpBase + 0, 586, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1338 = LFDXTLS { 1337, 3, 1, 4, 348, 0, 0, PPCImpOpBase + 0, 575, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1337 = LFDX { 1336, 4, 2, 4, 115, 0, 0, PPCImpOpBase + 0, 582, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1336 = LFDUX { 1335, 4, 2, 4, 114, 0, 0, PPCImpOpBase + 0, 578, 0|(1ULL<<MCID::MayLoad), 0x10ULL }, // Inst #1335 = LFDU { 1334, 3, 1, 4, 226, 0, 0, PPCImpOpBase + 0, 575, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1334 = LFDEPX { 1333, 3, 1, 4, 545, 0, 0, PPCImpOpBase + 0, 572, 0|(1ULL<<MCID::MayLoad), 0x10ULL }, // Inst #1333 = LFD { 1332, 3, 1, 4, 542, 0, 0, PPCImpOpBase + 0, 569, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1332 = LDtocL { 1331, 3, 1, 4, 542, 0, 0, PPCImpOpBase + 0, 566, 0|(1ULL<<MCID::MayLoad), 0x10ULL }, // Inst #1331 = LDtocJTI { 1330, 3, 1, 4, 542, 0, 0, PPCImpOpBase + 0, 566, 0|(1ULL<<MCID::MayLoad), 0x10ULL }, // Inst #1330 = LDtocCPT { 1329, 3, 1, 4, 542, 0, 0, PPCImpOpBase + 0, 566, 0|(1ULL<<MCID::MayLoad), 0x10ULL }, // Inst #1329 = LDtocBA { 1328, 3, 1, 4, 542, 0, 0, PPCImpOpBase + 0, 566, 0|(1ULL<<MCID::MayLoad), 0x10ULL }, // Inst #1328 = LDtoc { 1327, 3, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 563, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1327 = LDgotTprelL32 { 1326, 3, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 560, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1326 = LDgotTprelL { 1325, 3, 1, 4, 223, 0, 0, PPCImpOpBase + 0, 554, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1325 = LDXTLS_ { 1324, 3, 1, 4, 223, 0, 0, PPCImpOpBase + 0, 554, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1324 = LDXTLS { 1323, 3, 1, 4, 223, 0, 0, PPCImpOpBase + 0, 551, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1323 = LDX { 1322, 4, 2, 4, 137, 0, 0, PPCImpOpBase + 0, 547, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1322 = LDUX { 1321, 4, 2, 4, 135, 0, 0, PPCImpOpBase + 0, 539, 0|(1ULL<<MCID::MayLoad), 0x10ULL }, // Inst #1321 = LDU { 1320, 3, 1, 4, 555, 0, 0, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1320 = LDCIX { 1319, 3, 1, 4, 550, 0, 0, PPCImpOpBase + 0, 551, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1319 = LDBRX { 1318, 3, 1, 4, 403, 0, 0, PPCImpOpBase + 0, 181, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x40ULL }, // Inst #1318 = LDAT { 1317, 3, 1, 4, 110, 0, 0, PPCImpOpBase + 0, 551, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1317 = LDARXL { 1316, 3, 1, 4, 110, 0, 0, PPCImpOpBase + 0, 551, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1316 = LDARX { 1315, 3, 1, 4, 541, 0, 0, PPCImpOpBase + 0, 521, 0|(1ULL<<MCID::MayLoad), 0x10ULL }, // Inst #1315 = LD { 1314, 3, 1, 4, 340, 0, 0, PPCImpOpBase + 0, 557, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1314 = LBZXTLS_32 { 1313, 3, 1, 4, 340, 0, 0, PPCImpOpBase + 0, 554, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1313 = LBZXTLS_ { 1312, 3, 1, 4, 340, 0, 0, PPCImpOpBase + 0, 554, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1312 = LBZXTLS { 1311, 3, 1, 4, 340, 0, 0, PPCImpOpBase + 0, 551, 0|(1ULL<<MCID::MayLoad), 0x350ULL }, // Inst #1311 = LBZX8 { 1310, 3, 1, 4, 340, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::MayLoad), 0x350ULL }, // Inst #1310 = LBZX { 1309, 4, 2, 4, 136, 0, 0, PPCImpOpBase + 0, 547, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1309 = LBZUX8 { 1308, 4, 2, 4, 136, 0, 0, PPCImpOpBase + 0, 543, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1308 = LBZUX { 1307, 4, 2, 4, 134, 0, 0, PPCImpOpBase + 0, 539, 0|(1ULL<<MCID::MayLoad), 0x10ULL }, // Inst #1307 = LBZU8 { 1306, 4, 2, 4, 134, 0, 0, PPCImpOpBase + 0, 535, 0|(1ULL<<MCID::MayLoad), 0x10ULL }, // Inst #1306 = LBZU { 1305, 3, 1, 4, 555, 0, 0, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1305 = LBZCIX { 1304, 3, 1, 4, 540, 0, 0, PPCImpOpBase + 0, 521, 0|(1ULL<<MCID::MayLoad), 0x310ULL }, // Inst #1304 = LBZ8 { 1303, 3, 1, 4, 540, 0, 0, PPCImpOpBase + 0, 200, 0|(1ULL<<MCID::MayLoad), 0x310ULL }, // Inst #1303 = LBZ { 1302, 3, 1, 4, 225, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1302 = LBEPX { 1301, 3, 1, 4, 224, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1301 = LBARXL { 1300, 3, 1, 4, 117, 0, 0, PPCImpOpBase + 0, 532, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1300 = LBARX { 1299, 3, 1, 4, 289, 0, 0, PPCImpOpBase + 0, 208, 0, 0x8ULL }, // Inst #1299 = LA8 { 1298, 3, 1, 4, 289, 0, 0, PPCImpOpBase + 0, 245, 0, 0x8ULL }, // Inst #1298 = LA { 1297, 0, 0, 4, 343, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1297 = ISYNC { 1296, 4, 1, 4, 207, 0, 0, PPCImpOpBase + 0, 528, 0|(1ULL<<MCID::Select), 0x8ULL }, // Inst #1296 = ISEL8 { 1295, 4, 1, 4, 207, 0, 0, PPCImpOpBase + 0, 524, 0|(1ULL<<MCID::Select), 0x8ULL }, // Inst #1295 = ISEL { 1294, 2, 0, 4, 618, 0, 0, PPCImpOpBase + 0, 259, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1294 = ICCCI { 1293, 3, 0, 4, 339, 0, 0, PPCImpOpBase + 0, 342, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1293 = ICBTLS { 1292, 3, 0, 4, 549, 0, 0, PPCImpOpBase + 0, 342, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1292 = ICBT { 1291, 3, 0, 4, 618, 0, 0, PPCImpOpBase + 0, 342, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1291 = ICBLQ { 1290, 3, 0, 4, 414, 0, 0, PPCImpOpBase + 0, 342, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1290 = ICBLC { 1289, 2, 0, 4, 338, 0, 0, PPCImpOpBase + 0, 187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1289 = ICBIEP { 1288, 2, 0, 4, 606, 0, 0, PPCImpOpBase + 0, 187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1288 = ICBI { 1287, 0, 0, 4, 535, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1287 = HRFID { 1286, 3, 0, 4, 453, 0, 0, PPCImpOpBase + 0, 521, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1286 = HASHSTP8 { 1285, 3, 0, 4, 453, 0, 0, PPCImpOpBase + 0, 200, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1285 = HASHSTP { 1284, 3, 0, 4, 453, 0, 0, PPCImpOpBase + 0, 521, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1284 = HASHST8 { 1283, 3, 0, 4, 453, 0, 0, PPCImpOpBase + 0, 200, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1283 = HASHST { 1282, 3, 0, 4, 421, 0, 0, PPCImpOpBase + 0, 521, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1282 = HASHCHKP8 { 1281, 3, 0, 4, 421, 0, 0, PPCImpOpBase + 0, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1281 = HASHCHKP { 1280, 3, 0, 4, 421, 0, 0, PPCImpOpBase + 0, 521, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1280 = HASHCHK8 { 1279, 3, 0, 4, 421, 0, 0, PPCImpOpBase + 0, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1279 = HASHCHK { 1278, 3, 1, 4, 0, 0, 18, PPCImpOpBase + 183, 234, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1278 = GETtlsldADDRPCREL { 1277, 3, 1, 4, 0, 0, 17, PPCImpOpBase + 154, 225, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1277 = GETtlsldADDR32 { 1276, 3, 1, 4, 0, 0, 17, PPCImpOpBase + 137, 234, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1276 = GETtlsldADDR { 1275, 1, 1, 4, 0, 0, 2, PPCImpOpBase + 201, 171, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1275 = GETtlsTpointer32AIX { 1274, 2, 1, 4, 0, 0, 6, PPCImpOpBase + 177, 261, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1274 = GETtlsMOD64AIX { 1273, 2, 1, 4, 0, 0, 6, PPCImpOpBase + 171, 259, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1273 = GETtlsMOD32AIX { 1272, 3, 1, 8, 0, 0, 18, PPCImpOpBase + 183, 234, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1272 = GETtlsADDRPCREL { 1271, 3, 1, 4, 0, 0, 6, PPCImpOpBase + 177, 228, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1271 = GETtlsADDR64AIX { 1270, 3, 1, 4, 0, 0, 6, PPCImpOpBase + 171, 222, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1270 = GETtlsADDR32AIX { 1269, 3, 1, 4, 0, 0, 17, PPCImpOpBase + 154, 225, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1269 = GETtlsADDR32 { 1268, 3, 1, 8, 0, 0, 17, PPCImpOpBase + 137, 234, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1268 = GETtlsADDR { 1267, 2, 1, 4, 470, 0, 0, PPCImpOpBase + 0, 519, 0, 0x18ULL }, // Inst #1267 = FTSQRT { 1266, 3, 1, 4, 276, 0, 0, PPCImpOpBase + 0, 351, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x18ULL }, // Inst #1266 = FTDIV { 1265, 3, 1, 4, 157, 1, 1, PPCImpOpBase + 135, 336, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1265 = FSUB_rec { 1264, 3, 1, 4, 442, 1, 1, PPCImpOpBase + 135, 499, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1264 = FSUBS_rec { 1263, 3, 1, 4, 435, 1, 0, PPCImpOpBase + 134, 499, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1263 = FSUBS { 1262, 3, 1, 4, 316, 1, 0, PPCImpOpBase + 134, 336, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1262 = FSUB { 1261, 2, 1, 4, 176, 1, 1, PPCImpOpBase + 135, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1261 = FSQRT_rec { 1260, 2, 1, 4, 184, 1, 1, PPCImpOpBase + 135, 497, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1260 = FSQRTS_rec { 1259, 2, 1, 4, 398, 1, 0, PPCImpOpBase + 134, 497, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1259 = FSQRTS { 1258, 2, 1, 4, 397, 1, 0, PPCImpOpBase + 134, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1258 = FSQRT { 1257, 4, 1, 4, 319, 0, 1, PPCImpOpBase + 131, 515, 0, 0x18ULL }, // Inst #1257 = FSELS_rec { 1256, 4, 1, 4, 315, 0, 0, PPCImpOpBase + 0, 515, 0, 0x18ULL }, // Inst #1256 = FSELS { 1255, 4, 1, 4, 319, 0, 1, PPCImpOpBase + 131, 507, 0, 0x18ULL }, // Inst #1255 = FSELD_rec { 1254, 4, 1, 4, 315, 0, 0, PPCImpOpBase + 0, 507, 0, 0x18ULL }, // Inst #1254 = FSELD { 1253, 2, 1, 4, 444, 0, 1, PPCImpOpBase + 131, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1253 = FRSQRTE_rec { 1252, 2, 1, 4, 444, 0, 1, PPCImpOpBase + 131, 497, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1252 = FRSQRTES_rec { 1251, 2, 1, 4, 427, 0, 0, PPCImpOpBase + 0, 497, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1251 = FRSQRTES { 1250, 2, 1, 4, 427, 0, 0, PPCImpOpBase + 0, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1250 = FRSQRTE { 1249, 2, 1, 4, 444, 1, 1, PPCImpOpBase + 135, 502, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1249 = FRSP_rec { 1248, 2, 1, 4, 427, 1, 0, PPCImpOpBase + 134, 502, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1248 = FRSP { 1247, 2, 1, 4, 444, 0, 1, PPCImpOpBase + 131, 497, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1247 = FRIZS_rec { 1246, 2, 1, 4, 427, 0, 0, PPCImpOpBase + 0, 497, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1246 = FRIZS { 1245, 2, 1, 4, 444, 0, 1, PPCImpOpBase + 131, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1245 = FRIZD_rec { 1244, 2, 1, 4, 427, 0, 0, PPCImpOpBase + 0, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1244 = FRIZD { 1243, 2, 1, 4, 444, 0, 1, PPCImpOpBase + 131, 497, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1243 = FRIPS_rec { 1242, 2, 1, 4, 427, 0, 0, PPCImpOpBase + 0, 497, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1242 = FRIPS { 1241, 2, 1, 4, 444, 0, 1, PPCImpOpBase + 131, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1241 = FRIPD_rec { 1240, 2, 1, 4, 427, 0, 0, PPCImpOpBase + 0, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1240 = FRIPD { 1239, 2, 1, 4, 444, 0, 1, PPCImpOpBase + 131, 497, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1239 = FRINS_rec { 1238, 2, 1, 4, 427, 0, 0, PPCImpOpBase + 0, 497, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1238 = FRINS { 1237, 2, 1, 4, 444, 0, 1, PPCImpOpBase + 131, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1237 = FRIND_rec { 1236, 2, 1, 4, 427, 0, 0, PPCImpOpBase + 0, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1236 = FRIND { 1235, 2, 1, 4, 444, 0, 1, PPCImpOpBase + 131, 497, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1235 = FRIMS_rec { 1234, 2, 1, 4, 427, 0, 0, PPCImpOpBase + 0, 497, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1234 = FRIMS { 1233, 2, 1, 4, 444, 0, 1, PPCImpOpBase + 131, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1233 = FRIMD_rec { 1232, 2, 1, 4, 427, 0, 0, PPCImpOpBase + 0, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1232 = FRIMD { 1231, 2, 1, 4, 444, 0, 1, PPCImpOpBase + 131, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1231 = FRE_rec { 1230, 2, 1, 4, 444, 0, 1, PPCImpOpBase + 131, 497, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1230 = FRES_rec { 1229, 2, 1, 4, 427, 0, 0, PPCImpOpBase + 0, 497, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1229 = FRES { 1228, 2, 1, 4, 427, 0, 0, PPCImpOpBase + 0, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1228 = FRE { 1227, 4, 1, 4, 158, 1, 1, PPCImpOpBase + 135, 507, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1227 = FNMSUB_rec { 1226, 4, 1, 4, 320, 1, 1, PPCImpOpBase + 135, 511, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1226 = FNMSUBS_rec { 1225, 4, 1, 4, 315, 1, 0, PPCImpOpBase + 134, 511, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1225 = FNMSUBS { 1224, 4, 1, 4, 317, 1, 0, PPCImpOpBase + 134, 507, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1224 = FNMSUB { 1223, 4, 1, 4, 158, 1, 1, PPCImpOpBase + 135, 507, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1223 = FNMADD_rec { 1222, 4, 1, 4, 320, 1, 1, PPCImpOpBase + 135, 511, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1222 = FNMADDS_rec { 1221, 4, 1, 4, 315, 1, 0, PPCImpOpBase + 134, 511, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1221 = FNMADDS { 1220, 4, 1, 4, 317, 1, 0, PPCImpOpBase + 134, 507, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1220 = FNMADD { 1219, 2, 1, 4, 537, 0, 1, PPCImpOpBase + 131, 497, 0, 0x18ULL }, // Inst #1219 = FNEGS_rec { 1218, 2, 1, 4, 507, 0, 0, PPCImpOpBase + 0, 497, 0, 0x18ULL }, // Inst #1218 = FNEGS { 1217, 2, 1, 4, 537, 0, 1, PPCImpOpBase + 131, 345, 0, 0x18ULL }, // Inst #1217 = FNEGD_rec { 1216, 2, 1, 4, 507, 0, 0, PPCImpOpBase + 0, 345, 0, 0x18ULL }, // Inst #1216 = FNEGD { 1215, 2, 1, 4, 537, 0, 1, PPCImpOpBase + 131, 497, 0, 0x18ULL }, // Inst #1215 = FNABSS_rec { 1214, 2, 1, 4, 507, 0, 0, PPCImpOpBase + 0, 497, 0, 0x18ULL }, // Inst #1214 = FNABSS { 1213, 2, 1, 4, 537, 0, 1, PPCImpOpBase + 131, 345, 0, 0x18ULL }, // Inst #1213 = FNABSD_rec { 1212, 2, 1, 4, 507, 0, 0, PPCImpOpBase + 0, 345, 0, 0x18ULL }, // Inst #1212 = FNABSD { 1211, 3, 1, 4, 443, 1, 1, PPCImpOpBase + 135, 336, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1211 = FMUL_rec { 1210, 3, 1, 4, 442, 1, 1, PPCImpOpBase + 135, 499, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1210 = FMULS_rec { 1209, 3, 1, 4, 435, 1, 0, PPCImpOpBase + 134, 499, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1209 = FMULS { 1208, 3, 1, 4, 436, 1, 0, PPCImpOpBase + 134, 336, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1208 = FMUL { 1207, 4, 1, 4, 158, 1, 1, PPCImpOpBase + 135, 507, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1207 = FMSUB_rec { 1206, 4, 1, 4, 320, 1, 1, PPCImpOpBase + 135, 511, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1206 = FMSUBS_rec { 1205, 4, 1, 4, 315, 1, 0, PPCImpOpBase + 134, 511, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1205 = FMSUBS { 1204, 4, 1, 4, 317, 1, 0, PPCImpOpBase + 134, 507, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1204 = FMSUB { 1203, 2, 1, 4, 537, 0, 1, PPCImpOpBase + 131, 497, 0, 0x0ULL }, // Inst #1203 = FMR_rec { 1202, 2, 1, 4, 507, 0, 0, PPCImpOpBase + 0, 497, 0, 0x0ULL }, // Inst #1202 = FMR { 1201, 4, 1, 4, 158, 1, 1, PPCImpOpBase + 135, 507, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1201 = FMADD_rec { 1200, 4, 1, 4, 320, 1, 1, PPCImpOpBase + 135, 511, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1200 = FMADDS_rec { 1199, 4, 1, 4, 315, 1, 0, PPCImpOpBase + 134, 511, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1199 = FMADDS { 1198, 4, 1, 4, 317, 1, 0, PPCImpOpBase + 134, 507, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1198 = FMADD { 1197, 0, 0, 4, 0, 0, 1, PPCImpOpBase + 134, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1197 = FENCE { 1196, 3, 1, 4, 174, 1, 1, PPCImpOpBase + 135, 336, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1196 = FDIV_rec { 1195, 3, 1, 4, 171, 1, 1, PPCImpOpBase + 135, 499, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1195 = FDIVS_rec { 1194, 3, 1, 4, 399, 1, 0, PPCImpOpBase + 134, 499, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1194 = FDIVS { 1193, 3, 1, 4, 396, 1, 0, PPCImpOpBase + 134, 336, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1193 = FDIV { 1192, 2, 1, 4, 444, 1, 1, PPCImpOpBase + 135, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1192 = FCTIW_rec { 1191, 2, 1, 4, 444, 1, 1, PPCImpOpBase + 135, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1191 = FCTIWZ_rec { 1190, 2, 1, 4, 427, 1, 0, PPCImpOpBase + 134, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1190 = FCTIWZ { 1189, 2, 1, 4, 444, 1, 1, PPCImpOpBase + 135, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1189 = FCTIWU_rec { 1188, 2, 1, 4, 444, 1, 1, PPCImpOpBase + 135, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1188 = FCTIWUZ_rec { 1187, 2, 1, 4, 427, 1, 0, PPCImpOpBase + 134, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1187 = FCTIWUZ { 1186, 2, 1, 4, 427, 1, 0, PPCImpOpBase + 134, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1186 = FCTIWU { 1185, 2, 1, 4, 427, 1, 0, PPCImpOpBase + 134, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1185 = FCTIW { 1184, 2, 1, 4, 444, 1, 1, PPCImpOpBase + 135, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1184 = FCTID_rec { 1183, 2, 1, 4, 444, 1, 1, PPCImpOpBase + 135, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1183 = FCTIDZ_rec { 1182, 2, 1, 4, 427, 1, 0, PPCImpOpBase + 134, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1182 = FCTIDZ { 1181, 2, 1, 4, 444, 1, 1, PPCImpOpBase + 135, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1181 = FCTIDU_rec { 1180, 2, 1, 4, 444, 1, 1, PPCImpOpBase + 135, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1180 = FCTIDUZ_rec { 1179, 2, 1, 4, 427, 1, 0, PPCImpOpBase + 134, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1179 = FCTIDUZ { 1178, 2, 1, 4, 427, 1, 0, PPCImpOpBase + 134, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1178 = FCTIDU { 1177, 2, 1, 4, 427, 1, 0, PPCImpOpBase + 134, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1177 = FCTID { 1176, 3, 1, 4, 156, 0, 1, PPCImpOpBase + 131, 499, 0, 0x18ULL }, // Inst #1176 = FCPSGNS_rec { 1175, 3, 1, 4, 301, 0, 0, PPCImpOpBase + 0, 499, 0, 0x18ULL }, // Inst #1175 = FCPSGNS { 1174, 3, 1, 4, 156, 0, 1, PPCImpOpBase + 131, 336, 0, 0x18ULL }, // Inst #1174 = FCPSGND_rec { 1173, 3, 1, 4, 301, 0, 0, PPCImpOpBase + 0, 336, 0, 0x18ULL }, // Inst #1173 = FCPSGND { 1172, 3, 1, 4, 170, 0, 0, PPCImpOpBase + 0, 504, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1172 = FCMPUS { 1171, 3, 1, 4, 170, 0, 0, PPCImpOpBase + 0, 351, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1171 = FCMPUD { 1170, 3, 1, 4, 170, 0, 0, PPCImpOpBase + 0, 504, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1170 = FCMPOS { 1169, 3, 1, 4, 170, 0, 0, PPCImpOpBase + 0, 351, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1169 = FCMPOD { 1168, 2, 1, 4, 444, 1, 1, PPCImpOpBase + 135, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1168 = FCFID_rec { 1167, 2, 1, 4, 444, 1, 1, PPCImpOpBase + 135, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1167 = FCFIDU_rec { 1166, 2, 1, 4, 444, 1, 1, PPCImpOpBase + 135, 502, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1166 = FCFIDUS_rec { 1165, 2, 1, 4, 427, 1, 0, PPCImpOpBase + 134, 502, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1165 = FCFIDUS { 1164, 2, 1, 4, 427, 1, 0, PPCImpOpBase + 134, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1164 = FCFIDU { 1163, 2, 1, 4, 444, 1, 1, PPCImpOpBase + 135, 502, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1163 = FCFIDS_rec { 1162, 2, 1, 4, 427, 1, 0, PPCImpOpBase + 134, 502, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1162 = FCFIDS { 1161, 2, 1, 4, 427, 1, 0, PPCImpOpBase + 134, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1161 = FCFID { 1160, 3, 1, 4, 0, 1, 0, PPCImpOpBase + 134, 336, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #1160 = FADDrtz { 1159, 3, 1, 4, 157, 1, 1, PPCImpOpBase + 135, 336, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1159 = FADD_rec { 1158, 3, 1, 4, 442, 1, 1, PPCImpOpBase + 135, 499, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1158 = FADDS_rec { 1157, 3, 1, 4, 435, 1, 0, PPCImpOpBase + 134, 499, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1157 = FADDS { 1156, 3, 1, 4, 316, 1, 0, PPCImpOpBase + 134, 336, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1156 = FADD { 1155, 2, 1, 4, 537, 0, 1, PPCImpOpBase + 131, 497, 0, 0x18ULL }, // Inst #1155 = FABSS_rec { 1154, 2, 1, 4, 507, 0, 0, PPCImpOpBase + 0, 497, 0, 0x18ULL }, // Inst #1154 = FABSS { 1153, 2, 1, 4, 537, 0, 1, PPCImpOpBase + 131, 345, 0, 0x18ULL }, // Inst #1153 = FABSD_rec { 1152, 2, 1, 4, 507, 0, 0, PPCImpOpBase + 0, 345, 0, 0x18ULL }, // Inst #1152 = FABSD { 1151, 0, 0, 4, 610, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1151 = EnforceIEIO { 1150, 2, 1, 4, 506, 0, 1, PPCImpOpBase + 0, 261, 0, 0x108ULL }, // Inst #1150 = EXTSW_rec { 1149, 2, 1, 4, 506, 0, 1, PPCImpOpBase + 0, 492, 0, 0x108ULL }, // Inst #1149 = EXTSW_32_64_rec { 1148, 2, 1, 4, 506, 0, 0, PPCImpOpBase + 0, 492, 0, 0x108ULL }, // Inst #1148 = EXTSW_32_64 { 1147, 2, 1, 4, 506, 0, 0, PPCImpOpBase + 0, 259, 0, 0x8ULL }, // Inst #1147 = EXTSW_32 { 1146, 3, 1, 4, 395, 0, 2, PPCImpOpBase + 11, 181, 0, 0x8ULL }, // Inst #1146 = EXTSWSLI_rec { 1145, 3, 1, 4, 395, 0, 1, PPCImpOpBase + 0, 494, 0, 0x8ULL }, // Inst #1145 = EXTSWSLI_32_64_rec { 1144, 3, 1, 4, 285, 0, 0, PPCImpOpBase + 0, 494, 0, 0x8ULL }, // Inst #1144 = EXTSWSLI_32_64 { 1143, 3, 1, 4, 285, 0, 1, PPCImpOpBase + 5, 181, 0, 0x8ULL }, // Inst #1143 = EXTSWSLI { 1142, 2, 1, 4, 506, 0, 0, PPCImpOpBase + 0, 261, 0, 0x108ULL }, // Inst #1142 = EXTSW { 1141, 2, 1, 4, 506, 0, 1, PPCImpOpBase + 0, 259, 0, 0x108ULL }, // Inst #1141 = EXTSH_rec { 1140, 2, 1, 4, 506, 0, 1, PPCImpOpBase + 0, 261, 0, 0x108ULL }, // Inst #1140 = EXTSH8_rec { 1139, 2, 1, 4, 506, 0, 0, PPCImpOpBase + 0, 492, 0, 0x108ULL }, // Inst #1139 = EXTSH8_32_64 { 1138, 2, 1, 4, 506, 0, 0, PPCImpOpBase + 0, 261, 0, 0x108ULL }, // Inst #1138 = EXTSH8 { 1137, 2, 1, 4, 506, 0, 0, PPCImpOpBase + 0, 259, 0, 0x108ULL }, // Inst #1137 = EXTSH { 1136, 2, 1, 4, 506, 0, 1, PPCImpOpBase + 0, 259, 0, 0x108ULL }, // Inst #1136 = EXTSB_rec { 1135, 2, 1, 4, 506, 0, 1, PPCImpOpBase + 0, 261, 0, 0x108ULL }, // Inst #1135 = EXTSB8_rec { 1134, 2, 1, 4, 506, 0, 0, PPCImpOpBase + 0, 492, 0, 0x108ULL }, // Inst #1134 = EXTSB8_32_64 { 1133, 2, 1, 4, 506, 0, 0, PPCImpOpBase + 0, 261, 0, 0x108ULL }, // Inst #1133 = EXTSB8 { 1132, 2, 1, 4, 506, 0, 0, PPCImpOpBase + 0, 259, 0, 0x108ULL }, // Inst #1132 = EXTSB { 1131, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1131 = EVXOR { 1130, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 489, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1130 = EVSUBIFW { 1129, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1129 = EVSUBFW { 1128, 2, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1128 = EVSUBFUSIAAW { 1127, 2, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1127 = EVSUBFUMIAAW { 1126, 2, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1126 = EVSUBFSSIAAW { 1125, 2, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1125 = EVSUBFSMIAAW { 1124, 3, 0, 4, 409, 0, 0, PPCImpOpBase + 0, 477, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1124 = EVSTWWOX { 1123, 3, 0, 4, 409, 0, 0, PPCImpOpBase + 0, 474, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1123 = EVSTWWO { 1122, 3, 0, 4, 409, 0, 0, PPCImpOpBase + 0, 477, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1122 = EVSTWWEX { 1121, 3, 0, 4, 409, 0, 0, PPCImpOpBase + 0, 474, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1121 = EVSTWWE { 1120, 3, 0, 4, 409, 0, 0, PPCImpOpBase + 0, 477, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1120 = EVSTWHOX { 1119, 3, 0, 4, 409, 0, 0, PPCImpOpBase + 0, 474, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1119 = EVSTWHO { 1118, 3, 0, 4, 409, 0, 0, PPCImpOpBase + 0, 477, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1118 = EVSTWHEX { 1117, 3, 0, 4, 409, 0, 0, PPCImpOpBase + 0, 474, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1117 = EVSTWHE { 1116, 3, 0, 4, 409, 0, 0, PPCImpOpBase + 0, 477, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1116 = EVSTDWX { 1115, 3, 0, 4, 409, 0, 0, PPCImpOpBase + 0, 474, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1115 = EVSTDW { 1114, 3, 0, 4, 409, 0, 0, PPCImpOpBase + 0, 477, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1114 = EVSTDHX { 1113, 3, 0, 4, 409, 0, 0, PPCImpOpBase + 0, 474, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1113 = EVSTDH { 1112, 3, 0, 4, 409, 0, 0, PPCImpOpBase + 0, 477, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1112 = EVSTDDX { 1111, 3, 0, 4, 409, 0, 0, PPCImpOpBase + 0, 474, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1111 = EVSTDD { 1110, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1110 = EVSRWU { 1109, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1109 = EVSRWS { 1108, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 471, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1108 = EVSRWIU { 1107, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 471, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1107 = EVSRWIS { 1106, 2, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 487, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1106 = EVSPLATI { 1105, 2, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 487, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1105 = EVSPLATFI { 1104, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 471, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1104 = EVSLWI { 1103, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1103 = EVSLW { 1102, 4, 1, 4, 23, 0, 0, PPCImpOpBase + 0, 483, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1102 = EVSEL { 1101, 2, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1101 = EVRNDW { 1100, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 471, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1100 = EVRLWI { 1099, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1099 = EVRLW { 1098, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1098 = EVORC { 1097, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1097 = EVOR { 1096, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1096 = EVNOR { 1095, 2, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1095 = EVNEG { 1094, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1094 = EVNAND { 1093, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1093 = EVMWUMIAN { 1092, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1092 = EVMWUMIAA { 1091, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1091 = EVMWUMIA { 1090, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1090 = EVMWUMI { 1089, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1089 = EVMWSSFAN { 1088, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1088 = EVMWSSFAA { 1087, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1087 = EVMWSSFA { 1086, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1086 = EVMWSSF { 1085, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1085 = EVMWSMIAN { 1084, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1084 = EVMWSMIAA { 1083, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1083 = EVMWSMIA { 1082, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1082 = EVMWSMI { 1081, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1081 = EVMWSMFAN { 1080, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1080 = EVMWSMFAA { 1079, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1079 = EVMWSMFA { 1078, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1078 = EVMWSMF { 1077, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1077 = EVMWLUSIANW { 1076, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1076 = EVMWLUSIAAW { 1075, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1075 = EVMWLUMIANW { 1074, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1074 = EVMWLUMIAAW { 1073, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1073 = EVMWLUMIA { 1072, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1072 = EVMWLUMI { 1071, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1071 = EVMWLSSIANW { 1070, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1070 = EVMWLSSIAAW { 1069, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1069 = EVMWLSMIANW { 1068, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1068 = EVMWLSMIAAW { 1067, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1067 = EVMWHUMIA { 1066, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1066 = EVMWHUMI { 1065, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1065 = EVMWHSSFA { 1064, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1064 = EVMWHSSF { 1063, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1063 = EVMWHSMIA { 1062, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1062 = EVMWHSMI { 1061, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1061 = EVMWHSMFA { 1060, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1060 = EVMWHSMF { 1059, 2, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1059 = EVMRA { 1058, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1058 = EVMHOUSIANW { 1057, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1057 = EVMHOUSIAAW { 1056, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1056 = EVMHOUMIANW { 1055, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1055 = EVMHOUMIAAW { 1054, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1054 = EVMHOUMIA { 1053, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1053 = EVMHOUMI { 1052, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1052 = EVMHOSSIANW { 1051, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1051 = EVMHOSSIAAW { 1050, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1050 = EVMHOSSFANW { 1049, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1049 = EVMHOSSFAAW { 1048, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1048 = EVMHOSSFA { 1047, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1047 = EVMHOSSF { 1046, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1046 = EVMHOSMIANW { 1045, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1045 = EVMHOSMIAAW { 1044, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1044 = EVMHOSMIA { 1043, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1043 = EVMHOSMI { 1042, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1042 = EVMHOSMFANW { 1041, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1041 = EVMHOSMFAAW { 1040, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1040 = EVMHOSMFA { 1039, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1039 = EVMHOSMF { 1038, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1038 = EVMHOGUMIAN { 1037, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1037 = EVMHOGUMIAA { 1036, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1036 = EVMHOGSMIAN { 1035, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1035 = EVMHOGSMIAA { 1034, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1034 = EVMHOGSMFAN { 1033, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1033 = EVMHOGSMFAA { 1032, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1032 = EVMHEUSIANW { 1031, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1031 = EVMHEUSIAAW { 1030, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1030 = EVMHEUMIANW { 1029, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1029 = EVMHEUMIAAW { 1028, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1028 = EVMHEUMIA { 1027, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1027 = EVMHEUMI { 1026, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1026 = EVMHESSIANW { 1025, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1025 = EVMHESSIAAW { 1024, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1024 = EVMHESSFANW { 1023, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1023 = EVMHESSFAAW { 1022, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1022 = EVMHESSFA { 1021, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1021 = EVMHESSF { 1020, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1020 = EVMHESMIANW { 1019, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1019 = EVMHESMIAAW { 1018, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1018 = EVMHESMIA { 1017, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1017 = EVMHESMI { 1016, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1016 = EVMHESMFANW { 1015, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1015 = EVMHESMFAAW { 1014, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1014 = EVMHESMFA { 1013, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1013 = EVMHESMF { 1012, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1012 = EVMHEGUMIAN { 1011, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1011 = EVMHEGUMIAA { 1010, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1010 = EVMHEGSMIAN { 1009, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1009 = EVMHEGSMIAA { 1008, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1008 = EVMHEGSMFAN { 1007, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1007 = EVMHEGSMFAA { 1006, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1006 = EVMERGELOHI { 1005, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 480, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1005 = EVMERGELO { 1004, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1004 = EVMERGEHILO { 1003, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1003 = EVMERGEHI { 1002, 3, 1, 4, 408, 0, 0, PPCImpOpBase + 0, 477, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1002 = EVLWWSPLATX { 1001, 3, 1, 4, 408, 0, 0, PPCImpOpBase + 0, 474, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1001 = EVLWWSPLAT { 1000, 3, 1, 4, 408, 0, 0, PPCImpOpBase + 0, 477, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1000 = EVLWHSPLATX { 999, 3, 1, 4, 408, 0, 0, PPCImpOpBase + 0, 474, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #999 = EVLWHSPLAT { 998, 3, 1, 4, 408, 0, 0, PPCImpOpBase + 0, 477, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #998 = EVLWHOUX { 997, 3, 1, 4, 408, 0, 0, PPCImpOpBase + 0, 474, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #997 = EVLWHOU { 996, 3, 1, 4, 408, 0, 0, PPCImpOpBase + 0, 477, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #996 = EVLWHOSX { 995, 3, 1, 4, 408, 0, 0, PPCImpOpBase + 0, 474, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #995 = EVLWHOS { 994, 3, 1, 4, 408, 0, 0, PPCImpOpBase + 0, 477, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #994 = EVLWHEX { 993, 3, 1, 4, 408, 0, 0, PPCImpOpBase + 0, 474, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #993 = EVLWHE { 992, 3, 1, 4, 408, 0, 0, PPCImpOpBase + 0, 477, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #992 = EVLHHOUSPLATX { 991, 3, 1, 4, 408, 0, 0, PPCImpOpBase + 0, 474, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #991 = EVLHHOUSPLAT { 990, 3, 1, 4, 408, 0, 0, PPCImpOpBase + 0, 477, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #990 = EVLHHOSSPLATX { 989, 3, 1, 4, 408, 0, 0, PPCImpOpBase + 0, 474, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #989 = EVLHHOSSPLAT { 988, 3, 1, 4, 408, 0, 0, PPCImpOpBase + 0, 477, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #988 = EVLHHESPLATX { 987, 3, 1, 4, 408, 0, 0, PPCImpOpBase + 0, 474, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #987 = EVLHHESPLAT { 986, 3, 1, 4, 408, 0, 0, PPCImpOpBase + 0, 477, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #986 = EVLDWX { 985, 3, 1, 4, 408, 0, 0, PPCImpOpBase + 0, 474, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #985 = EVLDW { 984, 3, 1, 4, 408, 0, 0, PPCImpOpBase + 0, 477, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #984 = EVLDHX { 983, 3, 1, 4, 408, 0, 0, PPCImpOpBase + 0, 474, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #983 = EVLDH { 982, 3, 1, 4, 408, 0, 0, PPCImpOpBase + 0, 477, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #982 = EVLDDX { 981, 3, 1, 4, 408, 0, 0, PPCImpOpBase + 0, 474, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #981 = EVLDD { 980, 3, 1, 4, 23, 0, 0, PPCImpOpBase + 0, 463, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #980 = EVFSTSTLT { 979, 3, 1, 4, 23, 0, 0, PPCImpOpBase + 0, 463, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #979 = EVFSTSTGT { 978, 3, 1, 4, 23, 0, 0, PPCImpOpBase + 0, 463, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #978 = EVFSTSTEQ { 977, 3, 1, 4, 24, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #977 = EVFSSUB { 976, 2, 1, 4, 23, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #976 = EVFSNEG { 975, 2, 1, 4, 23, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #975 = EVFSNABS { 974, 3, 1, 4, 24, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #974 = EVFSMUL { 973, 3, 1, 4, 21, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #973 = EVFSDIV { 972, 2, 1, 4, 24, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #972 = EVFSCTUIZ { 971, 2, 1, 4, 24, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #971 = EVFSCTUI { 970, 2, 1, 4, 24, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #970 = EVFSCTUF { 969, 2, 1, 4, 24, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #969 = EVFSCTSIZ { 968, 2, 1, 4, 24, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #968 = EVFSCTSI { 967, 2, 1, 4, 24, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #967 = EVFSCTSF { 966, 3, 1, 4, 22, 0, 0, PPCImpOpBase + 0, 463, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #966 = EVFSCMPLT { 965, 3, 1, 4, 22, 0, 0, PPCImpOpBase + 0, 463, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #965 = EVFSCMPGT { 964, 3, 1, 4, 22, 0, 0, PPCImpOpBase + 0, 463, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #964 = EVFSCMPEQ { 963, 2, 1, 4, 24, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #963 = EVFSCFUI { 962, 2, 1, 4, 24, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #962 = EVFSCFUF { 961, 2, 1, 4, 24, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #961 = EVFSCFSI { 960, 2, 1, 4, 24, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #960 = EVFSCFSF { 959, 3, 1, 4, 24, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #959 = EVFSADD { 958, 2, 1, 4, 23, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #958 = EVFSABS { 957, 2, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #957 = EVEXTSH { 956, 2, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #956 = EVEXTSB { 955, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #955 = EVEQV { 954, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #954 = EVDIVWU { 953, 3, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #953 = EVDIVWS { 952, 2, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #952 = EVCNTLZW { 951, 2, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #951 = EVCNTLSW { 950, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 463, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #950 = EVCMPLTU { 949, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 463, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #949 = EVCMPLTS { 948, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 463, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #948 = EVCMPGTU { 947, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 463, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #947 = EVCMPGTS { 946, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 463, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #946 = EVCMPEQ { 945, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #945 = EVANDC { 944, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #944 = EVAND { 943, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #943 = EVADDW { 942, 2, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #942 = EVADDUSIAAW { 941, 2, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #941 = EVADDUMIAAW { 940, 2, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #940 = EVADDSSIAAW { 939, 2, 1, 4, 407, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #939 = EVADDSMIAAW { 938, 3, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 471, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #938 = EVADDIW { 937, 2, 1, 4, 406, 0, 0, PPCImpOpBase + 0, 456, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #937 = EVABS { 936, 3, 1, 4, 198, 0, 1, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #936 = EQV_rec { 935, 3, 1, 4, 198, 0, 1, PPCImpOpBase + 0, 228, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #935 = EQV8_rec { 934, 3, 1, 4, 198, 0, 0, PPCImpOpBase + 0, 228, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #934 = EQV8 { 933, 3, 1, 4, 198, 0, 0, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #933 = EQV { 932, 1, 0, 0, 0, 0, 0, PPCImpOpBase + 0, 285, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #932 = EH_SjLj_Setup { 931, 2, 1, 4, 0, 0, 1, PPCImpOpBase + 64, 469, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #931 = EH_SjLj_SetJmp64 { 930, 2, 1, 4, 0, 0, 1, PPCImpOpBase + 63, 469, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #930 = EH_SjLj_SetJmp32 { 929, 1, 0, 4, 0, 0, 0, PPCImpOpBase + 0, 468, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #929 = EH_SjLj_LongJmp64 { 928, 1, 0, 4, 0, 0, 0, PPCImpOpBase + 0, 468, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #928 = EH_SjLj_LongJmp32 { 927, 3, 1, 4, 16, 0, 0, PPCImpOpBase + 0, 463, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #927 = EFSTSTLT { 926, 3, 1, 4, 16, 0, 0, PPCImpOpBase + 0, 463, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #926 = EFSTSTGT { 925, 3, 1, 4, 16, 0, 0, PPCImpOpBase + 0, 463, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #925 = EFSTSTEQ { 924, 3, 1, 4, 22, 0, 0, PPCImpOpBase + 0, 222, 0, 0x0ULL }, // Inst #924 = EFSSUB { 923, 2, 1, 4, 12, 0, 0, PPCImpOpBase + 0, 259, 0, 0x0ULL }, // Inst #923 = EFSNEG { 922, 2, 1, 4, 12, 0, 0, PPCImpOpBase + 0, 259, 0, 0x0ULL }, // Inst #922 = EFSNABS { 921, 3, 1, 4, 12, 0, 0, PPCImpOpBase + 0, 222, 0, 0x0ULL }, // Inst #921 = EFSMUL { 920, 3, 1, 4, 21, 0, 0, PPCImpOpBase + 0, 222, 0, 0x0ULL }, // Inst #920 = EFSDIV { 919, 2, 1, 4, 22, 0, 0, PPCImpOpBase + 0, 259, 0, 0x0ULL }, // Inst #919 = EFSCTUIZ { 918, 2, 1, 4, 22, 0, 0, PPCImpOpBase + 0, 259, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #918 = EFSCTUI { 917, 2, 1, 4, 22, 0, 0, PPCImpOpBase + 0, 461, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #917 = EFSCTUF { 916, 2, 1, 4, 22, 0, 0, PPCImpOpBase + 0, 259, 0, 0x0ULL }, // Inst #916 = EFSCTSIZ { 915, 2, 1, 4, 22, 0, 0, PPCImpOpBase + 0, 259, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #915 = EFSCTSI { 914, 2, 1, 4, 22, 0, 0, PPCImpOpBase + 0, 259, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #914 = EFSCTSF { 913, 3, 1, 4, 16, 0, 0, PPCImpOpBase + 0, 317, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #913 = EFSCMPLT { 912, 3, 1, 4, 16, 0, 0, PPCImpOpBase + 0, 317, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #912 = EFSCMPGT { 911, 3, 1, 4, 16, 0, 0, PPCImpOpBase + 0, 317, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #911 = EFSCMPEQ { 910, 2, 1, 4, 22, 0, 0, PPCImpOpBase + 0, 259, 0, 0x0ULL }, // Inst #910 = EFSCFUI { 909, 2, 1, 4, 22, 0, 0, PPCImpOpBase + 0, 259, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #909 = EFSCFUF { 908, 2, 1, 4, 22, 0, 0, PPCImpOpBase + 0, 259, 0, 0x0ULL }, // Inst #908 = EFSCFSI { 907, 2, 1, 4, 22, 0, 0, PPCImpOpBase + 0, 259, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #907 = EFSCFSF { 906, 2, 1, 4, 22, 0, 0, PPCImpOpBase + 0, 466, 0, 0x0ULL }, // Inst #906 = EFSCFD { 905, 3, 1, 4, 20, 0, 0, PPCImpOpBase + 0, 222, 0, 0x0ULL }, // Inst #905 = EFSADD { 904, 2, 1, 4, 22, 0, 0, PPCImpOpBase + 0, 259, 0, 0x0ULL }, // Inst #904 = EFSABS { 903, 3, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 463, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #903 = EFDTSTLT { 902, 3, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 463, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #902 = EFDTSTGT { 901, 3, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 463, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #901 = EFDTSTEQ { 900, 3, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 458, 0, 0x0ULL }, // Inst #900 = EFDSUB { 899, 2, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 456, 0, 0x0ULL }, // Inst #899 = EFDNEG { 898, 2, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 456, 0, 0x0ULL }, // Inst #898 = EFDNABS { 897, 3, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 458, 0, 0x0ULL }, // Inst #897 = EFDMUL { 896, 3, 1, 4, 21, 0, 0, PPCImpOpBase + 0, 458, 0, 0x0ULL }, // Inst #896 = EFDDIV { 895, 2, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 466, 0, 0x0ULL }, // Inst #895 = EFDCTUIZ { 894, 2, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 466, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #894 = EFDCTUIDZ { 893, 2, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 466, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #893 = EFDCTUI { 892, 2, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 461, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #892 = EFDCTUF { 891, 2, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 466, 0, 0x0ULL }, // Inst #891 = EFDCTSIZ { 890, 2, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 466, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #890 = EFDCTSIDZ { 889, 2, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 466, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #889 = EFDCTSI { 888, 2, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 461, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #888 = EFDCTSF { 887, 3, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 463, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #887 = EFDCMPLT { 886, 3, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 463, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #886 = EFDCMPGT { 885, 3, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 463, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #885 = EFDCMPEQ { 884, 2, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 461, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #884 = EFDCFUID { 883, 2, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 461, 0, 0x0ULL }, // Inst #883 = EFDCFUI { 882, 2, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 461, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #882 = EFDCFUF { 881, 2, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 461, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #881 = EFDCFSID { 880, 2, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 461, 0, 0x0ULL }, // Inst #880 = EFDCFSI { 879, 2, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 461, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #879 = EFDCFSF { 878, 2, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 461, 0, 0x0ULL }, // Inst #878 = EFDCFS { 877, 3, 1, 4, 20, 0, 0, PPCImpOpBase + 0, 458, 0, 0x0ULL }, // Inst #877 = EFDADD { 876, 2, 1, 4, 19, 0, 0, PPCImpOpBase + 0, 456, 0, 0x0ULL }, // Inst #876 = EFDABS { 875, 2, 1, 4, 0, 1, 1, PPCImpOpBase + 105, 454, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #875 = DecreaseCTRloop { 874, 2, 1, 4, 0, 1, 1, PPCImpOpBase + 107, 454, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #874 = DecreaseCTR8loop { 873, 3, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 451, 0, 0x0ULL }, // Inst #873 = DYNAREAOFFSET8 { 872, 3, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 451, 0, 0x0ULL }, // Inst #872 = DYNAREAOFFSET { 871, 4, 1, 4, 0, 1, 1, PPCImpOpBase + 132, 447, 0, 0x0ULL }, // Inst #871 = DYNALLOC8 { 870, 4, 1, 4, 0, 1, 1, PPCImpOpBase + 61, 443, 0, 0x0ULL }, // Inst #870 = DYNALLOC { 869, 2, 1, 4, 244, 0, 1, PPCImpOpBase + 131, 345, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #869 = DXEX_rec { 868, 2, 1, 4, 244, 0, 1, PPCImpOpBase + 131, 357, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #868 = DXEXQ_rec { 867, 2, 1, 4, 244, 0, 0, PPCImpOpBase + 0, 357, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #867 = DXEXQ { 866, 2, 1, 4, 244, 0, 0, PPCImpOpBase + 0, 345, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #866 = DXEX { 865, 3, 1, 4, 243, 0, 0, PPCImpOpBase + 0, 440, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #865 = DTSTSFQ { 864, 3, 1, 4, 16, 0, 0, PPCImpOpBase + 0, 437, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #864 = DTSTSFIQ { 863, 3, 1, 4, 16, 0, 0, PPCImpOpBase + 0, 434, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #863 = DTSTSFI { 862, 3, 1, 4, 243, 0, 0, PPCImpOpBase + 0, 351, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #862 = DTSTSF { 861, 3, 1, 4, 248, 0, 0, PPCImpOpBase + 0, 354, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #861 = DTSTEXQ { 860, 3, 1, 4, 243, 0, 0, PPCImpOpBase + 0, 351, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #860 = DTSTEX { 859, 3, 1, 4, 243, 0, 0, PPCImpOpBase + 0, 431, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #859 = DTSTDGQ { 858, 3, 1, 4, 243, 0, 0, PPCImpOpBase + 0, 428, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #858 = DTSTDG { 857, 3, 1, 4, 243, 0, 0, PPCImpOpBase + 0, 431, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #857 = DTSTDCQ { 856, 3, 1, 4, 243, 0, 0, PPCImpOpBase + 0, 428, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #856 = DTSTDC { 855, 3, 1, 4, 245, 0, 1, PPCImpOpBase + 131, 336, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #855 = DSUB_rec { 854, 3, 1, 4, 250, 0, 1, PPCImpOpBase + 131, 339, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #854 = DSUBQ_rec { 853, 3, 1, 4, 250, 0, 0, PPCImpOpBase + 0, 339, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #853 = DSUBQ { 852, 3, 1, 4, 245, 0, 0, PPCImpOpBase + 0, 336, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #852 = DSUB { 851, 3, 0, 4, 526, 0, 0, PPCImpOpBase + 0, 425, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #851 = DSTT64 { 850, 3, 0, 4, 526, 0, 0, PPCImpOpBase + 0, 422, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #850 = DSTT { 849, 3, 0, 4, 526, 0, 0, PPCImpOpBase + 0, 425, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #849 = DSTSTT64 { 848, 3, 0, 4, 526, 0, 0, PPCImpOpBase + 0, 422, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #848 = DSTSTT { 847, 3, 0, 4, 526, 0, 0, PPCImpOpBase + 0, 425, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #847 = DSTST64 { 846, 3, 0, 4, 526, 0, 0, PPCImpOpBase + 0, 422, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #846 = DSTST { 845, 3, 0, 4, 526, 0, 0, PPCImpOpBase + 0, 425, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #845 = DST64 { 844, 3, 0, 4, 526, 0, 0, PPCImpOpBase + 0, 422, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #844 = DST { 843, 0, 0, 4, 496, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #843 = DSSALL { 842, 1, 0, 4, 496, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #842 = DSS { 841, 3, 1, 4, 244, 0, 1, PPCImpOpBase + 131, 416, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #841 = DSCRI_rec { 840, 3, 1, 4, 247, 0, 1, PPCImpOpBase + 131, 419, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #840 = DSCRIQ_rec { 839, 3, 1, 4, 247, 0, 0, PPCImpOpBase + 0, 419, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #839 = DSCRIQ { 838, 3, 1, 4, 244, 0, 0, PPCImpOpBase + 0, 416, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #838 = DSCRI { 837, 3, 1, 4, 244, 0, 1, PPCImpOpBase + 131, 416, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #837 = DSCLI_rec { 836, 3, 1, 4, 247, 0, 1, PPCImpOpBase + 131, 419, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #836 = DSCLIQ_rec { 835, 3, 1, 4, 247, 0, 0, PPCImpOpBase + 0, 419, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #835 = DSCLIQ { 834, 3, 1, 4, 244, 0, 0, PPCImpOpBase + 0, 416, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #834 = DSCLI { 833, 2, 1, 4, 252, 0, 1, PPCImpOpBase + 131, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #833 = DRSP_rec { 832, 2, 1, 4, 252, 0, 0, PPCImpOpBase + 0, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #832 = DRSP { 831, 4, 1, 4, 244, 0, 1, PPCImpOpBase + 131, 394, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #831 = DRRND_rec { 830, 4, 1, 4, 247, 0, 1, PPCImpOpBase + 131, 412, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #830 = DRRNDQ_rec { 829, 4, 1, 4, 247, 0, 0, PPCImpOpBase + 0, 412, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #829 = DRRNDQ { 828, 4, 1, 4, 244, 0, 0, PPCImpOpBase + 0, 394, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #828 = DRRND { 827, 4, 1, 4, 244, 0, 1, PPCImpOpBase + 131, 398, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #827 = DRINTX_rec { 826, 4, 1, 4, 247, 0, 1, PPCImpOpBase + 131, 402, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #826 = DRINTXQ_rec { 825, 4, 1, 4, 247, 0, 0, PPCImpOpBase + 0, 402, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #825 = DRINTXQ { 824, 4, 1, 4, 244, 0, 0, PPCImpOpBase + 0, 398, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #824 = DRINTX { 823, 4, 1, 4, 244, 0, 1, PPCImpOpBase + 131, 398, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #823 = DRINTN_rec { 822, 4, 1, 4, 247, 0, 1, PPCImpOpBase + 131, 402, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #822 = DRINTNQ_rec { 821, 4, 1, 4, 247, 0, 0, PPCImpOpBase + 0, 402, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #821 = DRINTNQ { 820, 4, 1, 4, 244, 0, 0, PPCImpOpBase + 0, 398, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #820 = DRINTN { 819, 2, 1, 4, 12, 0, 1, PPCImpOpBase + 131, 410, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #819 = DRDPQ_rec { 818, 2, 1, 4, 12, 0, 0, PPCImpOpBase + 0, 410, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #818 = DRDPQ { 817, 4, 1, 4, 244, 0, 1, PPCImpOpBase + 131, 394, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #817 = DQUA_rec { 816, 4, 1, 4, 251, 0, 1, PPCImpOpBase + 131, 406, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #816 = DQUAQ_rec { 815, 4, 1, 4, 251, 0, 0, PPCImpOpBase + 0, 406, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #815 = DQUAQ { 814, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 398, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #814 = DQUAI_rec { 813, 4, 1, 4, 247, 0, 1, PPCImpOpBase + 0, 402, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #813 = DQUAIQ_rec { 812, 4, 1, 4, 247, 0, 0, PPCImpOpBase + 0, 402, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #812 = DQUAIQ { 811, 4, 1, 4, 244, 0, 0, PPCImpOpBase + 0, 398, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #811 = DQUAI { 810, 4, 1, 4, 244, 0, 0, PPCImpOpBase + 0, 394, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #810 = DQUA { 809, 3, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 391, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #809 = DMXXINSTFDMR512_HI { 808, 3, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 388, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #808 = DMXXINSTFDMR512 { 807, 3, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 385, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #807 = DMXXINSTFDMR256 { 806, 3, 2, 4, 0, 0, 0, PPCImpOpBase + 0, 382, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #806 = DMXXEXTFDMR512_HI { 805, 3, 2, 4, 0, 0, 0, PPCImpOpBase + 0, 379, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #805 = DMXXEXTFDMR512 { 804, 3, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 376, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #804 = DMXXEXTFDMR256 { 803, 3, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 373, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #803 = DMXOR { 802, 3, 1, 4, 255, 0, 1, PPCImpOpBase + 131, 336, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #802 = DMUL_rec { 801, 3, 1, 4, 256, 0, 1, PPCImpOpBase + 131, 339, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #801 = DMULQ_rec { 800, 3, 1, 4, 256, 0, 0, PPCImpOpBase + 0, 339, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #800 = DMULQ { 799, 3, 1, 4, 255, 0, 0, PPCImpOpBase + 0, 336, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #799 = DMUL { 798, 1, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 372, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #798 = DMSETDMRZ { 797, 2, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 370, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #797 = DMMR { 796, 3, 1, 4, 389, 0, 1, PPCImpOpBase + 0, 222, 0, 0xdULL }, // Inst #796 = DIVW_rec { 795, 3, 1, 4, 389, 0, 1, PPCImpOpBase + 0, 222, 0, 0xdULL }, // Inst #795 = DIVWU_rec { 794, 3, 1, 4, 389, 0, 2, PPCImpOpBase + 3, 222, 0, 0x8ULL }, // Inst #794 = DIVWUO_rec { 793, 3, 1, 4, 383, 0, 1, PPCImpOpBase + 2, 222, 0, 0x8ULL }, // Inst #793 = DIVWUO { 792, 3, 1, 4, 209, 0, 0, PPCImpOpBase + 0, 222, 0, 0x8ULL }, // Inst #792 = DIVWU { 791, 3, 1, 4, 389, 0, 2, PPCImpOpBase + 3, 222, 0, 0x8ULL }, // Inst #791 = DIVWO_rec { 790, 3, 1, 4, 383, 0, 1, PPCImpOpBase + 2, 222, 0, 0x8ULL }, // Inst #790 = DIVWO { 789, 3, 1, 4, 154, 0, 1, PPCImpOpBase + 0, 222, 0, 0xdULL }, // Inst #789 = DIVWE_rec { 788, 3, 1, 4, 154, 0, 1, PPCImpOpBase + 0, 222, 0, 0xdULL }, // Inst #788 = DIVWEU_rec { 787, 3, 1, 4, 154, 0, 2, PPCImpOpBase + 3, 222, 0, 0x8ULL }, // Inst #787 = DIVWEUO_rec { 786, 3, 1, 4, 385, 0, 1, PPCImpOpBase + 2, 222, 0, 0x8ULL }, // Inst #786 = DIVWEUO { 785, 3, 1, 4, 211, 0, 0, PPCImpOpBase + 0, 222, 0, 0x8ULL }, // Inst #785 = DIVWEU { 784, 3, 1, 4, 154, 0, 2, PPCImpOpBase + 3, 222, 0, 0x8ULL }, // Inst #784 = DIVWEO_rec { 783, 3, 1, 4, 385, 0, 1, PPCImpOpBase + 2, 222, 0, 0x8ULL }, // Inst #783 = DIVWEO { 782, 3, 1, 4, 211, 0, 0, PPCImpOpBase + 0, 222, 0, 0x8ULL }, // Inst #782 = DIVWE { 781, 3, 1, 4, 209, 0, 0, PPCImpOpBase + 0, 222, 0, 0x8ULL }, // Inst #781 = DIVW { 780, 3, 1, 4, 155, 0, 1, PPCImpOpBase + 0, 228, 0, 0xdULL }, // Inst #780 = DIVD_rec { 779, 3, 1, 4, 155, 0, 1, PPCImpOpBase + 0, 228, 0, 0xdULL }, // Inst #779 = DIVDU_rec { 778, 3, 1, 4, 155, 0, 2, PPCImpOpBase + 3, 228, 0, 0x8ULL }, // Inst #778 = DIVDUO_rec { 777, 3, 1, 4, 386, 0, 1, PPCImpOpBase + 2, 228, 0, 0x8ULL }, // Inst #777 = DIVDUO { 776, 3, 1, 4, 210, 0, 0, PPCImpOpBase + 0, 228, 0, 0x8ULL }, // Inst #776 = DIVDU { 775, 3, 1, 4, 155, 0, 2, PPCImpOpBase + 3, 228, 0, 0x8ULL }, // Inst #775 = DIVDO_rec { 774, 3, 1, 4, 386, 0, 1, PPCImpOpBase + 2, 228, 0, 0x8ULL }, // Inst #774 = DIVDO { 773, 3, 1, 4, 153, 0, 1, PPCImpOpBase + 0, 228, 0, 0xdULL }, // Inst #773 = DIVDE_rec { 772, 3, 1, 4, 153, 0, 1, PPCImpOpBase + 0, 228, 0, 0xdULL }, // Inst #772 = DIVDEU_rec { 771, 3, 1, 4, 153, 0, 2, PPCImpOpBase + 3, 228, 0, 0x8ULL }, // Inst #771 = DIVDEUO_rec { 770, 3, 1, 4, 388, 0, 1, PPCImpOpBase + 2, 228, 0, 0x8ULL }, // Inst #770 = DIVDEUO { 769, 3, 1, 4, 388, 0, 0, PPCImpOpBase + 0, 228, 0, 0x8ULL }, // Inst #769 = DIVDEU { 768, 3, 1, 4, 153, 0, 2, PPCImpOpBase + 3, 228, 0, 0x8ULL }, // Inst #768 = DIVDEO_rec { 767, 3, 1, 4, 388, 0, 1, PPCImpOpBase + 2, 228, 0, 0x8ULL }, // Inst #767 = DIVDEO { 766, 3, 1, 4, 388, 0, 0, PPCImpOpBase + 0, 228, 0, 0x8ULL }, // Inst #766 = DIVDE { 765, 3, 1, 4, 210, 0, 0, PPCImpOpBase + 0, 228, 0, 0x8ULL }, // Inst #765 = DIVD { 764, 3, 1, 4, 244, 0, 1, PPCImpOpBase + 131, 336, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #764 = DIEX_rec { 763, 3, 1, 4, 247, 0, 1, PPCImpOpBase + 131, 367, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #763 = DIEXQ_rec { 762, 3, 1, 4, 247, 0, 0, PPCImpOpBase + 0, 367, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #762 = DIEXQ { 761, 3, 1, 4, 244, 0, 0, PPCImpOpBase + 0, 336, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #761 = DIEX { 760, 3, 1, 4, 244, 0, 1, PPCImpOpBase + 131, 361, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #760 = DENBCD_rec { 759, 3, 1, 4, 247, 0, 1, PPCImpOpBase + 131, 364, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #759 = DENBCDQ_rec { 758, 3, 1, 4, 247, 0, 0, PPCImpOpBase + 0, 364, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #758 = DENBCDQ { 757, 3, 1, 4, 244, 0, 0, PPCImpOpBase + 0, 361, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #757 = DENBCD { 756, 3, 1, 4, 257, 0, 1, PPCImpOpBase + 131, 336, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #756 = DDIV_rec { 755, 3, 1, 4, 258, 0, 1, PPCImpOpBase + 131, 339, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #755 = DDIVQ_rec { 754, 3, 1, 4, 258, 0, 0, PPCImpOpBase + 0, 339, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #754 = DDIVQ { 753, 3, 1, 4, 257, 0, 0, PPCImpOpBase + 0, 336, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #753 = DDIV { 752, 3, 1, 4, 244, 0, 1, PPCImpOpBase + 131, 361, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #752 = DDEDPD_rec { 751, 3, 1, 4, 247, 0, 1, PPCImpOpBase + 131, 364, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #751 = DDEDPDQ_rec { 750, 3, 1, 4, 247, 0, 0, PPCImpOpBase + 0, 364, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #750 = DDEDPDQ { 749, 3, 1, 4, 244, 0, 0, PPCImpOpBase + 0, 361, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #749 = DDEDPD { 748, 2, 1, 4, 249, 0, 1, PPCImpOpBase + 131, 347, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #748 = DCTQPQ_rec { 747, 2, 1, 4, 249, 0, 0, PPCImpOpBase + 0, 347, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #747 = DCTQPQ { 746, 2, 1, 4, 252, 0, 1, PPCImpOpBase + 131, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #746 = DCTFIX_rec { 745, 2, 1, 4, 12, 0, 1, PPCImpOpBase + 131, 357, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #745 = DCTFIXQ_rec { 744, 2, 1, 4, 12, 0, 0, PPCImpOpBase + 0, 359, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #744 = DCTFIXQQ { 743, 2, 1, 4, 12, 0, 0, PPCImpOpBase + 0, 357, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #743 = DCTFIXQ { 742, 2, 1, 4, 252, 0, 0, PPCImpOpBase + 0, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #742 = DCTFIX { 741, 2, 1, 4, 245, 0, 1, PPCImpOpBase + 131, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #741 = DCTDP_rec { 740, 2, 1, 4, 245, 0, 0, PPCImpOpBase + 0, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #740 = DCTDP { 739, 3, 1, 4, 248, 0, 0, PPCImpOpBase + 0, 354, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #739 = DCMPUQ { 738, 3, 1, 4, 243, 0, 0, PPCImpOpBase + 0, 351, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #738 = DCMPU { 737, 3, 1, 4, 248, 0, 0, PPCImpOpBase + 0, 354, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #737 = DCMPOQ { 736, 3, 1, 4, 243, 0, 0, PPCImpOpBase + 0, 351, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #736 = DCMPO { 735, 2, 1, 4, 253, 0, 1, PPCImpOpBase + 131, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #735 = DCFFIX_rec { 734, 2, 1, 4, 254, 0, 1, PPCImpOpBase + 131, 347, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #734 = DCFFIXQ_rec { 733, 2, 1, 4, 12, 0, 0, PPCImpOpBase + 0, 349, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #733 = DCFFIXQQ { 732, 2, 1, 4, 254, 0, 0, PPCImpOpBase + 0, 347, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #732 = DCFFIXQ { 731, 2, 1, 4, 253, 0, 0, PPCImpOpBase + 0, 345, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #731 = DCFFIX { 730, 2, 0, 4, 618, 0, 0, PPCImpOpBase + 0, 259, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #730 = DCCCI { 729, 2, 0, 4, 336, 0, 0, PPCImpOpBase + 0, 187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #729 = DCBZLEP { 728, 2, 0, 4, 617, 0, 0, PPCImpOpBase + 0, 187, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #728 = DCBZL { 727, 2, 0, 4, 336, 0, 0, PPCImpOpBase + 0, 187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #727 = DCBZEP { 726, 2, 0, 4, 605, 0, 0, PPCImpOpBase + 0, 187, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #726 = DCBZ { 725, 3, 0, 4, 336, 0, 0, PPCImpOpBase + 0, 189, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #725 = DCBTSTEP { 724, 3, 0, 4, 548, 0, 0, PPCImpOpBase + 0, 342, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #724 = DCBTST { 723, 3, 0, 4, 336, 0, 0, PPCImpOpBase + 0, 189, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #723 = DCBTEP { 722, 3, 0, 4, 548, 0, 0, PPCImpOpBase + 0, 342, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #722 = DCBT { 721, 2, 0, 4, 336, 0, 0, PPCImpOpBase + 0, 187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #721 = DCBSTEP { 720, 2, 0, 4, 605, 0, 0, PPCImpOpBase + 0, 187, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #720 = DCBST { 719, 2, 0, 4, 426, 0, 0, PPCImpOpBase + 0, 187, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #719 = DCBI { 718, 2, 0, 4, 336, 0, 0, PPCImpOpBase + 0, 187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #718 = DCBFEP { 717, 3, 0, 4, 605, 0, 0, PPCImpOpBase + 0, 342, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #717 = DCBF { 716, 2, 0, 4, 426, 0, 0, PPCImpOpBase + 0, 187, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #716 = DCBA { 715, 2, 1, 4, 342, 0, 0, PPCImpOpBase + 0, 217, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL }, // Inst #715 = DARN { 714, 3, 1, 4, 245, 0, 1, PPCImpOpBase + 131, 336, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #714 = DADD_rec { 713, 3, 1, 4, 250, 0, 1, PPCImpOpBase + 131, 339, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #713 = DADDQ_rec { 712, 3, 1, 4, 250, 0, 0, PPCImpOpBase + 0, 339, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #712 = DADDQ { 711, 3, 1, 4, 245, 0, 0, PPCImpOpBase + 0, 336, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #711 = DADD { 710, 3, 0, 4, 446, 0, 0, PPCImpOpBase + 0, 288, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #710 = CTRL_DEP { 709, 3, 1, 4, 304, 0, 0, PPCImpOpBase + 0, 331, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #709 = CRXOR { 708, 1, 1, 4, 525, 0, 0, PPCImpOpBase + 0, 296, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #708 = CRUNSET { 707, 1, 1, 4, 525, 0, 0, PPCImpOpBase + 0, 296, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #707 = CRSET { 706, 3, 1, 4, 525, 0, 0, PPCImpOpBase + 0, 331, 0, 0x0ULL }, // Inst #706 = CRORC { 705, 3, 1, 4, 525, 0, 0, PPCImpOpBase + 0, 331, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #705 = CROR { 704, 2, 1, 4, 107, 0, 0, PPCImpOpBase + 0, 334, 0, 0x0ULL }, // Inst #704 = CRNOT { 703, 3, 1, 4, 525, 0, 0, PPCImpOpBase + 0, 331, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #703 = CRNOR { 702, 3, 1, 4, 525, 0, 0, PPCImpOpBase + 0, 331, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #702 = CRNAND { 701, 3, 1, 4, 525, 0, 0, PPCImpOpBase + 0, 331, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #701 = CREQV { 700, 3, 1, 4, 525, 0, 0, PPCImpOpBase + 0, 331, 0, 0x0ULL }, // Inst #700 = CRANDC { 699, 3, 1, 4, 525, 0, 0, PPCImpOpBase + 0, 331, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #699 = CRAND { 698, 0, 0, 4, 525, 0, 1, PPCImpOpBase + 130, 1, 0, 0x0ULL }, // Inst #698 = CR6UNSET { 697, 0, 0, 4, 525, 0, 1, PPCImpOpBase + 130, 1, 0, 0x0ULL }, // Inst #697 = CR6SET { 696, 3, 0, 4, 358, 0, 1, PPCImpOpBase + 0, 184, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #696 = CP_PASTE_rec { 695, 3, 0, 4, 358, 0, 0, PPCImpOpBase + 0, 181, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #695 = CP_PASTE8_rec { 694, 3, 0, 4, 337, 0, 0, PPCImpOpBase + 0, 181, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #694 = CP_COPY8 { 693, 3, 0, 4, 337, 0, 0, PPCImpOpBase + 0, 184, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #693 = CP_COPY { 692, 0, 0, 4, 341, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #692 = CP_ABORT { 691, 2, 1, 4, 279, 0, 1, PPCImpOpBase + 0, 259, 0, 0x208ULL }, // Inst #691 = CNTTZW_rec { 690, 2, 1, 4, 279, 0, 1, PPCImpOpBase + 0, 261, 0, 0x308ULL }, // Inst #690 = CNTTZW8_rec { 689, 2, 1, 4, 279, 0, 0, PPCImpOpBase + 0, 261, 0, 0x308ULL }, // Inst #689 = CNTTZW8 { 688, 2, 1, 4, 279, 0, 0, PPCImpOpBase + 0, 259, 0, 0x208ULL }, // Inst #688 = CNTTZW { 687, 2, 1, 4, 279, 0, 1, PPCImpOpBase + 0, 261, 0, 0x308ULL }, // Inst #687 = CNTTZD_rec { 686, 3, 1, 4, 148, 0, 0, PPCImpOpBase + 0, 228, 0, 0x0ULL }, // Inst #686 = CNTTZDM { 685, 2, 1, 4, 279, 0, 0, PPCImpOpBase + 0, 261, 0, 0x308ULL }, // Inst #685 = CNTTZD { 684, 2, 1, 4, 205, 0, 1, PPCImpOpBase + 0, 259, 0, 0x208ULL }, // Inst #684 = CNTLZW_rec { 683, 2, 1, 4, 205, 0, 1, PPCImpOpBase + 0, 261, 0, 0x308ULL }, // Inst #683 = CNTLZW8_rec { 682, 2, 1, 4, 205, 0, 0, PPCImpOpBase + 0, 261, 0, 0x308ULL }, // Inst #682 = CNTLZW8 { 681, 2, 1, 4, 205, 0, 0, PPCImpOpBase + 0, 259, 0, 0x208ULL }, // Inst #681 = CNTLZW { 680, 2, 1, 4, 205, 0, 1, PPCImpOpBase + 0, 261, 0, 0x308ULL }, // Inst #680 = CNTLZD_rec { 679, 3, 1, 4, 148, 0, 0, PPCImpOpBase + 0, 228, 0, 0x0ULL }, // Inst #679 = CNTLZDM { 678, 2, 1, 4, 205, 0, 0, PPCImpOpBase + 0, 261, 0, 0x308ULL }, // Inst #678 = CNTLZD { 677, 3, 1, 4, 505, 0, 0, PPCImpOpBase + 0, 320, 0|(1ULL<<MCID::Compare), 0x8ULL }, // Inst #677 = CMPWI { 676, 3, 1, 4, 140, 0, 0, PPCImpOpBase + 0, 317, 0|(1ULL<<MCID::Compare), 0x8ULL }, // Inst #676 = CMPW { 675, 4, 1, 4, 274, 0, 0, PPCImpOpBase + 0, 327, 0|(1ULL<<MCID::Compare), 0x8ULL }, // Inst #675 = CMPRB8 { 674, 4, 1, 4, 274, 0, 0, PPCImpOpBase + 0, 323, 0|(1ULL<<MCID::Compare), 0x8ULL }, // Inst #674 = CMPRB { 673, 3, 1, 4, 505, 0, 0, PPCImpOpBase + 0, 320, 0|(1ULL<<MCID::Compare), 0x8ULL }, // Inst #673 = CMPLWI { 672, 3, 1, 4, 140, 0, 0, PPCImpOpBase + 0, 317, 0|(1ULL<<MCID::Compare), 0x8ULL }, // Inst #672 = CMPLW { 671, 3, 1, 4, 505, 0, 0, PPCImpOpBase + 0, 314, 0|(1ULL<<MCID::Compare), 0x8ULL }, // Inst #671 = CMPLDI { 670, 3, 1, 4, 140, 0, 0, PPCImpOpBase + 0, 311, 0|(1ULL<<MCID::Compare), 0x8ULL }, // Inst #670 = CMPLD { 669, 3, 1, 4, 274, 0, 0, PPCImpOpBase + 0, 311, 0|(1ULL<<MCID::Compare), 0x8ULL }, // Inst #669 = CMPEQB { 668, 3, 1, 4, 505, 0, 0, PPCImpOpBase + 0, 314, 0|(1ULL<<MCID::Compare), 0x8ULL }, // Inst #668 = CMPDI { 667, 3, 1, 4, 140, 0, 0, PPCImpOpBase + 0, 311, 0|(1ULL<<MCID::Compare), 0x8ULL }, // Inst #667 = CMPD { 666, 3, 1, 4, 524, 0, 0, PPCImpOpBase + 0, 228, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #666 = CMPB8 { 665, 3, 1, 4, 524, 0, 0, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #665 = CMPB { 664, 0, 0, 4, 619, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #664 = CLRBHRB { 663, 3, 1, 4, 449, 0, 0, PPCImpOpBase + 0, 228, 0, 0x0ULL }, // Inst #663 = CFUGED { 662, 2, 1, 4, 469, 0, 0, PPCImpOpBase + 0, 261, 0, 0x8ULL }, // Inst #662 = CDTBCD8 { 661, 2, 1, 4, 469, 0, 0, PPCImpOpBase + 0, 259, 0, 0x0ULL }, // Inst #661 = CDTBCD { 660, 2, 1, 4, 469, 0, 0, PPCImpOpBase + 0, 261, 0, 0x8ULL }, // Inst #660 = CBCDTD8 { 659, 2, 1, 4, 469, 0, 0, PPCImpOpBase + 0, 259, 0, 0x0ULL }, // Inst #659 = CBCDTD { 658, 2, 1, 4, 577, 0, 0, PPCImpOpBase + 0, 261, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #658 = BRW8 { 657, 2, 1, 4, 577, 0, 0, PPCImpOpBase + 0, 259, 0, 0x0ULL }, // Inst #657 = BRW { 656, 3, 1, 4, 405, 0, 0, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #656 = BRINC { 655, 2, 1, 4, 577, 0, 0, PPCImpOpBase + 0, 261, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #655 = BRH8 { 654, 2, 1, 4, 577, 0, 0, PPCImpOpBase + 0, 259, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #654 = BRH { 653, 2, 1, 4, 577, 0, 0, PPCImpOpBase + 0, 261, 0, 0x0ULL }, // Inst #653 = BRD { 652, 3, 1, 4, 281, 0, 0, PPCImpOpBase + 0, 228, 0, 0x8ULL }, // Inst #652 = BPERMD { 651, 2, 0, 4, 242, 1, 1, PPCImpOpBase + 71, 13, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #651 = BL_TLS { 650, 1, 0, 4, 242, 1, 2, PPCImpOpBase + 125, 285, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #650 = BL_RM { 649, 1, 0, 8, 242, 1, 2, PPCImpOpBase + 125, 285, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #649 = BL_NOP_RM { 648, 1, 0, 8, 242, 1, 1, PPCImpOpBase + 71, 285, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #648 = BL_NOP { 647, 0, 0, 4, 445, 2, 1, PPCImpOpBase + 75, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #647 = BLRL { 646, 0, 0, 4, 445, 2, 0, PPCImpOpBase + 128, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #646 = BLR8 { 645, 0, 0, 4, 445, 2, 0, PPCImpOpBase + 73, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #645 = BLR { 644, 1, 0, 4, 242, 1, 2, PPCImpOpBase + 125, 0, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #644 = BLA_RM { 643, 1, 0, 4, 242, 1, 2, PPCImpOpBase + 122, 0, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #643 = BLA8_RM { 642, 1, 0, 8, 242, 1, 2, PPCImpOpBase + 122, 0, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #642 = BLA8_NOP_RM { 641, 1, 0, 8, 242, 1, 1, PPCImpOpBase + 120, 0, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #641 = BLA8_NOP { 640, 1, 0, 4, 242, 1, 1, PPCImpOpBase + 120, 0, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #640 = BLA8 { 639, 1, 0, 4, 242, 1, 1, PPCImpOpBase + 71, 0, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #639 = BLA { 638, 2, 0, 4, 242, 1, 1, PPCImpOpBase + 120, 13, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #638 = BL8_TLS_ { 637, 2, 0, 4, 242, 1, 1, PPCImpOpBase + 120, 13, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #637 = BL8_TLS { 636, 1, 0, 4, 242, 1, 2, PPCImpOpBase + 122, 285, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #636 = BL8_RM { 635, 2, 0, 4, 101, 1, 1, PPCImpOpBase + 120, 13, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #635 = BL8_NOTOC_TLS { 634, 1, 0, 4, 101, 1, 2, PPCImpOpBase + 122, 285, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #634 = BL8_NOTOC_RM { 633, 1, 0, 4, 101, 1, 1, PPCImpOpBase + 120, 285, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #633 = BL8_NOTOC { 632, 2, 0, 8, 242, 1, 1, PPCImpOpBase + 120, 13, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #632 = BL8_NOP_TLS { 631, 1, 0, 8, 242, 1, 2, PPCImpOpBase + 122, 285, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #631 = BL8_NOP_RM { 630, 1, 0, 8, 242, 1, 1, PPCImpOpBase + 120, 285, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #630 = BL8_NOP { 629, 1, 0, 4, 242, 1, 1, PPCImpOpBase + 120, 285, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #629 = BL8 { 628, 1, 0, 4, 242, 1, 1, PPCImpOpBase + 71, 285, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #628 = BL { 627, 1, 0, 4, 102, 1, 1, PPCImpOpBase + 105, 285, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #627 = BDZp { 626, 1, 0, 4, 102, 1, 1, PPCImpOpBase + 105, 285, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #626 = BDZm { 625, 1, 0, 4, 102, 2, 1, PPCImpOpBase + 109, 285, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #625 = BDZLp { 624, 1, 0, 4, 102, 2, 1, PPCImpOpBase + 109, 285, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #624 = BDZLm { 623, 0, 0, 4, 445, 3, 1, PPCImpOpBase + 112, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #623 = BDZLRp { 622, 0, 0, 4, 445, 3, 1, PPCImpOpBase + 112, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #622 = BDZLRm { 621, 0, 0, 4, 445, 3, 1, PPCImpOpBase + 112, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #621 = BDZLRLp { 620, 0, 0, 4, 445, 3, 1, PPCImpOpBase + 112, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #620 = BDZLRLm { 619, 0, 0, 4, 445, 3, 1, PPCImpOpBase + 112, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #619 = BDZLRL { 618, 0, 0, 4, 445, 3, 1, PPCImpOpBase + 116, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #618 = BDZLR8 { 617, 0, 0, 4, 445, 3, 1, PPCImpOpBase + 112, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #617 = BDZLR { 616, 1, 0, 4, 102, 2, 1, PPCImpOpBase + 109, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #616 = BDZLAp { 615, 1, 0, 4, 102, 2, 1, PPCImpOpBase + 109, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #615 = BDZLAm { 614, 1, 0, 4, 102, 2, 1, PPCImpOpBase + 109, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #614 = BDZLA { 613, 1, 0, 4, 102, 2, 1, PPCImpOpBase + 109, 285, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #613 = BDZL { 612, 1, 0, 4, 102, 1, 1, PPCImpOpBase + 105, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #612 = BDZAp { 611, 1, 0, 4, 102, 1, 1, PPCImpOpBase + 105, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #611 = BDZAm { 610, 1, 0, 4, 102, 1, 1, PPCImpOpBase + 105, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #610 = BDZA { 609, 1, 0, 4, 102, 1, 1, PPCImpOpBase + 107, 285, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #609 = BDZ8 { 608, 1, 0, 4, 102, 1, 1, PPCImpOpBase + 105, 285, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #608 = BDZ { 607, 1, 0, 4, 102, 1, 1, PPCImpOpBase + 105, 285, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #607 = BDNZp { 606, 1, 0, 4, 102, 1, 1, PPCImpOpBase + 105, 285, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #606 = BDNZm { 605, 1, 0, 4, 102, 2, 1, PPCImpOpBase + 109, 285, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #605 = BDNZLp { 604, 1, 0, 4, 102, 2, 1, PPCImpOpBase + 109, 285, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #604 = BDNZLm { 603, 0, 0, 4, 445, 3, 1, PPCImpOpBase + 112, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #603 = BDNZLRp { 602, 0, 0, 4, 445, 3, 1, PPCImpOpBase + 112, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #602 = BDNZLRm { 601, 0, 0, 4, 445, 3, 1, PPCImpOpBase + 112, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #601 = BDNZLRLp { 600, 0, 0, 4, 445, 3, 1, PPCImpOpBase + 112, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #600 = BDNZLRLm { 599, 0, 0, 4, 445, 3, 1, PPCImpOpBase + 112, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #599 = BDNZLRL { 598, 0, 0, 4, 445, 3, 1, PPCImpOpBase + 116, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #598 = BDNZLR8 { 597, 0, 0, 4, 445, 3, 1, PPCImpOpBase + 112, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #597 = BDNZLR { 596, 1, 0, 4, 102, 2, 1, PPCImpOpBase + 109, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #596 = BDNZLAp { 595, 1, 0, 4, 102, 2, 1, PPCImpOpBase + 109, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #595 = BDNZLAm { 594, 1, 0, 4, 102, 2, 1, PPCImpOpBase + 109, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #594 = BDNZLA { 593, 1, 0, 4, 102, 2, 1, PPCImpOpBase + 109, 285, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #593 = BDNZL { 592, 1, 0, 4, 102, 1, 1, PPCImpOpBase + 105, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #592 = BDNZAp { 591, 1, 0, 4, 102, 1, 1, PPCImpOpBase + 105, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #591 = BDNZAm { 590, 1, 0, 4, 102, 1, 1, PPCImpOpBase + 105, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #590 = BDNZA { 589, 1, 0, 4, 102, 1, 1, PPCImpOpBase + 107, 285, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #589 = BDNZ8 { 588, 1, 0, 4, 102, 1, 1, PPCImpOpBase + 105, 285, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #588 = BDNZ { 587, 2, 0, 4, 102, 0, 0, PPCImpOpBase + 0, 286, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #587 = BCn { 586, 0, 0, 4, 102, 2, 2, PPCImpOpBase + 101, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x38ULL }, // Inst #586 = BCTRL_RM { 585, 2, 0, 8, 102, 2, 3, PPCImpOpBase + 96, 309, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #585 = BCTRL_LWZinto_toc_RM { 584, 2, 0, 8, 102, 2, 2, PPCImpOpBase + 92, 309, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #584 = BCTRL_LWZinto_toc { 583, 0, 0, 4, 102, 2, 2, PPCImpOpBase + 88, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x38ULL }, // Inst #583 = BCTRL8_RM { 582, 2, 0, 8, 102, 2, 3, PPCImpOpBase + 83, 309, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #582 = BCTRL8_LDinto_toc_RM { 581, 2, 0, 8, 102, 2, 2, PPCImpOpBase + 79, 309, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #581 = BCTRL8_LDinto_toc { 580, 0, 0, 4, 102, 2, 1, PPCImpOpBase + 68, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x38ULL }, // Inst #580 = BCTRL8 { 579, 0, 0, 4, 102, 2, 1, PPCImpOpBase + 65, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x38ULL }, // Inst #579 = BCTRL { 578, 0, 0, 4, 102, 1, 0, PPCImpOpBase + 64, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #578 = BCTR8 { 577, 0, 0, 4, 102, 1, 0, PPCImpOpBase + 63, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #577 = BCTR { 576, 2, 0, 4, 102, 1, 1, PPCImpOpBase + 71, 286, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #576 = BCLn { 575, 1, 0, 4, 102, 1, 1, PPCImpOpBase + 71, 285, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #575 = BCLalways { 574, 1, 0, 4, 445, 2, 0, PPCImpOpBase + 73, 296, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #574 = BCLRn { 573, 1, 0, 4, 445, 2, 1, PPCImpOpBase + 75, 296, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #573 = BCLRLn { 572, 1, 0, 4, 445, 2, 1, PPCImpOpBase + 75, 296, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #572 = BCLRL { 571, 1, 0, 4, 445, 2, 0, PPCImpOpBase + 73, 296, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #571 = BCLR { 570, 2, 0, 4, 102, 1, 1, PPCImpOpBase + 71, 286, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #570 = BCL { 569, 3, 1, 4, 465, 0, 1, PPCImpOpBase + 78, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #569 = BCDUTRUNC_rec { 568, 3, 1, 4, 465, 0, 1, PPCImpOpBase + 78, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #568 = BCDUS_rec { 567, 4, 1, 4, 465, 0, 1, PPCImpOpBase + 78, 297, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #567 = BCDTRUNC_rec { 566, 4, 1, 4, 465, 0, 1, PPCImpOpBase + 78, 297, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #566 = BCDS_rec { 565, 4, 1, 4, 246, 0, 1, PPCImpOpBase + 78, 297, 0, 0x0ULL }, // Inst #565 = BCDSUB_rec { 564, 4, 1, 4, 327, 0, 1, PPCImpOpBase + 78, 297, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #564 = BCDSR_rec { 563, 3, 1, 4, 463, 0, 1, PPCImpOpBase + 78, 301, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #563 = BCDSETSGN_rec { 562, 3, 1, 4, 463, 0, 1, PPCImpOpBase + 78, 301, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #562 = BCDCTZ_rec { 561, 2, 1, 4, 328, 0, 1, PPCImpOpBase + 78, 307, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #561 = BCDCTSQ_rec { 560, 2, 1, 4, 463, 0, 1, PPCImpOpBase + 78, 307, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #560 = BCDCTN_rec { 559, 3, 1, 4, 465, 0, 1, PPCImpOpBase + 78, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #559 = BCDCPSGN_rec { 558, 3, 1, 4, 463, 0, 1, PPCImpOpBase + 78, 301, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #558 = BCDCFZ_rec { 557, 3, 1, 4, 330, 0, 1, PPCImpOpBase + 78, 301, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #557 = BCDCFSQ_rec { 556, 3, 1, 4, 463, 0, 1, PPCImpOpBase + 78, 301, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #556 = BCDCFN_rec { 555, 4, 1, 4, 246, 0, 1, PPCImpOpBase + 78, 297, 0, 0x0ULL }, // Inst #555 = BCDADD_rec { 554, 1, 0, 4, 445, 1, 0, PPCImpOpBase + 63, 296, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #554 = BCCTRn { 553, 1, 0, 4, 445, 2, 1, PPCImpOpBase + 65, 296, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #553 = BCCTRLn { 552, 1, 0, 4, 445, 2, 1, PPCImpOpBase + 68, 296, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #552 = BCCTRL8n { 551, 1, 0, 4, 445, 2, 1, PPCImpOpBase + 68, 296, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #551 = BCCTRL8 { 550, 1, 0, 4, 445, 2, 1, PPCImpOpBase + 65, 296, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #550 = BCCTRL { 549, 1, 0, 4, 445, 1, 0, PPCImpOpBase + 64, 296, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #549 = BCCTR8n { 548, 1, 0, 4, 445, 1, 0, PPCImpOpBase + 64, 296, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #548 = BCCTR8 { 547, 1, 0, 4, 445, 1, 0, PPCImpOpBase + 63, 296, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #547 = BCCTR { 546, 2, 0, 4, 445, 2, 1, PPCImpOpBase + 75, 294, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #546 = BCCLRL { 545, 2, 0, 4, 445, 2, 0, PPCImpOpBase + 73, 294, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #545 = BCCLR { 544, 3, 0, 4, 445, 1, 1, PPCImpOpBase + 71, 291, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #544 = BCCLA { 543, 3, 0, 4, 445, 1, 1, PPCImpOpBase + 71, 288, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #543 = BCCL { 542, 2, 0, 4, 445, 2, 1, PPCImpOpBase + 68, 294, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #542 = BCCCTRL8 { 541, 2, 0, 4, 445, 2, 1, PPCImpOpBase + 65, 294, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #541 = BCCCTRL { 540, 2, 0, 4, 445, 1, 0, PPCImpOpBase + 64, 294, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #540 = BCCCTR8 { 539, 2, 0, 4, 445, 1, 0, PPCImpOpBase + 63, 294, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #539 = BCCCTR { 538, 3, 0, 4, 445, 0, 0, PPCImpOpBase + 0, 291, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #538 = BCCA { 537, 3, 0, 4, 445, 0, 0, PPCImpOpBase + 0, 288, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #537 = BCC { 536, 2, 0, 4, 102, 0, 0, PPCImpOpBase + 0, 286, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #536 = BC { 535, 1, 0, 4, 242, 0, 0, PPCImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #535 = BA { 534, 1, 0, 4, 242, 0, 0, PPCImpOpBase + 0, 285, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #534 = B { 533, 0, 0, 4, 616, 0, 0, PPCImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #533 = ATTN { 532, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #532 = ATOMIC_SWAP_I8 { 531, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 281, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #531 = ATOMIC_SWAP_I64 { 530, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #530 = ATOMIC_SWAP_I32 { 529, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #529 = ATOMIC_SWAP_I16 { 528, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #528 = ATOMIC_LOAD_XOR_I8 { 527, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 281, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #527 = ATOMIC_LOAD_XOR_I64 { 526, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #526 = ATOMIC_LOAD_XOR_I32 { 525, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #525 = ATOMIC_LOAD_XOR_I16 { 524, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #524 = ATOMIC_LOAD_UMIN_I8 { 523, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 281, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #523 = ATOMIC_LOAD_UMIN_I64 { 522, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #522 = ATOMIC_LOAD_UMIN_I32 { 521, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #521 = ATOMIC_LOAD_UMIN_I16 { 520, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #520 = ATOMIC_LOAD_UMAX_I8 { 519, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 281, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #519 = ATOMIC_LOAD_UMAX_I64 { 518, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #518 = ATOMIC_LOAD_UMAX_I32 { 517, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #517 = ATOMIC_LOAD_UMAX_I16 { 516, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #516 = ATOMIC_LOAD_SUB_I8 { 515, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 281, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #515 = ATOMIC_LOAD_SUB_I64 { 514, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #514 = ATOMIC_LOAD_SUB_I32 { 513, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #513 = ATOMIC_LOAD_SUB_I16 { 512, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #512 = ATOMIC_LOAD_OR_I8 { 511, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 281, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #511 = ATOMIC_LOAD_OR_I64 { 510, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #510 = ATOMIC_LOAD_OR_I32 { 509, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #509 = ATOMIC_LOAD_OR_I16 { 508, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #508 = ATOMIC_LOAD_NAND_I8 { 507, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 281, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #507 = ATOMIC_LOAD_NAND_I64 { 506, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #506 = ATOMIC_LOAD_NAND_I32 { 505, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #505 = ATOMIC_LOAD_NAND_I16 { 504, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #504 = ATOMIC_LOAD_MIN_I8 { 503, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 281, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #503 = ATOMIC_LOAD_MIN_I64 { 502, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #502 = ATOMIC_LOAD_MIN_I32 { 501, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #501 = ATOMIC_LOAD_MIN_I16 { 500, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #500 = ATOMIC_LOAD_MAX_I8 { 499, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 281, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #499 = ATOMIC_LOAD_MAX_I64 { 498, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #498 = ATOMIC_LOAD_MAX_I32 { 497, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #497 = ATOMIC_LOAD_MAX_I16 { 496, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #496 = ATOMIC_LOAD_AND_I8 { 495, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 281, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #495 = ATOMIC_LOAD_AND_I64 { 494, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #494 = ATOMIC_LOAD_AND_I32 { 493, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #493 = ATOMIC_LOAD_AND_I16 { 492, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #492 = ATOMIC_LOAD_ADD_I8 { 491, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 281, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #491 = ATOMIC_LOAD_ADD_I64 { 490, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #490 = ATOMIC_LOAD_ADD_I32 { 489, 4, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #489 = ATOMIC_LOAD_ADD_I16 { 488, 5, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 267, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #488 = ATOMIC_CMP_SWAP_I8 { 487, 5, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 272, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #487 = ATOMIC_CMP_SWAP_I64 { 486, 5, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 267, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #486 = ATOMIC_CMP_SWAP_I32 { 485, 5, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 267, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #485 = ATOMIC_CMP_SWAP_I16 { 484, 3, 1, 4, 198, 0, 1, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #484 = AND_rec { 483, 2, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 265, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #483 = ANDI_rec_1_GT_BIT8 { 482, 2, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 263, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #482 = ANDI_rec_1_GT_BIT { 481, 2, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 265, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #481 = ANDI_rec_1_EQ_BIT8 { 480, 2, 1, 4, 0, 0, 1, PPCImpOpBase + 0, 263, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #480 = ANDI_rec_1_EQ_BIT { 479, 3, 1, 4, 504, 0, 1, PPCImpOpBase + 0, 184, 0, 0x308ULL }, // Inst #479 = ANDI_rec { 478, 3, 1, 4, 504, 0, 1, PPCImpOpBase + 0, 184, 0, 0x208ULL }, // Inst #478 = ANDIS_rec { 477, 3, 1, 4, 502, 0, 1, PPCImpOpBase + 0, 181, 0, 0x208ULL }, // Inst #477 = ANDIS8_rec { 476, 3, 1, 4, 502, 0, 1, PPCImpOpBase + 0, 181, 0, 0x308ULL }, // Inst #476 = ANDI8_rec { 475, 3, 1, 4, 198, 0, 1, PPCImpOpBase + 0, 222, 0, 0x8ULL }, // Inst #475 = ANDC_rec { 474, 3, 1, 4, 198, 0, 1, PPCImpOpBase + 0, 228, 0, 0x8ULL }, // Inst #474 = ANDC8_rec { 473, 3, 1, 4, 198, 0, 0, PPCImpOpBase + 0, 228, 0, 0x8ULL }, // Inst #473 = ANDC8 { 472, 3, 1, 4, 198, 0, 0, PPCImpOpBase + 0, 222, 0, 0x8ULL }, // Inst #472 = ANDC { 471, 3, 1, 4, 198, 0, 1, PPCImpOpBase + 0, 228, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #471 = AND8_rec { 470, 3, 1, 4, 198, 0, 0, PPCImpOpBase + 0, 228, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #470 = AND8 { 469, 3, 1, 4, 198, 0, 0, PPCImpOpBase + 0, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #469 = AND { 468, 2, 0, 4, 0, 1, 1, PPCImpOpBase + 61, 21, 0, 0x0ULL }, // Inst #468 = ADJCALLSTACKUP { 467, 2, 0, 4, 0, 1, 1, PPCImpOpBase + 61, 21, 0, 0x0ULL }, // Inst #467 = ADJCALLSTACKDOWN { 466, 2, 1, 4, 532, 1, 2, PPCImpOpBase + 22, 259, 0, 0x8ULL }, // Inst #466 = ADDZE_rec { 465, 2, 1, 4, 532, 1, 3, PPCImpOpBase + 18, 259, 0, 0x8ULL }, // Inst #465 = ADDZEO_rec { 464, 2, 1, 4, 502, 1, 2, PPCImpOpBase + 15, 259, 0, 0x8ULL }, // Inst #464 = ADDZEO { 463, 2, 1, 4, 532, 1, 2, PPCImpOpBase + 22, 261, 0, 0x8ULL }, // Inst #463 = ADDZE8_rec { 462, 2, 1, 4, 532, 1, 3, PPCImpOpBase + 18, 261, 0, 0x8ULL }, // Inst #462 = ADDZE8O_rec { 461, 2, 1, 4, 502, 1, 2, PPCImpOpBase + 15, 261, 0, 0x8ULL }, // Inst #461 = ADDZE8O { 460, 2, 1, 4, 503, 1, 1, PPCImpOpBase + 13, 261, 0, 0x8ULL }, // Inst #460 = ADDZE8 { 459, 2, 1, 4, 503, 1, 1, PPCImpOpBase + 13, 259, 0, 0x8ULL }, // Inst #459 = ADDZE { 458, 2, 1, 4, 143, 0, 0, PPCImpOpBase + 0, 217, 0, 0x8ULL }, // Inst #458 = ADDPCIS { 457, 2, 1, 4, 532, 1, 2, PPCImpOpBase + 22, 259, 0, 0x8ULL }, // Inst #457 = ADDME_rec { 456, 2, 1, 4, 532, 1, 3, PPCImpOpBase + 18, 259, 0, 0x8ULL }, // Inst #456 = ADDMEO_rec { 455, 2, 1, 4, 502, 1, 2, PPCImpOpBase + 15, 259, 0, 0x8ULL }, // Inst #455 = ADDMEO { 454, 2, 1, 4, 532, 1, 2, PPCImpOpBase + 22, 261, 0, 0x8ULL }, // Inst #454 = ADDME8_rec { 453, 2, 1, 4, 532, 1, 3, PPCImpOpBase + 18, 261, 0, 0x8ULL }, // Inst #453 = ADDME8O_rec { 452, 2, 1, 4, 502, 1, 2, PPCImpOpBase + 15, 261, 0, 0x8ULL }, // Inst #452 = ADDME8O { 451, 2, 1, 4, 501, 1, 1, PPCImpOpBase + 13, 261, 0, 0x8ULL }, // Inst #451 = ADDME8 { 450, 2, 1, 4, 501, 1, 1, PPCImpOpBase + 13, 259, 0, 0x8ULL }, // Inst #450 = ADDME { 449, 3, 1, 4, 288, 0, 0, PPCImpOpBase + 0, 231, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #449 = ADDItocL8 { 448, 3, 1, 4, 288, 0, 0, PPCImpOpBase + 0, 248, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #448 = ADDItocL { 447, 3, 1, 4, 227, 0, 0, PPCImpOpBase + 0, 231, 0, 0x0ULL }, // Inst #447 = ADDItoc8 { 446, 3, 1, 4, 227, 0, 0, PPCImpOpBase + 0, 225, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #446 = ADDItoc { 445, 4, 1, 4, 500, 0, 18, PPCImpOpBase + 43, 255, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #445 = ADDItlsldLADDR32 { 444, 4, 1, 4, 0, 0, 18, PPCImpOpBase + 25, 251, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #444 = ADDItlsldLADDR { 443, 3, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 245, 0, 0x0ULL }, // Inst #443 = ADDItlsldL32 { 442, 3, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 208, 0, 0x0ULL }, // Inst #442 = ADDItlsldL { 441, 4, 1, 4, 227, 0, 18, PPCImpOpBase + 43, 255, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #441 = ADDItlsgdLADDR32 { 440, 4, 1, 4, 227, 0, 18, PPCImpOpBase + 25, 251, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #440 = ADDItlsgdLADDR { 439, 3, 1, 4, 227, 0, 0, PPCImpOpBase + 0, 245, 0, 0x0ULL }, // Inst #439 = ADDItlsgdL32 { 438, 3, 1, 4, 227, 0, 0, PPCImpOpBase + 0, 208, 0, 0x0ULL }, // Inst #438 = ADDItlsgdL { 437, 3, 1, 4, 499, 0, 0, PPCImpOpBase + 0, 245, 0, 0x0ULL }, // Inst #437 = ADDIdtprelL32 { 436, 3, 1, 4, 227, 0, 0, PPCImpOpBase + 0, 208, 0, 0x0ULL }, // Inst #436 = ADDIdtprelL { 435, 3, 1, 4, 288, 0, 0, PPCImpOpBase + 0, 231, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #435 = ADDIStocHA8 { 434, 3, 1, 4, 288, 0, 0, PPCImpOpBase + 0, 248, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #434 = ADDIStocHA { 433, 3, 1, 4, 0, 0, 0, PPCImpOpBase + 0, 208, 0, 0x0ULL }, // Inst #433 = ADDIStlsldHA { 432, 3, 1, 4, 227, 0, 0, PPCImpOpBase + 0, 208, 0, 0x0ULL }, // Inst #432 = ADDIStlsgdHA { 431, 3, 1, 4, 227, 0, 0, PPCImpOpBase + 0, 208, 0, 0x0ULL }, // Inst #431 = ADDISgotTprelHA { 430, 3, 1, 4, 499, 0, 0, PPCImpOpBase + 0, 245, 0, 0x0ULL }, // Inst #430 = ADDISdtprelHA32 { 429, 3, 1, 4, 227, 0, 0, PPCImpOpBase + 0, 208, 0, 0x0ULL }, // Inst #429 = ADDISdtprelHA { 428, 3, 1, 4, 498, 0, 0, PPCImpOpBase + 0, 208, 0, 0x8ULL }, // Inst #428 = ADDIS8 { 427, 3, 1, 4, 498, 0, 0, PPCImpOpBase + 0, 245, 0, 0x8ULL }, // Inst #427 = ADDIS { 426, 3, 1, 4, 532, 0, 2, PPCImpOpBase + 11, 184, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL }, // Inst #426 = ADDIC_rec { 425, 3, 1, 4, 501, 0, 1, PPCImpOpBase + 5, 181, 0, 0x8ULL }, // Inst #425 = ADDIC8 { 424, 3, 1, 4, 501, 0, 1, PPCImpOpBase + 5, 184, 0, 0xcULL }, // Inst #424 = ADDIC { 423, 3, 1, 4, 498, 0, 0, PPCImpOpBase + 0, 208, 0, 0x8ULL }, // Inst #423 = ADDI8 { 422, 3, 1, 4, 498, 0, 0, PPCImpOpBase + 0, 245, 0, 0x8ULL }, // Inst #422 = ADDI { 421, 3, 1, 4, 203, 0, 0, PPCImpOpBase + 0, 228, 0, 0x8ULL }, // Inst #421 = ADDG6S8 { 420, 3, 1, 4, 203, 0, 0, PPCImpOpBase + 0, 222, 0, 0x0ULL }, // Inst #420 = ADDG6S { 419, 3, 1, 4, 534, 1, 2, PPCImpOpBase + 22, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #419 = ADDE_rec { 418, 4, 1, 4, 522, 0, 0, PPCImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #418 = ADDEX8 { 417, 4, 1, 4, 522, 0, 0, PPCImpOpBase + 0, 237, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #417 = ADDEX { 416, 3, 1, 4, 534, 1, 3, PPCImpOpBase + 18, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #416 = ADDEO_rec { 415, 3, 1, 4, 521, 1, 2, PPCImpOpBase + 15, 222, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #415 = ADDEO { 414, 3, 1, 4, 534, 1, 2, PPCImpOpBase + 22, 228, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #414 = ADDE8_rec { 413, 3, 1, 4, 534, 1, 3, PPCImpOpBase + 18, 228, 0|(1ULL<<MCID::Commutable)<TRUNCATED>#ifdef __GNUC__#pragma GCC diagnostic push#pragma GCC diagnostic ignored "-Woverlength-strings"#endif#ifdef __GNUC__#pragma GCC diagnostic pop#endif#endif // GET_INSTRINFO_MC_DESC#ifdef GET_INSTRINFO_HEADER#undef GET_INSTRINFO_HEADER#endif // GET_INSTRINFO_HEADER#ifdef GET_INSTRINFO_HELPER_DECLS#undef GET_INSTRINFO_HELPER_DECLS#endif // GET_INSTRINFO_HELPER_DECLS#ifdef GET_INSTRINFO_HELPERS#undef GET_INSTRINFO_HELPERS#endif // GET_INSTRINFO_HELPERS#ifdef GET_INSTRINFO_CTOR_DTOR#undef GET_INSTRINFO_CTOR_DTOR#endif // GET_INSTRINFO_CTOR_DTOR#ifdef GET_INSTRINFO_OPERAND_ENUM#undef GET_INSTRINFO_OPERAND_ENUM#endif //GET_INSTRINFO_OPERAND_ENUM#ifdef GET_INSTRINFO_NAMED_OPS#undef GET_INSTRINFO_NAMED_OPS#endif //GET_INSTRINFO_NAMED_OPS#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM#undef GET_INSTRINFO_OPERAND_TYPES_ENUM#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM#ifdef GET_INSTRINFO_OPERAND_TYPE#undef GET_INSTRINFO_OPERAND_TYPE#endif // GET_INSTRINFO_OPERAND_TYPE#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE#undef GET_INSTRINFO_MEM_OPERAND_SIZE#endif // GET_INSTRINFO_MEM_OPERAND_SIZE#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP#ifdef GET_INSTRINFO_MC_HELPER_DECLS#undef GET_INSTRINFO_MC_HELPER_DECLSclass MCInstclass FeatureBitsetvoid verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features)#endif // GET_INSTRINFO_MC_HELPER_DECLS#ifdef GET_INSTRINFO_MC_HELPERS#undef GET_INSTRINFO_MC_HELPERS#endif // GET_GENISTRINFO_MC_HELPERS#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\ defined(GET_AVAILABLE_OPCODE_CHECKER)#define GET_COMPUTE_FEATURES#endif#ifdef GET_COMPUTE_FEATURES#undef GET_COMPUTE_FEATURES#endif // GET_COMPUTE_FEATURES#ifdef GET_AVAILABLE_OPCODE_CHECKER#undef GET_AVAILABLE_OPCODE_CHECKER#endif // GET_AVAILABLE_OPCODE_CHECKER#ifdef ENABLE_INSTR_PREDICATE_VERIFIER#undef ENABLE_INSTR_PREDICATE_VERIFIER#include <sstream>#ifndef NDEBUG#endif // NDEBUG#ifndef NDEBUG#endif // NDEBUG#endif // ENABLE_INSTR_PREDICATE_VERIFIER#ifdef GET_INSTRMAP_INFO#undef GET_INSTRMAP_INFO#endif // GET_INSTRMAP_INFO
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