/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Global Instruction Selector for the PPC target *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_GLOBALISEL_PREDICATE_BITSET const unsigned MAX_SUBTARGET_PREDICATES = …; PredicateBitset; #endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET #ifdef GET_GLOBALISEL_TEMPORARIES_DECL mutable MatcherState State; typedef ComplexRendererFns(PPCInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; typedef void(PPCInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const; const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo; static PPCInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; static PPCInstructionSelector::CustomRendererFn CustomRenderers[]; bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; const uint8_t *getMatchTable() const override; bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override; bool testSimplePredicate(unsigned PredicateID) const override; bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override; #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL #ifdef GET_GLOBALISEL_TEMPORARIES_INIT , State(0), ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers) #endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT #ifdef GET_GLOBALISEL_IMPL // LLT Objects. enum { GILLT_s1, GILLT_s32, GILLT_s64, GILLT_s128, GILLT_v2s64, GILLT_v4s32, GILLT_v8s16, GILLT_v16s8, GILLT_v256s1, GILLT_v512s1, }; const static size_t NumTypeObjects = 10; const static LLT TypeObjects[] = { LLT::scalar(1), LLT::scalar(32), LLT::scalar(64), LLT::scalar(128), LLT::vector(ElementCount::getFixed(2), 64), LLT::vector(ElementCount::getFixed(4), 32), LLT::vector(ElementCount::getFixed(8), 16), LLT::vector(ElementCount::getFixed(16), 8), LLT::vector(ElementCount::getFixed(256), 1), LLT::vector(ElementCount::getFixed(512), 1), }; // Bits for subtarget features that participate in instruction matching. enum SubtargetFeatureBits : uint8_t { Feature_In32BitModeBit = 1, Feature_In64BitModeBit = 9, Feature_HasOnlyMSYNCBit = 23, Feature_HasSYNCBit = 22, Feature_HasSPEBit = 8, Feature_HasICBTBit = 21, Feature_HasBPERMDBit = 10, Feature_HasExtDivBit = 3, Feature_IsISA2_06Bit = 11, Feature_IsISA2_07Bit = 40, Feature_IsISA3_0Bit = 2, Feature_HasFPUBit = 0, Feature_PCRelativeMemopsBit = 37, Feature_IsNotISA3_1Bit = 39, Feature_IsAIXBit = 24, Feature_NotAIXBit = 25, Feature_IsISAFutureBit = 20, Feature_IsNotISAFutureBit = 18, Feature_HasAltivecBit = 4, Feature_HasP8AltivecBit = 5, Feature_HasP8CryptoBit = 6, Feature_HasP9AltivecBit = 7, Feature_HasVSXBit = 12, Feature_IsLittleEndianBit = 26, Feature_IsBigEndianBit = 27, Feature_IsPPC64Bit = 31, Feature_HasOnlySwappingMemOpsBit = 29, Feature_NoP8VectorBit = 30, Feature_HasP8VectorBit = 13, Feature_HasDirectMoveBit = 14, Feature_NoP9VectorBit = 28, Feature_HasP9VectorBit = 15, Feature_NoP9AltivecBit = 32, Feature_NoP10VectorBit = 33, Feature_HasP10VectorBit = 36, Feature_HasHTMBit = 34, Feature_IsPPC32Bit = 38, Feature_PrefixInstrsBit = 16, Feature_IsISA3_1Bit = 17, Feature_PairedVectorMemopsBit = 35, Feature_MMABit = 19, }; PredicateBitset PPCInstructionSelector:: computeAvailableModuleFeatures(const PPCSubtarget *Subtarget) const { PredicateBitset Features{}; if (!Subtarget->isPPC64()) Features.set(Feature_In32BitModeBit); if (Subtarget->isPPC64()) Features.set(Feature_In64BitModeBit); if (Subtarget->hasOnlyMSYNC()) Features.set(Feature_HasOnlyMSYNCBit); if (!Subtarget->hasOnlyMSYNC()) Features.set(Feature_HasSYNCBit); if (Subtarget->hasSPE()) Features.set(Feature_HasSPEBit); if (Subtarget->hasICBT()) Features.set(Feature_HasICBTBit); if (Subtarget->hasBPERMD()) Features.set(Feature_HasBPERMDBit); if (Subtarget->hasExtDiv()) Features.set(Feature_HasExtDivBit); if (Subtarget->isISA2_06()) Features.set(Feature_IsISA2_06Bit); if (Subtarget->isISA2_07()) Features.set(Feature_IsISA2_07Bit); if (Subtarget->isISA3_0()) Features.set(Feature_IsISA3_0Bit); if (Subtarget->hasFPU()) Features.set(Feature_HasFPUBit); if (Subtarget->hasPCRelativeMemops()) Features.set(Feature_PCRelativeMemopsBit); if (!Subtarget->isISA3_1()) Features.set(Feature_IsNotISA3_1Bit); if (Subtarget->isAIXABI()) Features.set(Feature_IsAIXBit); if (!Subtarget->isAIXABI()) Features.set(Feature_NotAIXBit); if (Subtarget->isISAFuture()) Features.set(Feature_IsISAFutureBit); if (!Subtarget->isISAFuture()) Features.set(Feature_IsNotISAFutureBit); if (Subtarget->hasAltivec()) Features.set(Feature_HasAltivecBit); if (Subtarget->hasP8Altivec()) Features.set(Feature_HasP8AltivecBit); if (Subtarget->hasP8Crypto()) Features.set(Feature_HasP8CryptoBit); if (Subtarget->hasP9Altivec()) Features.set(Feature_HasP9AltivecBit); if (Subtarget->hasVSX()) Features.set(Feature_HasVSXBit); if (Subtarget->isLittleEndian()) Features.set(Feature_IsLittleEndianBit); if (!Subtarget->isLittleEndian()) Features.set(Feature_IsBigEndianBit); if (Subtarget->isPPC64()) Features.set(Feature_IsPPC64Bit); if (!Subtarget->hasP9Vector()) Features.set(Feature_HasOnlySwappingMemOpsBit); if (!Subtarget->hasP8Vector()) Features.set(Feature_NoP8VectorBit); if (Subtarget->hasP8Vector()) Features.set(Feature_HasP8VectorBit); if (Subtarget->hasDirectMove()) Features.set(Feature_HasDirectMoveBit); if (!Subtarget->hasP9Vector()) Features.set(Feature_NoP9VectorBit); if (Subtarget->hasP9Vector()) Features.set(Feature_HasP9VectorBit); if (!Subtarget->hasP9Altivec()) Features.set(Feature_NoP9AltivecBit); if (!Subtarget->hasP10Vector()) Features.set(Feature_NoP10VectorBit); if (Subtarget->hasP10Vector()) Features.set(Feature_HasP10VectorBit); if (Subtarget->hasHTM()) Features.set(Feature_HasHTMBit); if (!Subtarget->isPPC64()) Features.set(Feature_IsPPC32Bit); if (Subtarget->hasPrefixInstrs()) Features.set(Feature_PrefixInstrsBit); if (Subtarget->isISA3_1()) Features.set(Feature_IsISA3_1Bit); if (Subtarget->pairedVectorMemops()) Features.set(Feature_PairedVectorMemopsBit); if (Subtarget->hasMMA()) Features.set(Feature_MMABit); return Features; } void PPCInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) { AvailableFunctionFeatures = computeAvailableFunctionFeatures((const PPCSubtarget *)&MF.getSubtarget(), &MF); } PredicateBitset PPCInstructionSelector:: computeAvailableFunctionFeatures(const PPCSubtarget *Subtarget, const MachineFunction *MF) const { PredicateBitset Features{}; return Features; } // Feature bitsets. enum { GIFBS_Invalid, GIFBS_HasAltivec, GIFBS_HasBPERMD, GIFBS_HasExtDiv, GIFBS_HasFPU, GIFBS_HasHTM, GIFBS_HasOnlyMSYNC, GIFBS_HasP8Altivec, GIFBS_HasP8Crypto, GIFBS_HasP9Altivec, GIFBS_HasSPE, GIFBS_HasSYNC, GIFBS_HasVSX, GIFBS_In32BitMode, GIFBS_In64BitMode, GIFBS_IsAIX, GIFBS_IsISA3_0, GIFBS_IsISA3_1, GIFBS_IsNotISA3_1, GIFBS_NotAIX, GIFBS_HasDirectMove_HasVSX, GIFBS_HasFPU_IsISA3_1, GIFBS_HasP10Vector_PrefixInstrs, GIFBS_HasP8Altivec_HasVSX, GIFBS_HasP8Vector_HasVSX, GIFBS_HasP9Vector_HasVSX, GIFBS_HasVSX_IsISA3_1, GIFBS_In64BitMode_IsISA3_0, GIFBS_IsISAFuture_MMA, GIFBS_IsNotISAFuture_MMA, GIFBS_HasP8Altivec_HasVSX_IsBigEndian, GIFBS_HasP8Altivec_HasVSX_IsLittleEndian, GIFBS_IsISAFuture_MMA_PrefixInstrs, GIFBS_IsNotISAFuture_MMA_PrefixInstrs, GIFBS_HasDirectMove_HasVSX_IsISA3_0_IsLittleEndian, GIFBS_HasDirectMove_HasVSX_IsLittleEndian_NoP9Vector, GIFBS_HasVSX_IsBigEndian_IsISA3_1_IsPPC32, GIFBS_HasDirectMove_HasVSX_IsBigEndian_IsISA3_0_IsPPC64, GIFBS_HasDirectMove_HasVSX_IsBigEndian_IsPPC64_NoP9Vector, }; constexpr static PredicateBitset FeatureBitsets[] { {}, // GIFBS_Invalid {Feature_HasAltivecBit, }, {Feature_HasBPERMDBit, }, {Feature_HasExtDivBit, }, {Feature_HasFPUBit, }, {Feature_HasHTMBit, }, {Feature_HasOnlyMSYNCBit, }, {Feature_HasP8AltivecBit, }, {Feature_HasP8CryptoBit, }, {Feature_HasP9AltivecBit, }, {Feature_HasSPEBit, }, {Feature_HasSYNCBit, }, {Feature_HasVSXBit, }, {Feature_In32BitModeBit, }, {Feature_In64BitModeBit, }, {Feature_IsAIXBit, }, {Feature_IsISA3_0Bit, }, {Feature_IsISA3_1Bit, }, {Feature_IsNotISA3_1Bit, }, {Feature_NotAIXBit, }, {Feature_HasDirectMoveBit, Feature_HasVSXBit, }, {Feature_HasFPUBit, Feature_IsISA3_1Bit, }, {Feature_HasP10VectorBit, Feature_PrefixInstrsBit, }, {Feature_HasP8AltivecBit, Feature_HasVSXBit, }, {Feature_HasP8VectorBit, Feature_HasVSXBit, }, {Feature_HasP9VectorBit, Feature_HasVSXBit, }, {Feature_HasVSXBit, Feature_IsISA3_1Bit, }, {Feature_In64BitModeBit, Feature_IsISA3_0Bit, }, {Feature_IsISAFutureBit, Feature_MMABit, }, {Feature_IsNotISAFutureBit, Feature_MMABit, }, {Feature_HasP8AltivecBit, Feature_HasVSXBit, Feature_IsBigEndianBit, }, {Feature_HasP8AltivecBit, Feature_HasVSXBit, Feature_IsLittleEndianBit, }, {Feature_IsISAFutureBit, Feature_MMABit, Feature_PrefixInstrsBit, }, {Feature_IsNotISAFutureBit, Feature_MMABit, Feature_PrefixInstrsBit, }, {Feature_HasDirectMoveBit, Feature_HasVSXBit, Feature_IsISA3_0Bit, Feature_IsLittleEndianBit, }, {Feature_HasDirectMoveBit, Feature_HasVSXBit, Feature_IsLittleEndianBit, Feature_NoP9VectorBit, }, {Feature_HasVSXBit, Feature_IsBigEndianBit, Feature_IsISA3_1Bit, Feature_IsPPC32Bit, }, {Feature_HasDirectMoveBit, Feature_HasVSXBit, Feature_IsBigEndianBit, Feature_IsISA3_0Bit, Feature_IsPPC64Bit, }, {Feature_HasDirectMoveBit, Feature_HasVSXBit, Feature_IsBigEndianBit, Feature_IsPPC64Bit, Feature_NoP9VectorBit, }, }; // ComplexPattern predicates. enum { GICP_Invalid, }; // See constructor for table contents PPCInstructionSelector::ComplexMatcherMemFn PPCInstructionSelector::ComplexPredicateFns[] = { nullptr, // GICP_Invalid }; // PatFrag predicates. bool PPCInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const { const MachineFunction &MF = *MI.getParent()->getParent(); const MachineRegisterInfo &MRI = MF.getRegInfo(); const auto &Operands = State.RecordedOperands; (void)Operands; (void)MRI; llvm_unreachable("Unknown predicate"); return false; } // PatFrag predicates. enum { GICXXPred_I64_Predicate_Msk2Imm = GICXXPred_Invalid + 1, GICXXPred_I64_Predicate_Msk4Imm, GICXXPred_I64_Predicate_Msk8Imm, GICXXPred_I64_Predicate_i32immNonAllOneNonZero, GICXXPred_I64_Predicate_imm32SExt16, GICXXPred_I64_Predicate_imm64SExt16, GICXXPred_I64_Predicate_imm64ZExt32, GICXXPred_I64_Predicate_immNonAllOneAnyExt8, GICXXPred_I64_Predicate_immSExt5NonZero, }; bool PPCInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const { switch (PredicateID) { case GICXXPred_I64_Predicate_Msk2Imm: { return isUInt<2>(Imm); } case GICXXPred_I64_Predicate_Msk4Imm: { return isUInt<4>(Imm); } case GICXXPred_I64_Predicate_Msk8Imm: { return isUInt<8>(Imm); } case GICXXPred_I64_Predicate_i32immNonAllOneNonZero: { return Imm && (Imm != -1); } case GICXXPred_I64_Predicate_imm32SExt16: { // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit // sign extended field. Used by instructions like 'addi'. return (int32_t)Imm == (short)Imm; llvm_unreachable("imm32SExt16 should have returned"); } case GICXXPred_I64_Predicate_imm64SExt16: { // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit // sign extended field. Used by instructions like 'addi'. return (int64_t)Imm == (short)Imm; llvm_unreachable("imm64SExt16 should have returned"); } case GICXXPred_I64_Predicate_imm64ZExt32: { // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit // zero extended field. return isUInt<32>(Imm); llvm_unreachable("imm64ZExt32 should have returned"); } case GICXXPred_I64_Predicate_immNonAllOneAnyExt8: { return (isInt<8>(Imm) && (Imm != -1)) || (isUInt<8>(Imm) && (Imm != 0xFF)); } case GICXXPred_I64_Predicate_immSExt5NonZero: { return Imm && isInt<5>(Imm); } } llvm_unreachable("Unknown predicate"); return false; } // PatFrag predicates. bool PPCInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const { llvm_unreachable("Unknown predicate"); return false; } // PatFrag predicates. bool PPCInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const { llvm_unreachable("Unknown predicate"); return false; } bool PPCInstructionSelector::testSimplePredicate(unsigned) const { llvm_unreachable("PPCInstructionSelector does not support simple predicates!"); return false; } // Custom renderers. enum { GICR_Invalid, }; PPCInstructionSelector::CustomRendererFn PPCInstructionSelector::CustomRenderers[] = { nullptr, // GICR_Invalid }; bool PPCInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { const PredicateBitset AvailableFeatures = getAvailableFeatures(); MachineIRBuilder B(I); State.MIs.clear(); State.MIs.push_back(&I); if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) { return true; } return false; } bool PPCInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const { llvm_unreachable("PPCInstructionSelector does not support custom C++ actions!"); } #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ #define GIMT_Encode2 … #define GIMT_Encode4 … #define GIMT_Encode8 … #else #define GIMT_Encode2 … #define GIMT_Encode4 … #define GIMT_Encode8 … #endif const uint8_t *PPCInstructionSelector::getMatchTable() const { constexpr static uint8_t MatchTable0[] = { GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(53), GIMT_Encode2(281), /*)*//*default:*//*Label 82*/ GIMT_Encode4(97385), /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(922), /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(1239), /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(1680), /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(1962), /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(2118), /*TargetOpcode::G_SREM*//*Label 5*/ GIMT_Encode4(2274), /*TargetOpcode::G_UREM*//*Label 6*/ GIMT_Encode4(2436), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_AND*//*Label 7*/ GIMT_Encode4(2598), /*TargetOpcode::G_OR*//*Label 8*/ GIMT_Encode4(3232), /*TargetOpcode::G_XOR*//*Label 9*/ GIMT_Encode4(3866), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_BUILD_VECTOR*//*Label 10*/ GIMT_Encode4(5370), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_BITCAST*//*Label 11*/ GIMT_Encode4(6337), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 12*/ GIMT_Encode4(8614), /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 13*/ GIMT_Encode4(8886), /*TargetOpcode::G_INTRINSIC_LRINT*//*Label 14*/ GIMT_Encode4(9133), /*TargetOpcode::G_INTRINSIC_LLRINT*//*Label 15*/ GIMT_Encode4(9261), GIMT_Encode4(0), /*TargetOpcode::G_READCYCLECOUNTER*//*Label 16*/ GIMT_Encode4(9389), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_FENCE*//*Label 17*/ GIMT_Encode4(9409), GIMT_Encode4(0), /*TargetOpcode::G_BRCOND*//*Label 18*/ GIMT_Encode4(9534), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_INTRINSIC*//*Label 19*/ GIMT_Encode4(9597), /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 20*/ GIMT_Encode4(35509), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_ANYEXT*//*Label 21*/ GIMT_Encode4(38199), /*TargetOpcode::G_TRUNC*//*Label 22*/ GIMT_Encode4(38385), /*TargetOpcode::G_CONSTANT*//*Label 23*/ GIMT_Encode4(38571), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_SEXT*//*Label 24*/ GIMT_Encode4(38723), GIMT_Encode4(0), /*TargetOpcode::G_ZEXT*//*Label 25*/ GIMT_Encode4(38929), /*TargetOpcode::G_SHL*//*Label 26*/ GIMT_Encode4(39115), /*TargetOpcode::G_LSHR*//*Label 27*/ GIMT_Encode4(39465), /*TargetOpcode::G_ASHR*//*Label 28*/ GIMT_Encode4(39815), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_ROTL*//*Label 29*/ GIMT_Encode4(40179), /*TargetOpcode::G_ICMP*//*Label 30*/ GIMT_Encode4(40487), /*TargetOpcode::G_FCMP*//*Label 31*/ GIMT_Encode4(44489), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_SELECT*//*Label 32*/ GIMT_Encode4(48064), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_UMULH*//*Label 33*/ GIMT_Encode4(49161), /*TargetOpcode::G_SMULH*//*Label 34*/ GIMT_Encode4(49291), /*TargetOpcode::G_UADDSAT*//*Label 35*/ GIMT_Encode4(49421), /*TargetOpcode::G_SADDSAT*//*Label 36*/ GIMT_Encode4(49523), /*TargetOpcode::G_USUBSAT*//*Label 37*/ GIMT_Encode4(49625), /*TargetOpcode::G_SSUBSAT*//*Label 38*/ GIMT_Encode4(49727), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_FADD*//*Label 39*/ GIMT_Encode4(49829), /*TargetOpcode::G_FSUB*//*Label 40*/ GIMT_Encode4(50124), /*TargetOpcode::G_FMUL*//*Label 41*/ GIMT_Encode4(50419), /*TargetOpcode::G_FMA*//*Label 42*/ GIMT_Encode4(50769), GIMT_Encode4(0), /*TargetOpcode::G_FDIV*//*Label 43*/ GIMT_Encode4(51350), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_FNEG*//*Label 44*/ GIMT_Encode4(51620), /*TargetOpcode::G_FPEXT*//*Label 45*/ GIMT_Encode4(54010), /*TargetOpcode::G_FPTRUNC*//*Label 46*/ GIMT_Encode4(54171), /*TargetOpcode::G_FPTOSI*//*Label 47*/ GIMT_Encode4(54328), /*TargetOpcode::G_FPTOUI*//*Label 48*/ GIMT_Encode4(54588), /*TargetOpcode::G_SITOFP*//*Label 49*/ GIMT_Encode4(54848), /*TargetOpcode::G_UITOFP*//*Label 50*/ GIMT_Encode4(55092), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_FABS*//*Label 51*/ GIMT_Encode4(55336), /*TargetOpcode::G_FCOPYSIGN*//*Label 52*/ GIMT_Encode4(55625), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_FMINNUM*//*Label 53*/ GIMT_Encode4(55935), /*TargetOpcode::G_FMAXNUM*//*Label 54*/ GIMT_Encode4(56015), /*TargetOpcode::G_FMINNUM_IEEE*//*Label 55*/ GIMT_Encode4(56095), /*TargetOpcode::G_FMAXNUM_IEEE*//*Label 56*/ GIMT_Encode4(56234), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_SMIN*//*Label 57*/ GIMT_Encode4(56373), /*TargetOpcode::G_SMAX*//*Label 58*/ GIMT_Encode4(56547), /*TargetOpcode::G_UMIN*//*Label 59*/ GIMT_Encode4(56721), /*TargetOpcode::G_UMAX*//*Label 60*/ GIMT_Encode4(56895), GIMT_Encode4(0), /*TargetOpcode::G_LROUND*//*Label 61*/ GIMT_Encode4(57069), /*TargetOpcode::G_LLROUND*//*Label 62*/ GIMT_Encode4(57231), /*TargetOpcode::G_BR*//*Label 63*/ GIMT_Encode4(57393), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 64*/ GIMT_Encode4(57409), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_CTTZ*//*Label 65*/ GIMT_Encode4(57527), GIMT_Encode4(0), /*TargetOpcode::G_CTLZ*//*Label 66*/ GIMT_Encode4(57705), GIMT_Encode4(0), /*TargetOpcode::G_CTPOP*//*Label 67*/ GIMT_Encode4(57877), /*TargetOpcode::G_BSWAP*//*Label 68*/ GIMT_Encode4(58049), /*TargetOpcode::G_BITREVERSE*//*Label 69*/ GIMT_Encode4(58307), /*TargetOpcode::G_FCEIL*//*Label 70*/ GIMT_Encode4(94313), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_FSQRT*//*Label 71*/ GIMT_Encode4(94585), /*TargetOpcode::G_FFLOOR*//*Label 72*/ GIMT_Encode4(94802), /*TargetOpcode::G_FRINT*//*Label 73*/ GIMT_Encode4(95074), /*TargetOpcode::G_FNEARBYINT*//*Label 74*/ GIMT_Encode4(95283), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_STRICT_FADD*//*Label 75*/ GIMT_Encode4(95517), /*TargetOpcode::G_STRICT_FSUB*//*Label 76*/ GIMT_Encode4(95787), /*TargetOpcode::G_STRICT_FMUL*//*Label 77*/ GIMT_Encode4(96057), /*TargetOpcode::G_STRICT_FDIV*//*Label 78*/ GIMT_Encode4(96327), GIMT_Encode4(0), /*TargetOpcode::G_STRICT_FMA*//*Label 79*/ GIMT_Encode4(96597), /*TargetOpcode::G_STRICT_FSQRT*//*Label 80*/ GIMT_Encode4(97155), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_TRAP*//*Label 81*/ GIMT_Encode4(97372), // Label 0: @922 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 91*/ GIMT_Encode4(1238), /*GILLT_s1*//*Label 83*/ GIMT_Encode4(965), /*GILLT_s32*//*Label 84*/ GIMT_Encode4(988), /*GILLT_s64*//*Label 85*/ GIMT_Encode4(1048), /*GILLT_s128*//*Label 86*/ GIMT_Encode4(1108), /*GILLT_v2s64*//*Label 87*/ GIMT_Encode4(1134), /*GILLT_v4s32*//*Label 88*/ GIMT_Encode4(1160), /*GILLT_v8s16*//*Label 89*/ GIMT_Encode4(1186), /*GILLT_v16s8*//*Label 90*/ GIMT_Encode4(1212), // Label 83: @965 GIM_Try, /*On fail goto*//*Label 92*/ GIMT_Encode4(987), // Rule ID 3622 // GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), // (add:{ *:[i1] } i1:{ *:[i1] }:$a, i1:{ *:[i1] }:$b) => (CRXOR:{ *:[i1] } ?:{ *:[i1] }:$a, ?:{ *:[i1] }:$b) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CRXOR), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3622, GIR_Done, // Label 92: @987 GIM_Reject, // Label 84: @988 GIM_Try, /*On fail goto*//*Label 93*/ GIMT_Encode4(1047), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), GIM_Try, /*On fail goto*//*Label 94*/ GIMT_Encode4(1034), // Rule ID 107 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } i32:{ *:[i32] }:$RA, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$D) => (ADDI:{ *:[i32] } i32:{ *:[i32] }:$RA, (imm:{ *:[i32] }):$D) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ADDI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_RootToRootCopy, /*OpIdx*/1, // RA GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // D GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 107, GIR_EraseRootFromParent_Done, // Label 94: @1034 GIM_Try, /*On fail goto*//*Label 95*/ GIMT_Encode4(1046), // Rule ID 199 // // (add:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (ADD4:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::ADD4), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 199, GIR_Done, // Label 95: @1046 GIM_Reject, // Label 93: @1047 GIM_Reject, // Label 85: @1048 GIM_Try, /*On fail goto*//*Label 96*/ GIMT_Encode4(1107), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_Try, /*On fail goto*//*Label 97*/ GIMT_Encode4(1094), // Rule ID 659 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } i64:{ *:[i64] }:$RA, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$D) => (ADDI8:{ *:[i64] } i64:{ *:[i64] }:$RA, (imm:{ *:[i64] }):$D) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ADDI8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_RootToRootCopy, /*OpIdx*/1, // RA GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // D GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 659, GIR_EraseRootFromParent_Done, // Label 97: @1094 GIM_Try, /*On fail goto*//*Label 98*/ GIMT_Encode4(1106), // Rule ID 655 // // (add:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (ADD8:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::ADD8), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 655, GIR_Done, // Label 98: @1106 GIM_Reject, // Label 96: @1107 GIM_Reject, // Label 86: @1108 GIM_Try, /*On fail goto*//*Label 99*/ GIMT_Encode4(1133), // Rule ID 470 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (add:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VADDUQM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDUQM), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 470, GIR_Done, // Label 99: @1133 GIM_Reject, // Label 87: @1134 GIM_Try, /*On fail goto*//*Label 100*/ GIMT_Encode4(1159), // Rule ID 469 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (add:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VADDUDM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDUDM), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 469, GIR_Done, // Label 100: @1159 GIM_Reject, // Label 88: @1160 GIM_Try, /*On fail goto*//*Label 101*/ GIMT_Encode4(1185), // Rule ID 303 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (add:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VADDUWM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDUWM), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 303, GIR_Done, // Label 101: @1185 GIM_Reject, // Label 89: @1186 GIM_Try, /*On fail goto*//*Label 102*/ GIMT_Encode4(1211), // Rule ID 302 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (add:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VADDUHM:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDUHM), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 302, GIR_Done, // Label 102: @1211 GIM_Reject, // Label 90: @1212 GIM_Try, /*On fail goto*//*Label 103*/ GIMT_Encode4(1237), // Rule ID 301 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (add:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VADDUBM:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDUBM), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 301, GIR_Done, // Label 103: @1237 GIM_Reject, // Label 91: @1238 GIM_Reject, // Label 1: @1239 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 112*/ GIMT_Encode4(1679), /*GILLT_s1*//*Label 104*/ GIMT_Encode4(1282), /*GILLT_s32*//*Label 105*/ GIMT_Encode4(1305), /*GILLT_s64*//*Label 106*/ GIMT_Encode4(1390), /*GILLT_s128*//*Label 107*/ GIMT_Encode4(1475), /*GILLT_v2s64*//*Label 108*/ GIMT_Encode4(1501), /*GILLT_v4s32*//*Label 109*/ GIMT_Encode4(1564), /*GILLT_v8s16*//*Label 110*/ GIMT_Encode4(1627), /*GILLT_v16s8*//*Label 111*/ GIMT_Encode4(1653), // Label 104: @1282 GIM_Try, /*On fail goto*//*Label 113*/ GIMT_Encode4(1304), // Rule ID 3623 // GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), // (sub:{ *:[i1] } i1:{ *:[i1] }:$a, i1:{ *:[i1] }:$b) => (CRXOR:{ *:[i1] } ?:{ *:[i1] }:$a, ?:{ *:[i1] }:$b) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CRXOR), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3623, GIR_Done, // Label 113: @1304 GIM_Reject, // Label 105: @1305 GIM_Try, /*On fail goto*//*Label 114*/ GIMT_Encode4(1389), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), GIM_Try, /*On fail goto*//*Label 115*/ GIMT_Encode4(1338), // Rule ID 211 // GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0, // (sub:{ *:[i32] } 0:{ *:[i32] }, i32:{ *:[i32] }:$RA) => (NEG:{ *:[i32] } i32:{ *:[i32] }:$RA) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NEG), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 211, GIR_EraseRootFromParent_Done, // Label 115: @1338 GIM_Try, /*On fail goto*//*Label 116*/ GIMT_Encode4(1372), // Rule ID 1206 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, i32:{ *:[i32] }:$in) => (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$in, (imm:{ *:[i32] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SUBFIC), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_RootToRootCopy, /*OpIdx*/2, // in GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CARRY*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1206, GIR_EraseRootFromParent_Done, // Label 116: @1372 GIM_Try, /*On fail goto*//*Label 117*/ GIMT_Encode4(1388), // Rule ID 209 // // (sub:{ *:[i32] } i32:{ *:[i32] }:$RB, i32:{ *:[i32] }:$RA) => (SUBF:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SUBF), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/1, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 209, GIR_EraseRootFromParent_Done, // Label 117: @1388 GIM_Reject, // Label 114: @1389 GIM_Reject, // Label 106: @1390 GIM_Try, /*On fail goto*//*Label 118*/ GIMT_Encode4(1474), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_Try, /*On fail goto*//*Label 119*/ GIMT_Encode4(1423), // Rule ID 665 // GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0, // (sub:{ *:[i64] } 0:{ *:[i64] }, i64:{ *:[i64] }:$RA) => (NEG8:{ *:[i64] } i64:{ *:[i64] }:$RA) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NEG8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 665, GIR_EraseRootFromParent_Done, // Label 119: @1423 GIM_Try, /*On fail goto*//*Label 120*/ GIMT_Encode4(1457), // Rule ID 1528 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, i64:{ *:[i64] }:$in) => (SUBFIC8:{ *:[i64] }:{ *:[i32] } ?:{ *:[i64] }:$in, (imm:{ *:[i64] }):$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SUBFIC8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_RootToRootCopy, /*OpIdx*/2, // in GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CARRY*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1528, GIR_EraseRootFromParent_Done, // Label 120: @1457 GIM_Try, /*On fail goto*//*Label 121*/ GIMT_Encode4(1473), // Rule ID 664 // // (sub:{ *:[i64] } i64:{ *:[i64] }:$RB, i64:{ *:[i64] }:$RA) => (SUBF8:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SUBF8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/1, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 664, GIR_EraseRootFromParent_Done, // Label 121: @1473 GIM_Reject, // Label 118: @1474 GIM_Reject, // Label 107: @1475 GIM_Try, /*On fail goto*//*Label 122*/ GIMT_Encode4(1500), // Rule ID 475 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (sub:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VSUBUQM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBUQM), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 475, GIR_Done, // Label 122: @1500 GIM_Reject, // Label 108: @1501 GIM_Try, /*On fail goto*//*Label 123*/ GIMT_Encode4(1563), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_Try, /*On fail goto*//*Label 124*/ GIMT_Encode4(1547), // Rule ID 542 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllZeros, /*MI*/1, GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, v2i64:{ *:[v2i64] }:$VB) => (VNEGD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNEGD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 542, GIR_EraseRootFromParent_Done, // Label 124: @1547 GIM_Try, /*On fail goto*//*Label 125*/ GIMT_Encode4(1562), // Rule ID 474 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), // (sub:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VSUBUDM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBUDM), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 474, GIR_Done, // Label 125: @1562 GIM_Reject, // Label 123: @1563 GIM_Reject, // Label 109: @1564 GIM_Try, /*On fail goto*//*Label 126*/ GIMT_Encode4(1626), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_Try, /*On fail goto*//*Label 127*/ GIMT_Encode4(1610), // Rule ID 541 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllZeros, /*MI*/1, GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, v4i32:{ *:[v4i32] }:$VB) => (VNEGW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNEGW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 541, GIR_EraseRootFromParent_Done, // Label 127: @1610 GIM_Try, /*On fail goto*//*Label 128*/ GIMT_Encode4(1625), // Rule ID 373 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), // (sub:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSUBUWM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBUWM), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 373, GIR_Done, // Label 128: @1625 GIM_Reject, // Label 126: @1626 GIM_Reject, // Label 110: @1627 GIM_Try, /*On fail goto*//*Label 129*/ GIMT_Encode4(1652), // Rule ID 372 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (sub:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VSUBUHM:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBUHM), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 372, GIR_Done, // Label 129: @1652 GIM_Reject, // Label 111: @1653 GIM_Try, /*On fail goto*//*Label 130*/ GIMT_Encode4(1678), // Rule ID 371 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (sub:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSUBUBM:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBUBM), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 371, GIR_Done, // Label 130: @1678 GIM_Reject, // Label 112: @1679 GIM_Reject, // Label 2: @1680 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(7), /*)*//*default:*//*Label 137*/ GIMT_Encode4(1961), /*GILLT_s1*//*Label 131*/ GIMT_Encode4(1719), /*GILLT_s32*//*Label 132*/ GIMT_Encode4(1742), /*GILLT_s64*//*Label 133*/ GIMT_Encode4(1802), GIMT_Encode4(0), /*GILLT_v2s64*//*Label 134*/ GIMT_Encode4(1862), /*GILLT_v4s32*//*Label 135*/ GIMT_Encode4(1888), /*GILLT_v8s16*//*Label 136*/ GIMT_Encode4(1914), // Label 131: @1719 GIM_Try, /*On fail goto*//*Label 138*/ GIMT_Encode4(1741), // Rule ID 3624 // GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), // (mul:{ *:[i1] } i1:{ *:[i1] }:$a, i1:{ *:[i1] }:$b) => (CRAND:{ *:[i1] } ?:{ *:[i1] }:$a, ?:{ *:[i1] }:$b) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CRAND), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3624, GIR_Done, // Label 138: @1741 GIM_Reject, // Label 132: @1742 GIM_Try, /*On fail goto*//*Label 139*/ GIMT_Encode4(1801), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), GIM_Try, /*On fail goto*//*Label 140*/ GIMT_Encode4(1788), // Rule ID 111 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (mul:{ *:[i32] } i32:{ *:[i32] }:$RA, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$D) => (MULLI:{ *:[i32] } i32:{ *:[i32] }:$RA, (imm:{ *:[i32] }):$D) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MULLI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_RootToRootCopy, /*OpIdx*/1, // RA GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // D GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 111, GIR_EraseRootFromParent_Done, // Label 140: @1788 GIM_Try, /*On fail goto*//*Label 141*/ GIMT_Encode4(1800), // Rule ID 208 // // (mul:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (MULLW:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MULLW), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 208, GIR_Done, // Label 141: @1800 GIM_Reject, // Label 139: @1801 GIM_Reject, // Label 133: @1802 GIM_Try, /*On fail goto*//*Label 142*/ GIMT_Encode4(1861), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_Try, /*On fail goto*//*Label 143*/ GIMT_Encode4(1848), // Rule ID 702 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (mul:{ *:[i64] } i64:{ *:[i64] }:$RA, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$D) => (MULLI8:{ *:[i64] } i64:{ *:[i64] }:$RA, (imm:{ *:[i64] }):$D) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MULLI8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_RootToRootCopy, /*OpIdx*/1, // RA GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // D GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 702, GIR_EraseRootFromParent_Done, // Label 143: @1848 GIM_Try, /*On fail goto*//*Label 144*/ GIMT_Encode4(1860), // Rule ID 701 // // (mul:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (MULLD:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MULLD), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 701, GIR_Done, // Label 144: @1860 GIM_Reject, // Label 142: @1861 GIM_Reject, // Label 134: @1862 GIM_Try, /*On fail goto*//*Label 145*/ GIMT_Encode4(1887), // Rule ID 1118 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (mul:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMULLD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMULLD), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1118, GIR_Done, // Label 145: @1887 GIM_Reject, // Label 135: @1888 GIM_Try, /*On fail goto*//*Label 146*/ GIMT_Encode4(1913), // Rule ID 461 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (mul:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMULUWM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMULUWM), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 461, GIR_Done, // Label 146: @1913 GIM_Reject, // Label 136: @1914 GIM_Try, /*On fail goto*//*Label 147*/ GIMT_Encode4(1960), // Rule ID 1284 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (mul:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VMLADDUHM:{ *:[v8i16] } ?:{ *:[v8i16] }:$vA, ?:{ *:[v8i16] }:$vB, (V_SET0H:{ *:[v8i16] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::V_SET0H), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMLADDUHM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/1, // vA GIR_RootToRootCopy, /*OpIdx*/2, // vB GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1284, GIR_EraseRootFromParent_Done, // Label 147: @1960 GIM_Reject, // Label 137: @1961 GIM_Reject, // Label 3: @1962 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 153*/ GIMT_Encode4(2117), /*GILLT_s32*//*Label 148*/ GIMT_Encode4(1993), /*GILLT_s64*//*Label 149*/ GIMT_Encode4(2016), /*GILLT_s128*//*Label 150*/ GIMT_Encode4(2039), /*GILLT_v2s64*//*Label 151*/ GIMT_Encode4(2065), /*GILLT_v4s32*//*Label 152*/ GIMT_Encode4(2091), // Label 148: @1993 GIM_Try, /*On fail goto*//*Label 154*/ GIMT_Encode4(2015), // Rule ID 202 // GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (sdiv:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (DIVW:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::DIVW), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 202, GIR_Done, // Label 154: @2015 GIM_Reject, // Label 149: @2016 GIM_Try, /*On fail goto*//*Label 155*/ GIMT_Encode4(2038), // Rule ID 693 // GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (sdiv:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (DIVD:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::DIVD), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 693, GIR_Done, // Label 155: @2038 GIM_Reject, // Label 150: @2039 GIM_Try, /*On fail goto*//*Label 156*/ GIMT_Encode4(2064), // Rule ID 1142 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (sdiv:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VDIVSQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VDIVSQ), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1142, GIR_Done, // Label 156: @2064 GIM_Reject, // Label 151: @2065 GIM_Try, /*On fail goto*//*Label 157*/ GIMT_Encode4(2090), // Rule ID 1129 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (sdiv:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VDIVSD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VDIVSD), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1129, GIR_Done, // Label 157: @2090 GIM_Reject, // Label 152: @2091 GIM_Try, /*On fail goto*//*Label 158*/ GIMT_Encode4(2116), // Rule ID 1127 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (sdiv:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VDIVSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VDIVSW), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1127, GIR_Done, // Label 158: @2116 GIM_Reject, // Label 153: @2117 GIM_Reject, // Label 4: @2118 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 164*/ GIMT_Encode4(2273), /*GILLT_s32*//*Label 159*/ GIMT_Encode4(2149), /*GILLT_s64*//*Label 160*/ GIMT_Encode4(2172), /*GILLT_s128*//*Label 161*/ GIMT_Encode4(2195), /*GILLT_v2s64*//*Label 162*/ GIMT_Encode4(2221), /*GILLT_v4s32*//*Label 163*/ GIMT_Encode4(2247), // Label 159: @2149 GIM_Try, /*On fail goto*//*Label 165*/ GIMT_Encode4(2171), // Rule ID 203 // GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (udiv:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (DIVWU:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::DIVWU), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 203, GIR_Done, // Label 165: @2171 GIM_Reject, // Label 160: @2172 GIM_Try, /*On fail goto*//*Label 166*/ GIMT_Encode4(2194), // Rule ID 694 // GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (udiv:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (DIVDU:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::DIVDU), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 694, GIR_Done, // Label 166: @2194 GIM_Reject, // Label 161: @2195 GIM_Try, /*On fail goto*//*Label 167*/ GIMT_Encode4(2220), // Rule ID 1143 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (udiv:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VDIVUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VDIVUQ), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1143, GIR_Done, // Label 167: @2220 GIM_Reject, // Label 162: @2221 GIM_Try, /*On fail goto*//*Label 168*/ GIMT_Encode4(2246), // Rule ID 1130 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (udiv:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VDIVUD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VDIVUD), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1130, GIR_Done, // Label 168: @2246 GIM_Reject, // Label 163: @2247 GIM_Try, /*On fail goto*//*Label 169*/ GIMT_Encode4(2272), // Rule ID 1128 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (udiv:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VDIVUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VDIVUW), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1128, GIR_Done, // Label 169: @2272 GIM_Reject, // Label 164: @2273 GIM_Reject, // Label 5: @2274 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 175*/ GIMT_Encode4(2435), /*GILLT_s32*//*Label 170*/ GIMT_Encode4(2305), /*GILLT_s64*//*Label 171*/ GIMT_Encode4(2331), /*GILLT_s128*//*Label 172*/ GIMT_Encode4(2357), /*GILLT_v2s64*//*Label 173*/ GIMT_Encode4(2383), /*GILLT_v4s32*//*Label 174*/ GIMT_Encode4(2409), // Label 170: @2305 GIM_Try, /*On fail goto*//*Label 176*/ GIMT_Encode4(2330), // Rule ID 197 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_0), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (srem:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (MODSW:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MODSW), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 197, GIR_Done, // Label 176: @2330 GIM_Reject, // Label 171: @2331 GIM_Try, /*On fail goto*//*Label 177*/ GIMT_Encode4(2356), // Rule ID 698 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_0), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (srem:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (MODSD:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MODSD), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 698, GIR_Done, // Label 177: @2356 GIM_Reject, // Label 172: @2357 GIM_Try, /*On fail goto*//*Label 178*/ GIMT_Encode4(2382), // Rule ID 1152 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (srem:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VMODSQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMODSQ), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1152, GIR_Done, // Label 178: @2382 GIM_Reject, // Label 173: @2383 GIM_Try, /*On fail goto*//*Label 179*/ GIMT_Encode4(2408), // Rule ID 1125 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (srem:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMODSD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMODSD), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1125, GIR_Done, // Label 179: @2408 GIM_Reject, // Label 174: @2409 GIM_Try, /*On fail goto*//*Label 180*/ GIMT_Encode4(2434), // Rule ID 1123 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (srem:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMODSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMODSW), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1123, GIR_Done, // Label 180: @2434 GIM_Reject, // Label 175: @2435 GIM_Reject, // Label 6: @2436 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 186*/ GIMT_Encode4(2597), /*GILLT_s32*//*Label 181*/ GIMT_Encode4(2467), /*GILLT_s64*//*Label 182*/ GIMT_Encode4(2493), /*GILLT_s128*//*Label 183*/ GIMT_Encode4(2519), /*GILLT_v2s64*//*Label 184*/ GIMT_Encode4(2545), /*GILLT_v4s32*//*Label 185*/ GIMT_Encode4(2571), // Label 181: @2467 GIM_Try, /*On fail goto*//*Label 187*/ GIMT_Encode4(2492), // Rule ID 198 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_0), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (urem:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (MODUW:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MODUW), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 198, GIR_Done, // Label 187: @2492 GIM_Reject, // Label 182: @2493 GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(2518), // Rule ID 699 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_0), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (urem:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (MODUD:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MODUD), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 699, GIR_Done, // Label 188: @2518 GIM_Reject, // Label 183: @2519 GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(2544), // Rule ID 1153 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (urem:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VMODUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMODUQ), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1153, GIR_Done, // Label 189: @2544 GIM_Reject, // Label 184: @2545 GIM_Try, /*On fail goto*//*Label 190*/ GIMT_Encode4(2570), // Rule ID 1126 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (urem:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMODUD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMODUD), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1126, GIR_Done, // Label 190: @2570 GIM_Reject, // Label 185: @2571 GIM_Try, /*On fail goto*//*Label 191*/ GIMT_Encode4(2596), // Rule ID 1124 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (urem:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMODUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMODUW), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1124, GIR_Done, // Label 191: @2596 GIM_Reject, // Label 186: @2597 GIM_Reject, // Label 7: @2598 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(6), /*)*//*default:*//*Label 196*/ GIMT_Encode4(3231), /*GILLT_s1*//*Label 192*/ GIMT_Encode4(2633), /*GILLT_s32*//*Label 193*/ GIMT_Encode4(2742), /*GILLT_s64*//*Label 194*/ GIMT_Encode4(2851), GIMT_Encode4(0), GIMT_Encode4(0), /*GILLT_v4s32*//*Label 195*/ GIMT_Encode4(2960), // Label 192: @2633 GIM_Try, /*On fail goto*//*Label 197*/ GIMT_Encode4(2741), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), GIM_Try, /*On fail goto*//*Label 198*/ GIMT_Encode4(2688), // Rule ID 4870 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i1] } (xor:{ *:[i1] } i1:{ *:[i1] }:$CRB, -1:{ *:[i1] }), i1:{ *:[i1] }:$CRA) => (CRANDC:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRANDC), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] GIR_RootToRootCopy, /*OpIdx*/2, // CRA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4870, GIR_EraseRootFromParent_Done, // Label 198: @2688 GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(2728), // Rule ID 182 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i1] } i1:{ *:[i1] }:$CRA, (xor:{ *:[i1] } i1:{ *:[i1] }:$CRB, -1:{ *:[i1] })) => (CRANDC:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRANDC), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] GIR_RootToRootCopy, /*OpIdx*/1, // CRA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 182, GIR_EraseRootFromParent_Done, // Label 199: @2728 GIM_Try, /*On fail goto*//*Label 200*/ GIMT_Encode4(2740), // Rule ID 175 // // (and:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) => (CRAND:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CRAND), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 175, GIR_Done, // Label 200: @2740 GIM_Reject, // Label 197: @2741 GIM_Reject, // Label 193: @2742 GIM_Try, /*On fail goto*//*Label 201*/ GIMT_Encode4(2850), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(2797), // Rule ID 4864 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$RB, -1:{ *:[i32] }), i32:{ *:[i32] }:$RST) => (ANDC:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ANDC), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/2, // RST GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4864, GIR_EraseRootFromParent_Done, // Label 202: @2797 GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(2837), // Rule ID 123 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } i32:{ *:[i32] }:$RST, (xor:{ *:[i32] } i32:{ *:[i32] }:$RB, -1:{ *:[i32] })) => (ANDC:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ANDC), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/1, // RST GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 123, GIR_EraseRootFromParent_Done, // Label 203: @2837 GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(2849), // Rule ID 122 // // (and:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) => (AND:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::AND), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 122, GIR_Done, // Label 204: @2849 GIM_Reject, // Label 201: @2850 GIM_Reject, // Label 194: @2851 GIM_Try, /*On fail goto*//*Label 205*/ GIMT_Encode4(2959), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_Try, /*On fail goto*//*Label 206*/ GIMT_Encode4(2906), // Rule ID 4877 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$RB, -1:{ *:[i64] }), i64:{ *:[i64] }:$RST) => (ANDC8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ANDC8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/2, // RST GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4877, GIR_EraseRootFromParent_Done, // Label 206: @2906 GIM_Try, /*On fail goto*//*Label 207*/ GIMT_Encode4(2946), // Rule ID 643 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i64] } i64:{ *:[i64] }:$RST, (xor:{ *:[i64] } i64:{ *:[i64] }:$RB, -1:{ *:[i64] })) => (ANDC8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ANDC8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/1, // RST GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 643, GIR_EraseRootFromParent_Done, // Label 207: @2946 GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(2958), // Rule ID 642 // // (and:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (AND8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::AND8), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 642, GIR_Done, // Label 208: @2958 GIM_Reject, // Label 205: @2959 GIM_Reject, // Label 195: @2960 GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(3230), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 210*/ GIMT_Encode4(3026), // Rule ID 4885 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$XA) => (XXLANDC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLANDC), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4885, GIR_EraseRootFromParent_Done, // Label 210: @3026 GIM_Try, /*On fail goto*//*Label 211*/ GIMT_Encode4(3081), // Rule ID 929 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB, immAllOnesV:{ *:[v4i32] })) => (XXLANDC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLANDC), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/1, // XA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 929, GIR_EraseRootFromParent_Done, // Label 211: @3081 GIM_Try, /*On fail goto*//*Label 212*/ GIMT_Encode4(3100), // Rule ID 928 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) => (XXLAND:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XXLAND), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 928, GIR_Done, // Label 212: @3100 GIM_Try, /*On fail goto*//*Label 213*/ GIMT_Encode4(3155), // Rule ID 4873 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$VA) => (VANDC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VANDC), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4873, GIR_EraseRootFromParent_Done, // Label 213: @3155 GIM_Try, /*On fail goto*//*Label 214*/ GIMT_Encode4(3210), // Rule ID 312 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB, immAllOnesV:{ *:[v4i32] })) => (VANDC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VANDC), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/1, // VA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 312, GIR_EraseRootFromParent_Done, // Label 214: @3210 GIM_Try, /*On fail goto*//*Label 215*/ GIMT_Encode4(3229), // Rule ID 311 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VAND:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VAND), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 311, GIR_Done, // Label 215: @3229 GIM_Reject, // Label 209: @3230 GIM_Reject, // Label 196: @3231 GIM_Reject, // Label 8: @3232 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(6), /*)*//*default:*//*Label 220*/ GIMT_Encode4(3865), /*GILLT_s1*//*Label 216*/ GIMT_Encode4(3267), /*GILLT_s32*//*Label 217*/ GIMT_Encode4(3376), /*GILLT_s64*//*Label 218*/ GIMT_Encode4(3485), GIMT_Encode4(0), GIMT_Encode4(0), /*GILLT_v4s32*//*Label 219*/ GIMT_Encode4(3594), // Label 216: @3267 GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(3375), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), GIM_Try, /*On fail goto*//*Label 222*/ GIMT_Encode4(3322), // Rule ID 4871 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (or:{ *:[i1] } (xor:{ *:[i1] } i1:{ *:[i1] }:$CRB, -1:{ *:[i1] }), i1:{ *:[i1] }:$CRA) => (CRORC:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRORC), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] GIR_RootToRootCopy, /*OpIdx*/2, // CRA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4871, GIR_EraseRootFromParent_Done, // Label 222: @3322 GIM_Try, /*On fail goto*//*Label 223*/ GIMT_Encode4(3362), // Rule ID 183 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (or:{ *:[i1] } i1:{ *:[i1] }:$CRA, (xor:{ *:[i1] } i1:{ *:[i1] }:$CRB, -1:{ *:[i1] })) => (CRORC:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRORC), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] GIR_RootToRootCopy, /*OpIdx*/1, // CRA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 183, GIR_EraseRootFromParent_Done, // Label 223: @3362 GIM_Try, /*On fail goto*//*Label 224*/ GIMT_Encode4(3374), // Rule ID 177 // // (or:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) => (CROR:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CROR), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 177, GIR_Done, // Label 224: @3374 GIM_Reject, // Label 221: @3375 GIM_Reject, // Label 217: @3376 GIM_Try, /*On fail goto*//*Label 225*/ GIMT_Encode4(3484), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), GIM_Try, /*On fail goto*//*Label 226*/ GIMT_Encode4(3431), // Rule ID 4865 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (or:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$RB, -1:{ *:[i32] }), i32:{ *:[i32] }:$RST) => (ORC:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ORC), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/2, // RST GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4865, GIR_EraseRootFromParent_Done, // Label 226: @3431 GIM_Try, /*On fail goto*//*Label 227*/ GIMT_Encode4(3471), // Rule ID 126 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (or:{ *:[i32] } i32:{ *:[i32] }:$RST, (xor:{ *:[i32] } i32:{ *:[i32] }:$RB, -1:{ *:[i32] })) => (ORC:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ORC), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/1, // RST GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 126, GIR_EraseRootFromParent_Done, // Label 227: @3471 GIM_Try, /*On fail goto*//*Label 228*/ GIMT_Encode4(3483), // Rule ID 124 // // (or:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) => (OR:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::OR), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 124, GIR_Done, // Label 228: @3483 GIM_Reject, // Label 225: @3484 GIM_Reject, // Label 218: @3485 GIM_Try, /*On fail goto*//*Label 229*/ GIMT_Encode4(3593), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_Try, /*On fail goto*//*Label 230*/ GIMT_Encode4(3540), // Rule ID 4878 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (or:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$RB, -1:{ *:[i64] }), i64:{ *:[i64] }:$RST) => (ORC8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ORC8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/2, // RST GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4878, GIR_EraseRootFromParent_Done, // Label 230: @3540 GIM_Try, /*On fail goto*//*Label 231*/ GIMT_Encode4(3580), // Rule ID 646 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (or:{ *:[i64] } i64:{ *:[i64] }:$RST, (xor:{ *:[i64] } i64:{ *:[i64] }:$RB, -1:{ *:[i64] })) => (ORC8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ORC8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/1, // RST GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 646, GIR_EraseRootFromParent_Done, // Label 231: @3580 GIM_Try, /*On fail goto*//*Label 232*/ GIMT_Encode4(3592), // Rule ID 644 // // (or:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (OR8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::OR8), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 644, GIR_Done, // Label 232: @3592 GIM_Reject, // Label 229: @3593 GIM_Reject, // Label 219: @3594 GIM_Try, /*On fail goto*//*Label 233*/ GIMT_Encode4(3864), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 234*/ GIMT_Encode4(3660), // Rule ID 4888 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$XA) => (XXLORC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLORC), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4888, GIR_EraseRootFromParent_Done, // Label 234: @3660 GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(3715), // Rule ID 942 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB, immAllOnesV:{ *:[v4i32] })) => (XXLORC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLORC), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/1, // XA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 942, GIR_EraseRootFromParent_Done, // Label 235: @3715 GIM_Try, /*On fail goto*//*Label 236*/ GIMT_Encode4(3734), // Rule ID 931 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) => (XXLOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XXLOR), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 931, GIR_Done, // Label 236: @3734 GIM_Try, /*On fail goto*//*Label 237*/ GIMT_Encode4(3789), // Rule ID 4876 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$VA) => (VORC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VORC), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4876, GIR_EraseRootFromParent_Done, // Label 237: @3789 GIM_Try, /*On fail goto*//*Label 238*/ GIMT_Encode4(3844), // Rule ID 489 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB, immAllOnesV:{ *:[v4i32] })) => (VORC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VORC), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/1, // VA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 489, GIR_EraseRootFromParent_Done, // Label 238: @3844 GIM_Try, /*On fail goto*//*Label 239*/ GIMT_Encode4(3863), // Rule ID 386 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VOR), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 386, GIR_Done, // Label 239: @3863 GIM_Reject, // Label 233: @3864 GIM_Reject, // Label 220: @3865 GIM_Reject, // Label 9: @3866 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(6), /*)*//*default:*//*Label 244*/ GIMT_Encode4(5369), /*GILLT_s1*//*Label 240*/ GIMT_Encode4(3901), /*GILLT_s32*//*Label 241*/ GIMT_Encode4(4172), /*GILLT_s64*//*Label 242*/ GIMT_Encode4(4427), GIMT_Encode4(0), GIMT_Encode4(0), /*GILLT_v4s32*//*Label 243*/ GIMT_Encode4(4682), // Label 240: @3901 GIM_Try, /*On fail goto*//*Label 245*/ GIMT_Encode4(4171), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), GIM_Try, /*On fail goto*//*Label 246*/ GIMT_Encode4(3958), // Rule ID 176 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (xor:{ *:[i1] } (and:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB), -1:{ *:[i1] }) => (CRNAND:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNAND), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // CRB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 176, GIR_EraseRootFromParent_Done, // Label 246: @3958 GIM_Try, /*On fail goto*//*Label 247*/ GIMT_Encode4(4000), // Rule ID 179 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (xor:{ *:[i1] } (or:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB), -1:{ *:[i1] }) => (CRNOR:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // CRB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 179, GIR_EraseRootFromParent_Done, // Label 247: @4000 GIM_Try, /*On fail goto*//*Label 248*/ GIMT_Encode4(4040), // Rule ID 4868 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (xor:{ *:[i1] } (xor:{ *:[i1] } i1:{ *:[i1] }:$CRA, -1:{ *:[i1] }), i1:{ *:[i1] }:$CRB) => (CREQV:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CREQV), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRA GIR_RootToRootCopy, /*OpIdx*/2, // CRB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4868, GIR_EraseRootFromParent_Done, // Label 248: @4040 GIM_Try, /*On fail goto*//*Label 249*/ GIMT_Encode4(4082), // Rule ID 180 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (xor:{ *:[i1] } (xor:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB), -1:{ *:[i1] }) => (CREQV:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CREQV), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // CRB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 180, GIR_EraseRootFromParent_Done, // Label 249: @4082 GIM_Try, /*On fail goto*//*Label 250*/ GIMT_Encode4(4122), // Rule ID 4869 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (xor:{ *:[i1] } i1:{ *:[i1] }:$CRB, (xor:{ *:[i1] } i1:{ *:[i1] }:$CRA, -1:{ *:[i1] })) => (CREQV:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CREQV), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRA GIR_RootToRootCopy, /*OpIdx*/1, // CRB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4869, GIR_EraseRootFromParent_Done, // Label 250: @4122 GIM_Try, /*On fail goto*//*Label 251*/ GIMT_Encode4(4140), // Rule ID 181 // GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), // (xor:{ *:[i1] } i1:{ *:[i1] }:$CRA, -1:{ *:[i1] }) => (CRNOT:{ *:[i1] } i1:{ *:[i1] }:$CRA) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] GIR_RootToRootCopy, /*OpIdx*/1, // CRA GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 181, GIR_EraseRootFromParent_Done, // Label 251: @4140 GIM_Try, /*On fail goto*//*Label 252*/ GIMT_Encode4(4158), // Rule ID 2893 // GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), // (xor:{ *:[i1] } i1:{ *:[i1] }:$in, -1:{ *:[i1] }) => (CRNOT:{ *:[i1] } ?:{ *:[i1] }:$in) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] GIR_RootToRootCopy, /*OpIdx*/1, // in GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2893, GIR_EraseRootFromParent_Done, // Label 252: @4158 GIM_Try, /*On fail goto*//*Label 253*/ GIMT_Encode4(4170), // Rule ID 178 // // (xor:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) => (CRXOR:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CRXOR), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 178, GIR_Done, // Label 253: @4170 GIM_Reject, // Label 245: @4171 GIM_Reject, // Label 241: @4172 GIM_Try, /*On fail goto*//*Label 254*/ GIMT_Encode4(4426), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), GIM_Try, /*On fail goto*//*Label 255*/ GIMT_Encode4(4229), // Rule ID 121 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (xor:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB), -1:{ *:[i32] }) => (NAND:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NAND), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 121, GIR_EraseRootFromParent_Done, // Label 255: @4229 GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(4271), // Rule ID 125 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (xor:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB), -1:{ *:[i32] }) => (NOR:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NOR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 125, GIR_EraseRootFromParent_Done, // Label 256: @4271 GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(4311), // Rule ID 4866 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (xor:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$RST, -1:{ *:[i32] }), i32:{ *:[i32] }:$RB) => (EQV:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EQV), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST GIR_RootToRootCopy, /*OpIdx*/2, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4866, GIR_EraseRootFromParent_Done, // Label 257: @4311 GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(4353), // Rule ID 127 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (xor:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB), -1:{ *:[i32] }) => (EQV:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EQV), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 127, GIR_EraseRootFromParent_Done, // Label 258: @4353 GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(4393), // Rule ID 4867 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (xor:{ *:[i32] } i32:{ *:[i32] }:$RB, (xor:{ *:[i32] } i32:{ *:[i32] }:$RST, -1:{ *:[i32] })) => (EQV:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EQV), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST GIR_RootToRootCopy, /*OpIdx*/1, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4867, GIR_EraseRootFromParent_Done, // Label 259: @4393 GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(4413), // Rule ID 1202 // GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), // (xor:{ *:[i32] } i32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR:{ *:[i32] } ?:{ *:[i32] }:$in, ?:{ *:[i32] }:$in) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NOR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/1, // in GIR_RootToRootCopy, /*OpIdx*/1, // in GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1202, GIR_EraseRootFromParent_Done, // Label 260: @4413 GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(4425), // Rule ID 128 // // (xor:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) => (XOR:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XOR), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 128, GIR_Done, // Label 261: @4425 GIM_Reject, // Label 254: @4426 GIM_Reject, // Label 242: @4427 GIM_Try, /*On fail goto*//*Label 262*/ GIMT_Encode4(4681), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_Try, /*On fail goto*//*Label 263*/ GIMT_Encode4(4484), // Rule ID 641 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (xor:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB), -1:{ *:[i64] }) => (NAND8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NAND8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 641, GIR_EraseRootFromParent_Done, // Label 263: @4484 GIM_Try, /*On fail goto*//*Label 264*/ GIMT_Encode4(4526), // Rule ID 645 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (xor:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB), -1:{ *:[i64] }) => (NOR8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NOR8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 645, GIR_EraseRootFromParent_Done, // Label 264: @4526 GIM_Try, /*On fail goto*//*Label 265*/ GIMT_Encode4(4566), // Rule ID 4879 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (xor:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$RST, -1:{ *:[i64] }), i64:{ *:[i64] }:$RB) => (EQV8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EQV8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST GIR_RootToRootCopy, /*OpIdx*/2, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4879, GIR_EraseRootFromParent_Done, // Label 265: @4566 GIM_Try, /*On fail goto*//*Label 266*/ GIMT_Encode4(4608), // Rule ID 647 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (xor:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB), -1:{ *:[i64] }) => (EQV8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EQV8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 647, GIR_EraseRootFromParent_Done, // Label 266: @4608 GIM_Try, /*On fail goto*//*Label 267*/ GIMT_Encode4(4648), // Rule ID 4880 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (xor:{ *:[i64] } i64:{ *:[i64] }:$RB, (xor:{ *:[i64] } i64:{ *:[i64] }:$RST, -1:{ *:[i64] })) => (EQV8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EQV8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST GIR_RootToRootCopy, /*OpIdx*/1, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4880, GIR_EraseRootFromParent_Done, // Label 267: @4648 GIM_Try, /*On fail goto*//*Label 268*/ GIMT_Encode4(4668), // Rule ID 1514 // GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), // (xor:{ *:[i64] } i64:{ *:[i64] }:$in, -1:{ *:[i64] }) => (NOR8:{ *:[i64] } ?:{ *:[i64] }:$in, ?:{ *:[i64] }:$in) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NOR8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/1, // in GIR_RootToRootCopy, /*OpIdx*/1, // in GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1514, GIR_EraseRootFromParent_Done, // Label 268: @4668 GIM_Try, /*On fail goto*//*Label 269*/ GIMT_Encode4(4680), // Rule ID 648 // // (xor:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (XOR8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XOR8), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 648, GIR_Done, // Label 269: @4680 GIM_Reject, // Label 262: @4681 GIM_Reject, // Label 243: @4682 GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(5368), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 271*/ GIMT_Encode4(4750), // Rule ID 940 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB), immAllOnesV:{ *:[v4i32] }) => (XXLNAND:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLNAND), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 940, GIR_EraseRootFromParent_Done, // Label 271: @4750 GIM_Try, /*On fail goto*//*Label 272*/ GIMT_Encode4(4807), // Rule ID 930 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB), immAllOnesV:{ *:[v4i32] }) => (XXLNOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLNOR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 930, GIR_EraseRootFromParent_Done, // Label 272: @4807 GIM_Try, /*On fail goto*//*Label 273*/ GIMT_Encode4(4862), // Rule ID 4886 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$XB) => (XXLEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLEQV), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA GIR_RootToRootCopy, /*OpIdx*/2, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4886, GIR_EraseRootFromParent_Done, // Label 273: @4862 GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(4919), // Rule ID 939 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB), immAllOnesV:{ *:[v4i32] }) => (XXLEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLEQV), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 939, GIR_EraseRootFromParent_Done, // Label 274: @4919 GIM_Try, /*On fail goto*//*Label 275*/ GIMT_Encode4(4974), // Rule ID 4887 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, immAllOnesV:{ *:[v4i32] })) => (XXLEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLEQV), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA GIR_RootToRootCopy, /*OpIdx*/1, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4887, GIR_EraseRootFromParent_Done, // Label 275: @4974 GIM_Try, /*On fail goto*//*Label 276*/ GIMT_Encode4(5011), // Rule ID 1575 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/1, GIM_CheckIsSafeToFold, /*NumInsns*/1, // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$A, immAllOnesV:{ *:[v4i32] }) => (XXLNOR:{ *:[v4i32] } ?:{ *:[v4i32] }:$A, ?:{ *:[v4i32] }:$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLNOR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/1, // A GIR_RootToRootCopy, /*OpIdx*/1, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1575, GIR_EraseRootFromParent_Done, // Label 276: @5011 GIM_Try, /*On fail goto*//*Label 277*/ GIMT_Encode4(5030), // Rule ID 932 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) => (XXLXOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XXLXOR), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 932, GIR_Done, // Label 277: @5030 GIM_Try, /*On fail goto*//*Label 278*/ GIMT_Encode4(5087), // Rule ID 488 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB), immAllOnesV:{ *:[v4i32] }) => (VNAND:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNAND), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 488, GIR_EraseRootFromParent_Done, // Label 278: @5087 GIM_Try, /*On fail goto*//*Label 279*/ GIMT_Encode4(5144), // Rule ID 385 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB), immAllOnesV:{ *:[v4i32] }) => (VNOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNOR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 385, GIR_EraseRootFromParent_Done, // Label 279: @5144 GIM_Try, /*On fail goto*//*Label 280*/ GIMT_Encode4(5199), // Rule ID 4874 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$VB) => (VEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEQV), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VA GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4874, GIR_EraseRootFromParent_Done, // Label 280: @5199 GIM_Try, /*On fail goto*//*Label 281*/ GIMT_Encode4(5256), // Rule ID 487 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB), immAllOnesV:{ *:[v4i32] }) => (VEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEQV), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 487, GIR_EraseRootFromParent_Done, // Label 281: @5256 GIM_Try, /*On fail goto*//*Label 282*/ GIMT_Encode4(5311), // Rule ID 4875 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, immAllOnesV:{ *:[v4i32] })) => (VEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEQV), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VA GIR_RootToRootCopy, /*OpIdx*/1, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4875, GIR_EraseRootFromParent_Done, // Label 282: @5311 GIM_Try, /*On fail goto*//*Label 283*/ GIMT_Encode4(5348), // Rule ID 1371 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/1, GIM_CheckIsSafeToFold, /*NumInsns*/1, // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] }) => (VNOR:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vA) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNOR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/1, // vA GIR_RootToRootCopy, /*OpIdx*/1, // vA GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1371, GIR_EraseRootFromParent_Done, // Label 283: @5348 GIM_Try, /*On fail goto*//*Label 284*/ GIMT_Encode4(5367), // Rule ID 387 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VXOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VXOR), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 387, GIR_Done, // Label 284: @5367 GIM_Reject, // Label 270: @5368 GIM_Reject, // Label 244: @5369 GIM_Reject, // Label 10: @5370 GIM_Try, /*On fail goto*//*Label 285*/ GIMT_Encode4(5670), GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_Try, /*On fail goto*//*Label 286*/ GIMT_Encode4(5513), // Rule ID 2117 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX_IsBigEndian_IsPPC64_NoP9Vector), // (build_vector:{ *:[v2i64] } i64:{ *:[i64] }:$A, i64:{ *:[i64] }:$B) => (XXPERMDI:{ *:[v2i64] } (SUBREG_TO_REG:{ *:[v4i32] } 1:{ *:[i64] }, (MTVSRD:{ *:[f64] } ?:{ *:[i64] }:$A), sub_64:{ *:[i32] }), (SUBREG_TO_REG:{ *:[v4i32] } 1:{ *:[i64] }, (MTVSRD:{ *:[f64] } ?:{ *:[i64] }:$B), sub_64:{ *:[i32] }), 0:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::MTVSRD), GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // B GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddImm8, /*InsnID*/3, /*Imm*/1, GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, GIR_AddImm8, /*InsnID*/3, /*Imm*/3, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(PPC::VSFRCRegClassID), GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::MTVSRD), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // A GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddImm8, /*InsnID*/1, /*Imm*/1, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_AddImm8, /*InsnID*/1, /*Imm*/3, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(PPC::VSFRCRegClassID), GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXPERMDI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2117, GIR_EraseRootFromParent_Done, // Label 286: @5513 GIM_Try, /*On fail goto*//*Label 287*/ GIMT_Encode4(5635), // Rule ID 2120 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX_IsLittleEndian_NoP9Vector), // (build_vector:{ *:[v2i64] } i64:{ *:[i64] }:$A, i64:{ *:[i64] }:$B) => (XXPERMDI:{ *:[v2i64] } (SUBREG_TO_REG:{ *:[v4i32] } 1:{ *:[i64] }, (MTVSRD:{ *:[f64] } ?:{ *:[i64] }:$B), sub_64:{ *:[i32] }), (SUBREG_TO_REG:{ *:[v4i32] } 1:{ *:[i64] }, (MTVSRD:{ *:[f64] } ?:{ *:[i64] }:$A), sub_64:{ *:[i32] }), 0:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::MTVSRD), GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // A GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddImm8, /*InsnID*/3, /*Imm*/1, GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, GIR_AddImm8, /*InsnID*/3, /*Imm*/3, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(PPC::VSFRCRegClassID), GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::MTVSRD), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // B GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddImm8, /*InsnID*/1, /*Imm*/1, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_AddImm8, /*InsnID*/1, /*Imm*/3, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(PPC::VSFRCRegClassID), GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXPERMDI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2120, GIR_EraseRootFromParent_Done, // Label 287: @5635 GIM_Try, /*On fail goto*//*Label 288*/ GIMT_Encode4(5650), // Rule ID 2863 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX_IsBigEndian_IsISA3_0_IsPPC64), // (build_vector:{ *:[v2i64] } i64:{ *:[i64] }:$rB, i64:{ *:[i64] }:$rA) => (MTVSRDD:{ *:[v2i64] } ?:{ *:[i64] }:$rB, ?:{ *:[i64] }:$rA) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MTVSRDD), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2863, GIR_Done, // Label 288: @5650 GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(5669), // Rule ID 2867 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX_IsISA3_0_IsLittleEndian), // (build_vector:{ *:[v2i64] } i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) => (MTVSRDD:{ *:[v2i64] } ?:{ *:[i64] }:$rB, ?:{ *:[i64] }:$rA) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRDD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // rB GIR_RootToRootCopy, /*OpIdx*/1, // rA GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2867, GIR_EraseRootFromParent_Done, // Label 289: @5669 GIM_Reject, // Label 285: @5670 GIM_Try, /*On fail goto*//*Label 290*/ GIMT_Encode4(6195), GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 291*/ GIMT_Encode4(5735), // Rule ID 2031 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExt5NonZero), // MIs[1] Operand 1 // No operand predicates // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, GIM_CheckIsSafeToFold, /*NumInsns*/1, // (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immSExt5NonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_immSExt5NonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_immSExt5NonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_immSExt5NonZero>>:$A) => (VSPLTISW:{ *:[v4i32] } (imm:{ *:[i32] }):$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSPLTISW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2031, GIR_EraseRootFromParent_Done, // Label 291: @5735 GIM_Try, /*On fail goto*//*Label 292*/ GIMT_Encode4(5786), // Rule ID 3364 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32immNonAllOneNonZero), // MIs[1] Operand 1 // No operand predicates // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, GIM_CheckIsSafeToFold, /*NumInsns*/1, // (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_i32immNonAllOneNonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_i32immNonAllOneNonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_i32immNonAllOneNonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_i32immNonAllOneNonZero>>:$A) => (XXSPLTIW:{ *:[v4i32] } (imm:{ *:[i32] }):$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSPLTIW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3364, GIR_EraseRootFromParent_Done, // Label 292: @5786 GIM_Try, /*On fail goto*//*Label 293*/ GIMT_Encode4(5922), // Rule ID 1723 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTRUNC), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FPTRUNC), // MIs[2] A GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FPTRUNC), // MIs[3] A GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/4, // MIs[4] GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_FPTRUNC), // MIs[4] A GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_CheckIsSafeToFold, /*NumInsns*/4, // (build_vector:{ *:[v4f32] } (fpround:{ *:[f32] } f64:{ *:[f64] }:$A), (fpround:{ *:[f32] } f64:{ *:[f64] }:$A), (fpround:{ *:[f32] } f64:{ *:[f64] }:$A), (fpround:{ *:[f32] } f64:{ *:[f64] }:$A)) => (XXSPLTW:{ *:[v4f32] } (SUBREG_TO_REG:{ *:[v4i32] } 1:{ *:[i64] }, (XSCVDPSP:{ *:[f64] } f64:{ *:[f64] }:$A), sub_64:{ *:[i32] }), 0:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCVDPSP), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // A GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddImm8, /*InsnID*/1, /*Imm*/1, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_AddImm8, /*InsnID*/1, /*Imm*/3, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(PPC::VSFRCRegClassID), GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSPLTW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1723, GIR_EraseRootFromParent_Done, // Label 293: @5922 GIM_Try, /*On fail goto*//*Label 294*/ GIMT_Encode4(5980), // Rule ID 1724 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, // (build_vector:{ *:[v4f32] } f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$A) => (XXSPLTW:{ *:[v4f32] } (XSCVDPSPN:{ *:[v4f32] } ?:{ *:[f32] }:$A), 0:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCVDPSPN), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // A GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSPLTW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1724, GIR_EraseRootFromParent_Done, // Label 294: @5980 GIM_Try, /*On fail goto*//*Label 295*/ GIMT_Encode4(6069), // Rule ID 2119 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX_IsBigEndian_IsPPC64_NoP9Vector), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, // (build_vector:{ *:[v4i32] } i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A) => (XXSPLTW:{ *:[v4i32] } (SUBREG_TO_REG:{ *:[v4i32] } 1:{ *:[i64] }, (MTVSRWZ:{ *:[f64] } ?:{ *:[i32] }:$A), sub_64:{ *:[i32] }), 1:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::MTVSRWZ), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // A GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddImm8, /*InsnID*/1, /*Imm*/1, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_AddImm8, /*InsnID*/1, /*Imm*/3, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(PPC::VSFRCRegClassID), GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSPLTW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2119, GIR_EraseRootFromParent_Done, // Label 295: @6069 GIM_Try, /*On fail goto*//*Label 296*/ GIMT_Encode4(6158), // Rule ID 2122 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX_IsLittleEndian_NoP9Vector), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, // (build_vector:{ *:[v4i32] } i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A) => (XXSPLTW:{ *:[v4i32] } (SUBREG_TO_REG:{ *:[v4i32] } 1:{ *:[i64] }, (MTVSRWZ:{ *:[f64] } ?:{ *:[i32] }:$A), sub_64:{ *:[i32] }), 1:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::MTVSRWZ), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // A GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddImm8, /*InsnID*/1, /*Imm*/1, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_AddImm8, /*InsnID*/1, /*Imm*/3, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(PPC::VSFRCRegClassID), GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSPLTW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2122, GIR_EraseRootFromParent_Done, // Label 296: @6158 GIM_Try, /*On fail goto*//*Label 297*/ GIMT_Encode4(6194), // Rule ID 2253 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, // (build_vector:{ *:[v4i32] } i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A) => (MTVSRWS:{ *:[v4i32] } ?:{ *:[i32] }:$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRWS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/1, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2253, GIR_EraseRootFromParent_Done, // Label 297: @6194 GIM_Reject, // Label 290: @6195 GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(6336), // Rule ID 2254 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_CheckNumOperands, /*MI*/0, /*Expected*/17, GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immNonAllOneAnyExt8), // MIs[1] Operand 1 // No operand predicates // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/9, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/10, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/11, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/12, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/13, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/14, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/15, /*OtherMI*/0, /*OtherOpIdx*/1, // MIs[0] A GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/16, /*OtherMI*/0, /*OtherOpIdx*/1, GIM_CheckIsSafeToFold, /*NumInsns*/1, // (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A) => (COPY_TO_REGCLASS:{ *:[v16i8] } (XXSPLTIB:{ *:[v4i32] } (imm:{ *:[i32] }):$A), VSRC:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXSPLTIB), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // A GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), // GIR_Coverage, 2254, GIR_EraseRootFromParent_Done, // Label 298: @6336 GIM_Reject, // Label 11: @6337 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(8), /*)*//*default:*//*Label 306*/ GIMT_Encode4(8613), /*GILLT_s32*//*Label 299*/ GIMT_Encode4(6376), /*GILLT_s64*//*Label 300*/ GIMT_Encode4(6449), /*GILLT_s128*//*Label 301*/ GIMT_Encode4(6497), /*GILLT_v2s64*//*Label 302*/ GIMT_Encode4(6901), /*GILLT_v4s32*//*Label 303*/ GIMT_Encode4(7463), /*GILLT_v8s16*//*Label 304*/ GIMT_Encode4(8014), /*GILLT_v16s8*//*Label 305*/ GIMT_Encode4(8342), // Label 299: @6376 GIM_Try, /*On fail goto*//*Label 307*/ GIMT_Encode4(6448), // Rule ID 2017 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (bitconvert:{ *:[i32] } f32:{ *:[f32] }:$A) => (MFVSRWZ:{ *:[i32] } (EXTRACT_SUBREG:{ *:[f64] } (XSCVDPSPN:{ *:[v4i32] } ?:{ *:[f32] }:$A), sub_64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCVDPSPN), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // A GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_64), GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID), GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::VSRCRegClassID), GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRWZ), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2017, GIR_EraseRootFromParent_Done, // Label 307: @6448 GIM_Reject, // Label 300: @6449 GIM_Try, /*On fail goto*//*Label 308*/ GIMT_Encode4(6496), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_Try, /*On fail goto*//*Label 309*/ GIMT_Encode4(6476), // Rule ID 2019 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (bitconvert:{ *:[i64] } f64:{ *:[f64] }:$A) => (MFVSRD:{ *:[i64] } ?:{ *:[f64] }:$A) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MFVSRD), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2019, GIR_Done, // Label 309: @6476 GIM_Try, /*On fail goto*//*Label 310*/ GIMT_Encode4(6495), // Rule ID 2020 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), // (bitconvert:{ *:[f64] } i64:{ *:[i64] }:$S) => (MTVSRD:{ *:[f64] } ?:{ *:[i64] }:$S) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MTVSRD), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2020, GIR_Done, // Label 310: @6495 GIM_Reject, // Label 308: @6496 GIM_Reject, // Label 301: @6497 GIM_Try, /*On fail goto*//*Label 311*/ GIMT_Encode4(6554), // Rule ID 1923 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/1, GIM_CheckIsSafeToFold, /*NumInsns*/1, // (bitconvert:{ *:[v1i128] } immAllOnesV:{ *:[v16i8] }) => (COPY_TO_REGCLASS:{ *:[v1i128] } (XXLEQVOnes:{ *:[v4i32] }), VSRC:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXLEQVOnes), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), // GIR_Coverage, 1923, GIR_EraseRootFromParent_Done, // Label 311: @6554 GIM_Try, /*On fail goto*//*Label 312*/ GIMT_Encode4(6580), // Rule ID 1610 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v1i128] } v2f64:{ *:[v2f64] }:$A) => (COPY_TO_REGCLASS:{ *:[v1i128] } ?:{ *:[v2f64] }:$A, VRRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1610, GIR_Done, // Label 312: @6580 GIM_Try, /*On fail goto*//*Label 313*/ GIMT_Encode4(6612), // Rule ID 1325 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v1i128] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[v1i128] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1325, GIR_EraseRootFromParent_Done, // Label 313: @6612 GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(6644), // Rule ID 1326 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v1i128] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[v1i128] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1326, GIR_EraseRootFromParent_Done, // Label 314: @6644 GIM_Try, /*On fail goto*//*Label 315*/ GIMT_Encode4(6676), // Rule ID 1327 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v1i128] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[v1i128] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1327, GIR_EraseRootFromParent_Done, // Label 315: @6676 GIM_Try, /*On fail goto*//*Label 316*/ GIMT_Encode4(6708), // Rule ID 1328 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v1i128] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[v1i128] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1328, GIR_EraseRootFromParent_Done, // Label 316: @6708 GIM_Try, /*On fail goto*//*Label 317*/ GIMT_Encode4(6740), // Rule ID 1329 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v1i128] } VRRC:{ *:[v2i64] }:$src) => VRRC:{ *:[v1i128] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1329, GIR_EraseRootFromParent_Done, // Label 317: @6740 GIM_Try, /*On fail goto*//*Label 318*/ GIMT_Encode4(6772), // Rule ID 1330 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[f128] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[f128] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1330, GIR_EraseRootFromParent_Done, // Label 318: @6772 GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(6804), // Rule ID 1331 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[f128] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[f128] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1331, GIR_EraseRootFromParent_Done, // Label 319: @6804 GIM_Try, /*On fail goto*//*Label 320*/ GIMT_Encode4(6836), // Rule ID 1332 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[f128] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[f128] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1332, GIR_EraseRootFromParent_Done, // Label 320: @6836 GIM_Try, /*On fail goto*//*Label 321*/ GIMT_Encode4(6868), // Rule ID 1333 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[f128] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[f128] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1333, GIR_EraseRootFromParent_Done, // Label 321: @6868 GIM_Try, /*On fail goto*//*Label 322*/ GIMT_Encode4(6900), // Rule ID 1334 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[f128] } VRRC:{ *:[v2f64] }:$src) => VRRC:{ *:[f128] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1334, GIR_EraseRootFromParent_Done, // Label 322: @6900 GIM_Reject, // Label 302: @6901 GIM_Try, /*On fail goto*//*Label 323*/ GIMT_Encode4(6958), // Rule ID 1924 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/1, GIM_CheckIsSafeToFold, /*NumInsns*/1, // (bitconvert:{ *:[v2i64] } immAllOnesV:{ *:[v16i8] }) => (COPY_TO_REGCLASS:{ *:[v2i64] } (XXLEQVOnes:{ *:[v4i32] }), VSRC:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXLEQVOnes), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), // GIR_Coverage, 1924, GIR_EraseRootFromParent_Done, // Label 323: @6958 GIM_Try, /*On fail goto*//*Label 324*/ GIMT_Encode4(6984), // Rule ID 1591 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$A) => (COPY_TO_REGCLASS:{ *:[v2f64] } ?:{ *:[v4f32] }:$A, VSRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), // GIR_Coverage, 1591, GIR_Done, // Label 324: @6984 GIM_Try, /*On fail goto*//*Label 325*/ GIMT_Encode4(7010), // Rule ID 1592 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$A) => (COPY_TO_REGCLASS:{ *:[v2f64] } ?:{ *:[v4i32] }:$A, VSRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), // GIR_Coverage, 1592, GIR_Done, // Label 325: @7010 GIM_Try, /*On fail goto*//*Label 326*/ GIMT_Encode4(7036), // Rule ID 1593 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$A) => (COPY_TO_REGCLASS:{ *:[v2f64] } ?:{ *:[v8i16] }:$A, VSRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), // GIR_Coverage, 1593, GIR_Done, // Label 326: @7036 GIM_Try, /*On fail goto*//*Label 327*/ GIMT_Encode4(7062), // Rule ID 1594 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$A) => (COPY_TO_REGCLASS:{ *:[v2f64] } ?:{ *:[v16i8] }:$A, VSRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), // GIR_Coverage, 1594, GIR_Done, // Label 327: @7062 GIM_Try, /*On fail goto*//*Label 328*/ GIMT_Encode4(7088), // Rule ID 1599 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$A) => (COPY_TO_REGCLASS:{ *:[v2i64] } ?:{ *:[v4f32] }:$A, VSRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), // GIR_Coverage, 1599, GIR_Done, // Label 328: @7088 GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(7114), // Rule ID 1600 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$A) => (COPY_TO_REGCLASS:{ *:[v2i64] } ?:{ *:[v4i32] }:$A, VSRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), // GIR_Coverage, 1600, GIR_Done, // Label 329: @7114 GIM_Try, /*On fail goto*//*Label 330*/ GIMT_Encode4(7140), // Rule ID 1601 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$A) => (COPY_TO_REGCLASS:{ *:[v2i64] } ?:{ *:[v8i16] }:$A, VSRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), // GIR_Coverage, 1601, GIR_Done, // Label 330: @7140 GIM_Try, /*On fail goto*//*Label 331*/ GIMT_Encode4(7166), // Rule ID 1602 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$A) => (COPY_TO_REGCLASS:{ *:[v2i64] } ?:{ *:[v16i8] }:$A, VSRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), // GIR_Coverage, 1602, GIR_Done, // Label 331: @7166 GIM_Try, /*On fail goto*//*Label 332*/ GIMT_Encode4(7192), // Rule ID 1607 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$A) => (COPY_TO_REGCLASS:{ *:[v2f64] } ?:{ *:[v2i64] }:$A, VRRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1607, GIR_Done, // Label 332: @7192 GIM_Try, /*On fail goto*//*Label 333*/ GIMT_Encode4(7218), // Rule ID 1608 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$A) => (COPY_TO_REGCLASS:{ *:[v2i64] } ?:{ *:[v2f64] }:$A, VRRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1608, GIR_Done, // Label 333: @7218 GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(7244), // Rule ID 1609 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v2f64] } v1i128:{ *:[v1i128] }:$A) => (COPY_TO_REGCLASS:{ *:[v2f64] } ?:{ *:[v1i128] }:$A, VRRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1609, GIR_Done, // Label 334: @7244 GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(7270), // Rule ID 1611 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v2i64] } f128:{ *:[f128] }:$A) => (COPY_TO_REGCLASS:{ *:[v2i64] } ?:{ *:[f128] }:$A, VRRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1611, GIR_Done, // Label 335: @7270 GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(7302), // Rule ID 1320 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v2i64] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[v2i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1320, GIR_EraseRootFromParent_Done, // Label 336: @7302 GIM_Try, /*On fail goto*//*Label 337*/ GIMT_Encode4(7334), // Rule ID 1321 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v2i64] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[v2i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1321, GIR_EraseRootFromParent_Done, // Label 337: @7334 GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(7366), // Rule ID 1322 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v2i64] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[v2i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1322, GIR_EraseRootFromParent_Done, // Label 338: @7366 GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(7398), // Rule ID 1323 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v2i64] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[v2i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1323, GIR_EraseRootFromParent_Done, // Label 339: @7398 GIM_Try, /*On fail goto*//*Label 340*/ GIMT_Encode4(7430), // Rule ID 1324 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v2i64] } VRRC:{ *:[v1i128] }:$src) => VRRC:{ *:[v2i64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1324, GIR_EraseRootFromParent_Done, // Label 340: @7430 GIM_Try, /*On fail goto*//*Label 341*/ GIMT_Encode4(7462), // Rule ID 1339 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v2f64] } VRRC:{ *:[f128] }:$src) => VRRC:{ *:[v2f64] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1339, GIR_EraseRootFromParent_Done, // Label 341: @7462 GIM_Reject, // Label 303: @7463 GIM_Try, /*On fail goto*//*Label 342*/ GIMT_Encode4(7499), // Rule ID 941 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/1, GIM_CheckIsSafeToFold, /*NumInsns*/1, // (bitconvert:{ *:[v4i32] } immAllOnesV:{ *:[v16i8] }) => (XXLEQVOnes:{ *:[v4i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLEQVOnes), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 941, GIR_EraseRootFromParent_Done, // Label 342: @7499 GIM_Try, /*On fail goto*//*Label 343*/ GIMT_Encode4(7525), // Rule ID 1595 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$A) => (COPY_TO_REGCLASS:{ *:[v4f32] } ?:{ *:[v2f64] }:$A, VRRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1595, GIR_Done, // Label 343: @7525 GIM_Try, /*On fail goto*//*Label 344*/ GIMT_Encode4(7551), // Rule ID 1596 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$A) => (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v2f64] }:$A, VRRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1596, GIR_Done, // Label 344: @7551 GIM_Try, /*On fail goto*//*Label 345*/ GIMT_Encode4(7577), // Rule ID 1603 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$A) => (COPY_TO_REGCLASS:{ *:[v4f32] } ?:{ *:[v2i64] }:$A, VRRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1603, GIR_Done, // Label 345: @7577 GIM_Try, /*On fail goto*//*Label 346*/ GIMT_Encode4(7603), // Rule ID 1604 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$A) => (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v2i64] }:$A, VRRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1604, GIR_Done, // Label 346: @7603 GIM_Try, /*On fail goto*//*Label 347*/ GIMT_Encode4(7629), // Rule ID 1612 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v4i32] } f128:{ *:[f128] }:$A) => (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[f128] }:$A, VRRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1612, GIR_Done, // Label 347: @7629 GIM_Try, /*On fail goto*//*Label 348*/ GIMT_Encode4(7661), // Rule ID 1310 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v4i32] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[v4i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1310, GIR_EraseRootFromParent_Done, // Label 348: @7661 GIM_Try, /*On fail goto*//*Label 349*/ GIMT_Encode4(7693), // Rule ID 1311 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v4i32] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[v4i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1311, GIR_EraseRootFromParent_Done, // Label 349: @7693 GIM_Try, /*On fail goto*//*Label 350*/ GIMT_Encode4(7725), // Rule ID 1312 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v4i32] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[v4i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1312, GIR_EraseRootFromParent_Done, // Label 350: @7725 GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(7757), // Rule ID 1313 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v4i32] } VRRC:{ *:[v2i64] }:$src) => VRRC:{ *:[v4i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1313, GIR_EraseRootFromParent_Done, // Label 351: @7757 GIM_Try, /*On fail goto*//*Label 352*/ GIMT_Encode4(7789), // Rule ID 1314 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v4i32] } VRRC:{ *:[v1i128] }:$src) => VRRC:{ *:[v4i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1314, GIR_EraseRootFromParent_Done, // Label 352: @7789 GIM_Try, /*On fail goto*//*Label 353*/ GIMT_Encode4(7821), // Rule ID 1315 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v4f32] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[v4f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1315, GIR_EraseRootFromParent_Done, // Label 353: @7821 GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(7853), // Rule ID 1316 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v4f32] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[v4f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1316, GIR_EraseRootFromParent_Done, // Label 354: @7853 GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(7885), // Rule ID 1317 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v4f32] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[v4f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1317, GIR_EraseRootFromParent_Done, // Label 355: @7885 GIM_Try, /*On fail goto*//*Label 356*/ GIMT_Encode4(7917), // Rule ID 1318 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v4f32] } VRRC:{ *:[v2i64] }:$src) => VRRC:{ *:[v4f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1318, GIR_EraseRootFromParent_Done, // Label 356: @7917 GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(7949), // Rule ID 1319 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v4f32] } VRRC:{ *:[v1i128] }:$src) => VRRC:{ *:[v4f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1319, GIR_EraseRootFromParent_Done, // Label 357: @7949 GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(7981), // Rule ID 1337 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v4i32] } VRRC:{ *:[f128] }:$src) => VRRC:{ *:[v4i32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1337, GIR_EraseRootFromParent_Done, // Label 358: @7981 GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(8013), // Rule ID 1338 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v4f32] } VRRC:{ *:[f128] }:$src) => VRRC:{ *:[v4f32] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1338, GIR_EraseRootFromParent_Done, // Label 359: @8013 GIM_Reject, // Label 304: @8014 GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(8071), // Rule ID 1925 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), GIM_CheckIsBuildVectorAllOnes, /*MI*/1, GIM_CheckIsSafeToFold, /*NumInsns*/1, // (bitconvert:{ *:[v8i16] } immAllOnesV:{ *:[v16i8] }) => (COPY_TO_REGCLASS:{ *:[v8i16] } (XXLEQVOnes:{ *:[v4i32] }), VSRC:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXLEQVOnes), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), // GIR_Coverage, 1925, GIR_EraseRootFromParent_Done, // Label 360: @8071 GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(8097), // Rule ID 1597 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$A) => (COPY_TO_REGCLASS:{ *:[v8i16] } ?:{ *:[v2f64] }:$A, VRRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1597, GIR_Done, // Label 361: @8097 GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(8123), // Rule ID 1605 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$A) => (COPY_TO_REGCLASS:{ *:[v8i16] } ?:{ *:[v2i64] }:$A, VRRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1605, GIR_Done, // Label 362: @8123 GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(8149), // Rule ID 1613 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v8i16] } f128:{ *:[f128] }:$A) => (COPY_TO_REGCLASS:{ *:[v8i16] } ?:{ *:[f128] }:$A, VRRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1613, GIR_Done, // Label 363: @8149 GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(8181), // Rule ID 1305 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v8i16] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[v8i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1305, GIR_EraseRootFromParent_Done, // Label 364: @8181 GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(8213), // Rule ID 1306 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v8i16] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[v8i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1306, GIR_EraseRootFromParent_Done, // Label 365: @8213 GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(8245), // Rule ID 1307 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v8i16] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[v8i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1307, GIR_EraseRootFromParent_Done, // Label 366: @8245 GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(8277), // Rule ID 1308 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v8i16] } VRRC:{ *:[v2i64] }:$src) => VRRC:{ *:[v8i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1308, GIR_EraseRootFromParent_Done, // Label 367: @8277 GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(8309), // Rule ID 1309 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v8i16] } VRRC:{ *:[v1i128] }:$src) => VRRC:{ *:[v8i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1309, GIR_EraseRootFromParent_Done, // Label 368: @8309 GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(8341), // Rule ID 1336 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v8i16] } VRRC:{ *:[f128] }:$src) => VRRC:{ *:[v8i16] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1336, GIR_EraseRootFromParent_Done, // Label 369: @8341 GIM_Reject, // Label 305: @8342 GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(8368), // Rule ID 1598 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$A) => (COPY_TO_REGCLASS:{ *:[v16i8] } ?:{ *:[v2f64] }:$A, VRRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1598, GIR_Done, // Label 370: @8368 GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(8394), // Rule ID 1606 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$A) => (COPY_TO_REGCLASS:{ *:[v16i8] } ?:{ *:[v2i64] }:$A, VRRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1606, GIR_Done, // Label 371: @8394 GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(8420), // Rule ID 1614 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v16i8] } f128:{ *:[f128] }:$A) => (COPY_TO_REGCLASS:{ *:[v16i8] } ?:{ *:[f128] }:$A, VRRC:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1614, GIR_Done, // Label 372: @8420 GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(8452), // Rule ID 1300 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v16i8] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[v16i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1300, GIR_EraseRootFromParent_Done, // Label 373: @8452 GIM_Try, /*On fail goto*//*Label 374*/ GIMT_Encode4(8484), // Rule ID 1301 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v16i8] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[v16i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1301, GIR_EraseRootFromParent_Done, // Label 374: @8484 GIM_Try, /*On fail goto*//*Label 375*/ GIMT_Encode4(8516), // Rule ID 1302 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v16i8] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[v16i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1302, GIR_EraseRootFromParent_Done, // Label 375: @8516 GIM_Try, /*On fail goto*//*Label 376*/ GIMT_Encode4(8548), // Rule ID 1303 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v16i8] } VRRC:{ *:[v2i64] }:$src) => VRRC:{ *:[v16i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1303, GIR_EraseRootFromParent_Done, // Label 376: @8548 GIM_Try, /*On fail goto*//*Label 377*/ GIMT_Encode4(8580), // Rule ID 1304 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v16i8] } VRRC:{ *:[v1i128] }:$src) => VRRC:{ *:[v16i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1304, GIR_EraseRootFromParent_Done, // Label 377: @8580 GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(8612), // Rule ID 1335 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (bitconvert:{ *:[v16i8] } VRRC:{ *:[f128] }:$src) => VRRC:{ *:[v16i8] }:$src GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // dst GIR_RootToRootCopy, /*OpIdx*/1, // src GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 1335, GIR_EraseRootFromParent_Done, // Label 378: @8612 GIM_Reject, // Label 306: @8613 GIM_Reject, // Label 12: @8614 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 384*/ GIMT_Encode4(8885), /*GILLT_s32*//*Label 379*/ GIMT_Encode4(8645), /*GILLT_s64*//*Label 380*/ GIMT_Encode4(8735), /*GILLT_s128*//*Label 381*/ GIMT_Encode4(8783), /*GILLT_v2s64*//*Label 382*/ GIMT_Encode4(8814), /*GILLT_v4s32*//*Label 383*/ GIMT_Encode4(8837), // Label 379: @8645 GIM_Try, /*On fail goto*//*Label 385*/ GIMT_Encode4(8734), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 386*/ GIMT_Encode4(8714), // Rule ID 1701 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), // (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$S) => (COPY_TO_REGCLASS:{ *:[f32] } (XSRDPIZ:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSRDPIZ), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID), // GIR_Coverage, 1701, GIR_EraseRootFromParent_Done, // Label 386: @8714 GIM_Try, /*On fail goto*//*Label 387*/ GIMT_Encode4(8733), // Rule ID 150 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), // (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$RB) => (FRIZS:{ *:[f32] } f32:{ *:[f32] }:$RB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FRIZS), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 150, GIR_Done, // Label 387: @8733 GIM_Reject, // Label 385: @8734 GIM_Reject, // Label 380: @8735 GIM_Try, /*On fail goto*//*Label 388*/ GIMT_Encode4(8782), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_Try, /*On fail goto*//*Label 389*/ GIMT_Encode4(8762), // Rule ID 911 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), // (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSRDPIZ:{ *:[f64] } f64:{ *:[f64] }:$XB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSRDPIZ), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 911, GIR_Done, // Label 389: @8762 GIM_Try, /*On fail goto*//*Label 390*/ GIMT_Encode4(8781), // Rule ID 148 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), // (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$RB) => (FRIZD:{ *:[f64] } f64:{ *:[f64] }:$RB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FRIZD), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 148, GIR_Done, // Label 390: @8781 GIM_Reject, // Label 388: @8782 GIM_Reject, // Label 381: @8783 GIM_Try, /*On fail goto*//*Label 391*/ GIMT_Encode4(8813), // Rule ID 2150 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (ftrunc:{ *:[f128] } f128:{ *:[f128] }:$vB) => (XSRQPI:{ *:[f128] } 1:{ *:[i32] }, ?:{ *:[f128] }:$vB, 1:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRQPI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VRT] GIR_AddImm8, /*InsnID*/0, /*Imm*/1, GIR_RootToRootCopy, /*OpIdx*/1, // vB GIR_AddImm8, /*InsnID*/0, /*Imm*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2150, GIR_EraseRootFromParent_Done, // Label 391: @8813 GIM_Reject, // Label 382: @8814 GIM_Try, /*On fail goto*//*Label 392*/ GIMT_Encode4(8836), // Rule ID 919 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (ftrunc:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVRDPIZ:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRDPIZ), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 919, GIR_Done, // Label 392: @8836 GIM_Reject, // Label 383: @8837 GIM_Try, /*On fail goto*//*Label 393*/ GIMT_Encode4(8884), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 394*/ GIMT_Encode4(8864), // Rule ID 927 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (ftrunc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVRSPIZ:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRSPIZ), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 927, GIR_Done, // Label 394: @8864 GIM_Try, /*On fail goto*//*Label 395*/ GIMT_Encode4(8883), // Rule ID 1410 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (ftrunc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vA) => (VRFIZ:{ *:[v4f32] } ?:{ *:[v4f32] }:$vA) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VRFIZ), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1410, GIR_Done, // Label 395: @8883 GIM_Reject, // Label 393: @8884 GIM_Reject, // Label 384: @8885 GIM_Reject, // Label 13: @8886 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 401*/ GIMT_Encode4(9132), /*GILLT_s32*//*Label 396*/ GIMT_Encode4(8917), /*GILLT_s64*//*Label 397*/ GIMT_Encode4(9007), /*GILLT_s128*//*Label 398*/ GIMT_Encode4(9055), /*GILLT_v2s64*//*Label 399*/ GIMT_Encode4(9086), /*GILLT_v4s32*//*Label 400*/ GIMT_Encode4(9109), // Label 396: @8917 GIM_Try, /*On fail goto*//*Label 402*/ GIMT_Encode4(9006), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 403*/ GIMT_Encode4(8986), // Rule ID 1695 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), // (fround:{ *:[f32] } f32:{ *:[f32] }:$S) => (COPY_TO_REGCLASS:{ *:[f32] } (XSRDPI:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSRDPI), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID), // GIR_Coverage, 1695, GIR_EraseRootFromParent_Done, // Label 403: @8986 GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(9005), // Rule ID 142 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), // (fround:{ *:[f32] } f32:{ *:[f32] }:$RB) => (FRINS:{ *:[f32] } f32:{ *:[f32] }:$RB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FRINS), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 142, GIR_Done, // Label 404: @9005 GIM_Reject, // Label 402: @9006 GIM_Reject, // Label 397: @9007 GIM_Try, /*On fail goto*//*Label 405*/ GIMT_Encode4(9054), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_Try, /*On fail goto*//*Label 406*/ GIMT_Encode4(9034), // Rule ID 905 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), // (fround:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSRDPI:{ *:[f64] } f64:{ *:[f64] }:$XB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSRDPI), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 905, GIR_Done, // Label 406: @9034 GIM_Try, /*On fail goto*//*Label 407*/ GIMT_Encode4(9053), // Rule ID 140 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), // (fround:{ *:[f64] } f64:{ *:[f64] }:$RB) => (FRIND:{ *:[f64] } f64:{ *:[f64] }:$RB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FRIND), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 140, GIR_Done, // Label 407: @9053 GIM_Reject, // Label 405: @9054 GIM_Reject, // Label 398: @9055 GIM_Try, /*On fail goto*//*Label 408*/ GIMT_Encode4(9085), // Rule ID 2148 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (fround:{ *:[f128] } f128:{ *:[f128] }:$vB) => (XSRQPI:{ *:[f128] } 0:{ *:[i32] }, ?:{ *:[f128] }:$vB, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRQPI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VRT] GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootToRootCopy, /*OpIdx*/1, // vB GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2148, GIR_EraseRootFromParent_Done, // Label 408: @9085 GIM_Reject, // Label 399: @9086 GIM_Try, /*On fail goto*//*Label 409*/ GIMT_Encode4(9108), // Rule ID 913 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (fround:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVRDPI:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRDPI), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 913, GIR_Done, // Label 409: @9108 GIM_Reject, // Label 400: @9109 GIM_Try, /*On fail goto*//*Label 410*/ GIMT_Encode4(9131), // Rule ID 921 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (fround:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVRSPI:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRSPI), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 921, GIR_Done, // Label 410: @9131 GIM_Reject, // Label 401: @9132 GIM_Reject, // Label 14: @9133 GIM_Try, /*On fail goto*//*Label 411*/ GIMT_Encode4(9260), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 414*/ GIMT_Encode4(9259), /*GILLT_s32*//*Label 412*/ GIMT_Encode4(9160), /*GILLT_s64*//*Label 413*/ GIMT_Encode4(9218), // Label 412: @9160 GIM_Try, /*On fail goto*//*Label 415*/ GIMT_Encode4(9217), // Rule ID 2022 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (lrint:{ *:[i64] } f32:{ *:[f32] }:$S) => (MFVSRD:{ *:[i64] } (FCTID:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, F8RC:{ *:[i32] }))) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCTID), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2022, GIR_EraseRootFromParent_Done, // Label 415: @9217 GIM_Reject, // Label 413: @9218 GIM_Try, /*On fail goto*//*Label 416*/ GIMT_Encode4(9258), // Rule ID 2021 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (lrint:{ *:[i64] } f64:{ *:[f64] }:$S) => (MFVSRD:{ *:[i64] } (FCTID:{ *:[f64] } ?:{ *:[f64] }:$S)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCTID), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // S GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2021, GIR_EraseRootFromParent_Done, // Label 416: @9258 GIM_Reject, // Label 414: @9259 GIM_Reject, // Label 411: @9260 GIM_Reject, // Label 15: @9261 GIM_Try, /*On fail goto*//*Label 417*/ GIMT_Encode4(9388), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 420*/ GIMT_Encode4(9387), /*GILLT_s32*//*Label 418*/ GIMT_Encode4(9288), /*GILLT_s64*//*Label 419*/ GIMT_Encode4(9346), // Label 418: @9288 GIM_Try, /*On fail goto*//*Label 421*/ GIMT_Encode4(9345), // Rule ID 2024 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (llrint:{ *:[i64] } f32:{ *:[f32] }:$S) => (MFVSRD:{ *:[i64] } (FCTID:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, F8RC:{ *:[i32] }))) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCTID), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2024, GIR_EraseRootFromParent_Done, // Label 421: @9345 GIM_Reject, // Label 419: @9346 GIM_Try, /*On fail goto*//*Label 422*/ GIMT_Encode4(9386), // Rule ID 2023 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (llrint:{ *:[i64] } f64:{ *:[f64] }:$S) => (MFVSRD:{ *:[i64] } (FCTID:{ *:[f64] } ?:{ *:[f64] }:$S)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCTID), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // S GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2023, GIR_EraseRootFromParent_Done, // Label 422: @9386 GIM_Reject, // Label 420: @9387 GIM_Reject, // Label 417: @9388 GIM_Reject, // Label 16: @9389 GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(9408), // Rule ID 635 // GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (readcyclecounter:{ *:[i64] }) => (MFTB8:{ *:[i64] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MFTB8), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 635, GIR_Done, // Label 423: @9408 GIM_Reject, // Label 17: @9409 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 426*/ GIMT_Encode4(9484), /*GILLT_s32*//*Label 424*/ GIMT_Encode4(9428), /*GILLT_s64*//*Label 425*/ GIMT_Encode4(9456), // Label 424: @9428 GIM_Try, /*On fail goto*//*Label 427*/ GIMT_Encode4(9455), // Rule ID 1260 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSYNC), GIM_CheckConstantInt8, /*MI*/0, /*Op*/0, 7, // MIs[0] Operand 1 GIM_CheckIsImm, /*MI*/0, /*Op*/1, // (atomic_fence 7:{ *:[i32] }, (timm:{ *:[i32] })) => (SYNC 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SYNC), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1260, GIR_EraseRootFromParent_Done, // Label 427: @9455 GIM_Reject, // Label 425: @9456 GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(9483), // Rule ID 1259 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSYNC), GIM_CheckConstantInt8, /*MI*/0, /*Op*/0, 7, // MIs[0] Operand 1 GIM_CheckIsImm, /*MI*/0, /*Op*/1, // (atomic_fence 7:{ *:[i64] }, (timm:{ *:[i64] })) => (SYNC 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SYNC), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1259, GIR_EraseRootFromParent_Done, // Label 428: @9483 GIM_Reject, // Label 426: @9484 GIM_Try, /*On fail goto*//*Label 429*/ GIMT_Encode4(9533), GIM_CheckIsImm, /*MI*/0, /*Op*/0, GIM_CheckIsImm, /*MI*/0, /*Op*/1, GIM_Try, /*On fail goto*//*Label 430*/ GIMT_Encode4(9515), // Rule ID 1261 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSYNC), // (atomic_fence (timm:{ *:[iPTR] }), (timm:{ *:[iPTR] })) => (SYNC 1:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SYNC), GIR_AddImm8, /*InsnID*/0, /*Imm*/1, GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1261, GIR_EraseRootFromParent_Done, // Label 430: @9515 GIM_Try, /*On fail goto*//*Label 431*/ GIMT_Encode4(9532), // Rule ID 1262 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasOnlyMSYNC), // (atomic_fence (timm:{ *:[iPTR] }), (timm:{ *:[iPTR] })) => (MSYNC) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MSYNC), GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1262, GIR_EraseRootFromParent_Done, // Label 431: @9532 GIM_Reject, // Label 429: @9533 GIM_Reject, // Label 18: @9534 GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(9596), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, GIM_CheckIsMBB, /*MI*/0, /*Op*/1, GIM_Try, /*On fail goto*//*Label 433*/ GIMT_Encode4(9583), // Rule ID 17 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (brcond (xor:{ *:[i1] } i1:{ *:[i1] }:$BI, -1:{ *:[i1] }), (bb:{ *:[Other] }):$BD) => (BCn i1:{ *:[i1] }:$BI, (bb:{ *:[Other] }):$BD) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::BCn), GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // BI GIR_RootToRootCopy, /*OpIdx*/1, // BD GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 17, GIR_EraseRootFromParent_Done, // Label 433: @9583 GIM_Try, /*On fail goto*//*Label 434*/ GIMT_Encode4(9595), // Rule ID 16 // // (brcond i1:{ *:[i1] }:$BI, (bb:{ *:[Other] }):$BD) => (BC i1:{ *:[i1] }:$BI, (bb:{ *:[Other] }):$BD) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::BC), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 16, GIR_Done, // Label 434: @9595 GIM_Reject, // Label 432: @9596 GIM_Reject, // Label 19: @9597 GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(9718), GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(9632), // Rule ID 1161 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xxsetaccz), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10057:{ *:[iPTR] }) => (XXSETACCZ:{ *:[v512i1] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSETACCZ), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1161, GIR_EraseRootFromParent_Done, // Label 436: @9632 GIM_Try, /*On fail goto*//*Label 437*/ GIMT_Encode4(9659), // Rule ID 1162 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xxsetaccz), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10057:{ *:[iPTR] }) => (XXSETACCZW:{ *:[v512i1] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSETACCZW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1162, GIR_EraseRootFromParent_Done, // Label 437: @9659 GIM_Try, /*On fail goto*//*Label 438*/ GIMT_Encode4(9683), // Rule ID 4853 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mfmsr), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 9989:{ *:[iPTR] }) => (MFMSR:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFMSR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4853, GIR_EraseRootFromParent_Done, // Label 438: @9683 GIM_Try, /*On fail goto*//*Label 439*/ GIMT_Encode4(9717), // Rule ID 4854 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mftbu), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 9991:{ *:[iPTR] }) => (MFTB:{ *:[i32] } 269:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFTB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(269), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4854, GIR_EraseRootFromParent_Done, // Label 439: @9717 GIM_Reject, // Label 435: @9718 GIM_Try, /*On fail goto*//*Label 440*/ GIMT_Encode4(13347), GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, GIM_Try, /*On fail goto*//*Label 441*/ GIMT_Encode4(9762), // Rule ID 1743 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_frsqrte), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 9964:{ *:[iPTR] }, vsfrc:{ *:[f64] }:$XB) => (XSRSQRTEDP:{ *:[f64] } ?:{ *:[f64] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRSQRTEDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1743, GIR_EraseRootFromParent_Done, // Label 441: @9762 GIM_Try, /*On fail goto*//*Label 442*/ GIMT_Encode4(9798), // Rule ID 1934 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_frsqrtes), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), // (intrinsic_wo_chain:{ *:[f32] } 9965:{ *:[iPTR] }, vssrc:{ *:[f32] }:$XB) => (XSRSQRTESP:{ *:[f32] } ?:{ *:[f32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRSQRTESP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1934, GIR_EraseRootFromParent_Done, // Label 442: @9798 GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(9830), // Rule ID 872 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvdpsp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 10150:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB) => (XVCVDPSP:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVDPSP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 872, GIR_EraseRootFromParent_Done, // Label 443: @9830 GIM_Try, /*On fail goto*//*Label 444*/ GIMT_Encode4(9862), // Rule ID 875 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvdpsxws), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 10151:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB) => (XVCVDPSXWS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVDPSXWS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 875, GIR_EraseRootFromParent_Done, // Label 444: @9862 GIM_Try, /*On fail goto*//*Label 445*/ GIMT_Encode4(9894), // Rule ID 878 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvdpuxws), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 10152:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB) => (XVCVDPUXWS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVDPUXWS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 878, GIR_EraseRootFromParent_Done, // Label 445: @9894 GIM_Try, /*On fail goto*//*Label 446*/ GIMT_Encode4(9926), // Rule ID 879 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvspdp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v2f64] } 10155:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVCVSPDP:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVSPDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 879, GIR_EraseRootFromParent_Done, // Label 446: @9926 GIM_Try, /*On fail goto*//*Label 447*/ GIMT_Encode4(9958), // Rule ID 880 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvspsxds), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 10157:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVCVSPSXDS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVSPSXDS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 880, GIR_EraseRootFromParent_Done, // Label 447: @9958 GIM_Try, /*On fail goto*//*Label 448*/ GIMT_Encode4(9990), // Rule ID 883 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvspuxds), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 10158:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVCVSPUXDS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVSPUXDS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 883, GIR_EraseRootFromParent_Done, // Label 448: @9990 GIM_Try, /*On fail goto*//*Label 449*/ GIMT_Encode4(10022), // Rule ID 888 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvsxdsp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 10159:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$XB) => (XVCVSXDSP:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVSXDSP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 888, GIR_EraseRootFromParent_Done, // Label 449: @10022 GIM_Try, /*On fail goto*//*Label 450*/ GIMT_Encode4(10054), // Rule ID 893 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvuxdsp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 10161:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$XB) => (XVCVUXDSP:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVUXDSP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 893, GIR_EraseRootFromParent_Done, // Label 450: @10054 GIM_Try, /*On fail goto*//*Label 451*/ GIMT_Encode4(10086), // Rule ID 896 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvsxwdp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v2f64] } 10160:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$XB) => (XVCVSXWDP:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVSXWDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 896, GIR_EraseRootFromParent_Done, // Label 451: @10086 GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(10118), // Rule ID 897 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvuxwdp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v2f64] } 10162:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$XB) => (XVCVUXWDP:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVUXWDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 897, GIR_EraseRootFromParent_Done, // Label 452: @10118 GIM_Try, /*On fail goto*//*Label 453*/ GIMT_Encode4(10150), // Rule ID 1005 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_sqrtf128_round_to_odd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[f128] } 10086:{ *:[iPTR] }, f128:{ *:[f128] }:$RB) => (XSSQRTQPO:{ *:[f128] } f128:{ *:[f128] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSSQRTQPO), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_RootToRootCopy, /*OpIdx*/2, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1005, GIR_EraseRootFromParent_Done, // Label 453: @10150 GIM_Try, /*On fail goto*//*Label 454*/ GIMT_Encode4(10182), // Rule ID 1012 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_truncf128_round_to_odd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VFRCRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 10113:{ *:[iPTR] }, f128:{ *:[f128] }:$RB) => (XSCVQPDPO:{ *:[f64] } f128:{ *:[f128] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVQPDPO), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_RootToRootCopy, /*OpIdx*/2, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1012, GIR_EraseRootFromParent_Done, // Label 454: @10182 GIM_Try, /*On fail goto*//*Label 455*/ GIMT_Encode4(10214), // Rule ID 1021 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvsphp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 10156:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVCVSPHP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVSPHP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1021, GIR_EraseRootFromParent_Done, // Label 455: @10214 GIM_Try, /*On fail goto*//*Label 456*/ GIMT_Encode4(10246), // Rule ID 1025 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvxexpdp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 10184:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB) => (XVXEXPDP:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVXEXPDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1025, GIR_EraseRootFromParent_Done, // Label 456: @10246 GIM_Try, /*On fail goto*//*Label 457*/ GIMT_Encode4(10278), // Rule ID 1026 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvxexpsp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 10185:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVXEXPSP:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVXEXPSP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1026, GIR_EraseRootFromParent_Done, // Label 457: @10278 GIM_Try, /*On fail goto*//*Label 458*/ GIMT_Encode4(10310), // Rule ID 1027 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvxsigdp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 10186:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB) => (XVXSIGDP:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVXSIGDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1027, GIR_EraseRootFromParent_Done, // Label 458: @10310 GIM_Try, /*On fail goto*//*Label 459*/ GIMT_Encode4(10342), // Rule ID 1028 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvxsigsp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 10187:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVXSIGSP:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVXSIGSP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1028, GIR_EraseRootFromParent_Done, // Label 459: @10342 GIM_Try, /*On fail goto*//*Label 460*/ GIMT_Encode4(10397), // Rule ID 1651 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtsqrtdp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 10180:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$A) => (COPY_TO_REGCLASS:{ *:[i32] } (XVTSQRTDP:{ *:[i32] } ?:{ *:[v2f64] }:$A), GPRC:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVTSQRTDP), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // A GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID), // GIR_Coverage, 1651, GIR_EraseRootFromParent_Done, // Label 460: @10397 GIM_Try, /*On fail goto*//*Label 461*/ GIMT_Encode4(10452), // Rule ID 1652 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtsqrtsp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 10181:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$A) => (COPY_TO_REGCLASS:{ *:[i32] } (XVTSQRTSP:{ *:[i32] } ?:{ *:[v4f32] }:$A), GPRC:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVTSQRTSP), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // A GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID), // GIR_Coverage, 1652, GIR_EraseRootFromParent_Done, // Label 461: @10452 GIM_Try, /*On fail goto*//*Label 462*/ GIMT_Encode4(10484), // Rule ID 1653 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvresp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 10173:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$A) => (XVRESP:{ *:[v4f32] } ?:{ *:[v4f32] }:$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVRESP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1653, GIR_EraseRootFromParent_Done, // Label 462: @10484 GIM_Try, /*On fail goto*//*Label 463*/ GIMT_Encode4(10516), // Rule ID 1654 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvredp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v2f64] } 10172:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$A) => (XVREDP:{ *:[v2f64] } ?:{ *:[v2f64] }:$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVREDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1654, GIR_EraseRootFromParent_Done, // Label 463: @10516 GIM_Try, /*On fail goto*//*Label 464*/ GIMT_Encode4(10548), // Rule ID 1655 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvrsqrtesp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 10176:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$A) => (XVRSQRTESP:{ *:[v4f32] } ?:{ *:[v4f32] }:$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVRSQRTESP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1655, GIR_EraseRootFromParent_Done, // Label 464: @10548 GIM_Try, /*On fail goto*//*Label 465*/ GIMT_Encode4(10580), // Rule ID 1656 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvrsqrtedp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v2f64] } 10175:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$A) => (XVRSQRTEDP:{ *:[v2f64] } ?:{ *:[v2f64] }:$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVRSQRTEDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1656, GIR_EraseRootFromParent_Done, // Label 465: @10580 GIM_Try, /*On fail goto*//*Label 466*/ GIMT_Encode4(10612), // Rule ID 1742 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fre), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 9962:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSREDP:{ *:[f64] } ?:{ *:[f64] }:$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSREDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1742, GIR_EraseRootFromParent_Done, // Label 466: @10612 GIM_Try, /*On fail goto*//*Label 467*/ GIMT_Encode4(10644), // Rule ID 1744 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnabs), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 9957:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSNABSDP:{ *:[f64] } ?:{ *:[f64] }:$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNABSDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1744, GIR_EraseRootFromParent_Done, // Label 467: @10644 GIM_Try, /*On fail goto*//*Label 468*/ GIMT_Encode4(10676), // Rule ID 1745 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnabss), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), // (intrinsic_wo_chain:{ *:[f32] } 9958:{ *:[iPTR] }, f32:{ *:[f32] }:$A) => (XSNABSDPs:{ *:[f32] } ?:{ *:[f32] }:$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNABSDPs), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1745, GIR_EraseRootFromParent_Done, // Label 468: @10676 GIM_Try, /*On fail goto*//*Label 469*/ GIMT_Encode4(10708), // Rule ID 1929 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fres), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), // (intrinsic_wo_chain:{ *:[f32] } 9963:{ *:[iPTR] }, f32:{ *:[f32] }:$A) => (XSRESP:{ *:[f32] } ?:{ *:[f32] }:$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRESP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1929, GIR_EraseRootFromParent_Done, // Label 469: @10708 GIM_Try, /*On fail goto*//*Label 470*/ GIMT_Encode4(10789), // Rule ID 1930 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_extract_exp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 9942:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (EXTRACT_SUBREG:{ *:[i32] } (XSXEXPDP:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f64] }:$A, VSFRC:{ *:[i32] })), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // A GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSXEXPDP), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), // GIR_Coverage, 1930, GIR_EraseRootFromParent_Done, // Label 470: @10789 GIM_Try, /*On fail goto*//*Label 471*/ GIMT_Encode4(10840), // Rule ID 1931 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_extract_sig), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (intrinsic_wo_chain:{ *:[i64] } 9943:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSXSIGDP:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f64] }:$A, VSFRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // A GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSXSIGDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1931, GIR_EraseRootFromParent_Done, // Label 471: @10840 GIM_Try, /*On fail goto*//*Label 472*/ GIMT_Encode4(10891), // Rule ID 2144 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvhpsp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 10153:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$A) => (XVCVHPSP:{ *:[v4f32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v8i16] }:$A, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // A GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVHPSP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2144, GIR_EraseRootFromParent_Done, // Label 472: @10891 GIM_Try, /*On fail goto*//*Label 473*/ GIMT_Encode4(10971), // Rule ID 2158 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_scalar_extract_expq), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (intrinsic_wo_chain:{ *:[i64] } 10077:{ *:[iPTR] }, f128:{ *:[f128] }:$vA) => (MFVSRD:{ *:[i64] } (EXTRACT_SUBREG:{ *:[f64] } (XSXEXPQP:{ *:[v2i64] } ?:{ *:[f128] }:$vA), sub_64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSXEXPQP), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // vA GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_64), GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VFRCRegClassID), GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::VRRCRegClassID), GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2158, GIR_EraseRootFromParent_Done, // Label 473: @10971 GIM_Try, /*On fail goto*//*Label 474*/ GIMT_Encode4(11014), // Rule ID 1091 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_mtvsrbm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 9607:{ *:[iPTR] }, (imm:{ *:[i64] }):$D) => (MTVSRBMI:{ *:[v16i8] } (imm:{ *:[i64] }):$D) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRBMI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // D GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1091, GIR_EraseRootFromParent_Done, // Label 474: @11014 GIM_Try, /*On fail goto*//*Label 475*/ GIMT_Encode4(11047), // Rule ID 4811 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_frsqrte), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 9964:{ *:[iPTR] }, f8rc:{ *:[f64] }:$frB) => (FRSQRTE:{ *:[f64] } ?:{ *:[f64] }:$frB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FRSQRTE), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_RootToRootCopy, /*OpIdx*/2, // frB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4811, GIR_EraseRootFromParent_Done, // Label 475: @11047 GIM_Try, /*On fail goto*//*Label 476*/ GIMT_Encode4(11080), // Rule ID 4812 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_frsqrtes), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), // (intrinsic_wo_chain:{ *:[f32] } 9965:{ *:[iPTR] }, f4rc:{ *:[f32] }:$frB) => (FRSQRTES:{ *:[f32] } ?:{ *:[f32] }:$frB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FRSQRTES), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_RootToRootCopy, /*OpIdx*/2, // frB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4812, GIR_EraseRootFromParent_Done, // Label 476: @11080 GIM_Try, /*On fail goto*//*Label 477*/ GIMT_Encode4(11109), // Rule ID 73 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_popcntb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 10072:{ *:[iPTR] }, i32:{ *:[i32] }:$RST) => (POPCNTB:{ *:[i32] } i32:{ *:[i32] }:$RST) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::POPCNTB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/2, // RST GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73, GIR_EraseRootFromParent_Done, // Label 477: @11109 GIM_Try, /*On fail goto*//*Label 478*/ GIMT_Encode4(11138), // Rule ID 74 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cdtbcd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 9901:{ *:[iPTR] }, i32:{ *:[i32] }:$RST) => (CDTBCD:{ *:[i32] } i32:{ *:[i32] }:$RST) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CDTBCD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/2, // RST GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 74, GIR_EraseRootFromParent_Done, // Label 478: @11138 GIM_Try, /*On fail goto*//*Label 479*/ GIMT_Encode4(11167), // Rule ID 75 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cbcdtd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 9899:{ *:[iPTR] }, i32:{ *:[i32] }:$RST) => (CBCDTD:{ *:[i32] } i32:{ *:[i32] }:$RST) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CBCDTD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/2, // RST GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 75, GIR_EraseRootFromParent_Done, // Label 479: @11167 GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(11199), // Rule ID 321 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vexptefp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 9714:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VEXPTEFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXPTEFP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 321, GIR_EraseRootFromParent_Done, // Label 480: @11199 GIM_Try, /*On fail goto*//*Label 481*/ GIMT_Encode4(11231), // Rule ID 322 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vlogefp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 9752:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VLOGEFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VLOGEFP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 322, GIR_EraseRootFromParent_Done, // Label 481: @11231 GIM_Try, /*On fail goto*//*Label 482*/ GIMT_Encode4(11263), // Rule ID 363 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrefp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 9820:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VREFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VREFP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 363, GIR_EraseRootFromParent_Done, // Label 482: @11263 GIM_Try, /*On fail goto*//*Label 483*/ GIMT_Encode4(11295), // Rule ID 364 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrfim), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 9821:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VRFIM:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRFIM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 364, GIR_EraseRootFromParent_Done, // Label 483: @11295 GIM_Try, /*On fail goto*//*Label 484*/ GIMT_Encode4(11327), // Rule ID 365 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrfin), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 9822:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VRFIN:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRFIN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 365, GIR_EraseRootFromParent_Done, // Label 484: @11327 GIM_Try, /*On fail goto*//*Label 485*/ GIMT_Encode4(11359), // Rule ID 366 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrfip), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 9823:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VRFIP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRFIP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 366, GIR_EraseRootFromParent_Done, // Label 485: @11359 GIM_Try, /*On fail goto*//*Label 486*/ GIMT_Encode4(11391), // Rule ID 367 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrfiz), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 9824:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VRFIZ:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRFIZ), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 367, GIR_EraseRootFromParent_Done, // Label 486: @11391 GIM_Try, /*On fail goto*//*Label 487*/ GIMT_Encode4(11423), // Rule ID 368 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrsqrtefp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 9835:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VRSQRTEFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRSQRTEFP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 368, GIR_EraseRootFromParent_Done, // Label 487: @11423 GIM_Try, /*On fail goto*//*Label 488*/ GIMT_Encode4(11455), // Rule ID 419 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupkhpx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9877:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VUPKHPX:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKHPX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 419, GIR_EraseRootFromParent_Done, // Label 488: @11455 GIM_Try, /*On fail goto*//*Label 489*/ GIMT_Encode4(11487), // Rule ID 420 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupkhsb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9878:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VUPKHSB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKHSB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 420, GIR_EraseRootFromParent_Done, // Label 489: @11487 GIM_Try, /*On fail goto*//*Label 490*/ GIMT_Encode4(11519), // Rule ID 421 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupkhsh), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9879:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VUPKHSH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKHSH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 421, GIR_EraseRootFromParent_Done, // Label 490: @11519 GIM_Try, /*On fail goto*//*Label 491*/ GIMT_Encode4(11551), // Rule ID 422 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupklpx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9881:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VUPKLPX:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKLPX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 422, GIR_EraseRootFromParent_Done, // Label 491: @11551 GIM_Try, /*On fail goto*//*Label 492*/ GIMT_Encode4(11583), // Rule ID 423 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupklsb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9882:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VUPKLSB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKLSB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 423, GIR_EraseRootFromParent_Done, // Label 492: @11583 GIM_Try, /*On fail goto*//*Label 493*/ GIMT_Encode4(11615), // Rule ID 424 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupklsh), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9883:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VUPKLSH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKLSH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 424, GIR_EraseRootFromParent_Done, // Label 493: @11615 GIM_Try, /*On fail goto*//*Label 494*/ GIMT_Encode4(11647), // Rule ID 504 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupkhsw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9880:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB) => (VUPKHSW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKHSW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 504, GIR_EraseRootFromParent_Done, // Label 494: @11647 GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(11679), // Rule ID 505 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupklsw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9884:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB) => (VUPKLSW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKLSW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 505, GIR_EraseRootFromParent_Done, // Label 495: @11679 GIM_Try, /*On fail goto*//*Label 496*/ GIMT_Encode4(11711), // Rule ID 506 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vgbbd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9734:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VGBBD:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VGBBD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 506, GIR_EraseRootFromParent_Done, // Label 496: @11711 GIM_Try, /*On fail goto*//*Label 497*/ GIMT_Encode4(11743), // Rule ID 514 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Crypto), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vsbox), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9589:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA) => (VSBOX:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSBOX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 514, GIR_EraseRootFromParent_Done, // Label 497: @11743 GIM_Try, /*On fail goto*//*Label 498*/ GIMT_Encode4(11775), // Rule ID 530 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vclzlsbb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 9644:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VCLZLSBB:{ *:[i32] } v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCLZLSBB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 530, GIR_EraseRootFromParent_Done, // Label 498: @11775 GIM_Try, /*On fail goto*//*Label 499*/ GIMT_Encode4(11807), // Rule ID 531 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vctzlsbb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 9702:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VCTZLSBB:{ *:[i32] } v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCTZLSBB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 531, GIR_EraseRootFromParent_Done, // Label 499: @11807 GIM_Try, /*On fail goto*//*Label 500*/ GIMT_Encode4(11839), // Rule ID 536 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextsb2w), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9729:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VEXTSB2W:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTSB2W), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 536, GIR_EraseRootFromParent_Done, // Label 500: @11839 GIM_Try, /*On fail goto*//*Label 501*/ GIMT_Encode4(11871), // Rule ID 537 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextsh2w), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9732:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VEXTSH2W:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTSH2W), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 537, GIR_EraseRootFromParent_Done, // Label 501: @11871 GIM_Try, /*On fail goto*//*Label 502*/ GIMT_Encode4(11903), // Rule ID 538 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextsb2d), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9728:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VEXTSB2D:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTSB2D), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 538, GIR_EraseRootFromParent_Done, // Label 502: @11903 GIM_Try, /*On fail goto*//*Label 503*/ GIMT_Encode4(11935), // Rule ID 539 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextsh2d), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9731:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VEXTSH2D:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTSH2D), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 539, GIR_EraseRootFromParent_Done, // Label 503: @11935 GIM_Try, /*On fail goto*//*Label 504*/ GIMT_Encode4(11967), // Rule ID 540 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextsw2d), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9733:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB) => (VEXTSW2D:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTSW2D), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 540, GIR_EraseRootFromParent_Done, // Label 504: @11967 GIM_Try, /*On fail goto*//*Label 505*/ GIMT_Encode4(11999), // Rule ID 543 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vprtybw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9819:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB) => (VPRTYBW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPRTYBW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 543, GIR_EraseRootFromParent_Done, // Label 505: @11999 GIM_Try, /*On fail goto*//*Label 506*/ GIMT_Encode4(12031), // Rule ID 544 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vprtybd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9817:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VB) => (VPRTYBD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPRTYBD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 544, GIR_EraseRootFromParent_Done, // Label 506: @12031 GIM_Try, /*On fail goto*//*Label 507*/ GIMT_Encode4(12063), // Rule ID 545 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vprtybq), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v1i128] } 9818:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VB) => (VPRTYBQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPRTYBQ), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 545, GIR_EraseRootFromParent_Done, // Label 507: @12063 GIM_Try, /*On fail goto*//*Label 508*/ GIMT_Encode4(12092), // Rule ID 689 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_popcntb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (intrinsic_wo_chain:{ *:[i64] } 10072:{ *:[iPTR] }, i64:{ *:[i64] }:$RST) => (POPCNTB8:{ *:[i64] } i64:{ *:[i64] }:$RST) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::POPCNTB8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/2, // RST GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 689, GIR_EraseRootFromParent_Done, // Label 508: @12092 GIM_Try, /*On fail goto*//*Label 509*/ GIMT_Encode4(12121), // Rule ID 690 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cdtbcdd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (intrinsic_wo_chain:{ *:[i64] } 9902:{ *:[iPTR] }, i64:{ *:[i64] }:$RST) => (CDTBCD8:{ *:[i64] } i64:{ *:[i64] }:$RST) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CDTBCD8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/2, // RST GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 690, GIR_EraseRootFromParent_Done, // Label 509: @12121 GIM_Try, /*On fail goto*//*Label 510*/ GIMT_Encode4(12150), // Rule ID 691 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cbcdtdd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (intrinsic_wo_chain:{ *:[i64] } 9900:{ *:[iPTR] }, i64:{ *:[i64] }:$RST) => (CBCDTD8:{ *:[i64] } i64:{ *:[i64] }:$RST) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CBCDTD8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/2, // RST GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 691, GIR_EraseRootFromParent_Done, // Label 510: @12150 GIM_Try, /*On fail goto*//*Label 511*/ GIMT_Encode4(12182), // Rule ID 1056 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vstribr), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9856:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VSTRIBR:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSTRIBR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VT] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1056, GIR_EraseRootFromParent_Done, // Label 511: @12182 GIM_Try, /*On fail goto*//*Label 512*/ GIMT_Encode4(12214), // Rule ID 1057 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vstribl), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9854:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VSTRIBL:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSTRIBL), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VT] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1057, GIR_EraseRootFromParent_Done, // Label 512: @12214 GIM_Try, /*On fail goto*//*Label 513*/ GIMT_Encode4(12246), // Rule ID 1058 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vstrihr), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9860:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VSTRIHR:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSTRIHR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VT] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1058, GIR_EraseRootFromParent_Done, // Label 513: @12246 GIM_Try, /*On fail goto*//*Label 514*/ GIMT_Encode4(12278), // Rule ID 1059 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vstrihl), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9858:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VSTRIHL:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSTRIHL), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VT] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1059, GIR_EraseRootFromParent_Done, // Label 514: @12278 GIM_Try, /*On fail goto*//*Label 515*/ GIMT_Encode4(12310), // Rule ID 1076 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextractbm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 9723:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VEXTRACTBM:{ *:[i32] } v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTRACTBM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1076, GIR_EraseRootFromParent_Done, // Label 515: @12310 GIM_Try, /*On fail goto*//*Label 516*/ GIMT_Encode4(12342), // Rule ID 1077 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextracthm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 9725:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VEXTRACTHM:{ *:[i32] } v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTRACTHM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1077, GIR_EraseRootFromParent_Done, // Label 516: @12342 GIM_Try, /*On fail goto*//*Label 517*/ GIMT_Encode4(12374), // Rule ID 1078 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextractwm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 9727:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB) => (VEXTRACTWM:{ *:[i32] } v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTRACTWM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1078, GIR_EraseRootFromParent_Done, // Label 517: @12374 GIM_Try, /*On fail goto*//*Label 518*/ GIMT_Encode4(12406), // Rule ID 1079 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextractdm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 9724:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VB) => (VEXTRACTDM:{ *:[i32] } v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTRACTDM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1079, GIR_EraseRootFromParent_Done, // Label 518: @12406 GIM_Try, /*On fail goto*//*Label 519*/ GIMT_Encode4(12438), // Rule ID 1080 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextractqm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 9726:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VB) => (VEXTRACTQM:{ *:[i32] } v1i128:{ *:[v1i128] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTRACTQM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1080, GIR_EraseRootFromParent_Done, // Label 519: @12438 GIM_Try, /*On fail goto*//*Label 520*/ GIMT_Encode4(12470), // Rule ID 1081 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vexpandbm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9709:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VEXPANDBM:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXPANDBM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1081, GIR_EraseRootFromParent_Done, // Label 520: @12470 GIM_Try, /*On fail goto*//*Label 521*/ GIMT_Encode4(12502), // Rule ID 1082 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vexpandhm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9711:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VEXPANDHM:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXPANDHM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1082, GIR_EraseRootFromParent_Done, // Label 521: @12502 GIM_Try, /*On fail goto*//*Label 522*/ GIMT_Encode4(12534), // Rule ID 1083 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vexpandwm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9713:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB) => (VEXPANDWM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXPANDWM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1083, GIR_EraseRootFromParent_Done, // Label 522: @12534 GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(12566), // Rule ID 1084 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vexpanddm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9710:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VB) => (VEXPANDDM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXPANDDM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1084, GIR_EraseRootFromParent_Done, // Label 523: @12566 GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(12598), // Rule ID 1085 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vexpandqm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v1i128] } 9712:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VB) => (VEXPANDQM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXPANDQM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1085, GIR_EraseRootFromParent_Done, // Label 524: @12598 GIM_Try, /*On fail goto*//*Label 525*/ GIMT_Encode4(12630), // Rule ID 1086 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_mtvsrbm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9607:{ *:[iPTR] }, i64:{ *:[i64] }:$VB) => (MTVSRBM:{ *:[v16i8] } i64:{ *:[i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRBM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1086, GIR_EraseRootFromParent_Done, // Label 525: @12630 GIM_Try, /*On fail goto*//*Label 526*/ GIMT_Encode4(12662), // Rule ID 1087 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_mtvsrhm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9609:{ *:[iPTR] }, i64:{ *:[i64] }:$VB) => (MTVSRHM:{ *:[v8i16] } i64:{ *:[i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRHM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1087, GIR_EraseRootFromParent_Done, // Label 526: @12662 GIM_Try, /*On fail goto*//*Label 527*/ GIMT_Encode4(12694), // Rule ID 1088 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_mtvsrwm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9611:{ *:[iPTR] }, i64:{ *:[i64] }:$VB) => (MTVSRWM:{ *:[v4i32] } i64:{ *:[i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRWM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1088, GIR_EraseRootFromParent_Done, // Label 527: @12694 GIM_Try, /*On fail goto*//*Label 528*/ GIMT_Encode4(12726), // Rule ID 1089 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_mtvsrdm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9608:{ *:[iPTR] }, i64:{ *:[i64] }:$VB) => (MTVSRDM:{ *:[v2i64] } i64:{ *:[i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRDM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1089, GIR_EraseRootFromParent_Done, // Label 528: @12726 GIM_Try, /*On fail goto*//*Label 529*/ GIMT_Encode4(12758), // Rule ID 1090 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_mtvsrqm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v1i128] } 9610:{ *:[iPTR] }, i64:{ *:[i64] }:$VB) => (MTVSRQM:{ *:[v1i128] } i64:{ *:[i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRQM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1090, GIR_EraseRootFromParent_Done, // Label 529: @12758 GIM_Try, /*On fail goto*//*Label 530*/ GIMT_Encode4(12790), // Rule ID 1154 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextsd2q), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v1i128] } 9730:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VB) => (VEXTSD2Q:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTSD2Q), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1154, GIR_EraseRootFromParent_Done, // Label 530: @12790 GIM_Try, /*On fail goto*//*Label 531*/ GIMT_Encode4(12822), // Rule ID 1159 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xxmfacc), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10055:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$AT) => (XXMFACC:{ *:[v512i1] } v512i1:{ *:[v512i1] }:$AT) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXMFACC), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[ATo] GIR_RootToRootCopy, /*OpIdx*/2, // AT GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1159, GIR_EraseRootFromParent_Done, // Label 531: @12822 GIM_Try, /*On fail goto*//*Label 532*/ GIMT_Encode4(12854), // Rule ID 1160 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xxmtacc), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10056:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi) => (XXMTACC:{ *:[v512i1] } v512i1:{ *:[v512i1] }:$ATi) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXMTACC), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1160, GIR_EraseRootFromParent_Done, // Label 532: @12854 GIM_Try, /*On fail goto*//*Label 533*/ GIMT_Encode4(12883), // Rule ID 1275 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fre), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 9962:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (FRE:{ *:[f64] } ?:{ *:[f64] }:$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FRE), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1275, GIR_EraseRootFromParent_Done, // Label 533: @12883 GIM_Try, /*On fail goto*//*Label 534*/ GIMT_Encode4(12912), // Rule ID 1276 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fres), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), // (intrinsic_wo_chain:{ *:[f32] } 9963:{ *:[iPTR] }, f32:{ *:[f32] }:$A) => (FRES:{ *:[f32] } ?:{ *:[f32] }:$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FRES), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1276, GIR_EraseRootFromParent_Done, // Label 534: @12912 GIM_Try, /*On fail goto*//*Label 535*/ GIMT_Encode4(12941), // Rule ID 1277 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnabs), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 9957:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (FNABSD:{ *:[f64] } ?:{ *:[f64] }:$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNABSD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1277, GIR_EraseRootFromParent_Done, // Label 535: @12941 GIM_Try, /*On fail goto*//*Label 536*/ GIMT_Encode4(12970), // Rule ID 1278 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnabss), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), // (intrinsic_wo_chain:{ *:[f32] } 9958:{ *:[iPTR] }, f32:{ *:[f32] }:$A) => (FNABSS:{ *:[f32] } ?:{ *:[f32] }:$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNABSS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1278, GIR_EraseRootFromParent_Done, // Label 536: @12970 GIM_Try, /*On fail goto*//*Label 537*/ GIMT_Encode4(13042), // Rule ID 3346 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvspbf16), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 10154:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA) => (COPY_TO_REGCLASS:{ *:[v16i8] } (XVCVSPBF16:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] })), VRRC:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVCVSPBF16), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 3346, GIR_EraseRootFromParent_Done, // Label 537: @13042 GIM_Try, /*On fail goto*//*Label 538*/ GIMT_Encode4(13114), // Rule ID 3347 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvbf16spn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 10149:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA) => (COPY_TO_REGCLASS:{ *:[v16i8] } (XVCVBF16SPN:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] })), VRRC:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVCVBF16SPN), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 3347, GIR_EraseRootFromParent_Done, // Label 538: @13114 GIM_Try, /*On fail goto*//*Label 539*/ GIMT_Encode4(13143), // Rule ID 4845 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fcfid), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 9944:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSCVSXDDP:{ *:[f64] } ?:{ *:[f64] }:$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVSXDDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4845, GIR_EraseRootFromParent_Done, // Label 539: @13143 GIM_Try, /*On fail goto*//*Label 540*/ GIMT_Encode4(13172), // Rule ID 4846 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fcfud), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 9945:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSCVUXDDP:{ *:[f64] } ?:{ *:[f64] }:$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVUXDDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4846, GIR_EraseRootFromParent_Done, // Label 540: @13172 GIM_Try, /*On fail goto*//*Label 541*/ GIMT_Encode4(13201), // Rule ID 4847 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fctid), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 9946:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (FCTID:{ *:[f64] } ?:{ *:[f64] }:$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FCTID), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4847, GIR_EraseRootFromParent_Done, // Label 541: @13201 GIM_Try, /*On fail goto*//*Label 542*/ GIMT_Encode4(13230), // Rule ID 4848 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fctidz), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 9947:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSCVDPSXDS:{ *:[f64] } ?:{ *:[f64] }:$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVDPSXDS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4848, GIR_EraseRootFromParent_Done, // Label 542: @13230 GIM_Try, /*On fail goto*//*Label 543*/ GIMT_Encode4(13259), // Rule ID 4849 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fctiw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 9948:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (FCTIW:{ *:[f64] } ?:{ *:[f64] }:$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FCTIW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4849, GIR_EraseRootFromParent_Done, // Label 543: @13259 GIM_Try, /*On fail goto*//*Label 544*/ GIMT_Encode4(13288), // Rule ID 4850 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fctiwz), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 9949:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSCVDPSXWS:{ *:[f64] } ?:{ *:[f64] }:$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVDPSXWS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4850, GIR_EraseRootFromParent_Done, // Label 544: @13288 GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(13317), // Rule ID 4851 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fctudz), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 9950:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSCVDPUXDS:{ *:[f64] } ?:{ *:[f64] }:$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVDPUXDS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4851, GIR_EraseRootFromParent_Done, // Label 545: @13317 GIM_Try, /*On fail goto*//*Label 546*/ GIMT_Encode4(13346), // Rule ID 4852 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fctuwz), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 9951:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSCVDPUXWS:{ *:[f64] } ?:{ *:[f64] }:$A) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVDPUXWS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4852, GIR_EraseRootFromParent_Done, // Label 546: @13346 GIM_Reject, // Label 440: @13347 GIM_Try, /*On fail goto*//*Label 547*/ GIMT_Encode4(21613), GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, GIM_Try, /*On fail goto*//*Label 548*/ GIMT_Encode4(13426), // Rule ID 2160 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxextractuw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (intrinsic_wo_chain:{ *:[v2i64] } 10193:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$A, (imm:{ *:[i32] }):$IMM) => (COPY_TO_REGCLASS:{ *:[v2i64] } (XXEXTRACTUW:{ *:[f64] } ?:{ *:[v2i64] }:$A, (imm:{ *:[i32] }):$IMM), VSRC:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXEXTRACTUW), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // A GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // IMM GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), // GIR_Coverage, 2160, GIR_EraseRootFromParent_Done, // Label 548: @13426 GIM_Try, /*On fail goto*//*Label 549*/ GIMT_Encode4(13463), // Rule ID 1029 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtstdcsp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // MIs[0] DCMX GIM_CheckIsImm, /*MI*/0, /*Op*/3, // (intrinsic_wo_chain:{ *:[v4i32] } 10183:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB, (timm:{ *:[i32] }):$DCMX) => (XVTSTDCSP:{ *:[v4i32] } (timm:{ *:[i32] }):$DCMX, v4f32:{ *:[v4f32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVTSTDCSP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/3, // DCMX GIR_RootToRootCopy, /*OpIdx*/2, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1029, GIR_EraseRootFromParent_Done, // Label 549: @13463 GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(13500), // Rule ID 1030 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtstdcdp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // MIs[0] DCMX GIM_CheckIsImm, /*MI*/0, /*Op*/3, // (intrinsic_wo_chain:{ *:[v2i64] } 10182:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB, (timm:{ *:[i32] }):$DCMX) => (XVTSTDCDP:{ *:[v2i64] } (timm:{ *:[i32] }):$DCMX, v2f64:{ *:[v2f64] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVTSTDCDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/3, // DCMX GIR_RootToRootCopy, /*OpIdx*/2, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1030, GIR_EraseRootFromParent_Done, // Label 550: @13500 GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(13545), // Rule ID 898 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xsmaxdp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 10135:{ *:[iPTR] }, vsfrc:{ *:[f64] }:$XA, vsfrc:{ *:[f64] }:$XB) => (XSMAXDP:{ *:[f64] } vsfrc:{ *:[f64] }:$XA, vsfrc:{ *:[f64] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMAXDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XA GIR_RootToRootCopy, /*OpIdx*/3, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 898, GIR_EraseRootFromParent_Done, // Label 551: @13545 GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(13590), // Rule ID 899 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xsmindp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 10136:{ *:[iPTR] }, vsfrc:{ *:[f64] }:$XA, vsfrc:{ *:[f64] }:$XB) => (XSMINDP:{ *:[f64] } vsfrc:{ *:[f64] }:$XA, vsfrc:{ *:[f64] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMINDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XA GIR_RootToRootCopy, /*OpIdx*/3, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 899, GIR_EraseRootFromParent_Done, // Label 552: @13590 GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(13635), // Rule ID 900 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvmaxdp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v2f64] } 10167:{ *:[iPTR] }, vsrc:{ *:[v2f64] }:$XA, vsrc:{ *:[v2f64] }:$XB) => (XVMAXDP:{ *:[v2f64] } vsrc:{ *:[v2f64] }:$XA, vsrc:{ *:[v2f64] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMAXDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XA GIR_RootToRootCopy, /*OpIdx*/3, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 900, GIR_EraseRootFromParent_Done, // Label 553: @13635 GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(13680), // Rule ID 901 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvmindp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v2f64] } 10169:{ *:[iPTR] }, vsrc:{ *:[v2f64] }:$XA, vsrc:{ *:[v2f64] }:$XB) => (XVMINDP:{ *:[v2f64] } vsrc:{ *:[v2f64] }:$XA, vsrc:{ *:[v2f64] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMINDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XA GIR_RootToRootCopy, /*OpIdx*/3, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 901, GIR_EraseRootFromParent_Done, // Label 554: @13680 GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(13725), // Rule ID 902 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvmaxsp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 10168:{ *:[iPTR] }, vsrc:{ *:[v4f32] }:$XA, vsrc:{ *:[v4f32] }:$XB) => (XVMAXSP:{ *:[v4f32] } vsrc:{ *:[v4f32] }:$XA, vsrc:{ *:[v4f32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMAXSP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XA GIR_RootToRootCopy, /*OpIdx*/3, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 902, GIR_EraseRootFromParent_Done, // Label 555: @13725 GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(13770), // Rule ID 903 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvminsp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 10170:{ *:[iPTR] }, vsrc:{ *:[v4f32] }:$XA, vsrc:{ *:[v4f32] }:$XB) => (XVMINSP:{ *:[v4f32] } vsrc:{ *:[v4f32] }:$XA, vsrc:{ *:[v4f32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMINSP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XA GIR_RootToRootCopy, /*OpIdx*/3, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 903, GIR_EraseRootFromParent_Done, // Label 556: @13770 GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(13807), // Rule ID 827 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcmpeqdp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 10137:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVCMPEQDP:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCMPEQDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XA GIR_RootToRootCopy, /*OpIdx*/3, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 827, GIR_EraseRootFromParent_Done, // Label 557: @13807 GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(13844), // Rule ID 829 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcmpeqsp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 10139:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVCMPEQSP:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCMPEQSP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XA GIR_RootToRootCopy, /*OpIdx*/3, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 829, GIR_EraseRootFromParent_Done, // Label 558: @13844 GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(13881), // Rule ID 831 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcmpgedp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 10141:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVCMPGEDP:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCMPGEDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XA GIR_RootToRootCopy, /*OpIdx*/3, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 831, GIR_EraseRootFromParent_Done, // Label 559: @13881 GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(13918), // Rule ID 833 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcmpgesp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 10143:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVCMPGESP:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCMPGESP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XA GIR_RootToRootCopy, /*OpIdx*/3, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 833, GIR_EraseRootFromParent_Done, // Label 560: @13918 GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(13955), // Rule ID 835 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcmpgtdp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 10145:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVCMPGTDP:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCMPGTDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XA GIR_RootToRootCopy, /*OpIdx*/3, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 835, GIR_EraseRootFromParent_Done, // Label 561: @13955 GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(13992), // Rule ID 837 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcmpgtsp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 10147:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVCMPGTSP:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCMPGTSP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XA GIR_RootToRootCopy, /*OpIdx*/3, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 837, GIR_EraseRootFromParent_Done, // Label 562: @13992 GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(14029), // Rule ID 1001 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_addf128_round_to_odd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[f128] } 9576:{ *:[iPTR] }, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSADDQPO:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSADDQPO), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1001, GIR_EraseRootFromParent_Done, // Label 563: @14029 GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(14066), // Rule ID 1002 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mulf128_round_to_odd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[f128] } 10064:{ *:[iPTR] }, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSMULQPO:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMULQPO), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1002, GIR_EraseRootFromParent_Done, // Label 564: @14066 GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(14103), // Rule ID 1003 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_subf128_round_to_odd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[f128] } 10095:{ *:[iPTR] }, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSSUBQPO:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSSUBQPO), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1003, GIR_EraseRootFromParent_Done, // Label 565: @14103 GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(14140), // Rule ID 1004 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_divf128_round_to_odd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[f128] } 9938:{ *:[iPTR] }, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSDIVQPO:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSDIVQPO), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1004, GIR_EraseRootFromParent_Done, // Label 566: @14140 GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(14177), // Rule ID 1023 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xviexpdp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v2f64] } 10165:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$XA, v2i64:{ *:[v2i64] }:$XB) => (XVIEXPDP:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$XA, v2i64:{ *:[v2i64] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVIEXPDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XA GIR_RootToRootCopy, /*OpIdx*/3, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1023, GIR_EraseRootFromParent_Done, // Label 567: @14177 GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(14214), // Rule ID 1024 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xviexpsp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 10166:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) => (XVIEXPSP:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVIEXPSP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XA GIR_RootToRootCopy, /*OpIdx*/3, // XB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1024, GIR_EraseRootFromParent_Done, // Label 568: @14214 GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(14251), // Rule ID 1647 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvdivsp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 10164:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$A, v4f32:{ *:[v4f32] }:$B) => (XVDIVSP:{ *:[v4f32] } ?:{ *:[v4f32] }:$A, ?:{ *:[v4f32] }:$B) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVDIVSP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootToRootCopy, /*OpIdx*/3, // B GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1647, GIR_EraseRootFromParent_Done, // Label 569: @14251 GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(14288), // Rule ID 1648 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvdivdp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v2f64] } 10163:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$A, v2f64:{ *:[v2f64] }:$B) => (XVDIVDP:{ *:[v2f64] } ?:{ *:[v2f64] }:$A, ?:{ *:[v2f64] }:$B) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVDIVDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootToRootCopy, /*OpIdx*/3, // B GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1648, GIR_EraseRootFromParent_Done, // Label 570: @14288 GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(14350), // Rule ID 1649 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtdivdp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 10177:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$A, v2f64:{ *:[v2f64] }:$B) => (COPY_TO_REGCLASS:{ *:[i32] } (XVTDIVDP:{ *:[i32] } ?:{ *:[v2f64] }:$A, ?:{ *:[v2f64] }:$B), GPRC:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVTDIVDP), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // A GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // B GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID), // GIR_Coverage, 1649, GIR_EraseRootFromParent_Done, // Label 571: @14350 GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(14412), // Rule ID 1650 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtdivsp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 10178:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$A, v4f32:{ *:[v4f32] }:$B) => (COPY_TO_REGCLASS:{ *:[i32] } (XVTDIVSP:{ *:[i32] } ?:{ *:[v4f32] }:$A, ?:{ *:[v4f32] }:$B), GPRC:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVTDIVSP), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // A GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // B GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID), // GIR_Coverage, 1650, GIR_EraseRootFromParent_Done, // Label 572: @14412 GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(14449), // Rule ID 1894 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxleqv), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 10199:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$A, v4i32:{ *:[v4i32] }:$B) => (XXLEQV:{ *:[v4i32] } ?:{ *:[v4i32] }:$A, ?:{ *:[v4i32] }:$B) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLEQV), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootToRootCopy, /*OpIdx*/3, // B GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1894, GIR_EraseRootFromParent_Done, // Label 573: @14449 GIM_Try, /*On fail goto*//*Label 574*/ GIMT_Encode4(14528), // Rule ID 1932 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_insert_exp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 9973:{ *:[iPTR] }, f64:{ *:[f64] }:$A, i64:{ *:[i64] }:$B) => (COPY_TO_REGCLASS:{ *:[f64] } (XSIEXPDP:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[i64] } ?:{ *:[f64] }:$A, G8RC:{ *:[i32] }), ?:{ *:[i64] }:$B), F8RC:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // A GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSIEXPDP), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // B GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::F8RCRegClassID), // GIR_Coverage, 1932, GIR_EraseRootFromParent_Done, // Label 574: @14528 GIM_Try, /*On fail goto*//*Label 575*/ GIMT_Encode4(14584), // Rule ID 2157 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_scalar_insert_exp_qp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[f128] } 10078:{ *:[iPTR] }, f128:{ *:[f128] }:$vA, i64:{ *:[i64] }:$vB) => (XSIEXPQP:{ *:[f128] } ?:{ *:[f128] }:$vA, (MTVSRD:{ *:[f64] } ?:{ *:[i64] }:$vB)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::MTVSRD), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vB GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSIEXPQP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] GIR_RootToRootCopy, /*OpIdx*/2, // vA GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2157, GIR_EraseRootFromParent_Done, // Label 575: @14584 GIM_Try, /*On fail goto*//*Label 576*/ GIMT_Encode4(14672), // Rule ID 3336 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtlsbb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, // (intrinsic_wo_chain:{ *:[i32] } 10179:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XB, 1:{ *:[i32] }) => (EXTRACT_SUBREG:{ *:[i32] } (XVTLSBB:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })), sub_lt:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVTLSBB), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), // GIR_Coverage, 3336, GIR_EraseRootFromParent_Done, // Label 576: @14672 GIM_Try, /*On fail goto*//*Label 577*/ GIMT_Encode4(14760), // Rule ID 3337 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtlsbb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, // (intrinsic_wo_chain:{ *:[i32] } 10179:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XB, 0:{ *:[i32] }) => (EXTRACT_SUBREG:{ *:[i32] } (XVTLSBB:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })), sub_eq:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVTLSBB), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), // GIR_Coverage, 3337, GIR_EraseRootFromParent_Done, // Label 577: @14760 GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(14803), // Rule ID 317 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcfsx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // MIs[0] Operand 3 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0), // (intrinsic_wo_chain:{ *:[v4f32] } 9638:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB, 0:{ *:[i32] }) => (VCFSX_0:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCFSX_0), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 317, GIR_EraseRootFromParent_Done, // Label 578: @14803 GIM_Try, /*On fail goto*//*Label 579*/ GIMT_Encode4(14846), // Rule ID 318 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vctuxs), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // MIs[0] Operand 3 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0), // (intrinsic_wo_chain:{ *:[v4i32] } 9700:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB, 0:{ *:[i32] }) => (VCTUXS_0:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCTUXS_0), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 318, GIR_EraseRootFromParent_Done, // Label 579: @14846 GIM_Try, /*On fail goto*//*Label 580*/ GIMT_Encode4(14889), // Rule ID 319 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcfux), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // MIs[0] Operand 3 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0), // (intrinsic_wo_chain:{ *:[v4f32] } 9640:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB, 0:{ *:[i32] }) => (VCFUX_0:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCFUX_0), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 319, GIR_EraseRootFromParent_Done, // Label 580: @14889 GIM_Try, /*On fail goto*//*Label 581*/ GIMT_Encode4(14932), // Rule ID 320 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vctsxs), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // MIs[0] Operand 3 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0), // (intrinsic_wo_chain:{ *:[v4i32] } 9699:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB, 0:{ *:[i32] }) => (VCTSXS_0:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCTSXS_0), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 320, GIR_EraseRootFromParent_Done, // Label 581: @14932 GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(15003), // Rule ID 3332 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxgenpcvbm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 10194:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VRB, (imm:{ *:[i32] }):$IMM) => (COPY_TO_REGCLASS:{ *:[v16i8] } (XXGENPCVBM:{ *:[v4i32] } ?:{ *:[v16i8] }:$VRB, (imm:{ *:[i32] }):$IMM), VRRC:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXGENPCVBM), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // VRB GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // IMM GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 3332, GIR_EraseRootFromParent_Done, // Label 582: @15003 GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(15074), // Rule ID 3333 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxgenpcvhm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 10196:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VRB, (imm:{ *:[i32] }):$IMM) => (COPY_TO_REGCLASS:{ *:[v8i16] } (XXGENPCVHM:{ *:[v4i32] } ?:{ *:[v8i16] }:$VRB, (imm:{ *:[i32] }):$IMM), VRRC:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXGENPCVHM), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // VRB GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // IMM GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 3333, GIR_EraseRootFromParent_Done, // Label 583: @15074 GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(15145), // Rule ID 3334 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxgenpcvwm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 10197:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VRB, (imm:{ *:[i32] }):$IMM) => (COPY_TO_REGCLASS:{ *:[v4i32] } (XXGENPCVWM:{ *:[v4i32] } ?:{ *:[v4i32] }:$VRB, (imm:{ *:[i32] }):$IMM), VRRC:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXGENPCVWM), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // VRB GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // IMM GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 3334, GIR_EraseRootFromParent_Done, // Label 584: @15145 GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(15216), // Rule ID 3335 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxgenpcvdm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (intrinsic_wo_chain:{ *:[v2i64] } 10195:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VRB, (imm:{ *:[i32] }):$IMM) => (COPY_TO_REGCLASS:{ *:[v2i64] } (XXGENPCVDM:{ *:[v4i32] } ?:{ *:[v2i64] }:$VRB, (imm:{ *:[i32] }):$IMM), VRRC:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXGENPCVDM), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // VRB GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // IMM GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), // GIR_Coverage, 3335, GIR_EraseRootFromParent_Done, // Label 585: @15216 GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(15253), // Rule ID 313 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcfsx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // MIs[0] VA GIM_CheckIsImm, /*MI*/0, /*Op*/3, // (intrinsic_wo_chain:{ *:[v4f32] } 9638:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB, (timm:{ *:[i32] }):$VA) => (VCFSX:{ *:[v4f32] } (timm:{ *:[i32] }):$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCFSX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/3, // VA GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 313, GIR_EraseRootFromParent_Done, // Label 586: @15253 GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(15290), // Rule ID 314 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcfux), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // MIs[0] VA GIM_CheckIsImm, /*MI*/0, /*Op*/3, // (intrinsic_wo_chain:{ *:[v4f32] } 9640:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB, (timm:{ *:[i32] }):$VA) => (VCFUX:{ *:[v4f32] } (timm:{ *:[i32] }):$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCFUX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/3, // VA GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 314, GIR_EraseRootFromParent_Done, // Label 587: @15290 GIM_Try, /*On fail goto*//*Label 588*/ GIMT_Encode4(15327), // Rule ID 315 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vctsxs), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // MIs[0] VA GIM_CheckIsImm, /*MI*/0, /*Op*/3, // (intrinsic_wo_chain:{ *:[v4i32] } 9699:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB, (timm:{ *:[i32] }):$VA) => (VCTSXS:{ *:[v4i32] } (timm:{ *:[i32] }):$VA, v4f32:{ *:[v4f32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCTSXS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/3, // VA GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 315, GIR_EraseRootFromParent_Done, // Label 588: @15327 GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(15364), // Rule ID 316 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vctuxs), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // MIs[0] VA GIM_CheckIsImm, /*MI*/0, /*Op*/3, // (intrinsic_wo_chain:{ *:[v4i32] } 9700:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB, (timm:{ *:[i32] }):$VA) => (VCTUXS:{ *:[v4i32] } (timm:{ *:[i32] }):$VA, v4f32:{ *:[v4f32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCTUXS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/3, // VA GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 316, GIR_EraseRootFromParent_Done, // Label 589: @15364 GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(15401), // Rule ID 1092 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcntmbb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // MIs[0] MP GIM_CheckIsImm, /*MI*/0, /*Op*/3, // (intrinsic_wo_chain:{ *:[i64] } 9695:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB, (timm:{ *:[i32] }):$MP) => (VCNTMBB:{ *:[i64] } v16i8:{ *:[v16i8] }:$VB, (timm:{ *:[i32] }):$MP) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCNTMBB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootToRootCopy, /*OpIdx*/3, // MP GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1092, GIR_EraseRootFromParent_Done, // Label 590: @15401 GIM_Try, /*On fail goto*//*Label 591*/ GIMT_Encode4(15438), // Rule ID 1093 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcntmbh), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // MIs[0] MP GIM_CheckIsImm, /*MI*/0, /*Op*/3, // (intrinsic_wo_chain:{ *:[i64] } 9697:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB, (timm:{ *:[i32] }):$MP) => (VCNTMBH:{ *:[i64] } v8i16:{ *:[v8i16] }:$VB, (timm:{ *:[i32] }):$MP) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCNTMBH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootToRootCopy, /*OpIdx*/3, // MP GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1093, GIR_EraseRootFromParent_Done, // Label 591: @15438 GIM_Try, /*On fail goto*//*Label 592*/ GIMT_Encode4(15475), // Rule ID 1094 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcntmbw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // MIs[0] MP GIM_CheckIsImm, /*MI*/0, /*Op*/3, // (intrinsic_wo_chain:{ *:[i64] } 9698:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB, (timm:{ *:[i32] }):$MP) => (VCNTMBW:{ *:[i64] } v4i32:{ *:[v4i32] }:$VB, (timm:{ *:[i32] }):$MP) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCNTMBW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootToRootCopy, /*OpIdx*/3, // MP GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1094, GIR_EraseRootFromParent_Done, // Label 592: @15475 GIM_Try, /*On fail goto*//*Label 593*/ GIMT_Encode4(15512), // Rule ID 1095 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcntmbd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // MIs[0] MP GIM_CheckIsImm, /*MI*/0, /*Op*/3, // (intrinsic_wo_chain:{ *:[i64] } 9696:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VB, (timm:{ *:[i32] }):$MP) => (VCNTMBD:{ *:[i64] } v2i64:{ *:[v2i64] }:$VB, (timm:{ *:[i32] }):$MP) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCNTMBD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootToRootCopy, /*OpIdx*/3, // MP GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1095, GIR_EraseRootFromParent_Done, // Label 593: @15512 GIM_Try, /*On fail goto*//*Label 594*/ GIMT_Encode4(15549), // Rule ID 1109 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vgnb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // MIs[0] N GIM_CheckIsImm, /*MI*/0, /*Op*/3, // (intrinsic_wo_chain:{ *:[i64] } 9735:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VB, (timm:{ *:[i32] }):$N) => (VGNB:{ *:[i64] } v1i128:{ *:[v1i128] }:$VB, (timm:{ *:[i32] }):$N) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VGNB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RD] GIR_RootToRootCopy, /*OpIdx*/2, // VB GIR_RootToRootCopy, /*OpIdx*/3, // N GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1109, GIR_EraseRootFromParent_Done, // Label 594: @15549 GIM_Try, /*On fail goto*//*Label 595*/ GIMT_Encode4(15594), // Rule ID 204 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasExtDiv), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_divwe), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 9939:{ *:[iPTR] }, gprc:{ *:[i32] }:$RA, gprc:{ *:[i32] }:$RB) => (DIVWE:{ *:[i32] } gprc:{ *:[i32] }:$RA, gprc:{ *:[i32] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DIVWE), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 204, GIR_EraseRootFromParent_Done, // Label 595: @15594 GIM_Try, /*On fail goto*//*Label 596*/ GIMT_Encode4(15639), // Rule ID 205 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasExtDiv), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_divweu), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 9940:{ *:[iPTR] }, gprc:{ *:[i32] }:$RA, gprc:{ *:[i32] }:$RB) => (DIVWEU:{ *:[i32] } gprc:{ *:[i32] }:$RA, gprc:{ *:[i32] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DIVWEU), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 205, GIR_EraseRootFromParent_Done, // Label 596: @15639 GIM_Try, /*On fail goto*//*Label 597*/ GIMT_Encode4(15684), // Rule ID 686 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBPERMD), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_bpermd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (intrinsic_wo_chain:{ *:[i64] } 9898:{ *:[iPTR] }, g8rc:{ *:[i64] }:$RST, g8rc:{ *:[i64] }:$RB) => (BPERMD:{ *:[i64] } g8rc:{ *:[i64] }:$RST, g8rc:{ *:[i64] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::BPERMD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/2, // RST GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 686, GIR_EraseRootFromParent_Done, // Label 597: @15684 GIM_Try, /*On fail goto*//*Label 598*/ GIMT_Encode4(15729), // Rule ID 695 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasExtDiv), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_divde), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (intrinsic_wo_chain:{ *:[i64] } 9936:{ *:[iPTR] }, g8rc:{ *:[i64] }:$RA, g8rc:{ *:[i64] }:$RB) => (DIVDE:{ *:[i64] } g8rc:{ *:[i64] }:$RA, g8rc:{ *:[i64] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DIVDE), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 695, GIR_EraseRootFromParent_Done, // Label 598: @15729 GIM_Try, /*On fail goto*//*Label 599*/ GIMT_Encode4(15774), // Rule ID 700 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasExtDiv), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_divdeu), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (intrinsic_wo_chain:{ *:[i64] } 9937:{ *:[iPTR] }, g8rc:{ *:[i64] }:$RA, g8rc:{ *:[i64] }:$RB) => (DIVDEU:{ *:[i64] } g8rc:{ *:[i64] }:$RA, g8rc:{ *:[i64] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DIVDEU), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 700, GIR_EraseRootFromParent_Done, // Label 599: @15774 GIM_Try, /*On fail goto*//*Label 600*/ GIMT_Encode4(15840), // Rule ID 1553 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_In64BitMode_IsISA3_0), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cmpeqb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (intrinsic_wo_chain:{ *:[i64] } 9906:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b) => (SETB8:{ *:[i64] } (CMPEQB:{ *:[i32] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPEQB), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // b GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETB8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1553, GIR_EraseRootFromParent_Done, // Label 600: @15840 GIM_Try, /*On fail goto*//*Label 601*/ GIMT_Encode4(15906), // Rule ID 1554 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_In64BitMode_IsISA3_0), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_setb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (intrinsic_wo_chain:{ *:[i64] } 10083:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b) => (SETB8:{ *:[i64] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPD), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // b GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETB8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1554, GIR_EraseRootFromParent_Done, // Label 601: @15906 GIM_Try, /*On fail goto*//*Label 602*/ GIMT_Encode4(15951), // Rule ID 1558 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_In64BitMode), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mulhd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (intrinsic_wo_chain:{ *:[i64] } 10065:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b) => (MULHD:{ *:[i64] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MULHD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // a GIR_RootToRootCopy, /*OpIdx*/3, // b GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1558, GIR_EraseRootFromParent_Done, // Label 602: @15951 GIM_Try, /*On fail goto*//*Label 603*/ GIMT_Encode4(15996), // Rule ID 1559 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_In64BitMode), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mulhdu), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (intrinsic_wo_chain:{ *:[i64] } 10066:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b) => (MULHDU:{ *:[i64] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MULHDU), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // a GIR_RootToRootCopy, /*OpIdx*/3, // b GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1559, GIR_EraseRootFromParent_Done, // Label 603: @15996 GIM_Try, /*On fail goto*//*Label 604*/ GIMT_Encode4(16038), // Rule ID 1562 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cmpb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (intrinsic_wo_chain:{ *:[i64] } 9905:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b) => (CMPB8:{ *:[i64] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CMPB8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/2, // a GIR_RootToRootCopy, /*OpIdx*/3, // b GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1562, GIR_EraseRootFromParent_Done, // Label 604: @16038 GIM_Try, /*On fail goto*//*Label 605*/ GIMT_Encode4(16080), // Rule ID 4831 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mulhw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 10067:{ *:[iPTR] }, gprc:{ *:[i32] }:$a, gprc:{ *:[i32] }:$b) => (MULHW:{ *:[i32] } ?:{ *:[i32] }:$a, ?:{ *:[i32] }:$b) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MULHW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // a GIR_RootToRootCopy, /*OpIdx*/3, // b GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4831, GIR_EraseRootFromParent_Done, // Label 605: @16080 GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(16122), // Rule ID 4832 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mulhwu), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 10068:{ *:[iPTR] }, gprc:{ *:[i32] }:$a, gprc:{ *:[i32] }:$b) => (MULHWU:{ *:[i32] } ?:{ *:[i32] }:$a, ?:{ *:[i32] }:$b) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MULHWU), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // a GIR_RootToRootCopy, /*OpIdx*/3, // b GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4832, GIR_EraseRootFromParent_Done, // Label 606: @16122 GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(16164), // Rule ID 4833 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cmpb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 9905:{ *:[iPTR] }, gprc:{ *:[i32] }:$a, gprc:{ *:[i32] }:$b) => (CMPB:{ *:[i32] } ?:{ *:[i32] }:$a, ?:{ *:[i32] }:$b) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CMPB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/2, // a GIR_RootToRootCopy, /*OpIdx*/3, // b GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4833, GIR_EraseRootFromParent_Done, // Label 607: @16164 GIM_Try, /*On fail goto*//*Label 608*/ GIMT_Encode4(16198), // Rule ID 76 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_addg6s), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), // (intrinsic_wo_chain:{ *:[i32] } 9577:{ *:[iPTR] }, i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (ADDG6S:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ADDG6S), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 76, GIR_EraseRootFromParent_Done, // Label 608: @16198 GIM_Try, /*On fail goto*//*Label 609*/ GIMT_Encode4(16235), // Rule ID 304 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddcuw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9621:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VADDCUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDCUW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 304, GIR_EraseRootFromParent_Done, // Label 609: @16235 GIM_Try, /*On fail goto*//*Label 610*/ GIMT_Encode4(16272), // Rule ID 305 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddsbs), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9624:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VADDSBS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDSBS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 305, GIR_EraseRootFromParent_Done, // Label 610: @16272 GIM_Try, /*On fail goto*//*Label 611*/ GIMT_Encode4(16309), // Rule ID 306 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddshs), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9625:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VADDSHS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDSHS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 306, GIR_EraseRootFromParent_Done, // Label 611: @16309 GIM_Try, /*On fail goto*//*Label 612*/ GIMT_Encode4(16346), // Rule ID 307 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddsws), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9626:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VADDSWS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDSWS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 307, GIR_EraseRootFromParent_Done, // Label 612: @16346 GIM_Try, /*On fail goto*//*Label 613*/ GIMT_Encode4(16383), // Rule ID 308 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddubs), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9627:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VADDUBS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDUBS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 308, GIR_EraseRootFromParent_Done, // Label 613: @16383 GIM_Try, /*On fail goto*//*Label 614*/ GIMT_Encode4(16420), // Rule ID 309 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vadduhs), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9628:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VADDUHS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDUHS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 309, GIR_EraseRootFromParent_Done, // Label 614: @16420 GIM_Try, /*On fail goto*//*Label 615*/ GIMT_Encode4(16457), // Rule ID 310 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vadduws), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9629:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VADDUWS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDUWS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 310, GIR_EraseRootFromParent_Done, // Label 615: @16457 GIM_Try, /*On fail goto*//*Label 616*/ GIMT_Encode4(16494), // Rule ID 323 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vavgsb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9630:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VAVGSB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VAVGSB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 323, GIR_EraseRootFromParent_Done, // Label 616: @16494 GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(16531), // Rule ID 324 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vavgsh), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9631:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VAVGSH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VAVGSH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 324, GIR_EraseRootFromParent_Done, // Label 617: @16531 GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(16568), // Rule ID 325 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vavgsw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9632:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VAVGSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VAVGSW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 325, GIR_EraseRootFromParent_Done, // Label 618: @16568 GIM_Try, /*On fail goto*//*Label 619*/ GIMT_Encode4(16605), // Rule ID 326 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vavgub), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9633:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VAVGUB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VAVGUB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 326, GIR_EraseRootFromParent_Done, // Label 619: @16605 GIM_Try, /*On fail goto*//*Label 620*/ GIMT_Encode4(16642), // Rule ID 327 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vavguh), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9634:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VAVGUH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VAVGUH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 327, GIR_EraseRootFromParent_Done, // Label 620: @16642 GIM_Try, /*On fail goto*//*Label 621*/ GIMT_Encode4(16679), // Rule ID 328 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vavguw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9635:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VAVGUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VAVGUW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 328, GIR_EraseRootFromParent_Done, // Label 621: @16679 GIM_Try, /*On fail goto*//*Label 622*/ GIMT_Encode4(16716), // Rule ID 329 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxfp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 9754:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VA, v4f32:{ *:[v4f32] }:$VB) => (VMAXFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VA, v4f32:{ *:[v4f32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXFP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 329, GIR_EraseRootFromParent_Done, // Label 622: @16716 GIM_Try, /*On fail goto*//*Label 623*/ GIMT_Encode4(16753), // Rule ID 330 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxsb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9755:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMAXSB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXSB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 330, GIR_EraseRootFromParent_Done, // Label 623: @16753 GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(16790), // Rule ID 331 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxsh), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9757:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMAXSH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXSH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 331, GIR_EraseRootFromParent_Done, // Label 624: @16790 GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(16827), // Rule ID 332 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxsw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9758:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMAXSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXSW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 332, GIR_EraseRootFromParent_Done, // Label 625: @16827 GIM_Try, /*On fail goto*//*Label 626*/ GIMT_Encode4(16864), // Rule ID 333 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxub), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9759:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMAXUB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXUB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 333, GIR_EraseRootFromParent_Done, // Label 626: @16864 GIM_Try, /*On fail goto*//*Label 627*/ GIMT_Encode4(16901), // Rule ID 334 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxuh), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9761:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMAXUH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXUH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 334, GIR_EraseRootFromParent_Done, // Label 627: @16901 GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(16938), // Rule ID 335 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxuw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9762:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMAXUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXUW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 335, GIR_EraseRootFromParent_Done, // Label 628: @16938 GIM_Try, /*On fail goto*//*Label 629*/ GIMT_Encode4(16975), // Rule ID 336 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminfp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 9765:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VA, v4f32:{ *:[v4f32] }:$VB) => (VMINFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VA, v4f32:{ *:[v4f32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINFP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 336, GIR_EraseRootFromParent_Done, // Label 629: @16975 GIM_Try, /*On fail goto*//*Label 630*/ GIMT_Encode4(17012), // Rule ID 337 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminsb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9766:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMINSB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINSB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 337, GIR_EraseRootFromParent_Done, // Label 630: @17012 GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(17049), // Rule ID 338 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminsh), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9768:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMINSH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINSH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 338, GIR_EraseRootFromParent_Done, // Label 631: @17049 GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(17086), // Rule ID 339 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminsw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9769:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMINSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINSW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 339, GIR_EraseRootFromParent_Done, // Label 632: @17086 GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(17123), // Rule ID 340 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminub), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9770:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMINUB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINUB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 340, GIR_EraseRootFromParent_Done, // Label 633: @17123 GIM_Try, /*On fail goto*//*Label 634*/ GIMT_Encode4(17160), // Rule ID 341 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminuh), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9772:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMINUH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINUH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 341, GIR_EraseRootFromParent_Done, // Label 634: @17160 GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(17197), // Rule ID 342 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminuw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9773:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMINUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINUW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 342, GIR_EraseRootFromParent_Done, // Label 635: @17197 GIM_Try, /*On fail goto*//*Label 636*/ GIMT_Encode4(17234), // Rule ID 355 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulesb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9783:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMULESB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULESB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 355, GIR_EraseRootFromParent_Done, // Label 636: @17234 GIM_Try, /*On fail goto*//*Label 637*/ GIMT_Encode4(17271), // Rule ID 356 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulesh), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9785:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMULESH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULESH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 356, GIR_EraseRootFromParent_Done, // Label 637: @17271 GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(17308), // Rule ID 357 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmuleub), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9787:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMULEUB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULEUB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 357, GIR_EraseRootFromParent_Done, // Label 638: @17308 GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(17345), // Rule ID 358 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmuleuh), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9789:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMULEUH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULEUH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 358, GIR_EraseRootFromParent_Done, // Label 639: @17345 GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(17382), // Rule ID 359 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulosb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9795:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMULOSB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOSB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 359, GIR_EraseRootFromParent_Done, // Label 640: @17382 GIM_Try, /*On fail goto*//*Label 641*/ GIMT_Encode4(17419), // Rule ID 360 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulosh), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9797:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMULOSH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOSH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 360, GIR_EraseRootFromParent_Done, // Label 641: @17419 GIM_Try, /*On fail goto*//*Label 642*/ GIMT_Encode4(17456), // Rule ID 361 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmuloub), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9799:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMULOUB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOUB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 361, GIR_EraseRootFromParent_Done, // Label 642: @17456 GIM_Try, /*On fail goto*//*Label 643*/ GIMT_Encode4(17493), // Rule ID 362 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulouh), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9801:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMULOUH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOUH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 362, GIR_EraseRootFromParent_Done, // Label 643: @17493 GIM_Try, /*On fail goto*//*Label 644*/ GIMT_Encode4(17530), // Rule ID 369 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubcuw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9863:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSUBCUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBCUW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 369, GIR_EraseRootFromParent_Done, // Label 644: @17530 GIM_Try, /*On fail goto*//*Label 645*/ GIMT_Encode4(17567), // Rule ID 374 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubsbs), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9866:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSUBSBS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBSBS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 374, GIR_EraseRootFromParent_Done, // Label 645: @17567 GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(17604), // Rule ID 375 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubshs), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9867:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VSUBSHS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBSHS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 375, GIR_EraseRootFromParent_Done, // Label 646: @17604 GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(17641), // Rule ID 376 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubsws), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9868:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSUBSWS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBSWS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 376, GIR_EraseRootFromParent_Done, // Label 647: @17641 GIM_Try, /*On fail goto*//*Label 648*/ GIMT_Encode4(17678), // Rule ID 377 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsububs), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9869:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSUBUBS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBUBS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 377, GIR_EraseRootFromParent_Done, // Label 648: @17678 GIM_Try, /*On fail goto*//*Label 649*/ GIMT_Encode4(17715), // Rule ID 378 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubuhs), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9870:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VSUBUHS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBUHS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 378, GIR_EraseRootFromParent_Done, // Label 649: @17715 GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(17752), // Rule ID 379 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubuws), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9871:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSUBUWS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBUWS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 379, GIR_EraseRootFromParent_Done, // Label 650: @17752 GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(17789), // Rule ID 388 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrlb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9825:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VRLB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 388, GIR_EraseRootFromParent_Done, // Label 651: @17789 GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(17826), // Rule ID 389 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrlh), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9829:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VRLH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 389, GIR_EraseRootFromParent_Done, // Label 652: @17826 GIM_Try, /*On fail goto*//*Label 653*/ GIMT_Encode4(17863), // Rule ID 390 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrlw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9832:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VRLW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 390, GIR_EraseRootFromParent_Done, // Label 653: @17863 GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(17900), // Rule ID 391 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsl), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9837:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSL:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSL), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 391, GIR_EraseRootFromParent_Done, // Label 654: @17900 GIM_Try, /*On fail goto*//*Label 655*/ GIMT_Encode4(17937), // Rule ID 392 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vslo), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9841:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSLO:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSLO), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 392, GIR_EraseRootFromParent_Done, // Label 655: @17937 GIM_Try, /*On fail goto*//*Label 656*/ GIMT_Encode4(17974), // Rule ID 393 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vslb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9838:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSLB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSLB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 393, GIR_EraseRootFromParent_Done, // Label 656: @17974 GIM_Try, /*On fail goto*//*Label 657*/ GIMT_Encode4(18011), // Rule ID 394 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vslh), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9840:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VSLH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSLH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 394, GIR_EraseRootFromParent_Done, // Label 657: @18011 GIM_Try, /*On fail goto*//*Label 658*/ GIMT_Encode4(18048), // Rule ID 395 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vslw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9843:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSLW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSLW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 395, GIR_EraseRootFromParent_Done, // Label 658: @18048 GIM_Try, /*On fail goto*//*Label 659*/ GIMT_Encode4(18085), // Rule ID 399 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsr), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9844:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 399, GIR_EraseRootFromParent_Done, // Label 659: @18085 GIM_Try, /*On fail goto*//*Label 660*/ GIMT_Encode4(18122), // Rule ID 400 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsro), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9851:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSRO:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRO), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 400, GIR_EraseRootFromParent_Done, // Label 660: @18122 GIM_Try, /*On fail goto*//*Label 661*/ GIMT_Encode4(18159), // Rule ID 401 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsrab), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9845:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSRAB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRAB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 401, GIR_EraseRootFromParent_Done, // Label 661: @18159 GIM_Try, /*On fail goto*//*Label 662*/ GIMT_Encode4(18196), // Rule ID 402 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsrah), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9846:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VSRAH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRAH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 402, GIR_EraseRootFromParent_Done, // Label 662: @18196 GIM_Try, /*On fail goto*//*Label 663*/ GIMT_Encode4(18233), // Rule ID 403 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsraw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9847:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSRAW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRAW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 403, GIR_EraseRootFromParent_Done, // Label 663: @18233 GIM_Try, /*On fail goto*//*Label 664*/ GIMT_Encode4(18270), // Rule ID 404 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsrb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9848:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSRB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 404, GIR_EraseRootFromParent_Done, // Label 664: @18270 GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(18307), // Rule ID 405 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsrh), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9850:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VSRH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 405, GIR_EraseRootFromParent_Done, // Label 665: @18307 GIM_Try, /*On fail goto*//*Label 666*/ GIMT_Encode4(18344), // Rule ID 406 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsrw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9853:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSRW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 406, GIR_EraseRootFromParent_Done, // Label 666: @18344 GIM_Try, /*On fail goto*//*Label 667*/ GIMT_Encode4(18381), // Rule ID 410 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpkpx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9807:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VPKPX:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPKPX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 410, GIR_EraseRootFromParent_Done, // Label 667: @18381 GIM_Try, /*On fail goto*//*Label 668*/ GIMT_Encode4(18418), // Rule ID 457 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulesw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9786:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMULESW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULESW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 457, GIR_EraseRootFromParent_Done, // Label 668: @18418 GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(18455), // Rule ID 458 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmuleuw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9790:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMULEUW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULEUW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 458, GIR_EraseRootFromParent_Done, // Label 669: @18455 GIM_Try, /*On fail goto*//*Label 670*/ GIMT_Encode4(18492), // Rule ID 459 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulosw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9798:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMULOSW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOSW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 459, GIR_EraseRootFromParent_Done, // Label 670: @18492 GIM_Try, /*On fail goto*//*Label 671*/ GIMT_Encode4(18529), // Rule ID 460 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulouw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9802:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMULOUW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOUW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 460, GIR_EraseRootFromParent_Done, // Label 671: @18529 GIM_Try, /*On fail goto*//*Label 672*/ GIMT_Encode4(18566), // Rule ID 462 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxsd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9756:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMAXSD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXSD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 462, GIR_EraseRootFromParent_Done, // Label 672: @18566 GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(18603), // Rule ID 463 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxud), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9760:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMAXUD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXUD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 463, GIR_EraseRootFromParent_Done, // Label 673: @18603 GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(18640), // Rule ID 464 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminsd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9767:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMINSD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINSD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 464, GIR_EraseRootFromParent_Done, // Label 674: @18640 GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(18677), // Rule ID 465 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminud), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9771:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMINUD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINUD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 465, GIR_EraseRootFromParent_Done, // Label 675: @18677 GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(18714), // Rule ID 468 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrld), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9826:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VRLD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 468, GIR_EraseRootFromParent_Done, // Label 676: @18714 GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(18751), // Rule ID 472 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddcuq), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v1i128] } 9620:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VADDCUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDCUQ), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 472, GIR_EraseRootFromParent_Done, // Label 677: @18751 GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(18788), // Rule ID 477 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubcuq), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v1i128] } 9862:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VSUBCUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBCUQ), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 477, GIR_EraseRootFromParent_Done, // Label 678: @18788 GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(18825), // Rule ID 496 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vpmsumb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9585:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VPMSUMB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPMSUMB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 496, GIR_EraseRootFromParent_Done, // Label 679: @18825 GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(18862), // Rule ID 497 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vpmsumh), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9587:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VPMSUMH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPMSUMH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 497, GIR_EraseRootFromParent_Done, // Label 680: @18862 GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(18899), // Rule ID 498 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vpmsumw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9588:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VPMSUMW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPMSUMW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 498, GIR_EraseRootFromParent_Done, // Label 681: @18899 GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(18936), // Rule ID 499 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vpmsumd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9586:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VPMSUMD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPMSUMD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 499, GIR_EraseRootFromParent_Done, // Label 682: @18936 GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(18973), // Rule ID 507 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vbpermq), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9637:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VBPERMQ:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VBPERMQ), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 507, GIR_EraseRootFromParent_Done, // Label 683: @18973 GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(19010), // Rule ID 510 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Crypto), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vcipher), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9579:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VCIPHER:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCIPHER), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 510, GIR_EraseRootFromParent_Done, // Label 684: @19010 GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(19047), // Rule ID 511 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Crypto), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vcipherlast), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9580:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VCIPHERLAST:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCIPHERLAST), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 511, GIR_EraseRootFromParent_Done, // Label 685: @19047 GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(19084), // Rule ID 512 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Crypto), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vncipher), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9581:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VNCIPHER:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNCIPHER), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 512, GIR_EraseRootFromParent_Done, // Label 686: @19084 GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(19121), // Rule ID 513 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Crypto), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vncipherlast), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9582:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VNCIPHERLAST:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNCIPHERLAST), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 513, GIR_EraseRootFromParent_Done, // Label 687: @19121 GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(19158), // Rule ID 546 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vbpermd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9636:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VBPERMD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VBPERMD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 546, GIR_EraseRootFromParent_Done, // Label 688: @19158 GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(19195), // Rule ID 547 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrlwnm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9834:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VRLWNM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLWNM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 547, GIR_EraseRootFromParent_Done, // Label 689: @19195 GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(19232), // Rule ID 549 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrldnm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9828:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VRLDNM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLDNM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 549, GIR_EraseRootFromParent_Done, // Label 690: @19232 GIM_Try, /*On fail goto*//*Label 691*/ GIMT_Encode4(19269), // Rule ID 551 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vslv), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9842:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSLV:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSLV), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 551, GIR_EraseRootFromParent_Done, // Label 691: @19269 GIM_Try, /*On fail goto*//*Label 692*/ GIMT_Encode4(19306), // Rule ID 552 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsrv), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9852:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSRV:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRV), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 552, GIR_EraseRootFromParent_Done, // Label 692: @19306 GIM_Try, /*On fail goto*//*Label 693*/ GIMT_Encode4(19343), // Rule ID 553 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vabsdub), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9617:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VABSDUB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VABSDUB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 553, GIR_EraseRootFromParent_Done, // Label 693: @19343 GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(19380), // Rule ID 554 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vabsduh), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9618:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VABSDUH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VABSDUH), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 554, GIR_EraseRootFromParent_Done, // Label 694: @19380 GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(19417), // Rule ID 555 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vabsduw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9619:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VABSDUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VABSDUW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 555, GIR_EraseRootFromParent_Done, // Label 695: @19417 GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(19451), // Rule ID 692 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_addg6sd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (intrinsic_wo_chain:{ *:[i64] } 9578:{ *:[iPTR] }, i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (ADDG6S8:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ADDG6S8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 692, GIR_EraseRootFromParent_Done, // Label 696: @19451 GIM_Try, /*On fail goto*//*Label 697*/ GIMT_Encode4(19488), // Rule ID 1104 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpdepd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9804:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VPDEPD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPDEPD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1104, GIR_EraseRootFromParent_Done, // Label 697: @19488 GIM_Try, /*On fail goto*//*Label 698*/ GIMT_Encode4(19525), // Rule ID 1105 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpextd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9806:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VPEXTD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPEXTD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1105, GIR_EraseRootFromParent_Done, // Label 698: @19525 GIM_Try, /*On fail goto*//*Label 699*/ GIMT_Encode4(19562), // Rule ID 1106 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_pdepd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (intrinsic_wo_chain:{ *:[i64] } 10070:{ *:[iPTR] }, i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (PDEPD:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PDEPD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/2, // RST GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1106, GIR_EraseRootFromParent_Done, // Label 699: @19562 GIM_Try, /*On fail goto*//*Label 700*/ GIMT_Encode4(19599), // Rule ID 1107 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_pextd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (intrinsic_wo_chain:{ *:[i64] } 10071:{ *:[iPTR] }, i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (PEXTD:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PEXTD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/2, // RST GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1107, GIR_EraseRootFromParent_Done, // Label 700: @19599 GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(19636), // Rule ID 1108 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcfuged), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9639:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VCFUGED:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCFUGED), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1108, GIR_EraseRootFromParent_Done, // Label 701: @19636 GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(19673), // Rule ID 1110 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cfuged), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (intrinsic_wo_chain:{ *:[i64] } 9904:{ *:[iPTR] }, i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (CFUGED:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CFUGED), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/2, // RST GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1110, GIR_EraseRootFromParent_Done, // Label 702: @19673 GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(19710), // Rule ID 1112 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vclzdm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9643:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VCLZDM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCLZDM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1112, GIR_EraseRootFromParent_Done, // Label 703: @19710 GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(19747), // Rule ID 1113 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vctzdm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9701:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VCTZDM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCTZDM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1113, GIR_EraseRootFromParent_Done, // Label 704: @19747 GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(19784), // Rule ID 1114 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cntlzdm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (intrinsic_wo_chain:{ *:[i64] } 9909:{ *:[iPTR] }, i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (CNTLZDM:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CNTLZDM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/2, // RST GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1114, GIR_EraseRootFromParent_Done, // Label 705: @19784 GIM_Try, /*On fail goto*//*Label 706*/ GIMT_Encode4(19821), // Rule ID 1115 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cnttzdm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (intrinsic_wo_chain:{ *:[i64] } 9910:{ *:[iPTR] }, i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (CNTTZDM:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CNTTZDM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] GIR_RootToRootCopy, /*OpIdx*/2, // RST GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1115, GIR_EraseRootFromParent_Done, // Label 706: @19821 GIM_Try, /*On fail goto*//*Label 707*/ GIMT_Encode4(19858), // Rule ID 1116 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vclrlb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9641:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, i32:{ *:[i32] }:$VB) => (VCLRLB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, i32:{ *:[i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCLRLB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1116, GIR_EraseRootFromParent_Done, // Label 707: @19858 GIM_Try, /*On fail goto*//*Label 708*/ GIMT_Encode4(19895), // Rule ID 1117 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vclrrb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9642:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, i32:{ *:[i32] }:$VB) => (VCLRRB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, i32:{ *:[i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCLRRB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1117, GIR_EraseRootFromParent_Done, // Label 708: @19895 GIM_Try, /*On fail goto*//*Label 709*/ GIMT_Encode4(19932), // Rule ID 1131 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vdivesw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9705:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VDIVESW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VDIVESW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1131, GIR_EraseRootFromParent_Done, // Label 709: @19932 GIM_Try, /*On fail goto*//*Label 710*/ GIMT_Encode4(19969), // Rule ID 1132 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vdiveuw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9708:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VDIVEUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VDIVEUW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1132, GIR_EraseRootFromParent_Done, // Label 710: @19969 GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(20006), // Rule ID 1133 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vdivesd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9703:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VDIVESD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VDIVESD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1133, GIR_EraseRootFromParent_Done, // Label 711: @20006 GIM_Try, /*On fail goto*//*Label 712*/ GIMT_Encode4(20043), // Rule ID 1134 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vdiveud), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9706:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VDIVEUD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VDIVEUD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1134, GIR_EraseRootFromParent_Done, // Label 712: @20043 GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(20080), // Rule ID 1137 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulesd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v1i128] } 9784:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMULESD:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULESD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1137, GIR_EraseRootFromParent_Done, // Label 713: @20080 GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(20117), // Rule ID 1138 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmuleud), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v1i128] } 9788:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMULEUD:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULEUD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1138, GIR_EraseRootFromParent_Done, // Label 714: @20117 GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(20154), // Rule ID 1139 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulosd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v1i128] } 9796:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMULOSD:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOSD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1139, GIR_EraseRootFromParent_Done, // Label 715: @20154 GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(20191), // Rule ID 1140 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmuloud), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v1i128] } 9800:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMULOUD:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOUD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1140, GIR_EraseRootFromParent_Done, // Label 716: @20191 GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(20228), // Rule ID 1144 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vdivesq), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v1i128] } 9704:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VDIVESQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VDIVESQ), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1144, GIR_EraseRootFromParent_Done, // Label 717: @20228 GIM_Try, /*On fail goto*//*Label 718*/ GIMT_Encode4(20265), // Rule ID 1145 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vdiveuq), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v1i128] } 9707:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VDIVEUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VDIVEUQ), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1145, GIR_EraseRootFromParent_Done, // Label 718: @20265 GIM_Try, /*On fail goto*//*Label 719*/ GIMT_Encode4(20302), // Rule ID 1155 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrlqnm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v1i128] } 9831:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VRLQNM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLQNM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1155, GIR_EraseRootFromParent_Done, // Label 719: @20302 GIM_Try, /*On fail goto*//*Label 720*/ GIMT_Encode4(20339), // Rule ID 3328 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulhsw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9792:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VMULHSW:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULHSW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // vA GIR_RootToRootCopy, /*OpIdx*/3, // vB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3328, GIR_EraseRootFromParent_Done, // Label 720: @20339 GIM_Try, /*On fail goto*//*Label 721*/ GIMT_Encode4(20376), // Rule ID 3329 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulhuw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9794:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VMULHUW:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULHUW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // vA GIR_RootToRootCopy, /*OpIdx*/3, // vB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3329, GIR_EraseRootFromParent_Done, // Label 721: @20376 GIM_Try, /*On fail goto*//*Label 722*/ GIMT_Encode4(20413), // Rule ID 3330 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulhsd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9791:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VMULHSD:{ *:[v2i64] } ?:{ *:[v2i64] }:$vA, ?:{ *:[v2i64] }:$vB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULHSD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // vA GIR_RootToRootCopy, /*OpIdx*/3, // vB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3330, GIR_EraseRootFromParent_Done, // Label 722: @20413 GIM_Try, /*On fail goto*//*Label 723*/ GIMT_Encode4(20450), // Rule ID 3331 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulhud), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9793:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VMULHUD:{ *:[v2i64] } ?:{ *:[v2i64] }:$vA, ?:{ *:[v2i64] }:$vB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULHUD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // vA GIR_RootToRootCopy, /*OpIdx*/3, // vB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3331, GIR_EraseRootFromParent_Done, // Label 723: @20450 GIM_Try, /*On fail goto*//*Label 724*/ GIMT_Encode4(20525), // Rule ID 3496 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi4ger8), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10050:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI4GER8:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI4GER8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3496, GIR_EraseRootFromParent_Done, // Label 724: @20525 GIM_Try, /*On fail goto*//*Label 725*/ GIMT_Encode4(20600), // Rule ID 3498 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi8ger4), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10052:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI8GER4:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI8GER4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3498, GIR_EraseRootFromParent_Done, // Label 725: @20600 GIM_Try, /*On fail goto*//*Label 726*/ GIMT_Encode4(20675), // Rule ID 3500 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2s), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10048:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2S:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2S), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3500, GIR_EraseRootFromParent_Done, // Label 726: @20675 GIM_Try, /*On fail goto*//*Label 727*/ GIMT_Encode4(20750), // Rule ID 3502 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi4ger8), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10050:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI4GER8W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI4GER8W), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3502, GIR_EraseRootFromParent_Done, // Label 727: @20750 GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(20825), // Rule ID 3504 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi8ger4), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10052:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI8GER4W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI8GER4W), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3504, GIR_EraseRootFromParent_Done, // Label 728: @20825 GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(20900), // Rule ID 3506 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2s), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10048:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2SW:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2SW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3506, GIR_EraseRootFromParent_Done, // Label 729: @20900 GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(20975), // Rule ID 3508 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10031:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3508, GIR_EraseRootFromParent_Done, // Label 730: @20975 GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(21050), // Rule ID 3513 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10031:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2W), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3513, GIR_EraseRootFromParent_Done, // Label 731: @21050 GIM_Try, /*On fail goto*//*Label 732*/ GIMT_Encode4(21125), // Rule ID 3518 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32ger), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10036:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GER:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GER), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3518, GIR_EraseRootFromParent_Done, // Label 732: @21125 GIM_Try, /*On fail goto*//*Label 733*/ GIMT_Encode4(21181), // Rule ID 3523 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64ger), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v256s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10041:{ *:[iPTR] }, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GER:{ *:[v512i1] } ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GER), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // XA GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3523, GIR_EraseRootFromParent_Done, // Label 733: @21181 GIM_Try, /*On fail goto*//*Label 734*/ GIMT_Encode4(21256), // Rule ID 3528 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10026:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3528, GIR_EraseRootFromParent_Done, // Label 734: @21256 GIM_Try, /*On fail goto*//*Label 735*/ GIMT_Encode4(21331), // Rule ID 3533 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10046:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3533, GIR_EraseRootFromParent_Done, // Label 735: @21331 GIM_Try, /*On fail goto*//*Label 736*/ GIMT_Encode4(21406), // Rule ID 3536 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32ger), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10036:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERW:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3536, GIR_EraseRootFromParent_Done, // Label 736: @21406 GIM_Try, /*On fail goto*//*Label 737*/ GIMT_Encode4(21462), // Rule ID 3541 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64ger), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v256s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10041:{ *:[iPTR] }, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERW:{ *:[v512i1] } ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // XA GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3541, GIR_EraseRootFromParent_Done, // Label 737: @21462 GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(21537), // Rule ID 3546 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10026:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2W), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3546, GIR_EraseRootFromParent_Done, // Label 738: @21537 GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(21612), // Rule ID 3551 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10046:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2W), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3551, GIR_EraseRootFromParent_Done, // Label 739: @21612 GIM_Reject, // Label 547: @21613 GIM_Try, /*On fail goto*//*Label 740*/ GIMT_Encode4(28049), GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(21679), // Rule ID 1007 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fmaf128_round_to_odd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckIsSafeToFold, /*NumInsns*/1, // (intrinsic_wo_chain:{ *:[f128] } 9954:{ *:[iPTR] }, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, (fneg:{ *:[f128] } f128:{ *:[f128] }:$RSTi)) => (XSMSUBQPO:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMSUBQPO), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RSTi GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1007, GIR_EraseRootFromParent_Done, // Label 741: @21679 GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(21732), // Rule ID 2159 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxinsertw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 10198:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$A, v2i64:{ *:[v2i64] }:$B, (imm:{ *:[i32] }):$IMM) => (XXINSERTW:{ *:[v4i32] } ?:{ *:[v4i32] }:$A, ?:{ *:[v2i64] }:$B, (imm:{ *:[i32] }):$IMM) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXINSERTW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootToRootCopy, /*OpIdx*/3, // B GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // IMM GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2159, GIR_EraseRootFromParent_Done, // Label 742: @21732 GIM_Try, /*On fail goto*//*Label 743*/ GIMT_Encode4(21774), // Rule ID 1006 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fmaf128_round_to_odd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[f128] } 9954:{ *:[iPTR] }, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, f128:{ *:[f128] }:$RSTi) => (XSMADDQPO:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMADDQPO), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] GIR_RootToRootCopy, /*OpIdx*/4, // RSTi GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1006, GIR_EraseRootFromParent_Done, // Label 743: @21774 GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(21816), // Rule ID 1740 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fmsub), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 9955:{ *:[iPTR] }, f64:{ *:[f64] }:$A, f64:{ *:[f64] }:$B, f64:{ *:[f64] }:$C) => (XSMSUBMDP:{ *:[f64] } ?:{ *:[f64] }:$A, ?:{ *:[f64] }:$B, ?:{ *:[f64] }:$C) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMSUBMDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootToRootCopy, /*OpIdx*/3, // B GIR_RootToRootCopy, /*OpIdx*/4, // C GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1740, GIR_EraseRootFromParent_Done, // Label 744: @21816 GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(21858), // Rule ID 1741 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnmadd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 9959:{ *:[iPTR] }, f64:{ *:[f64] }:$A, f64:{ *:[f64] }:$B, f64:{ *:[f64] }:$C) => (XSNMADDMDP:{ *:[f64] } ?:{ *:[f64] }:$A, ?:{ *:[f64] }:$B, ?:{ *:[f64] }:$C) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMADDMDP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootToRootCopy, /*OpIdx*/3, // B GIR_RootToRootCopy, /*OpIdx*/4, // C GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1741, GIR_EraseRootFromParent_Done, // Label 745: @21858 GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(21900), // Rule ID 1927 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fmsubs), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), // (intrinsic_wo_chain:{ *:[f32] } 9956:{ *:[iPTR] }, f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$B, f32:{ *:[f32] }:$C) => (XSMSUBMSP:{ *:[f32] } ?:{ *:[f32] }:$A, ?:{ *:[f32] }:$B, ?:{ *:[f32] }:$C) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMSUBMSP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootToRootCopy, /*OpIdx*/3, // B GIR_RootToRootCopy, /*OpIdx*/4, // C GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1927, GIR_EraseRootFromParent_Done, // Label 746: @21900 GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(21942), // Rule ID 1928 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnmadds), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), // (intrinsic_wo_chain:{ *:[f32] } 9960:{ *:[iPTR] }, f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$B, f32:{ *:[f32] }:$C) => (XSNMADDMSP:{ *:[f32] } ?:{ *:[f32] }:$A, ?:{ *:[f32] }:$B, ?:{ *:[f32] }:$C) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMADDMSP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootToRootCopy, /*OpIdx*/3, // B GIR_RootToRootCopy, /*OpIdx*/4, // C GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1928, GIR_EraseRootFromParent_Done, // Label 747: @21942 GIM_Try, /*On fail goto*//*Label 748*/ GIMT_Encode4(21984), // Rule ID 508 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Crypto), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vshasigmaw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // MIs[0] ST GIM_CheckIsImm, /*MI*/0, /*Op*/3, // MIs[0] SIX GIM_CheckIsImm, /*MI*/0, /*Op*/4, // (intrinsic_wo_chain:{ *:[v4i32] } 9591:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, (timm:{ *:[i32] }):$ST, (timm:{ *:[i32] }):$SIX) => (VSHASIGMAW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, (timm:{ *:[i32] }):$ST, (timm:{ *:[i32] }):$SIX) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSHASIGMAW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // ST GIR_RootToRootCopy, /*OpIdx*/4, // SIX GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 508, GIR_EraseRootFromParent_Done, // Label 748: @21984 GIM_Try, /*On fail goto*//*Label 749*/ GIMT_Encode4(22026), // Rule ID 509 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Crypto), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vshasigmad), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // MIs[0] ST GIM_CheckIsImm, /*MI*/0, /*Op*/3, // MIs[0] SIX GIM_CheckIsImm, /*MI*/0, /*Op*/4, // (intrinsic_wo_chain:{ *:[v2i64] } 9590:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, (timm:{ *:[i32] }):$ST, (timm:{ *:[i32] }):$SIX) => (VSHASIGMAD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, (timm:{ *:[i32] }):$ST, (timm:{ *:[i32] }):$SIX) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSHASIGMAD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // ST GIR_RootToRootCopy, /*OpIdx*/4, // SIX GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 509, GIR_EraseRootFromParent_Done, // Label 749: @22026 GIM_Try, /*On fail goto*//*Label 750*/ GIMT_Encode4(22068), // Rule ID 1054 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsldbi), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // MIs[0] SD GIM_CheckIsImm, /*MI*/0, /*Op*/4, // (intrinsic_wo_chain:{ *:[v16i8] } 9839:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VRA, v16i8:{ *:[v16i8] }:$VRB, (timm:{ *:[i32] }):$SD) => (VSLDBI:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VRA, v16i8:{ *:[v16i8] }:$VRB, (timm:{ *:[i32] }):$SD) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSLDBI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VRT] GIR_RootToRootCopy, /*OpIdx*/2, // VRA GIR_RootToRootCopy, /*OpIdx*/3, // VRB GIR_RootToRootCopy, /*OpIdx*/4, // SD GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1054, GIR_EraseRootFromParent_Done, // Label 750: @22068 GIM_Try, /*On fail goto*//*Label 751*/ GIMT_Encode4(22110), // Rule ID 1055 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsrdbi), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // MIs[0] SD GIM_CheckIsImm, /*MI*/0, /*Op*/4, // (intrinsic_wo_chain:{ *:[v16i8] } 9849:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VRA, v16i8:{ *:[v16i8] }:$VRB, (timm:{ *:[i32] }):$SD) => (VSRDBI:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VRA, v16i8:{ *:[v16i8] }:$VRB, (timm:{ *:[i32] }):$SD) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRDBI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VRT] GIR_RootToRootCopy, /*OpIdx*/2, // VRA GIR_RootToRootCopy, /*OpIdx*/3, // VRB GIR_RootToRootCopy, /*OpIdx*/4, // SD GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1055, GIR_EraseRootFromParent_Done, // Label 751: @22110 GIM_Try, /*On fail goto*//*Label 752*/ GIMT_Encode4(22152), // Rule ID 1060 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // MIs[0] VA GIM_CheckIsImm, /*MI*/0, /*Op*/4, // (intrinsic_wo_chain:{ *:[v4i32] } 9747:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VB, (timm:{ *:[i32] }):$VA) => (VINSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VDi, (timm:{ *:[i32] }):$VA, i32:{ *:[i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VDi GIR_RootToRootCopy, /*OpIdx*/4, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1060, GIR_EraseRootFromParent_Done, // Label 752: @22152 GIM_Try, /*On fail goto*//*Label 753*/ GIMT_Encode4(22194), // Rule ID 1061 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // MIs[0] VA GIM_CheckIsImm, /*MI*/0, /*Op*/4, // (intrinsic_wo_chain:{ *:[v2i64] } 9740:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VDi, i64:{ *:[i64] }:$VB, (timm:{ *:[i32] }):$VA) => (VINSD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VDi, (timm:{ *:[i32] }):$VA, i64:{ *:[i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VDi GIR_RootToRootCopy, /*OpIdx*/4, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1061, GIR_EraseRootFromParent_Done, // Label 753: @22194 GIM_Try, /*On fail goto*//*Label 754*/ GIMT_Encode4(22239), // Rule ID 1439 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_bcdadd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // MIs[0] PS GIM_CheckIsImm, /*MI*/0, /*Op*/4, // (intrinsic_wo_chain:{ *:[v16i8] } 9894:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB, (timm:{ *:[i32] }):$PS) => (BCDADD_rec:{ *:[v16i8] }:{ *:[i32] } ?:{ *:[v16i8] }:$vA, ?:{ *:[v16i8] }:$vB, ?:{ *:[i32] }:$PS) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::BCDADD_rec), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // vA GIR_RootToRootCopy, /*OpIdx*/3, // vB GIR_RootToRootCopy, /*OpIdx*/4, // PS GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CR6*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1439, GIR_EraseRootFromParent_Done, // Label 754: @22239 GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(22284), // Rule ID 1440 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_bcdsub), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // MIs[0] PS GIM_CheckIsImm, /*MI*/0, /*Op*/4, // (intrinsic_wo_chain:{ *:[v16i8] } 9896:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB, (timm:{ *:[i32] }):$PS) => (BCDSUB_rec:{ *:[v16i8] }:{ *:[i32] } ?:{ *:[v16i8] }:$vA, ?:{ *:[v16i8] }:$vB, ?:{ *:[i32] }:$PS) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::BCDSUB_rec), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // vA GIR_RootToRootCopy, /*OpIdx*/3, // vB GIR_RootToRootCopy, /*OpIdx*/4, // PS GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CR6*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1440, GIR_EraseRootFromParent_Done, // Label 755: @22284 GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(22338), // Rule ID 1555 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_In64BitMode_IsISA3_0), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_maddhd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (intrinsic_wo_chain:{ *:[i64] } 9982:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b, g8rc:{ *:[i64] }:$c) => (MADDHD:{ *:[i64] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b, ?:{ *:[i64] }:$c) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MADDHD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // a GIR_RootToRootCopy, /*OpIdx*/3, // b GIR_RootToRootCopy, /*OpIdx*/4, // c GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1555, GIR_EraseRootFromParent_Done, // Label 756: @22338 GIM_Try, /*On fail goto*//*Label 757*/ GIMT_Encode4(22392), // Rule ID 1556 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_In64BitMode_IsISA3_0), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_maddhdu), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (intrinsic_wo_chain:{ *:[i64] } 9983:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b, g8rc:{ *:[i64] }:$c) => (MADDHDU:{ *:[i64] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b, ?:{ *:[i64] }:$c) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MADDHDU), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // a GIR_RootToRootCopy, /*OpIdx*/3, // b GIR_RootToRootCopy, /*OpIdx*/4, // c GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1556, GIR_EraseRootFromParent_Done, // Label 757: @22392 GIM_Try, /*On fail goto*//*Label 758*/ GIMT_Encode4(22446), // Rule ID 1557 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_In64BitMode_IsISA3_0), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_maddld), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), // (intrinsic_wo_chain:{ *:[i64] } 9984:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b, g8rc:{ *:[i64] }:$c) => (MADDLD8:{ *:[i64] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b, ?:{ *:[i64] }:$c) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MADDLD8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // a GIR_RootToRootCopy, /*OpIdx*/3, // b GIR_RootToRootCopy, /*OpIdx*/4, // c GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1557, GIR_EraseRootFromParent_Done, // Label 758: @22446 GIM_Try, /*On fail goto*//*Label 759*/ GIMT_Encode4(22497), // Rule ID 4810 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fsel), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 9966:{ *:[iPTR] }, f8rc:{ *:[f64] }:$FRA, f8rc:{ *:[f64] }:$FRC, f8rc:{ *:[f64] }:$FRB) => (FSELD:{ *:[f64] } ?:{ *:[f64] }:$FRA, ?:{ *:[f64] }:$FRC, ?:{ *:[f64] }:$FRB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FSELD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] GIR_RootToRootCopy, /*OpIdx*/2, // FRA GIR_RootToRootCopy, /*OpIdx*/3, // FRC GIR_RootToRootCopy, /*OpIdx*/4, // FRB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 4810, GIR_EraseRootFromParent_Done, // Label 759: @22497 GIM_Try, /*On fail goto*//*Label 760*/ GIMT_Encode4(22539), // Rule ID 296 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmladduhm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9774:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v8i16:{ *:[v8i16] }:$RC) => (VMLADDUHM:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v8i16:{ *:[v8i16] }:$RC) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMLADDUHM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootToRootCopy, /*OpIdx*/4, // RC GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 296, GIR_EraseRootFromParent_Done, // Label 760: @22539 GIM_Try, /*On fail goto*//*Label 761*/ GIMT_Encode4(22581), // Rule ID 297 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vperm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9805:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, v16i8:{ *:[v16i8] }:$RC) => (VPERM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, v16i8:{ *:[v16i8] }:$RC) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPERM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootToRootCopy, /*OpIdx*/4, // RC GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 297, GIR_EraseRootFromParent_Done, // Label 761: @22581 GIM_Try, /*On fail goto*//*Label 762*/ GIMT_Encode4(22623), // Rule ID 298 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsel), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9836:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, v4i32:{ *:[v4i32] }:$RC) => (VSEL:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, v4i32:{ *:[v4i32] }:$RC) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSEL), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootToRootCopy, /*OpIdx*/4, // RC GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 298, GIR_EraseRootFromParent_Done, // Label 762: @22623 GIM_Try, /*On fail goto*//*Label 763*/ GIMT_Encode4(22665), // Rule ID 349 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmsummbm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9776:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, v4i32:{ *:[v4i32] }:$RC) => (VMSUMMBM:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, v4i32:{ *:[v4i32] }:$RC) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMSUMMBM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootToRootCopy, /*OpIdx*/4, // RC GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 349, GIR_EraseRootFromParent_Done, // Label 763: @22665 GIM_Try, /*On fail goto*//*Label 764*/ GIMT_Encode4(22707), // Rule ID 350 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmsumshm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9777:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v4i32:{ *:[v4i32] }:$RC) => (VMSUMSHM:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v4i32:{ *:[v4i32] }:$RC) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMSUMSHM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootToRootCopy, /*OpIdx*/4, // RC GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 350, GIR_EraseRootFromParent_Done, // Label 764: @22707 GIM_Try, /*On fail goto*//*Label 765*/ GIMT_Encode4(22749), // Rule ID 351 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmsumubm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9779:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, v4i32:{ *:[v4i32] }:$RC) => (VMSUMUBM:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, v4i32:{ *:[v4i32] }:$RC) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMSUMUBM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootToRootCopy, /*OpIdx*/4, // RC GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 351, GIR_EraseRootFromParent_Done, // Label 765: @22749 GIM_Try, /*On fail goto*//*Label 766*/ GIMT_Encode4(22791), // Rule ID 352 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmsumuhm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9781:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v4i32:{ *:[v4i32] }:$RC) => (VMSUMUHM:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v4i32:{ *:[v4i32] }:$RC) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMSUMUHM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootToRootCopy, /*OpIdx*/4, // RC GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 352, GIR_EraseRootFromParent_Done, // Label 766: @22791 GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(22833), // Rule ID 471 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddeuqm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v1i128] } 9623:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC) => (VADDEUQM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDEUQM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootToRootCopy, /*OpIdx*/4, // RC GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 471, GIR_EraseRootFromParent_Done, // Label 767: @22833 GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(22875), // Rule ID 473 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddecuq), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v1i128] } 9622:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC) => (VADDECUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDECUQ), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootToRootCopy, /*OpIdx*/4, // RC GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 473, GIR_EraseRootFromParent_Done, // Label 768: @22875 GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(22917), // Rule ID 476 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubeuqm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v1i128] } 9865:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC) => (VSUBEUQM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBEUQM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootToRootCopy, /*OpIdx*/4, // RC GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 476, GIR_EraseRootFromParent_Done, // Label 769: @22917 GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(22959), // Rule ID 478 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubecuq), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v1i128] } 9864:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC) => (VSUBECUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBECUQ), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootToRootCopy, /*OpIdx*/4, // RC GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 478, GIR_EraseRootFromParent_Done, // Label 770: @22959 GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(23001), // Rule ID 515 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmsumudm), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v1i128] } 9780:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, v1i128:{ *:[v1i128] }:$RC) => (VMSUMUDM:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, v1i128:{ *:[v1i128] }:$RC) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMSUMUDM), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootToRootCopy, /*OpIdx*/4, // RC GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 515, GIR_EraseRootFromParent_Done, // Label 771: @23001 GIM_Try, /*On fail goto*//*Label 772*/ GIMT_Encode4(23043), // Rule ID 548 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrlwmi), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9833:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB, v4i32:{ *:[v4i32] }:$VDi) => (VRLWMI:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB, v4i32:{ *:[v4i32] }:$VDi) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLWMI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootToRootCopy, /*OpIdx*/4, // VDi GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 548, GIR_EraseRootFromParent_Done, // Label 772: @23043 GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(23085), // Rule ID 550 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrldmi), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9827:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB, v2i64:{ *:[v2i64] }:$VDi) => (VRLDMI:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB, v2i64:{ *:[v2i64] }:$VDi) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLDMI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootToRootCopy, /*OpIdx*/4, // VDi GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 550, GIR_EraseRootFromParent_Done, // Label 773: @23085 GIM_Try, /*On fail goto*//*Label 774*/ GIMT_Encode4(23127), // Rule ID 1062 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsbvlx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9738:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VINSBVLX:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSBVLX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VDi GIR_RootToRootCopy, /*OpIdx*/3, // VA GIR_RootToRootCopy, /*OpIdx*/4, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1062, GIR_EraseRootFromParent_Done, // Label 774: @23127 GIM_Try, /*On fail goto*//*Label 775*/ GIMT_Encode4(23169), // Rule ID 1063 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsbvrx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9739:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VINSBVRX:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, v16i8:{ *:[v16i8] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSBVRX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VDi GIR_RootToRootCopy, /*OpIdx*/3, // VA GIR_RootToRootCopy, /*OpIdx*/4, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1063, GIR_EraseRootFromParent_Done, // Label 775: @23169 GIM_Try, /*On fail goto*//*Label 776*/ GIMT_Encode4(23211), // Rule ID 1064 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinshvlx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9745:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VINSHVLX:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSHVLX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VDi GIR_RootToRootCopy, /*OpIdx*/3, // VA GIR_RootToRootCopy, /*OpIdx*/4, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1064, GIR_EraseRootFromParent_Done, // Label 776: @23211 GIM_Try, /*On fail goto*//*Label 777*/ GIMT_Encode4(23253), // Rule ID 1065 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinshvrx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9746:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VINSHVRX:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, v8i16:{ *:[v8i16] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSHVRX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VDi GIR_RootToRootCopy, /*OpIdx*/3, // VA GIR_RootToRootCopy, /*OpIdx*/4, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1065, GIR_EraseRootFromParent_Done, // Label 777: @23253 GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(23295), // Rule ID 1066 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinswvlx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9750:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VINSWVLX:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSWVLX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VDi GIR_RootToRootCopy, /*OpIdx*/3, // VA GIR_RootToRootCopy, /*OpIdx*/4, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1066, GIR_EraseRootFromParent_Done, // Label 778: @23295 GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(23337), // Rule ID 1067 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinswvrx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9751:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VINSWVRX:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSWVRX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VDi GIR_RootToRootCopy, /*OpIdx*/3, // VA GIR_RootToRootCopy, /*OpIdx*/4, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1067, GIR_EraseRootFromParent_Done, // Label 779: @23337 GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(23379), // Rule ID 1068 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsblx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9736:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) => (VINSBLX:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSBLX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VDi GIR_RootToRootCopy, /*OpIdx*/3, // VA GIR_RootToRootCopy, /*OpIdx*/4, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1068, GIR_EraseRootFromParent_Done, // Label 780: @23379 GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(23421), // Rule ID 1069 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsbrx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9737:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) => (VINSBRX:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSBRX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VDi GIR_RootToRootCopy, /*OpIdx*/3, // VA GIR_RootToRootCopy, /*OpIdx*/4, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1069, GIR_EraseRootFromParent_Done, // Label 781: @23421 GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(23463), // Rule ID 1070 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinshlx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9743:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) => (VINSHLX:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSHLX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VDi GIR_RootToRootCopy, /*OpIdx*/3, // VA GIR_RootToRootCopy, /*OpIdx*/4, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1070, GIR_EraseRootFromParent_Done, // Label 782: @23463 GIM_Try, /*On fail goto*//*Label 783*/ GIMT_Encode4(23505), // Rule ID 1071 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinshrx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 9744:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) => (VINSHRX:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSHRX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VDi GIR_RootToRootCopy, /*OpIdx*/3, // VA GIR_RootToRootCopy, /*OpIdx*/4, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1071, GIR_EraseRootFromParent_Done, // Label 783: @23505 GIM_Try, /*On fail goto*//*Label 784*/ GIMT_Encode4(23547), // Rule ID 1072 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinswlx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9748:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) => (VINSWLX:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSWLX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VDi GIR_RootToRootCopy, /*OpIdx*/3, // VA GIR_RootToRootCopy, /*OpIdx*/4, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1072, GIR_EraseRootFromParent_Done, // Label 784: @23547 GIM_Try, /*On fail goto*//*Label 785*/ GIMT_Encode4(23589), // Rule ID 1073 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinswrx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 9749:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) => (VINSWRX:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSWRX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VDi GIR_RootToRootCopy, /*OpIdx*/3, // VA GIR_RootToRootCopy, /*OpIdx*/4, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1073, GIR_EraseRootFromParent_Done, // Label 785: @23589 GIM_Try, /*On fail goto*//*Label 786*/ GIMT_Encode4(23631), // Rule ID 1074 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsdlx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9741:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VDi, i64:{ *:[i64] }:$VA, i64:{ *:[i64] }:$VB) => (VINSDLX:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VDi, i64:{ *:[i64] }:$VA, i64:{ *:[i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSDLX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VDi GIR_RootToRootCopy, /*OpIdx*/3, // VA GIR_RootToRootCopy, /*OpIdx*/4, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1074, GIR_EraseRootFromParent_Done, // Label 786: @23631 GIM_Try, /*On fail goto*//*Label 787*/ GIMT_Encode4(23673), // Rule ID 1075 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsdrx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9742:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VDi, i64:{ *:[i64] }:$VA, i64:{ *:[i64] }:$VB) => (VINSDRX:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VDi, i64:{ *:[i64] }:$VA, i64:{ *:[i64] }:$VB) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSDRX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VDi GIR_RootToRootCopy, /*OpIdx*/3, // VA GIR_RootToRootCopy, /*OpIdx*/4, // VB GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1075, GIR_EraseRootFromParent_Done, // Label 787: @23673 GIM_Try, /*On fail goto*//*Label 788*/ GIMT_Encode4(23715), // Rule ID 1096 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextdubvlx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9717:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDUBVLX:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, i32:{ *:[i32] }:$RC) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDUBVLX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootToRootCopy, /*OpIdx*/4, // RC GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1096, GIR_EraseRootFromParent_Done, // Label 788: @23715 GIM_Try, /*On fail goto*//*Label 789*/ GIMT_Encode4(23757), // Rule ID 1097 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextdubvrx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9718:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDUBVRX:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, i32:{ *:[i32] }:$RC) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDUBVRX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootToRootCopy, /*OpIdx*/4, // RC GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1097, GIR_EraseRootFromParent_Done, // Label 789: @23757 GIM_Try, /*On fail goto*//*Label 790*/ GIMT_Encode4(23799), // Rule ID 1098 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextduhvlx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9719:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDUHVLX:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, i32:{ *:[i32] }:$RC) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDUHVLX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootToRootCopy, /*OpIdx*/4, // RC GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1098, GIR_EraseRootFromParent_Done, // Label 790: @23799 GIM_Try, /*On fail goto*//*Label 791*/ GIMT_Encode4(23841), // Rule ID 1099 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextduhvrx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9720:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDUHVRX:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, i32:{ *:[i32] }:$RC) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDUHVRX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootToRootCopy, /*OpIdx*/4, // RC GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1099, GIR_EraseRootFromParent_Done, // Label 791: @23841 GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(23883), // Rule ID 1100 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextduwvlx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9721:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDUWVLX:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, i32:{ *:[i32] }:$RC) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDUWVLX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootToRootCopy, /*OpIdx*/4, // RC GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1100, GIR_EraseRootFromParent_Done, // Label 792: @23883 GIM_Try, /*On fail goto*//*Label 793*/ GIMT_Encode4(23925), // Rule ID 1101 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextduwvrx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9722:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDUWVRX:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, i32:{ *:[i32] }:$RC) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDUWVRX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootToRootCopy, /*OpIdx*/4, // RC GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1101, GIR_EraseRootFromParent_Done, // Label 793: @23925 GIM_Try, /*On fail goto*//*Label 794*/ GIMT_Encode4(23967), // Rule ID 1102 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextddvlx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9715:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDDVLX:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, i32:{ *:[i32] }:$RC) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDDVLX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootToRootCopy, /*OpIdx*/4, // RC GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1102, GIR_EraseRootFromParent_Done, // Label 794: @23967 GIM_Try, /*On fail goto*//*Label 795*/ GIMT_Encode4(24009), // Rule ID 1103 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextddvrx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 9716:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDDVRX:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, i32:{ *:[i32] }:$RC) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDDVRX), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootToRootCopy, /*OpIdx*/4, // RC GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1103, GIR_EraseRootFromParent_Done, // Label 795: @24009 GIM_Try, /*On fail goto*//*Label 796*/ GIMT_Encode4(24051), // Rule ID 1141 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmsumcud), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v1i128] } 9775:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, v1i128:{ *:[v1i128] }:$RC) => (VMSUMCUD:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, v1i128:{ *:[v1i128] }:$RC) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMSUMCUD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // RA GIR_RootToRootCopy, /*OpIdx*/3, // RB GIR_RootToRootCopy, /*OpIdx*/4, // RC GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1141, GIR_EraseRootFromParent_Done, // Label 796: @24051 GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(24093), // Rule ID 1156 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrlqmi), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v1i128] } 9830:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB, v1i128:{ *:[v1i128] }:$VDi) => (VRLQMI:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB, v1i128:{ *:[v1i128] }:$VDi) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLQMI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] GIR_RootToRootCopy, /*OpIdx*/2, // VA GIR_RootToRootCopy, /*OpIdx*/3, // VB GIR_RootToRootCopy, /*OpIdx*/4, // VDi GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1156, GIR_EraseRootFromParent_Done, // Label 797: @24093 GIM_Try, /*On fail goto*//*Label 798*/ GIMT_Encode4(24132), // Rule ID 1271 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fmsub), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 9955:{ *:[iPTR] }, f64:{ *:[f64] }:$A, f64:{ *:[f64] }:$B, f64:{ *:[f64] }:$C) => (FMSUB:{ *:[f64] } ?:{ *:[f64] }:$A, ?:{ *:[f64] }:$B, ?:{ *:[f64] }:$C) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FMSUB), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootToRootCopy, /*OpIdx*/3, // B GIR_RootToRootCopy, /*OpIdx*/4, // C GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1271, GIR_EraseRootFromParent_Done, // Label 798: @24132 GIM_Try, /*On fail goto*//*Label 799*/ GIMT_Encode4(24171), // Rule ID 1272 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fmsubs), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), // (intrinsic_wo_chain:{ *:[f32] } 9956:{ *:[iPTR] }, f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$B, f32:{ *:[f32] }:$C) => (FMSUBS:{ *:[f32] } ?:{ *:[f32] }:$A, ?:{ *:[f32] }:$B, ?:{ *:[f32] }:$C) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FMSUBS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootToRootCopy, /*OpIdx*/3, // B GIR_RootToRootCopy, /*OpIdx*/4, // C GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1272, GIR_EraseRootFromParent_Done, // Label 799: @24171 GIM_Try, /*On fail goto*//*Label 800*/ GIMT_Encode4(24210), // Rule ID 1273 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnmadd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), // (intrinsic_wo_chain:{ *:[f64] } 9959:{ *:[iPTR] }, f64:{ *:[f64] }:$A, f64:{ *:[f64] }:$B, f64:{ *:[f64] }:$C) => (FNMADD:{ *:[f64] } ?:{ *:[f64] }:$A, ?:{ *:[f64] }:$B, ?:{ *:[f64] }:$C) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNMADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootToRootCopy, /*OpIdx*/3, // B GIR_RootToRootCopy, /*OpIdx*/4, // C GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1273, GIR_EraseRootFromParent_Done, // Label 800: @24210 GIM_Try, /*On fail goto*//*Label 801*/ GIMT_Encode4(24249), // Rule ID 1274 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnmadds), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), // (intrinsic_wo_chain:{ *:[f32] } 9960:{ *:[iPTR] }, f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$B, f32:{ *:[f32] }:$C) => (FNMADDS:{ *:[f32] } ?:{ *:[f32] }:$A, ?:{ *:[f32] }:$B, ?:{ *:[f32] }:$C) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNMADDS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootToRootCopy, /*OpIdx*/3, // B GIR_RootToRootCopy, /*OpIdx*/4, // C GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1274, GIR_EraseRootFromParent_Done, // Label 801: @24249 GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(24291), // Rule ID 1376 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaddfp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 9753:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$A, v4f32:{ *:[v4f32] }:$B, v4f32:{ *:[v4f32] }:$C) => (VMADDFP:{ *:[v4f32] } ?:{ *:[v4f32] }:$A, ?:{ *:[v4f32] }:$B, ?:{ *:[v4f32] }:$C) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMADDFP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootToRootCopy, /*OpIdx*/3, // B GIR_RootToRootCopy, /*OpIdx*/4, // C GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1376, GIR_EraseRootFromParent_Done, // Label 802: @24291 GIM_Try, /*On fail goto*//*Label 803*/ GIMT_Encode4(24333), // Rule ID 1377 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vnmsubfp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v4f32] } 9803:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$A, v4f32:{ *:[v4f32] }:$B, v4f32:{ *:[v4f32] }:$C) => (VNMSUBFP:{ *:[v4f32] } ?:{ *:[v4f32] }:$A, ?:{ *:[v4f32] }:$B, ?:{ *:[v4f32] }:$C) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNMSUBFP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootToRootCopy, /*OpIdx*/3, // B GIR_RootToRootCopy, /*OpIdx*/4, // C GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1377, GIR_EraseRootFromParent_Done, // Label 803: @24333 GIM_Try, /*On fail goto*//*Label 804*/ GIMT_Encode4(24432), // Rule ID 1572 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec_HasVSX_IsLittleEndian), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vpermxor), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9583:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$a, v16i8:{ *:[v16i8] }:$b, v16i8:{ *:[v16i8] }:$c) => (VPERMXOR:{ *:[v16i8] } ?:{ *:[v16i8] }:$a, ?:{ *:[v16i8] }:$b, (XXLNOR:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$c, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$c, VSRC:{ *:[i32] }))) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/4, // c GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // c GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXLNOR), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPERMXOR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // a GIR_RootToRootCopy, /*OpIdx*/3, // b GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1572, GIR_EraseRootFromParent_Done, // Label 804: @24432 GIM_Try, /*On fail goto*//*Label 805*/ GIMT_Encode4(24474), // Rule ID 1573 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec_HasVSX_IsBigEndian), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vpermxor), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9583:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$a, v16i8:{ *:[v16i8] }:$b, v16i8:{ *:[v16i8] }:$c) => (VPERMXOR:{ *:[v16i8] } ?:{ *:[v16i8] }:$a, ?:{ *:[v16i8] }:$b, ?:{ *:[v16i8] }:$c) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPERMXOR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // a GIR_RootToRootCopy, /*OpIdx*/3, // b GIR_RootToRootCopy, /*OpIdx*/4, // c GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1573, GIR_EraseRootFromParent_Done, // Label 805: @24474 GIM_Try, /*On fail goto*//*Label 806*/ GIMT_Encode4(24516), // Rule ID 1574 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec_HasVSX), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vpermxor_be), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 9584:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$a, v16i8:{ *:[v16i8] }:$b, v16i8:{ *:[v16i8] }:$c) => (VPERMXOR:{ *:[v16i8] } ?:{ *:[v16i8] }:$a, ?:{ *:[v16i8] }:$b, ?:{ *:[v16i8] }:$c) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPERMXOR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] GIR_RootToRootCopy, /*OpIdx*/2, // a GIR_RootToRootCopy, /*OpIdx*/3, // b GIR_RootToRootCopy, /*OpIdx*/4, // c GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1574, GIR_EraseRootFromParent_Done, // Label 806: @24516 GIM_Try, /*On fail goto*//*Label 807*/ GIMT_Encode4(24636), // Rule ID 3414 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxblendvb), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v16i8] } 10188:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$A, v16i8:{ *:[v16i8] }:$B, v16i8:{ *:[v16i8] }:$C) => (COPY_TO_REGCLASS:{ *:[v16i8] } (XXBLENDVB:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$A, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$B, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$C, VSRC:{ *:[i32] })), VSRC:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/4, // C GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // B GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // A GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXBLENDVB), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), // GIR_Coverage, 3414, GIR_EraseRootFromParent_Done, // Label 807: @24636 GIM_Try, /*On fail goto*//*Label 808*/ GIMT_Encode4(24756), // Rule ID 3415 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxblendvh), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v8i16] } 10190:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$A, v8i16:{ *:[v8i16] }:$B, v8i16:{ *:[v8i16] }:$C) => (COPY_TO_REGCLASS:{ *:[v8i16] } (XXBLENDVH:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v8i16] }:$A, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v8i16] }:$B, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v8i16] }:$C, VSRC:{ *:[i32] })), VSRC:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/4, // C GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // B GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // A GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXBLENDVH), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), // GIR_Coverage, 3415, GIR_EraseRootFromParent_Done, // Label 808: @24756 GIM_Try, /*On fail goto*//*Label 809*/ GIMT_Encode4(24798), // Rule ID 3416 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxblendvw), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v4i32] } 10191:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$A, v4i32:{ *:[v4i32] }:$B, v4i32:{ *:[v4i32] }:$C) => (XXBLENDVW:{ *:[v4i32] } ?:{ *:[v4i32] }:$A, ?:{ *:[v4i32] }:$B, ?:{ *:[v4i32] }:$C) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXBLENDVW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootToRootCopy, /*OpIdx*/3, // B GIR_RootToRootCopy, /*OpIdx*/4, // C GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3416, GIR_EraseRootFromParent_Done, // Label 809: @24798 GIM_Try, /*On fail goto*//*Label 810*/ GIMT_Encode4(24840), // Rule ID 3417 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxblendvd), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // (intrinsic_wo_chain:{ *:[v2i64] } 10189:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$A, v2i64:{ *:[v2i64] }:$B, v2i64:{ *:[v2i64] }:$C) => (XXBLENDVD:{ *:[v2i64] } ?:{ *:[v2i64] }:$A, ?:{ *:[v2i64] }:$B, ?:{ *:[v2i64] }:$C) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXBLENDVD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // A GIR_RootToRootCopy, /*OpIdx*/3, // B GIR_RootToRootCopy, /*OpIdx*/4, // C GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3417, GIR_EraseRootFromParent_Done, // Label 810: @24840 GIM_Try, /*On fail goto*//*Label 811*/ GIMT_Encode4(24920), // Rule ID 3497 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi4ger8pp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10051:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI4GER8PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI4GER8PP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3497, GIR_EraseRootFromParent_Done, // Label 811: @24920 GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(25000), // Rule ID 3499 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi8ger4pp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10053:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI8GER4PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI8GER4PP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3499, GIR_EraseRootFromParent_Done, // Label 812: @25000 GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(25080), // Rule ID 3501 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2spp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10049:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2SPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2SPP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3501, GIR_EraseRootFromParent_Done, // Label 813: @25080 GIM_Try, /*On fail goto*//*Label 814*/ GIMT_Encode4(25160), // Rule ID 3503 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi4ger8pp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10051:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI4GER8WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI4GER8WPP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3503, GIR_EraseRootFromParent_Done, // Label 814: @25160 GIM_Try, /*On fail goto*//*Label 815*/ GIMT_Encode4(25240), // Rule ID 3505 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi8ger4pp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10053:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI8GER4WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI8GER4WPP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3505, GIR_EraseRootFromParent_Done, // Label 815: @25240 GIM_Try, /*On fail goto*//*Label 816*/ GIMT_Encode4(25320), // Rule ID 3507 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2spp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10049:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2SWPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2SWPP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3507, GIR_EraseRootFromParent_Done, // Label 816: @25320 GIM_Try, /*On fail goto*//*Label 817*/ GIMT_Encode4(25400), // Rule ID 3509 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2pp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10035:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2PP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3509, GIR_EraseRootFromParent_Done, // Label 817: @25400 GIM_Try, /*On fail goto*//*Label 818*/ GIMT_Encode4(25480), // Rule ID 3510 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2pn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10034:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2PN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2PN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3510, GIR_EraseRootFromParent_Done, // Label 818: @25480 GIM_Try, /*On fail goto*//*Label 819*/ GIMT_Encode4(25560), // Rule ID 3511 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2np), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10033:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2NP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2NP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3511, GIR_EraseRootFromParent_Done, // Label 819: @25560 GIM_Try, /*On fail goto*//*Label 820*/ GIMT_Encode4(25640), // Rule ID 3512 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2nn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10032:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2NN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2NN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3512, GIR_EraseRootFromParent_Done, // Label 820: @25640 GIM_Try, /*On fail goto*//*Label 821*/ GIMT_Encode4(25720), // Rule ID 3514 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2pp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10035:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2WPP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3514, GIR_EraseRootFromParent_Done, // Label 821: @25720 GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(25800), // Rule ID 3515 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2pn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10034:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2WPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2WPN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3515, GIR_EraseRootFromParent_Done, // Label 822: @25800 GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(25880), // Rule ID 3516 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2np), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10033:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2WNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2WNP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3516, GIR_EraseRootFromParent_Done, // Label 823: @25880 GIM_Try, /*On fail goto*//*Label 824*/ GIMT_Encode4(25960), // Rule ID 3517 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2nn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10032:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2WNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2WNN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3517, GIR_EraseRootFromParent_Done, // Label 824: @25960 GIM_Try, /*On fail goto*//*Label 825*/ GIMT_Encode4(26040), // Rule ID 3519 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gerpp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10040:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERPP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3519, GIR_EraseRootFromParent_Done, // Label 825: @26040 GIM_Try, /*On fail goto*//*Label 826*/ GIMT_Encode4(26120), // Rule ID 3520 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gerpn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10039:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERPN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3520, GIR_EraseRootFromParent_Done, // Label 826: @26120 GIM_Try, /*On fail goto*//*Label 827*/ GIMT_Encode4(26200), // Rule ID 3521 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gernp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10038:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERNP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3521, GIR_EraseRootFromParent_Done, // Label 827: @26200 GIM_Try, /*On fail goto*//*Label 828*/ GIMT_Encode4(26280), // Rule ID 3522 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gernn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10037:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERNN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3522, GIR_EraseRootFromParent_Done, // Label 828: @26280 GIM_Try, /*On fail goto*//*Label 829*/ GIMT_Encode4(26341), // Rule ID 3524 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gerpp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10045:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERPP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_RootToRootCopy, /*OpIdx*/3, // XA GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3524, GIR_EraseRootFromParent_Done, // Label 829: @26341 GIM_Try, /*On fail goto*//*Label 830*/ GIMT_Encode4(26402), // Rule ID 3525 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gerpn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10044:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERPN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_RootToRootCopy, /*OpIdx*/3, // XA GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3525, GIR_EraseRootFromParent_Done, // Label 830: @26402 GIM_Try, /*On fail goto*//*Label 831*/ GIMT_Encode4(26463), // Rule ID 3526 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gernp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10043:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERNP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_RootToRootCopy, /*OpIdx*/3, // XA GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3526, GIR_EraseRootFromParent_Done, // Label 831: @26463 GIM_Try, /*On fail goto*//*Label 832*/ GIMT_Encode4(26524), // Rule ID 3527 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gernn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10042:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERNN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_RootToRootCopy, /*OpIdx*/3, // XA GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3527, GIR_EraseRootFromParent_Done, // Label 832: @26524 GIM_Try, /*On fail goto*//*Label 833*/ GIMT_Encode4(26604), // Rule ID 3529 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2pp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10030:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2PP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3529, GIR_EraseRootFromParent_Done, // Label 833: @26604 GIM_Try, /*On fail goto*//*Label 834*/ GIMT_Encode4(26684), // Rule ID 3530 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2pn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10029:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2PN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2PN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3530, GIR_EraseRootFromParent_Done, // Label 834: @26684 GIM_Try, /*On fail goto*//*Label 835*/ GIMT_Encode4(26764), // Rule ID 3531 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2np), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10028:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2NP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2NP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3531, GIR_EraseRootFromParent_Done, // Label 835: @26764 GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(26844), // Rule ID 3532 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2nn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10027:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2NN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2NN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3532, GIR_EraseRootFromParent_Done, // Label 836: @26844 GIM_Try, /*On fail goto*//*Label 837*/ GIMT_Encode4(26924), // Rule ID 3534 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2pp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10047:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2PP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3534, GIR_EraseRootFromParent_Done, // Label 837: @26924 GIM_Try, /*On fail goto*//*Label 838*/ GIMT_Encode4(27004), // Rule ID 3535 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi8ger4spp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10054:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI8GER4SPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI8GER4SPP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3535, GIR_EraseRootFromParent_Done, // Label 838: @27004 GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(27084), // Rule ID 3537 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gerpp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10040:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERWPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERWPP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3537, GIR_EraseRootFromParent_Done, // Label 839: @27084 GIM_Try, /*On fail goto*//*Label 840*/ GIMT_Encode4(27164), // Rule ID 3538 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gerpn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10039:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERWPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERWPN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3538, GIR_EraseRootFromParent_Done, // Label 840: @27164 GIM_Try, /*On fail goto*//*Label 841*/ GIMT_Encode4(27244), // Rule ID 3539 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gernp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10038:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERWNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERWNP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3539, GIR_EraseRootFromParent_Done, // Label 841: @27244 GIM_Try, /*On fail goto*//*Label 842*/ GIMT_Encode4(27324), // Rule ID 3540 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gernn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10037:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERWNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERWNN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3540, GIR_EraseRootFromParent_Done, // Label 842: @27324 GIM_Try, /*On fail goto*//*Label 843*/ GIMT_Encode4(27385), // Rule ID 3542 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gerpp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10045:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERWPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERWPP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_RootToRootCopy, /*OpIdx*/3, // XA GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3542, GIR_EraseRootFromParent_Done, // Label 843: @27385 GIM_Try, /*On fail goto*//*Label 844*/ GIMT_Encode4(27446), // Rule ID 3543 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gerpn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10044:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERWPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERWPN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_RootToRootCopy, /*OpIdx*/3, // XA GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3543, GIR_EraseRootFromParent_Done, // Label 844: @27446 GIM_Try, /*On fail goto*//*Label 845*/ GIMT_Encode4(27507), // Rule ID 3544 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gernp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10043:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERNP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_RootToRootCopy, /*OpIdx*/3, // XA GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3544, GIR_EraseRootFromParent_Done, // Label 845: @27507 GIM_Try, /*On fail goto*//*Label 846*/ GIMT_Encode4(27568), // Rule ID 3545 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gernn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10042:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERWNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERWNN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_RootToRootCopy, /*OpIdx*/3, // XA GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3545, GIR_EraseRootFromParent_Done, // Label 846: @27568 GIM_Try, /*On fail goto*//*Label 847*/ GIMT_Encode4(27648), // Rule ID 3547 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2pp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10030:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2WPP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3547, GIR_EraseRootFromParent_Done, // Label 847: @27648 GIM_Try, /*On fail goto*//*Label 848*/ GIMT_Encode4(27728), // Rule ID 3548 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2pn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10029:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2WPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2WPN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3548, GIR_EraseRootFromParent_Done, // Label 848: @27728 GIM_Try, /*On fail goto*//*Label 849*/ GIMT_Encode4(27808), // Rule ID 3549 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2np), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10028:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2WNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2WNP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3549, GIR_EraseRootFromParent_Done, // Label 849: @27808 GIM_Try, /*On fail goto*//*Label 850*/ GIMT_Encode4(27888), // Rule ID 3550 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2nn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10027:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2WNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2WNN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3550, GIR_EraseRootFromParent_Done, // Label 850: @27888 GIM_Try, /*On fail goto*//*Label 851*/ GIMT_Encode4(27968), // Rule ID 3552 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2pp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10047:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2WPP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3552, GIR_EraseRootFromParent_Done, // Label 851: @27968 GIM_Try, /*On fail goto*//*Label 852*/ GIMT_Encode4(28048), // Rule ID 3553 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi8ger4spp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), // (intrinsic_wo_chain:{ *:[v512i1] } 10054:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI8GER4WSPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI8GER4WSPP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3553, GIR_EraseRootFromParent_Done, // Label 852: @28048 GIM_Reject, // Label 740: @28049 GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(28646), GIM_CheckNumOperands, /*MI*/0, /*Expected*/6, GIM_Try, /*On fail goto*//*Label 854*/ GIMT_Encode4(28170), // Rule ID 3565 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32ger), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (intrinsic_wo_chain:{ *:[v512i1] } 10007:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GER:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GER), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3565, GIR_EraseRootFromParent_Done, // Label 854: @28170 GIM_Try, /*On fail goto*//*Label 855*/ GIMT_Encode4(28264), // Rule ID 3570 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64ger), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v256s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (intrinsic_wo_chain:{ *:[v512i1] } 10012:{ *:[iPTR] }, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GER:{ *:[v512i1] } ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GER), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // XA GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3570, GIR_EraseRootFromParent_Done, // Label 855: @28264 GIM_Try, /*On fail goto*//*Label 856*/ GIMT_Encode4(28377), // Rule ID 3594 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32ger), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (intrinsic_wo_chain:{ *:[v512i1] } 10007:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERW:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3594, GIR_EraseRootFromParent_Done, // Label 856: @28377 GIM_Try, /*On fail goto*//*Label 857*/ GIMT_Encode4(28471), // Rule ID 3599 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64ger), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v256s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (intrinsic_wo_chain:{ *:[v512i1] } 10012:{ *:[iPTR] }, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERW:{ *:[v512i1] } ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // XA GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3599, GIR_EraseRootFromParent_Done, // Label 857: @28471 GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(28518), // Rule ID 1111 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxeval), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // MIs[0] IMM GIM_CheckIsImm, /*MI*/0, /*Op*/5, // (intrinsic_wo_chain:{ *:[v2i64] } 10192:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$XA, v2i64:{ *:[v2i64] }:$XB, v2i64:{ *:[v2i64] }:$XC, (timm:{ *:[i32] }):$IMM) => (XXEVAL:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$XA, v2i64:{ *:[v2i64] }:$XB, v2i64:{ *:[v2i64] }:$XC, (timm:{ *:[i32] }):$IMM) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] GIR_RootToRootCopy, /*OpIdx*/2, // XA GIR_RootToRootCopy, /*OpIdx*/3, // XB GIR_RootToRootCopy, /*OpIdx*/4, // XC GIR_RootToRootCopy, /*OpIdx*/5, // IMM GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 1111, GIR_EraseRootFromParent_Done, // Label 858: @28518 GIM_Try, /*On fail goto*//*Label 859*/ GIMT_Encode4(28645), // Rule ID 3413 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxpermx), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), // MIs[0] D GIM_CheckIsImm, /*MI*/0, /*Op*/5, // (intrinsic_wo_chain:{ *:[v16i8] } 10200:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$A, v16i8:{ *:[v16i8] }:$B, v16i8:{ *:[v16i8] }:$C, (timm:{ *:[i32] }):$D) => (COPY_TO_REGCLASS:{ *:[v16i8] } (XXPERMX:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$A, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$B, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$C, VSRC:{ *:[i32] }), ?:{ *:[i32] }:$D), VSRC:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/4, // C GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // B GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // A GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXPERMX), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // D GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), // GIR_Coverage, 3413, GIR_EraseRootFromParent_Done, // Label 859: @28645 GIM_Reject, // Label 853: @28646 GIM_Try, /*On fail goto*//*Label 860*/ GIMT_Encode4(31963), GIM_CheckNumOperands, /*MI*/0, /*Expected*/7, GIM_Try, /*On fail goto*//*Label 861*/ GIMT_Encode4(28785), // Rule ID 3554 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi4ger8), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10021:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK) => (PMXVI4GER8:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI4GER8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3554, GIR_EraseRootFromParent_Done, // Label 861: @28785 GIM_Try, /*On fail goto*//*Label 862*/ GIMT_Encode4(28916), // Rule ID 3556 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi8ger4), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10023:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK) => (PMXVI8GER4:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI8GER4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3556, GIR_EraseRootFromParent_Done, // Label 862: @28916 GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(29047), // Rule ID 3558 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi16ger2s), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10019:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI16GER2S:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI16GER2S), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3558, GIR_EraseRootFromParent_Done, // Label 863: @29047 GIM_Try, /*On fail goto*//*Label 864*/ GIMT_Encode4(29178), // Rule ID 3560 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10002:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3560, GIR_EraseRootFromParent_Done, // Label 864: @29178 GIM_Try, /*On fail goto*//*Label 865*/ GIMT_Encode4(29309), // Rule ID 3575 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 9997:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3575, GIR_EraseRootFromParent_Done, // Label 865: @29309 GIM_Try, /*On fail goto*//*Label 866*/ GIMT_Encode4(29440), // Rule ID 3580 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi16ger2), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10017:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI16GER2:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI16GER2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3580, GIR_EraseRootFromParent_Done, // Label 866: @29440 GIM_Try, /*On fail goto*//*Label 867*/ GIMT_Encode4(29571), // Rule ID 3583 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi4ger8), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10021:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK) => (PMXVI4GER8W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI4GER8W), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3583, GIR_EraseRootFromParent_Done, // Label 867: @29571 GIM_Try, /*On fail goto*//*Label 868*/ GIMT_Encode4(29702), // Rule ID 3585 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi8ger4), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10023:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK) => (PMXVI8GER4W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI8GER4W), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3585, GIR_EraseRootFromParent_Done, // Label 868: @29702 GIM_Try, /*On fail goto*//*Label 869*/ GIMT_Encode4(29833), // Rule ID 3587 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi16ger2s), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10019:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI16GER2SW:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI16GER2SW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3587, GIR_EraseRootFromParent_Done, // Label 869: @29833 GIM_Try, /*On fail goto*//*Label 870*/ GIMT_Encode4(29964), // Rule ID 3589 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10002:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2W), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3589, GIR_EraseRootFromParent_Done, // Label 870: @29964 GIM_Try, /*On fail goto*//*Label 871*/ GIMT_Encode4(30095), // Rule ID 3604 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 9997:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2W), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3604, GIR_EraseRootFromParent_Done, // Label 871: @30095 GIM_Try, /*On fail goto*//*Label 872*/ GIMT_Encode4(30226), // Rule ID 3609 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi16ger2), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10017:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI16GER2W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI16GER2W), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3609, GIR_EraseRootFromParent_Done, // Label 872: @30226 GIM_Try, /*On fail goto*//*Label 873*/ GIMT_Encode4(30344), // Rule ID 3566 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gerpp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (intrinsic_wo_chain:{ *:[v512i1] } 10011:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERPP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3566, GIR_EraseRootFromParent_Done, // Label 873: @30344 GIM_Try, /*On fail goto*//*Label 874*/ GIMT_Encode4(30462), // Rule ID 3567 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gerpn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (intrinsic_wo_chain:{ *:[v512i1] } 10010:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERPN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3567, GIR_EraseRootFromParent_Done, // Label 874: @30462 GIM_Try, /*On fail goto*//*Label 875*/ GIMT_Encode4(30580), // Rule ID 3568 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gernp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (intrinsic_wo_chain:{ *:[v512i1] } 10009:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERNP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3568, GIR_EraseRootFromParent_Done, // Label 875: @30580 GIM_Try, /*On fail goto*//*Label 876*/ GIMT_Encode4(30698), // Rule ID 3569 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gernn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (intrinsic_wo_chain:{ *:[v512i1] } 10008:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERNN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3569, GIR_EraseRootFromParent_Done, // Label 876: @30698 GIM_Try, /*On fail goto*//*Label 877*/ GIMT_Encode4(30797), // Rule ID 3571 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gerpp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (intrinsic_wo_chain:{ *:[v512i1] } 10016:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERPP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_RootToRootCopy, /*OpIdx*/3, // XA GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3571, GIR_EraseRootFromParent_Done, // Label 877: @30797 GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(30896), // Rule ID 3572 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gerpn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (intrinsic_wo_chain:{ *:[v512i1] } 10015:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERPN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_RootToRootCopy, /*OpIdx*/3, // XA GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3572, GIR_EraseRootFromParent_Done, // Label 878: @30896 GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(30995), // Rule ID 3573 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gernp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (intrinsic_wo_chain:{ *:[v512i1] } 10014:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERNP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_RootToRootCopy, /*OpIdx*/3, // XA GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3573, GIR_EraseRootFromParent_Done, // Label 879: @30995 GIM_Try, /*On fail goto*//*Label 880*/ GIMT_Encode4(31094), // Rule ID 3574 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gernn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (intrinsic_wo_chain:{ *:[v512i1] } 10013:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERNN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_RootToRootCopy, /*OpIdx*/3, // XA GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3574, GIR_EraseRootFromParent_Done, // Label 880: @31094 GIM_Try, /*On fail goto*//*Label 881*/ GIMT_Encode4(31212), // Rule ID 3595 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gerpp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (intrinsic_wo_chain:{ *:[v512i1] } 10011:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERWPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERWPP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3595, GIR_EraseRootFromParent_Done, // Label 881: @31212 GIM_Try, /*On fail goto*//*Label 882*/ GIMT_Encode4(31330), // Rule ID 3596 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gerpn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (intrinsic_wo_chain:{ *:[v512i1] } 10010:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERWPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERWPN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3596, GIR_EraseRootFromParent_Done, // Label 882: @31330 GIM_Try, /*On fail goto*//*Label 883*/ GIMT_Encode4(31448), // Rule ID 3597 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gernp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (intrinsic_wo_chain:{ *:[v512i1] } 10009:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERWNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERWNP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3597, GIR_EraseRootFromParent_Done, // Label 883: @31448 GIM_Try, /*On fail goto*//*Label 884*/ GIMT_Encode4(31566), // Rule ID 3598 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gernn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (intrinsic_wo_chain:{ *:[v512i1] } 10008:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERWNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERWNN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3598, GIR_EraseRootFromParent_Done, // Label 884: @31566 GIM_Try, /*On fail goto*//*Label 885*/ GIMT_Encode4(31665), // Rule ID 3600 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gerpp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (intrinsic_wo_chain:{ *:[v512i1] } 10016:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERWPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERWPP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_RootToRootCopy, /*OpIdx*/3, // XA GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3600, GIR_EraseRootFromParent_Done, // Label 885: @31665 GIM_Try, /*On fail goto*//*Label 886*/ GIMT_Encode4(31764), // Rule ID 3601 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gerpn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (intrinsic_wo_chain:{ *:[v512i1] } 10015:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERWPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERWPN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_RootToRootCopy, /*OpIdx*/3, // XA GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3601, GIR_EraseRootFromParent_Done, // Label 886: @31764 GIM_Try, /*On fail goto*//*Label 887*/ GIMT_Encode4(31863), // Rule ID 3602 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gernp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (intrinsic_wo_chain:{ *:[v512i1] } 10014:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERWNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERWNP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_RootToRootCopy, /*OpIdx*/3, // XA GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3602, GIR_EraseRootFromParent_Done, // Label 887: @31863 GIM_Try, /*On fail goto*//*Label 888*/ GIMT_Encode4(31962), // Rule ID 3603 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gernn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (intrinsic_wo_chain:{ *:[v512i1] } 10013:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERWNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERWNN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_RootToRootCopy, /*OpIdx*/3, // XA GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3603, GIR_EraseRootFromParent_Done, // Label 888: @31962 GIM_Reject, // Label 860: @31963 GIM_Try, /*On fail goto*//*Label 889*/ GIMT_Encode4(35508), GIM_CheckNumOperands, /*MI*/0, /*Expected*/8, GIM_Try, /*On fail goto*//*Label 890*/ GIMT_Encode4(32107), // Rule ID 3555 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi4ger8pp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10022:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK) => (PMXVI4GER8PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI4GER8PP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3555, GIR_EraseRootFromParent_Done, // Label 890: @32107 GIM_Try, /*On fail goto*//*Label 891*/ GIMT_Encode4(32243), // Rule ID 3557 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi8ger4pp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10024:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK) => (PMXVI8GER4PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI8GER4PP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3557, GIR_EraseRootFromParent_Done, // Label 891: @32243 GIM_Try, /*On fail goto*//*Label 892*/ GIMT_Encode4(32379), // Rule ID 3559 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi16ger2spp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10020:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI16GER2SPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI16GER2SPP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3559, GIR_EraseRootFromParent_Done, // Label 892: @32379 GIM_Try, /*On fail goto*//*Label 893*/ GIMT_Encode4(32515), // Rule ID 3561 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2pp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10006:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2PP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3561, GIR_EraseRootFromParent_Done, // Label 893: @32515 GIM_Try, /*On fail goto*//*Label 894*/ GIMT_Encode4(32651), // Rule ID 3562 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2pn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10005:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2PN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2PN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3562, GIR_EraseRootFromParent_Done, // Label 894: @32651 GIM_Try, /*On fail goto*//*Label 895*/ GIMT_Encode4(32787), // Rule ID 3563 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2np), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10004:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2NP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2NP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3563, GIR_EraseRootFromParent_Done, // Label 895: @32787 GIM_Try, /*On fail goto*//*Label 896*/ GIMT_Encode4(32923), // Rule ID 3564 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2nn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10003:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2NN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2NN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3564, GIR_EraseRootFromParent_Done, // Label 896: @32923 GIM_Try, /*On fail goto*//*Label 897*/ GIMT_Encode4(33059), // Rule ID 3576 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2pp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10001:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2PP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3576, GIR_EraseRootFromParent_Done, // Label 897: @33059 GIM_Try, /*On fail goto*//*Label 898*/ GIMT_Encode4(33195), // Rule ID 3577 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2pn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10000:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2PN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2PN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3577, GIR_EraseRootFromParent_Done, // Label 898: @33195 GIM_Try, /*On fail goto*//*Label 899*/ GIMT_Encode4(33331), // Rule ID 3578 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2np), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 9999:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2NP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2NP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3578, GIR_EraseRootFromParent_Done, // Label 899: @33331 GIM_Try, /*On fail goto*//*Label 900*/ GIMT_Encode4(33467), // Rule ID 3579 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2nn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 9998:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2NN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2NN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3579, GIR_EraseRootFromParent_Done, // Label 900: @33467 GIM_Try, /*On fail goto*//*Label 901*/ GIMT_Encode4(33603), // Rule ID 3581 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi8ger4spp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10025:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI8GER4SPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI8GER4SPP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3581, GIR_EraseRootFromParent_Done, // Label 901: @33603 GIM_Try, /*On fail goto*//*Label 902*/ GIMT_Encode4(33739), // Rule ID 3582 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi16ger2pp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10018:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI16GER2PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI16GER2PP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3582, GIR_EraseRootFromParent_Done, // Label 902: @33739 GIM_Try, /*On fail goto*//*Label 903*/ GIMT_Encode4(33875), // Rule ID 3584 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi4ger8pp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10022:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK) => (PMXVI4GER8WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI4GER8WPP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3584, GIR_EraseRootFromParent_Done, // Label 903: @33875 GIM_Try, /*On fail goto*//*Label 904*/ GIMT_Encode4(34011), // Rule ID 3586 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi8ger4pp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10024:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK) => (PMXVI8GER4WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI8GER4WPP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3586, GIR_EraseRootFromParent_Done, // Label 904: @34011 GIM_Try, /*On fail goto*//*Label 905*/ GIMT_Encode4(34147), // Rule ID 3588 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi16ger2spp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10020:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI16GER2SWPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI16GER2SWPP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3588, GIR_EraseRootFromParent_Done, // Label 905: @34147 GIM_Try, /*On fail goto*//*Label 906*/ GIMT_Encode4(34283), // Rule ID 3590 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2pp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10006:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2WPP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3590, GIR_EraseRootFromParent_Done, // Label 906: @34283 GIM_Try, /*On fail goto*//*Label 907*/ GIMT_Encode4(34419), // Rule ID 3591 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2pn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10005:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2WPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2WPN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3591, GIR_EraseRootFromParent_Done, // Label 907: @34419 GIM_Try, /*On fail goto*//*Label 908*/ GIMT_Encode4(34555), // Rule ID 3592 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2np), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10004:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2WNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2WNP), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3592, GIR_EraseRootFromParent_Done, // Label 908: @34555 GIM_Try, /*On fail goto*//*Label 909*/ GIMT_Encode4(34691), // Rule ID 3593 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2nn), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10003:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2WNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2WNN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] GIR_RootToRootCopy, /*OpIdx*/2, // ATi GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 3593, GIR_EraseRootFromParent_Done, // Label 909: @34691 GIM_Try, /*On fail goto*//*Label 910*/ GIMT_Encode4(34827), // Rule ID 3605 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2pp), GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[1] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/3, // (intrinsic_wo_chain:{ *:[v512i1] } 10001:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1<TRUNCATED>#undef GIMT_Encode2#undef GIMT_Encode4#undef GIMT_Encode8#endif // ifdef GET_GLOBALISEL_IMPL#ifdef GET_GLOBALISEL_PREDICATES_DECL#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL#ifdef GET_GLOBALISEL_PREDICATES_INIT#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT
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