#ifdef GET_RISCVMaskedPseudosTable_DECL const RISCVMaskedPseudoInfo *getMaskedPseudoInfo(unsigned MaskedPseudo); const RISCVMaskedPseudoInfo *lookupMaskedIntrinsicByUnmasked(unsigned UnmaskedPseudo); #endif #ifdef GET_RISCVMaskedPseudosTable_IMPL constexpr RISCVMaskedPseudoInfo RISCVMaskedPseudosTable[] = { { PseudoTHVdotVMAQASU_VV_M1_MASK, PseudoTHVdotVMAQASU_VV_M1, 0x3 }, // 0 { PseudoTHVdotVMAQASU_VV_M2_MASK, PseudoTHVdotVMAQASU_VV_M2, 0x3 }, // 1 { PseudoTHVdotVMAQASU_VV_M4_MASK, PseudoTHVdotVMAQASU_VV_M4, 0x3 }, // 2 { PseudoTHVdotVMAQASU_VV_M8_MASK, PseudoTHVdotVMAQASU_VV_M8, 0x3 }, // 3 { PseudoTHVdotVMAQASU_VV_MF2_MASK, PseudoTHVdotVMAQASU_VV_MF2, 0x3 }, // 4 { PseudoTHVdotVMAQASU_VX_M1_MASK, PseudoTHVdotVMAQASU_VX_M1, 0x3 }, // 5 { PseudoTHVdotVMAQASU_VX_M2_MASK, PseudoTHVdotVMAQASU_VX_M2, 0x3 }, // 6 { PseudoTHVdotVMAQASU_VX_M4_MASK, PseudoTHVdotVMAQASU_VX_M4, 0x3 }, // 7 { PseudoTHVdotVMAQASU_VX_M8_MASK, PseudoTHVdotVMAQASU_VX_M8, 0x3 }, // 8 { PseudoTHVdotVMAQASU_VX_MF2_MASK, PseudoTHVdotVMAQASU_VX_MF2, 0x3 }, // 9 { PseudoTHVdotVMAQAUS_VX_M1_MASK, PseudoTHVdotVMAQAUS_VX_M1, 0x3 }, // 10 { PseudoTHVdotVMAQAUS_VX_M2_MASK, PseudoTHVdotVMAQAUS_VX_M2, 0x3 }, // 11 { PseudoTHVdotVMAQAUS_VX_M4_MASK, PseudoTHVdotVMAQAUS_VX_M4, 0x3 }, // 12 { PseudoTHVdotVMAQAUS_VX_M8_MASK, PseudoTHVdotVMAQAUS_VX_M8, 0x3 }, // 13 { PseudoTHVdotVMAQAUS_VX_MF2_MASK, PseudoTHVdotVMAQAUS_VX_MF2, 0x3 }, // 14 { PseudoTHVdotVMAQAU_VV_M1_MASK, PseudoTHVdotVMAQAU_VV_M1, 0x3 }, // 15 { PseudoTHVdotVMAQAU_VV_M2_MASK, PseudoTHVdotVMAQAU_VV_M2, 0x3 }, // 16 { PseudoTHVdotVMAQAU_VV_M4_MASK, PseudoTHVdotVMAQAU_VV_M4, 0x3 }, // 17 { PseudoTHVdotVMAQAU_VV_M8_MASK, PseudoTHVdotVMAQAU_VV_M8, 0x3 }, // 18 { PseudoTHVdotVMAQAU_VV_MF2_MASK, PseudoTHVdotVMAQAU_VV_MF2, 0x3 }, // 19 { PseudoTHVdotVMAQAU_VX_M1_MASK, PseudoTHVdotVMAQAU_VX_M1, 0x3 }, // 20 { PseudoTHVdotVMAQAU_VX_M2_MASK, PseudoTHVdotVMAQAU_VX_M2, 0x3 }, // 21 { PseudoTHVdotVMAQAU_VX_M4_MASK, PseudoTHVdotVMAQAU_VX_M4, 0x3 }, // 22 { PseudoTHVdotVMAQAU_VX_M8_MASK, PseudoTHVdotVMAQAU_VX_M8, 0x3 }, // 23 { PseudoTHVdotVMAQAU_VX_MF2_MASK, PseudoTHVdotVMAQAU_VX_MF2, 0x3 }, // 24 { PseudoTHVdotVMAQA_VV_M1_MASK, PseudoTHVdotVMAQA_VV_M1, 0x3 }, // 25 { PseudoTHVdotVMAQA_VV_M2_MASK, PseudoTHVdotVMAQA_VV_M2, 0x3 }, // 26 { PseudoTHVdotVMAQA_VV_M4_MASK, PseudoTHVdotVMAQA_VV_M4, 0x3 }, // 27 { PseudoTHVdotVMAQA_VV_M8_MASK, PseudoTHVdotVMAQA_VV_M8, 0x3 }, // 28 { PseudoTHVdotVMAQA_VV_MF2_MASK, PseudoTHVdotVMAQA_VV_MF2, 0x3 }, // 29 { PseudoTHVdotVMAQA_VX_M1_MASK, PseudoTHVdotVMAQA_VX_M1, 0x3 }, // 30 { PseudoTHVdotVMAQA_VX_M2_MASK, PseudoTHVdotVMAQA_VX_M2, 0x3 }, // 31 { PseudoTHVdotVMAQA_VX_M4_MASK, PseudoTHVdotVMAQA_VX_M4, 0x3 }, // 32 { PseudoTHVdotVMAQA_VX_M8_MASK, PseudoTHVdotVMAQA_VX_M8, 0x3 }, // 33 { PseudoTHVdotVMAQA_VX_MF2_MASK, PseudoTHVdotVMAQA_VX_MF2, 0x3 }, // 34 { PseudoVAADDU_VV_M1_MASK, PseudoVAADDU_VV_M1, 0x3 }, // 35 { PseudoVAADDU_VV_M2_MASK, PseudoVAADDU_VV_M2, 0x3 }, // 36 { PseudoVAADDU_VV_M4_MASK, PseudoVAADDU_VV_M4, 0x3 }, // 37 { PseudoVAADDU_VV_M8_MASK, PseudoVAADDU_VV_M8, 0x3 }, // 38 { PseudoVAADDU_VV_MF2_MASK, PseudoVAADDU_VV_MF2, 0x3 }, // 39 { PseudoVAADDU_VV_MF4_MASK, PseudoVAADDU_VV_MF4, 0x3 }, // 40 { PseudoVAADDU_VV_MF8_MASK, PseudoVAADDU_VV_MF8, 0x3 }, // 41 { PseudoVAADDU_VX_M1_MASK, PseudoVAADDU_VX_M1, 0x3 }, // 42 { PseudoVAADDU_VX_M2_MASK, PseudoVAADDU_VX_M2, 0x3 }, // 43 { PseudoVAADDU_VX_M4_MASK, PseudoVAADDU_VX_M4, 0x3 }, // 44 { PseudoVAADDU_VX_M8_MASK, PseudoVAADDU_VX_M8, 0x3 }, // 45 { PseudoVAADDU_VX_MF2_MASK, PseudoVAADDU_VX_MF2, 0x3 }, // 46 { PseudoVAADDU_VX_MF4_MASK, PseudoVAADDU_VX_MF4, 0x3 }, // 47 { PseudoVAADDU_VX_MF8_MASK, PseudoVAADDU_VX_MF8, 0x3 }, // 48 { PseudoVAADD_VV_M1_MASK, PseudoVAADD_VV_M1, 0x3 }, // 49 { PseudoVAADD_VV_M2_MASK, PseudoVAADD_VV_M2, 0x3 }, // 50 { PseudoVAADD_VV_M4_MASK, PseudoVAADD_VV_M4, 0x3 }, // 51 { PseudoVAADD_VV_M8_MASK, PseudoVAADD_VV_M8, 0x3 }, // 52 { PseudoVAADD_VV_MF2_MASK, PseudoVAADD_VV_MF2, 0x3 }, // 53 { PseudoVAADD_VV_MF4_MASK, PseudoVAADD_VV_MF4, 0x3 }, // 54 { PseudoVAADD_VV_MF8_MASK, PseudoVAADD_VV_MF8, 0x3 }, // 55 { PseudoVAADD_VX_M1_MASK, PseudoVAADD_VX_M1, 0x3 }, // 56 { PseudoVAADD_VX_M2_MASK, PseudoVAADD_VX_M2, 0x3 }, // 57 { PseudoVAADD_VX_M4_MASK, PseudoVAADD_VX_M4, 0x3 }, // 58 { PseudoVAADD_VX_M8_MASK, PseudoVAADD_VX_M8, 0x3 }, // 59 { PseudoVAADD_VX_MF2_MASK, PseudoVAADD_VX_MF2, 0x3 }, // 60 { PseudoVAADD_VX_MF4_MASK, PseudoVAADD_VX_MF4, 0x3 }, // 61 { PseudoVAADD_VX_MF8_MASK, PseudoVAADD_VX_MF8, 0x3 }, // 62 { PseudoVADD_VI_M1_MASK, PseudoVADD_VI_M1, 0x3 }, // 63 { PseudoVADD_VI_M2_MASK, PseudoVADD_VI_M2, 0x3 }, // 64 { PseudoVADD_VI_M4_MASK, PseudoVADD_VI_M4, 0x3 }, // 65 { PseudoVADD_VI_M8_MASK, PseudoVADD_VI_M8, 0x3 }, // 66 { PseudoVADD_VI_MF2_MASK, PseudoVADD_VI_MF2, 0x3 }, // 67 { PseudoVADD_VI_MF4_MASK, PseudoVADD_VI_MF4, 0x3 }, // 68 { PseudoVADD_VI_MF8_MASK, PseudoVADD_VI_MF8, 0x3 }, // 69 { PseudoVADD_VV_M1_MASK, PseudoVADD_VV_M1, 0x3 }, // 70 { PseudoVADD_VV_M2_MASK, PseudoVADD_VV_M2, 0x3 }, // 71 { PseudoVADD_VV_M4_MASK, PseudoVADD_VV_M4, 0x3 }, // 72 { PseudoVADD_VV_M8_MASK, PseudoVADD_VV_M8, 0x3 }, // 73 { PseudoVADD_VV_MF2_MASK, PseudoVADD_VV_MF2, 0x3 }, // 74 { PseudoVADD_VV_MF4_MASK, PseudoVADD_VV_MF4, 0x3 }, // 75 { PseudoVADD_VV_MF8_MASK, PseudoVADD_VV_MF8, 0x3 }, // 76 { PseudoVADD_VX_M1_MASK, PseudoVADD_VX_M1, 0x3 }, // 77 { PseudoVADD_VX_M2_MASK, PseudoVADD_VX_M2, 0x3 }, // 78 { PseudoVADD_VX_M4_MASK, PseudoVADD_VX_M4, 0x3 }, // 79 { PseudoVADD_VX_M8_MASK, PseudoVADD_VX_M8, 0x3 }, // 80 { PseudoVADD_VX_MF2_MASK, PseudoVADD_VX_MF2, 0x3 }, // 81 { PseudoVADD_VX_MF4_MASK, PseudoVADD_VX_MF4, 0x3 }, // 82 { PseudoVADD_VX_MF8_MASK, PseudoVADD_VX_MF8, 0x3 }, // 83 { PseudoVANDN_VV_M1_MASK, PseudoVANDN_VV_M1, 0x3 }, // 84 { PseudoVANDN_VV_M2_MASK, PseudoVANDN_VV_M2, 0x3 }, // 85 { PseudoVANDN_VV_M4_MASK, PseudoVANDN_VV_M4, 0x3 }, // 86 { PseudoVANDN_VV_M8_MASK, PseudoVANDN_VV_M8, 0x3 }, // 87 { PseudoVANDN_VV_MF2_MASK, PseudoVANDN_VV_MF2, 0x3 }, // 88 { PseudoVANDN_VV_MF4_MASK, PseudoVANDN_VV_MF4, 0x3 }, // 89 { PseudoVANDN_VV_MF8_MASK, PseudoVANDN_VV_MF8, 0x3 }, // 90 { PseudoVANDN_VX_M1_MASK, PseudoVANDN_VX_M1, 0x3 }, // 91 { PseudoVANDN_VX_M2_MASK, PseudoVANDN_VX_M2, 0x3 }, // 92 { PseudoVANDN_VX_M4_MASK, PseudoVANDN_VX_M4, 0x3 }, // 93 { PseudoVANDN_VX_M8_MASK, PseudoVANDN_VX_M8, 0x3 }, // 94 { PseudoVANDN_VX_MF2_MASK, PseudoVANDN_VX_MF2, 0x3 }, // 95 { PseudoVANDN_VX_MF4_MASK, PseudoVANDN_VX_MF4, 0x3 }, // 96 { PseudoVANDN_VX_MF8_MASK, PseudoVANDN_VX_MF8, 0x3 }, // 97 { PseudoVAND_VI_M1_MASK, PseudoVAND_VI_M1, 0x3 }, // 98 { PseudoVAND_VI_M2_MASK, PseudoVAND_VI_M2, 0x3 }, // 99 { PseudoVAND_VI_M4_MASK, PseudoVAND_VI_M4, 0x3 }, // 100 { PseudoVAND_VI_M8_MASK, PseudoVAND_VI_M8, 0x3 }, // 101 { PseudoVAND_VI_MF2_MASK, PseudoVAND_VI_MF2, 0x3 }, // 102 { PseudoVAND_VI_MF4_MASK, PseudoVAND_VI_MF4, 0x3 }, // 103 { PseudoVAND_VI_MF8_MASK, PseudoVAND_VI_MF8, 0x3 }, // 104 { PseudoVAND_VV_M1_MASK, PseudoVAND_VV_M1, 0x3 }, // 105 { PseudoVAND_VV_M2_MASK, PseudoVAND_VV_M2, 0x3 }, // 106 { PseudoVAND_VV_M4_MASK, PseudoVAND_VV_M4, 0x3 }, // 107 { PseudoVAND_VV_M8_MASK, PseudoVAND_VV_M8, 0x3 }, // 108 { PseudoVAND_VV_MF2_MASK, PseudoVAND_VV_MF2, 0x3 }, // 109 { PseudoVAND_VV_MF4_MASK, PseudoVAND_VV_MF4, 0x3 }, // 110 { PseudoVAND_VV_MF8_MASK, PseudoVAND_VV_MF8, 0x3 }, // 111 { PseudoVAND_VX_M1_MASK, PseudoVAND_VX_M1, 0x3 }, // 112 { PseudoVAND_VX_M2_MASK, PseudoVAND_VX_M2, 0x3 }, // 113 { PseudoVAND_VX_M4_MASK, PseudoVAND_VX_M4, 0x3 }, // 114 { PseudoVAND_VX_M8_MASK, PseudoVAND_VX_M8, 0x3 }, // 115 { PseudoVAND_VX_MF2_MASK, PseudoVAND_VX_MF2, 0x3 }, // 116 { PseudoVAND_VX_MF4_MASK, PseudoVAND_VX_MF4, 0x3 }, // 117 { PseudoVAND_VX_MF8_MASK, PseudoVAND_VX_MF8, 0x3 }, // 118 { PseudoVASUBU_VV_M1_MASK, PseudoVASUBU_VV_M1, 0x3 }, // 119 { PseudoVASUBU_VV_M2_MASK, PseudoVASUBU_VV_M2, 0x3 }, // 120 { PseudoVASUBU_VV_M4_MASK, PseudoVASUBU_VV_M4, 0x3 }, // 121 { PseudoVASUBU_VV_M8_MASK, PseudoVASUBU_VV_M8, 0x3 }, // 122 { PseudoVASUBU_VV_MF2_MASK, PseudoVASUBU_VV_MF2, 0x3 }, // 123 { PseudoVASUBU_VV_MF4_MASK, PseudoVASUBU_VV_MF4, 0x3 }, // 124 { PseudoVASUBU_VV_MF8_MASK, PseudoVASUBU_VV_MF8, 0x3 }, // 125 { PseudoVASUBU_VX_M1_MASK, PseudoVASUBU_VX_M1, 0x3 }, // 126 { PseudoVASUBU_VX_M2_MASK, PseudoVASUBU_VX_M2, 0x3 }, // 127 { PseudoVASUBU_VX_M4_MASK, PseudoVASUBU_VX_M4, 0x3 }, // 128 { PseudoVASUBU_VX_M8_MASK, PseudoVASUBU_VX_M8, 0x3 }, // 129 { PseudoVASUBU_VX_MF2_MASK, PseudoVASUBU_VX_MF2, 0x3 }, // 130 { PseudoVASUBU_VX_MF4_MASK, PseudoVASUBU_VX_MF4, 0x3 }, // 131 { PseudoVASUBU_VX_MF8_MASK, PseudoVASUBU_VX_MF8, 0x3 }, // 132 { PseudoVASUB_VV_M1_MASK, PseudoVASUB_VV_M1, 0x3 }, // 133 { PseudoVASUB_VV_M2_MASK, PseudoVASUB_VV_M2, 0x3 }, // 134 { PseudoVASUB_VV_M4_MASK, PseudoVASUB_VV_M4, 0x3 }, // 135 { PseudoVASUB_VV_M8_MASK, PseudoVASUB_VV_M8, 0x3 }, // 136 { PseudoVASUB_VV_MF2_MASK, PseudoVASUB_VV_MF2, 0x3 }, // 137 { PseudoVASUB_VV_MF4_MASK, PseudoVASUB_VV_MF4, 0x3 }, // 138 { PseudoVASUB_VV_MF8_MASK, PseudoVASUB_VV_MF8, 0x3 }, // 139 { PseudoVASUB_VX_M1_MASK, PseudoVASUB_VX_M1, 0x3 }, // 140 { PseudoVASUB_VX_M2_MASK, PseudoVASUB_VX_M2, 0x3 }, // 141 { PseudoVASUB_VX_M4_MASK, PseudoVASUB_VX_M4, 0x3 }, // 142 { PseudoVASUB_VX_M8_MASK, PseudoVASUB_VX_M8, 0x3 }, // 143 { PseudoVASUB_VX_MF2_MASK, PseudoVASUB_VX_MF2, 0x3 }, // 144 { PseudoVASUB_VX_MF4_MASK, PseudoVASUB_VX_MF4, 0x3 }, // 145 { PseudoVASUB_VX_MF8_MASK, PseudoVASUB_VX_MF8, 0x3 }, // 146 { PseudoVBREV8_V_M1_MASK, PseudoVBREV8_V_M1, 0x2 }, // 147 { PseudoVBREV8_V_M2_MASK, PseudoVBREV8_V_M2, 0x2 }, // 148 { PseudoVBREV8_V_M4_MASK, PseudoVBREV8_V_M4, 0x2 }, // 149 { PseudoVBREV8_V_M8_MASK, PseudoVBREV8_V_M8, 0x2 }, // 150 { PseudoVBREV8_V_MF2_MASK, PseudoVBREV8_V_MF2, 0x2 }, // 151 { PseudoVBREV8_V_MF4_MASK, PseudoVBREV8_V_MF4, 0x2 }, // 152 { PseudoVBREV8_V_MF8_MASK, PseudoVBREV8_V_MF8, 0x2 }, // 153 { PseudoVBREV_V_M1_MASK, PseudoVBREV_V_M1, 0x2 }, // 154 { PseudoVBREV_V_M2_MASK, PseudoVBREV_V_M2, 0x2 }, // 155 { PseudoVBREV_V_M4_MASK, PseudoVBREV_V_M4, 0x2 }, // 156 { PseudoVBREV_V_M8_MASK, PseudoVBREV_V_M8, 0x2 }, // 157 { PseudoVBREV_V_MF2_MASK, PseudoVBREV_V_MF2, 0x2 }, // 158 { PseudoVBREV_V_MF4_MASK, PseudoVBREV_V_MF4, 0x2 }, // 159 { PseudoVBREV_V_MF8_MASK, PseudoVBREV_V_MF8, 0x2 }, // 160 { PseudoVCLMULH_VV_M1_MASK, PseudoVCLMULH_VV_M1, 0x3 }, // 161 { PseudoVCLMULH_VV_M2_MASK, PseudoVCLMULH_VV_M2, 0x3 }, // 162 { PseudoVCLMULH_VV_M4_MASK, PseudoVCLMULH_VV_M4, 0x3 }, // 163 { PseudoVCLMULH_VV_M8_MASK, PseudoVCLMULH_VV_M8, 0x3 }, // 164 { PseudoVCLMULH_VV_MF2_MASK, PseudoVCLMULH_VV_MF2, 0x3 }, // 165 { PseudoVCLMULH_VV_MF4_MASK, PseudoVCLMULH_VV_MF4, 0x3 }, // 166 { PseudoVCLMULH_VV_MF8_MASK, PseudoVCLMULH_VV_MF8, 0x3 }, // 167 { PseudoVCLMULH_VX_M1_MASK, PseudoVCLMULH_VX_M1, 0x3 }, // 168 { PseudoVCLMULH_VX_M2_MASK, PseudoVCLMULH_VX_M2, 0x3 }, // 169 { PseudoVCLMULH_VX_M4_MASK, PseudoVCLMULH_VX_M4, 0x3 }, // 170 { PseudoVCLMULH_VX_M8_MASK, PseudoVCLMULH_VX_M8, 0x3 }, // 171 { PseudoVCLMULH_VX_MF2_MASK, PseudoVCLMULH_VX_MF2, 0x3 }, // 172 { PseudoVCLMULH_VX_MF4_MASK, PseudoVCLMULH_VX_MF4, 0x3 }, // 173 { PseudoVCLMULH_VX_MF8_MASK, PseudoVCLMULH_VX_MF8, 0x3 }, // 174 { PseudoVCLMUL_VV_M1_MASK, PseudoVCLMUL_VV_M1, 0x3 }, // 175 { PseudoVCLMUL_VV_M2_MASK, PseudoVCLMUL_VV_M2, 0x3 }, // 176 { PseudoVCLMUL_VV_M4_MASK, PseudoVCLMUL_VV_M4, 0x3 }, // 177 { PseudoVCLMUL_VV_M8_MASK, PseudoVCLMUL_VV_M8, 0x3 }, // 178 { PseudoVCLMUL_VV_MF2_MASK, PseudoVCLMUL_VV_MF2, 0x3 }, // 179 { PseudoVCLMUL_VV_MF4_MASK, PseudoVCLMUL_VV_MF4, 0x3 }, // 180 { PseudoVCLMUL_VV_MF8_MASK, PseudoVCLMUL_VV_MF8, 0x3 }, // 181 { PseudoVCLMUL_VX_M1_MASK, PseudoVCLMUL_VX_M1, 0x3 }, // 182 { PseudoVCLMUL_VX_M2_MASK, PseudoVCLMUL_VX_M2, 0x3 }, // 183 { PseudoVCLMUL_VX_M4_MASK, PseudoVCLMUL_VX_M4, 0x3 }, // 184 { PseudoVCLMUL_VX_M8_MASK, PseudoVCLMUL_VX_M8, 0x3 }, // 185 { PseudoVCLMUL_VX_MF2_MASK, PseudoVCLMUL_VX_MF2, 0x3 }, // 186 { PseudoVCLMUL_VX_MF4_MASK, PseudoVCLMUL_VX_MF4, 0x3 }, // 187 { PseudoVCLMUL_VX_MF8_MASK, PseudoVCLMUL_VX_MF8, 0x3 }, // 188 { PseudoVCLZ_V_M1_MASK, PseudoVCLZ_V_M1, 0x2 }, // 189 { PseudoVCLZ_V_M2_MASK, PseudoVCLZ_V_M2, 0x2 }, // 190 { PseudoVCLZ_V_M4_MASK, PseudoVCLZ_V_M4, 0x2 }, // 191 { PseudoVCLZ_V_M8_MASK, PseudoVCLZ_V_M8, 0x2 }, // 192 { PseudoVCLZ_V_MF2_MASK, PseudoVCLZ_V_MF2, 0x2 }, // 193 { PseudoVCLZ_V_MF4_MASK, PseudoVCLZ_V_MF4, 0x2 }, // 194 { PseudoVCLZ_V_MF8_MASK, PseudoVCLZ_V_MF8, 0x2 }, // 195 { PseudoVCPOP_V_M1_MASK, PseudoVCPOP_V_M1, 0x2 }, // 196 { PseudoVCPOP_V_M2_MASK, PseudoVCPOP_V_M2, 0x2 }, // 197 { PseudoVCPOP_V_M4_MASK, PseudoVCPOP_V_M4, 0x2 }, // 198 { PseudoVCPOP_V_M8_MASK, PseudoVCPOP_V_M8, 0x2 }, // 199 { PseudoVCPOP_V_MF2_MASK, PseudoVCPOP_V_MF2, 0x2 }, // 200 { PseudoVCPOP_V_MF4_MASK, PseudoVCPOP_V_MF4, 0x2 }, // 201 { PseudoVCPOP_V_MF8_MASK, PseudoVCPOP_V_MF8, 0x2 }, // 202 { PseudoVCTZ_V_M1_MASK, PseudoVCTZ_V_M1, 0x2 }, // 203 { PseudoVCTZ_V_M2_MASK, PseudoVCTZ_V_M2, 0x2 }, // 204 { PseudoVCTZ_V_M4_MASK, PseudoVCTZ_V_M4, 0x2 }, // 205 { PseudoVCTZ_V_M8_MASK, PseudoVCTZ_V_M8, 0x2 }, // 206 { PseudoVCTZ_V_MF2_MASK, PseudoVCTZ_V_MF2, 0x2 }, // 207 { PseudoVCTZ_V_MF4_MASK, PseudoVCTZ_V_MF4, 0x2 }, // 208 { PseudoVCTZ_V_MF8_MASK, PseudoVCTZ_V_MF8, 0x2 }, // 209 { PseudoVDIVU_VV_M1_E16_MASK, PseudoVDIVU_VV_M1_E16, 0x3 }, // 210 { PseudoVDIVU_VV_M1_E32_MASK, PseudoVDIVU_VV_M1_E32, 0x3 }, // 211 { PseudoVDIVU_VV_M1_E64_MASK, PseudoVDIVU_VV_M1_E64, 0x3 }, // 212 { PseudoVDIVU_VV_M1_E8_MASK, PseudoVDIVU_VV_M1_E8, 0x3 }, // 213 { PseudoVDIVU_VV_M2_E16_MASK, PseudoVDIVU_VV_M2_E16, 0x3 }, // 214 { PseudoVDIVU_VV_M2_E32_MASK, PseudoVDIVU_VV_M2_E32, 0x3 }, // 215 { PseudoVDIVU_VV_M2_E64_MASK, PseudoVDIVU_VV_M2_E64, 0x3 }, // 216 { PseudoVDIVU_VV_M2_E8_MASK, PseudoVDIVU_VV_M2_E8, 0x3 }, // 217 { PseudoVDIVU_VV_M4_E16_MASK, PseudoVDIVU_VV_M4_E16, 0x3 }, // 218 { PseudoVDIVU_VV_M4_E32_MASK, PseudoVDIVU_VV_M4_E32, 0x3 }, // 219 { PseudoVDIVU_VV_M4_E64_MASK, PseudoVDIVU_VV_M4_E64, 0x3 }, // 220 { PseudoVDIVU_VV_M4_E8_MASK, PseudoVDIVU_VV_M4_E8, 0x3 }, // 221 { PseudoVDIVU_VV_M8_E16_MASK, PseudoVDIVU_VV_M8_E16, 0x3 }, // 222 { PseudoVDIVU_VV_M8_E32_MASK, PseudoVDIVU_VV_M8_E32, 0x3 }, // 223 { PseudoVDIVU_VV_M8_E64_MASK, PseudoVDIVU_VV_M8_E64, 0x3 }, // 224 { PseudoVDIVU_VV_M8_E8_MASK, PseudoVDIVU_VV_M8_E8, 0x3 }, // 225 { PseudoVDIVU_VV_MF2_E16_MASK, PseudoVDIVU_VV_MF2_E16, 0x3 }, // 226 { PseudoVDIVU_VV_MF2_E32_MASK, PseudoVDIVU_VV_MF2_E32, 0x3 }, // 227 { PseudoVDIVU_VV_MF2_E8_MASK, PseudoVDIVU_VV_MF2_E8, 0x3 }, // 228 { PseudoVDIVU_VV_MF4_E16_MASK, PseudoVDIVU_VV_MF4_E16, 0x3 }, // 229 { PseudoVDIVU_VV_MF4_E8_MASK, PseudoVDIVU_VV_MF4_E8, 0x3 }, // 230 { PseudoVDIVU_VV_MF8_E8_MASK, PseudoVDIVU_VV_MF8_E8, 0x3 }, // 231 { PseudoVDIVU_VX_M1_E16_MASK, PseudoVDIVU_VX_M1_E16, 0x3 }, // 232 { PseudoVDIVU_VX_M1_E32_MASK, PseudoVDIVU_VX_M1_E32, 0x3 }, // 233 { PseudoVDIVU_VX_M1_E64_MASK, PseudoVDIVU_VX_M1_E64, 0x3 }, // 234 { PseudoVDIVU_VX_M1_E8_MASK, PseudoVDIVU_VX_M1_E8, 0x3 }, // 235 { PseudoVDIVU_VX_M2_E16_MASK, PseudoVDIVU_VX_M2_E16, 0x3 }, // 236 { PseudoVDIVU_VX_M2_E32_MASK, PseudoVDIVU_VX_M2_E32, 0x3 }, // 237 { PseudoVDIVU_VX_M2_E64_MASK, PseudoVDIVU_VX_M2_E64, 0x3 }, // 238 { PseudoVDIVU_VX_M2_E8_MASK, PseudoVDIVU_VX_M2_E8, 0x3 }, // 239 { PseudoVDIVU_VX_M4_E16_MASK, PseudoVDIVU_VX_M4_E16, 0x3 }, // 240 { PseudoVDIVU_VX_M4_E32_MASK, PseudoVDIVU_VX_M4_E32, 0x3 }, // 241 { PseudoVDIVU_VX_M4_E64_MASK, PseudoVDIVU_VX_M4_E64, 0x3 }, // 242 { PseudoVDIVU_VX_M4_E8_MASK, PseudoVDIVU_VX_M4_E8, 0x3 }, // 243 { PseudoVDIVU_VX_M8_E16_MASK, PseudoVDIVU_VX_M8_E16, 0x3 }, // 244 { PseudoVDIVU_VX_M8_E32_MASK, PseudoVDIVU_VX_M8_E32, 0x3 }, // 245 { PseudoVDIVU_VX_M8_E64_MASK, PseudoVDIVU_VX_M8_E64, 0x3 }, // 246 { PseudoVDIVU_VX_M8_E8_MASK, PseudoVDIVU_VX_M8_E8, 0x3 }, // 247 { PseudoVDIVU_VX_MF2_E16_MASK, PseudoVDIVU_VX_MF2_E16, 0x3 }, // 248 { PseudoVDIVU_VX_MF2_E32_MASK, PseudoVDIVU_VX_MF2_E32, 0x3 }, // 249 { PseudoVDIVU_VX_MF2_E8_MASK, PseudoVDIVU_VX_MF2_E8, 0x3 }, // 250 { PseudoVDIVU_VX_MF4_E16_MASK, PseudoVDIVU_VX_MF4_E16, 0x3 }, // 251 { PseudoVDIVU_VX_MF4_E8_MASK, PseudoVDIVU_VX_MF4_E8, 0x3 }, // 252 { PseudoVDIVU_VX_MF8_E8_MASK, PseudoVDIVU_VX_MF8_E8, 0x3 }, // 253 { PseudoVDIV_VV_M1_E16_MASK, PseudoVDIV_VV_M1_E16, 0x3 }, // 254 { PseudoVDIV_VV_M1_E32_MASK, PseudoVDIV_VV_M1_E32, 0x3 }, // 255 { PseudoVDIV_VV_M1_E64_MASK, PseudoVDIV_VV_M1_E64, 0x3 }, // 256 { PseudoVDIV_VV_M1_E8_MASK, PseudoVDIV_VV_M1_E8, 0x3 }, // 257 { PseudoVDIV_VV_M2_E16_MASK, PseudoVDIV_VV_M2_E16, 0x3 }, // 258 { PseudoVDIV_VV_M2_E32_MASK, PseudoVDIV_VV_M2_E32, 0x3 }, // 259 { PseudoVDIV_VV_M2_E64_MASK, PseudoVDIV_VV_M2_E64, 0x3 }, // 260 { PseudoVDIV_VV_M2_E8_MASK, PseudoVDIV_VV_M2_E8, 0x3 }, // 261 { PseudoVDIV_VV_M4_E16_MASK, PseudoVDIV_VV_M4_E16, 0x3 }, // 262 { PseudoVDIV_VV_M4_E32_MASK, PseudoVDIV_VV_M4_E32, 0x3 }, // 263 { PseudoVDIV_VV_M4_E64_MASK, PseudoVDIV_VV_M4_E64, 0x3 }, // 264 { PseudoVDIV_VV_M4_E8_MASK, PseudoVDIV_VV_M4_E8, 0x3 }, // 265 { PseudoVDIV_VV_M8_E16_MASK, PseudoVDIV_VV_M8_E16, 0x3 }, // 266 { PseudoVDIV_VV_M8_E32_MASK, PseudoVDIV_VV_M8_E32, 0x3 }, // 267 { PseudoVDIV_VV_M8_E64_MASK, PseudoVDIV_VV_M8_E64, 0x3 }, // 268 { PseudoVDIV_VV_M8_E8_MASK, PseudoVDIV_VV_M8_E8, 0x3 }, // 269 { PseudoVDIV_VV_MF2_E16_MASK, PseudoVDIV_VV_MF2_E16, 0x3 }, // 270 { PseudoVDIV_VV_MF2_E32_MASK, PseudoVDIV_VV_MF2_E32, 0x3 }, // 271 { PseudoVDIV_VV_MF2_E8_MASK, PseudoVDIV_VV_MF2_E8, 0x3 }, // 272 { PseudoVDIV_VV_MF4_E16_MASK, PseudoVDIV_VV_MF4_E16, 0x3 }, // 273 { PseudoVDIV_VV_MF4_E8_MASK, PseudoVDIV_VV_MF4_E8, 0x3 }, // 274 { PseudoVDIV_VV_MF8_E8_MASK, PseudoVDIV_VV_MF8_E8, 0x3 }, // 275 { PseudoVDIV_VX_M1_E16_MASK, PseudoVDIV_VX_M1_E16, 0x3 }, // 276 { PseudoVDIV_VX_M1_E32_MASK, PseudoVDIV_VX_M1_E32, 0x3 }, // 277 { PseudoVDIV_VX_M1_E64_MASK, PseudoVDIV_VX_M1_E64, 0x3 }, // 278 { PseudoVDIV_VX_M1_E8_MASK, PseudoVDIV_VX_M1_E8, 0x3 }, // 279 { PseudoVDIV_VX_M2_E16_MASK, PseudoVDIV_VX_M2_E16, 0x3 }, // 280 { PseudoVDIV_VX_M2_E32_MASK, PseudoVDIV_VX_M2_E32, 0x3 }, // 281 { PseudoVDIV_VX_M2_E64_MASK, PseudoVDIV_VX_M2_E64, 0x3 }, // 282 { PseudoVDIV_VX_M2_E8_MASK, PseudoVDIV_VX_M2_E8, 0x3 }, // 283 { PseudoVDIV_VX_M4_E16_MASK, PseudoVDIV_VX_M4_E16, 0x3 }, // 284 { PseudoVDIV_VX_M4_E32_MASK, PseudoVDIV_VX_M4_E32, 0x3 }, // 285 { PseudoVDIV_VX_M4_E64_MASK, PseudoVDIV_VX_M4_E64, 0x3 }, // 286 { PseudoVDIV_VX_M4_E8_MASK, PseudoVDIV_VX_M4_E8, 0x3 }, // 287 { PseudoVDIV_VX_M8_E16_MASK, PseudoVDIV_VX_M8_E16, 0x3 }, // 288 { PseudoVDIV_VX_M8_E32_MASK, PseudoVDIV_VX_M8_E32, 0x3 }, // 289 { PseudoVDIV_VX_M8_E64_MASK, PseudoVDIV_VX_M8_E64, 0x3 }, // 290 { PseudoVDIV_VX_M8_E8_MASK, PseudoVDIV_VX_M8_E8, 0x3 }, // 291 { PseudoVDIV_VX_MF2_E16_MASK, PseudoVDIV_VX_MF2_E16, 0x3 }, // 292 { PseudoVDIV_VX_MF2_E32_MASK, PseudoVDIV_VX_MF2_E32, 0x3 }, // 293 { PseudoVDIV_VX_MF2_E8_MASK, PseudoVDIV_VX_MF2_E8, 0x3 }, // 294 { PseudoVDIV_VX_MF4_E16_MASK, PseudoVDIV_VX_MF4_E16, 0x3 }, // 295 { PseudoVDIV_VX_MF4_E8_MASK, PseudoVDIV_VX_MF4_E8, 0x3 }, // 296 { PseudoVDIV_VX_MF8_E8_MASK, PseudoVDIV_VX_MF8_E8, 0x3 }, // 297 { PseudoVFADD_VFPR16_M1_E16_MASK, PseudoVFADD_VFPR16_M1_E16, 0x3 }, // 298 { PseudoVFADD_VFPR16_M2_E16_MASK, PseudoVFADD_VFPR16_M2_E16, 0x3 }, // 299 { PseudoVFADD_VFPR16_M4_E16_MASK, PseudoVFADD_VFPR16_M4_E16, 0x3 }, // 300 { PseudoVFADD_VFPR16_M8_E16_MASK, PseudoVFADD_VFPR16_M8_E16, 0x3 }, // 301 { PseudoVFADD_VFPR16_MF2_E16_MASK, PseudoVFADD_VFPR16_MF2_E16, 0x3 }, // 302 { PseudoVFADD_VFPR16_MF4_E16_MASK, PseudoVFADD_VFPR16_MF4_E16, 0x3 }, // 303 { PseudoVFADD_VFPR32_M1_E32_MASK, PseudoVFADD_VFPR32_M1_E32, 0x3 }, // 304 { PseudoVFADD_VFPR32_M2_E32_MASK, PseudoVFADD_VFPR32_M2_E32, 0x3 }, // 305 { PseudoVFADD_VFPR32_M4_E32_MASK, PseudoVFADD_VFPR32_M4_E32, 0x3 }, // 306 { PseudoVFADD_VFPR32_M8_E32_MASK, PseudoVFADD_VFPR32_M8_E32, 0x3 }, // 307 { PseudoVFADD_VFPR32_MF2_E32_MASK, PseudoVFADD_VFPR32_MF2_E32, 0x3 }, // 308 { PseudoVFADD_VFPR64_M1_E64_MASK, PseudoVFADD_VFPR64_M1_E64, 0x3 }, // 309 { PseudoVFADD_VFPR64_M2_E64_MASK, PseudoVFADD_VFPR64_M2_E64, 0x3 }, // 310 { PseudoVFADD_VFPR64_M4_E64_MASK, PseudoVFADD_VFPR64_M4_E64, 0x3 }, // 311 { PseudoVFADD_VFPR64_M8_E64_MASK, PseudoVFADD_VFPR64_M8_E64, 0x3 }, // 312 { PseudoVFADD_VV_M1_E16_MASK, PseudoVFADD_VV_M1_E16, 0x3 }, // 313 { PseudoVFADD_VV_M1_E32_MASK, PseudoVFADD_VV_M1_E32, 0x3 }, // 314 { PseudoVFADD_VV_M1_E64_MASK, PseudoVFADD_VV_M1_E64, 0x3 }, // 315 { PseudoVFADD_VV_M2_E16_MASK, PseudoVFADD_VV_M2_E16, 0x3 }, // 316 { PseudoVFADD_VV_M2_E32_MASK, PseudoVFADD_VV_M2_E32, 0x3 }, // 317 { PseudoVFADD_VV_M2_E64_MASK, PseudoVFADD_VV_M2_E64, 0x3 }, // 318 { PseudoVFADD_VV_M4_E16_MASK, PseudoVFADD_VV_M4_E16, 0x3 }, // 319 { PseudoVFADD_VV_M4_E32_MASK, PseudoVFADD_VV_M4_E32, 0x3 }, // 320 { PseudoVFADD_VV_M4_E64_MASK, PseudoVFADD_VV_M4_E64, 0x3 }, // 321 { PseudoVFADD_VV_M8_E16_MASK, PseudoVFADD_VV_M8_E16, 0x3 }, // 322 { PseudoVFADD_VV_M8_E32_MASK, PseudoVFADD_VV_M8_E32, 0x3 }, // 323 { PseudoVFADD_VV_M8_E64_MASK, PseudoVFADD_VV_M8_E64, 0x3 }, // 324 { PseudoVFADD_VV_MF2_E16_MASK, PseudoVFADD_VV_MF2_E16, 0x3 }, // 325 { PseudoVFADD_VV_MF2_E32_MASK, PseudoVFADD_VV_MF2_E32, 0x3 }, // 326 { PseudoVFADD_VV_MF4_E16_MASK, PseudoVFADD_VV_MF4_E16, 0x3 }, // 327 { PseudoVFCLASS_V_M1_MASK, PseudoVFCLASS_V_M1, 0x2 }, // 328 { PseudoVFCLASS_V_M2_MASK, PseudoVFCLASS_V_M2, 0x2 }, // 329 { PseudoVFCLASS_V_M4_MASK, PseudoVFCLASS_V_M4, 0x2 }, // 330 { PseudoVFCLASS_V_M8_MASK, PseudoVFCLASS_V_M8, 0x2 }, // 331 { PseudoVFCLASS_V_MF2_MASK, PseudoVFCLASS_V_MF2, 0x2 }, // 332 { PseudoVFCLASS_V_MF4_MASK, PseudoVFCLASS_V_MF4, 0x2 }, // 333 { PseudoVFCVT_F_XU_V_M1_E16_MASK, PseudoVFCVT_F_XU_V_M1_E16, 0x2 }, // 334 { PseudoVFCVT_F_XU_V_M1_E32_MASK, PseudoVFCVT_F_XU_V_M1_E32, 0x2 }, // 335 { PseudoVFCVT_F_XU_V_M1_E64_MASK, PseudoVFCVT_F_XU_V_M1_E64, 0x2 }, // 336 { PseudoVFCVT_F_XU_V_M2_E16_MASK, PseudoVFCVT_F_XU_V_M2_E16, 0x2 }, // 337 { PseudoVFCVT_F_XU_V_M2_E32_MASK, PseudoVFCVT_F_XU_V_M2_E32, 0x2 }, // 338 { PseudoVFCVT_F_XU_V_M2_E64_MASK, PseudoVFCVT_F_XU_V_M2_E64, 0x2 }, // 339 { PseudoVFCVT_F_XU_V_M4_E16_MASK, PseudoVFCVT_F_XU_V_M4_E16, 0x2 }, // 340 { PseudoVFCVT_F_XU_V_M4_E32_MASK, PseudoVFCVT_F_XU_V_M4_E32, 0x2 }, // 341 { PseudoVFCVT_F_XU_V_M4_E64_MASK, PseudoVFCVT_F_XU_V_M4_E64, 0x2 }, // 342 { PseudoVFCVT_F_XU_V_M8_E16_MASK, PseudoVFCVT_F_XU_V_M8_E16, 0x2 }, // 343 { PseudoVFCVT_F_XU_V_M8_E32_MASK, PseudoVFCVT_F_XU_V_M8_E32, 0x2 }, // 344 { PseudoVFCVT_F_XU_V_M8_E64_MASK, PseudoVFCVT_F_XU_V_M8_E64, 0x2 }, // 345 { PseudoVFCVT_F_XU_V_MF2_E16_MASK, PseudoVFCVT_F_XU_V_MF2_E16, 0x2 }, // 346 { PseudoVFCVT_F_XU_V_MF2_E32_MASK, PseudoVFCVT_F_XU_V_MF2_E32, 0x2 }, // 347 { PseudoVFCVT_F_XU_V_MF4_E16_MASK, PseudoVFCVT_F_XU_V_MF4_E16, 0x2 }, // 348 { PseudoVFCVT_F_X_V_M1_E16_MASK, PseudoVFCVT_F_X_V_M1_E16, 0x2 }, // 349 { PseudoVFCVT_F_X_V_M1_E32_MASK, PseudoVFCVT_F_X_V_M1_E32, 0x2 }, // 350 { PseudoVFCVT_F_X_V_M1_E64_MASK, PseudoVFCVT_F_X_V_M1_E64, 0x2 }, // 351 { PseudoVFCVT_F_X_V_M2_E16_MASK, PseudoVFCVT_F_X_V_M2_E16, 0x2 }, // 352 { PseudoVFCVT_F_X_V_M2_E32_MASK, PseudoVFCVT_F_X_V_M2_E32, 0x2 }, // 353 { PseudoVFCVT_F_X_V_M2_E64_MASK, PseudoVFCVT_F_X_V_M2_E64, 0x2 }, // 354 { PseudoVFCVT_F_X_V_M4_E16_MASK, PseudoVFCVT_F_X_V_M4_E16, 0x2 }, // 355 { PseudoVFCVT_F_X_V_M4_E32_MASK, PseudoVFCVT_F_X_V_M4_E32, 0x2 }, // 356 { PseudoVFCVT_F_X_V_M4_E64_MASK, PseudoVFCVT_F_X_V_M4_E64, 0x2 }, // 357 { PseudoVFCVT_F_X_V_M8_E16_MASK, PseudoVFCVT_F_X_V_M8_E16, 0x2 }, // 358 { PseudoVFCVT_F_X_V_M8_E32_MASK, PseudoVFCVT_F_X_V_M8_E32, 0x2 }, // 359 { PseudoVFCVT_F_X_V_M8_E64_MASK, PseudoVFCVT_F_X_V_M8_E64, 0x2 }, // 360 { PseudoVFCVT_F_X_V_MF2_E16_MASK, PseudoVFCVT_F_X_V_MF2_E16, 0x2 }, // 361 { PseudoVFCVT_F_X_V_MF2_E32_MASK, PseudoVFCVT_F_X_V_MF2_E32, 0x2 }, // 362 { PseudoVFCVT_F_X_V_MF4_E16_MASK, PseudoVFCVT_F_X_V_MF4_E16, 0x2 }, // 363 { PseudoVFCVT_RM_F_XU_V_M1_E16_MASK, PseudoVFCVT_RM_F_XU_V_M1_E16, 0x2 }, // 364 { PseudoVFCVT_RM_F_XU_V_M1_E32_MASK, PseudoVFCVT_RM_F_XU_V_M1_E32, 0x2 }, // 365 { PseudoVFCVT_RM_F_XU_V_M1_E64_MASK, PseudoVFCVT_RM_F_XU_V_M1_E64, 0x2 }, // 366 { PseudoVFCVT_RM_F_XU_V_M2_E16_MASK, PseudoVFCVT_RM_F_XU_V_M2_E16, 0x2 }, // 367 { PseudoVFCVT_RM_F_XU_V_M2_E32_MASK, PseudoVFCVT_RM_F_XU_V_M2_E32, 0x2 }, // 368 { PseudoVFCVT_RM_F_XU_V_M2_E64_MASK, PseudoVFCVT_RM_F_XU_V_M2_E64, 0x2 }, // 369 { PseudoVFCVT_RM_F_XU_V_M4_E16_MASK, PseudoVFCVT_RM_F_XU_V_M4_E16, 0x2 }, // 370 { PseudoVFCVT_RM_F_XU_V_M4_E32_MASK, PseudoVFCVT_RM_F_XU_V_M4_E32, 0x2 }, // 371 { PseudoVFCVT_RM_F_XU_V_M4_E64_MASK, PseudoVFCVT_RM_F_XU_V_M4_E64, 0x2 }, // 372 { PseudoVFCVT_RM_F_XU_V_M8_E16_MASK, PseudoVFCVT_RM_F_XU_V_M8_E16, 0x2 }, // 373 { PseudoVFCVT_RM_F_XU_V_M8_E32_MASK, PseudoVFCVT_RM_F_XU_V_M8_E32, 0x2 }, // 374 { PseudoVFCVT_RM_F_XU_V_M8_E64_MASK, PseudoVFCVT_RM_F_XU_V_M8_E64, 0x2 }, // 375 { PseudoVFCVT_RM_F_XU_V_MF2_E16_MASK, PseudoVFCVT_RM_F_XU_V_MF2_E16, 0x2 }, // 376 { PseudoVFCVT_RM_F_XU_V_MF2_E32_MASK, PseudoVFCVT_RM_F_XU_V_MF2_E32, 0x2 }, // 377 { PseudoVFCVT_RM_F_XU_V_MF4_E16_MASK, PseudoVFCVT_RM_F_XU_V_MF4_E16, 0x2 }, // 378 { PseudoVFCVT_RM_F_X_V_M1_E16_MASK, PseudoVFCVT_RM_F_X_V_M1_E16, 0x2 }, // 379 { PseudoVFCVT_RM_F_X_V_M1_E32_MASK, PseudoVFCVT_RM_F_X_V_M1_E32, 0x2 }, // 380 { PseudoVFCVT_RM_F_X_V_M1_E64_MASK, PseudoVFCVT_RM_F_X_V_M1_E64, 0x2 }, // 381 { PseudoVFCVT_RM_F_X_V_M2_E16_MASK, PseudoVFCVT_RM_F_X_V_M2_E16, 0x2 }, // 382 { PseudoVFCVT_RM_F_X_V_M2_E32_MASK, PseudoVFCVT_RM_F_X_V_M2_E32, 0x2 }, // 383 { PseudoVFCVT_RM_F_X_V_M2_E64_MASK, PseudoVFCVT_RM_F_X_V_M2_E64, 0x2 }, // 384 { PseudoVFCVT_RM_F_X_V_M4_E16_MASK, PseudoVFCVT_RM_F_X_V_M4_E16, 0x2 }, // 385 { PseudoVFCVT_RM_F_X_V_M4_E32_MASK, PseudoVFCVT_RM_F_X_V_M4_E32, 0x2 }, // 386 { PseudoVFCVT_RM_F_X_V_M4_E64_MASK, PseudoVFCVT_RM_F_X_V_M4_E64, 0x2 }, // 387 { PseudoVFCVT_RM_F_X_V_M8_E16_MASK, PseudoVFCVT_RM_F_X_V_M8_E16, 0x2 }, // 388 { PseudoVFCVT_RM_F_X_V_M8_E32_MASK, PseudoVFCVT_RM_F_X_V_M8_E32, 0x2 }, // 389 { PseudoVFCVT_RM_F_X_V_M8_E64_MASK, PseudoVFCVT_RM_F_X_V_M8_E64, 0x2 }, // 390 { PseudoVFCVT_RM_F_X_V_MF2_E16_MASK, PseudoVFCVT_RM_F_X_V_MF2_E16, 0x2 }, // 391 { PseudoVFCVT_RM_F_X_V_MF2_E32_MASK, PseudoVFCVT_RM_F_X_V_MF2_E32, 0x2 }, // 392 { PseudoVFCVT_RM_F_X_V_MF4_E16_MASK, PseudoVFCVT_RM_F_X_V_MF4_E16, 0x2 }, // 393 { PseudoVFCVT_RM_XU_F_V_M1_MASK, PseudoVFCVT_RM_XU_F_V_M1, 0x2 }, // 394 { PseudoVFCVT_RM_XU_F_V_M2_MASK, PseudoVFCVT_RM_XU_F_V_M2, 0x2 }, // 395 { PseudoVFCVT_RM_XU_F_V_M4_MASK, PseudoVFCVT_RM_XU_F_V_M4, 0x2 }, // 396 { PseudoVFCVT_RM_XU_F_V_M8_MASK, PseudoVFCVT_RM_XU_F_V_M8, 0x2 }, // 397 { PseudoVFCVT_RM_XU_F_V_MF2_MASK, PseudoVFCVT_RM_XU_F_V_MF2, 0x2 }, // 398 { PseudoVFCVT_RM_XU_F_V_MF4_MASK, PseudoVFCVT_RM_XU_F_V_MF4, 0x2 }, // 399 { PseudoVFCVT_RM_X_F_V_M1_MASK, PseudoVFCVT_RM_X_F_V_M1, 0x2 }, // 400 { PseudoVFCVT_RM_X_F_V_M2_MASK, PseudoVFCVT_RM_X_F_V_M2, 0x2 }, // 401 { PseudoVFCVT_RM_X_F_V_M4_MASK, PseudoVFCVT_RM_X_F_V_M4, 0x2 }, // 402 { PseudoVFCVT_RM_X_F_V_M8_MASK, PseudoVFCVT_RM_X_F_V_M8, 0x2 }, // 403 { PseudoVFCVT_RM_X_F_V_MF2_MASK, PseudoVFCVT_RM_X_F_V_MF2, 0x2 }, // 404 { PseudoVFCVT_RM_X_F_V_MF4_MASK, PseudoVFCVT_RM_X_F_V_MF4, 0x2 }, // 405 { PseudoVFCVT_RTZ_XU_F_V_M1_MASK, PseudoVFCVT_RTZ_XU_F_V_M1, 0x2 }, // 406 { PseudoVFCVT_RTZ_XU_F_V_M2_MASK, PseudoVFCVT_RTZ_XU_F_V_M2, 0x2 }, // 407 { PseudoVFCVT_RTZ_XU_F_V_M4_MASK, PseudoVFCVT_RTZ_XU_F_V_M4, 0x2 }, // 408 { PseudoVFCVT_RTZ_XU_F_V_M8_MASK, PseudoVFCVT_RTZ_XU_F_V_M8, 0x2 }, // 409 { PseudoVFCVT_RTZ_XU_F_V_MF2_MASK, PseudoVFCVT_RTZ_XU_F_V_MF2, 0x2 }, // 410 { PseudoVFCVT_RTZ_XU_F_V_MF4_MASK, PseudoVFCVT_RTZ_XU_F_V_MF4, 0x2 }, // 411 { PseudoVFCVT_RTZ_X_F_V_M1_MASK, PseudoVFCVT_RTZ_X_F_V_M1, 0x2 }, // 412 { PseudoVFCVT_RTZ_X_F_V_M2_MASK, PseudoVFCVT_RTZ_X_F_V_M2, 0x2 }, // 413 { PseudoVFCVT_RTZ_X_F_V_M4_MASK, PseudoVFCVT_RTZ_X_F_V_M4, 0x2 }, // 414 { PseudoVFCVT_RTZ_X_F_V_M8_MASK, PseudoVFCVT_RTZ_X_F_V_M8, 0x2 }, // 415 { PseudoVFCVT_RTZ_X_F_V_MF2_MASK, PseudoVFCVT_RTZ_X_F_V_MF2, 0x2 }, // 416 { PseudoVFCVT_RTZ_X_F_V_MF4_MASK, PseudoVFCVT_RTZ_X_F_V_MF4, 0x2 }, // 417 { PseudoVFCVT_XU_F_V_M1_MASK, PseudoVFCVT_XU_F_V_M1, 0x2 }, // 418 { PseudoVFCVT_XU_F_V_M2_MASK, PseudoVFCVT_XU_F_V_M2, 0x2 }, // 419 { PseudoVFCVT_XU_F_V_M4_MASK, PseudoVFCVT_XU_F_V_M4, 0x2 }, // 420 { PseudoVFCVT_XU_F_V_M8_MASK, PseudoVFCVT_XU_F_V_M8, 0x2 }, // 421 { PseudoVFCVT_XU_F_V_MF2_MASK, PseudoVFCVT_XU_F_V_MF2, 0x2 }, // 422 { PseudoVFCVT_XU_F_V_MF4_MASK, PseudoVFCVT_XU_F_V_MF4, 0x2 }, // 423 { PseudoVFCVT_X_F_V_M1_MASK, PseudoVFCVT_X_F_V_M1, 0x2 }, // 424 { PseudoVFCVT_X_F_V_M2_MASK, PseudoVFCVT_X_F_V_M2, 0x2 }, // 425 { PseudoVFCVT_X_F_V_M4_MASK, PseudoVFCVT_X_F_V_M4, 0x2 }, // 426 { PseudoVFCVT_X_F_V_M8_MASK, PseudoVFCVT_X_F_V_M8, 0x2 }, // 427 { PseudoVFCVT_X_F_V_MF2_MASK, PseudoVFCVT_X_F_V_MF2, 0x2 }, // 428 { PseudoVFCVT_X_F_V_MF4_MASK, PseudoVFCVT_X_F_V_MF4, 0x2 }, // 429 { PseudoVFDIV_VFPR16_M1_E16_MASK, PseudoVFDIV_VFPR16_M1_E16, 0x3 }, // 430 { PseudoVFDIV_VFPR16_M2_E16_MASK, PseudoVFDIV_VFPR16_M2_E16, 0x3 }, // 431 { PseudoVFDIV_VFPR16_M4_E16_MASK, PseudoVFDIV_VFPR16_M4_E16, 0x3 }, // 432 { PseudoVFDIV_VFPR16_M8_E16_MASK, PseudoVFDIV_VFPR16_M8_E16, 0x3 }, // 433 { PseudoVFDIV_VFPR16_MF2_E16_MASK, PseudoVFDIV_VFPR16_MF2_E16, 0x3 }, // 434 { PseudoVFDIV_VFPR16_MF4_E16_MASK, PseudoVFDIV_VFPR16_MF4_E16, 0x3 }, // 435 { PseudoVFDIV_VFPR32_M1_E32_MASK, PseudoVFDIV_VFPR32_M1_E32, 0x3 }, // 436 { PseudoVFDIV_VFPR32_M2_E32_MASK, PseudoVFDIV_VFPR32_M2_E32, 0x3 }, // 437 { PseudoVFDIV_VFPR32_M4_E32_MASK, PseudoVFDIV_VFPR32_M4_E32, 0x3 }, // 438 { PseudoVFDIV_VFPR32_M8_E32_MASK, PseudoVFDIV_VFPR32_M8_E32, 0x3 }, // 439 { PseudoVFDIV_VFPR32_MF2_E32_MASK, PseudoVFDIV_VFPR32_MF2_E32, 0x3 }, // 440 { PseudoVFDIV_VFPR64_M1_E64_MASK, PseudoVFDIV_VFPR64_M1_E64, 0x3 }, // 441 { PseudoVFDIV_VFPR64_M2_E64_MASK, PseudoVFDIV_VFPR64_M2_E64, 0x3 }, // 442 { PseudoVFDIV_VFPR64_M4_E64_MASK, PseudoVFDIV_VFPR64_M4_E64, 0x3 }, // 443 { PseudoVFDIV_VFPR64_M8_E64_MASK, PseudoVFDIV_VFPR64_M8_E64, 0x3 }, // 444 { PseudoVFDIV_VV_M1_E16_MASK, PseudoVFDIV_VV_M1_E16, 0x3 }, // 445 { PseudoVFDIV_VV_M1_E32_MASK, PseudoVFDIV_VV_M1_E32, 0x3 }, // 446 { PseudoVFDIV_VV_M1_E64_MASK, PseudoVFDIV_VV_M1_E64, 0x3 }, // 447 { PseudoVFDIV_VV_M2_E16_MASK, PseudoVFDIV_VV_M2_E16, 0x3 }, // 448 { PseudoVFDIV_VV_M2_E32_MASK, PseudoVFDIV_VV_M2_E32, 0x3 }, // 449 { PseudoVFDIV_VV_M2_E64_MASK, PseudoVFDIV_VV_M2_E64, 0x3 }, // 450 { PseudoVFDIV_VV_M4_E16_MASK, PseudoVFDIV_VV_M4_E16, 0x3 }, // 451 { PseudoVFDIV_VV_M4_E32_MASK, PseudoVFDIV_VV_M4_E32, 0x3 }, // 452 { PseudoVFDIV_VV_M4_E64_MASK, PseudoVFDIV_VV_M4_E64, 0x3 }, // 453 { PseudoVFDIV_VV_M8_E16_MASK, PseudoVFDIV_VV_M8_E16, 0x3 }, // 454 { PseudoVFDIV_VV_M8_E32_MASK, PseudoVFDIV_VV_M8_E32, 0x3 }, // 455 { PseudoVFDIV_VV_M8_E64_MASK, PseudoVFDIV_VV_M8_E64, 0x3 }, // 456 { PseudoVFDIV_VV_MF2_E16_MASK, PseudoVFDIV_VV_MF2_E16, 0x3 }, // 457 { PseudoVFDIV_VV_MF2_E32_MASK, PseudoVFDIV_VV_MF2_E32, 0x3 }, // 458 { PseudoVFDIV_VV_MF4_E16_MASK, PseudoVFDIV_VV_MF4_E16, 0x3 }, // 459 { PseudoVFMACC_VFPR16_M1_E16_MASK, PseudoVFMACC_VFPR16_M1_E16, 0x3 }, // 460 { PseudoVFMACC_VFPR16_M2_E16_MASK, PseudoVFMACC_VFPR16_M2_E16, 0x3 }, // 461 { PseudoVFMACC_VFPR16_M4_E16_MASK, PseudoVFMACC_VFPR16_M4_E16, 0x3 }, // 462 { PseudoVFMACC_VFPR16_M8_E16_MASK, PseudoVFMACC_VFPR16_M8_E16, 0x3 }, // 463 { PseudoVFMACC_VFPR16_MF2_E16_MASK, PseudoVFMACC_VFPR16_MF2_E16, 0x3 }, // 464 { PseudoVFMACC_VFPR16_MF4_E16_MASK, PseudoVFMACC_VFPR16_MF4_E16, 0x3 }, // 465 { PseudoVFMACC_VFPR32_M1_E32_MASK, PseudoVFMACC_VFPR32_M1_E32, 0x3 }, // 466 { PseudoVFMACC_VFPR32_M2_E32_MASK, PseudoVFMACC_VFPR32_M2_E32, 0x3 }, // 467 { PseudoVFMACC_VFPR32_M4_E32_MASK, PseudoVFMACC_VFPR32_M4_E32, 0x3 }, // 468 { PseudoVFMACC_VFPR32_M8_E32_MASK, PseudoVFMACC_VFPR32_M8_E32, 0x3 }, // 469 { PseudoVFMACC_VFPR32_MF2_E32_MASK, PseudoVFMACC_VFPR32_MF2_E32, 0x3 }, // 470 { PseudoVFMACC_VFPR64_M1_E64_MASK, PseudoVFMACC_VFPR64_M1_E64, 0x3 }, // 471 { PseudoVFMACC_VFPR64_M2_E64_MASK, PseudoVFMACC_VFPR64_M2_E64, 0x3 }, // 472 { PseudoVFMACC_VFPR64_M4_E64_MASK, PseudoVFMACC_VFPR64_M4_E64, 0x3 }, // 473 { PseudoVFMACC_VFPR64_M8_E64_MASK, PseudoVFMACC_VFPR64_M8_E64, 0x3 }, // 474 { PseudoVFMACC_VV_M1_E16_MASK, PseudoVFMACC_VV_M1_E16, 0x3 }, // 475 { PseudoVFMACC_VV_M1_E32_MASK, PseudoVFMACC_VV_M1_E32, 0x3 }, // 476 { PseudoVFMACC_VV_M1_E64_MASK, PseudoVFMACC_VV_M1_E64, 0x3 }, // 477 { PseudoVFMACC_VV_M2_E16_MASK, PseudoVFMACC_VV_M2_E16, 0x3 }, // 478 { PseudoVFMACC_VV_M2_E32_MASK, PseudoVFMACC_VV_M2_E32, 0x3 }, // 479 { PseudoVFMACC_VV_M2_E64_MASK, PseudoVFMACC_VV_M2_E64, 0x3 }, // 480 { PseudoVFMACC_VV_M4_E16_MASK, PseudoVFMACC_VV_M4_E16, 0x3 }, // 481 { PseudoVFMACC_VV_M4_E32_MASK, PseudoVFMACC_VV_M4_E32, 0x3 }, // 482 { PseudoVFMACC_VV_M4_E64_MASK, PseudoVFMACC_VV_M4_E64, 0x3 }, // 483 { PseudoVFMACC_VV_M8_E16_MASK, PseudoVFMACC_VV_M8_E16, 0x3 }, // 484 { PseudoVFMACC_VV_M8_E32_MASK, PseudoVFMACC_VV_M8_E32, 0x3 }, // 485 { PseudoVFMACC_VV_M8_E64_MASK, PseudoVFMACC_VV_M8_E64, 0x3 }, // 486 { PseudoVFMACC_VV_MF2_E16_MASK, PseudoVFMACC_VV_MF2_E16, 0x3 }, // 487 { PseudoVFMACC_VV_MF2_E32_MASK, PseudoVFMACC_VV_MF2_E32, 0x3 }, // 488 { PseudoVFMACC_VV_MF4_E16_MASK, PseudoVFMACC_VV_MF4_E16, 0x3 }, // 489 { PseudoVFMADD_VFPR16_M1_E16_MASK, PseudoVFMADD_VFPR16_M1_E16, 0x3 }, // 490 { PseudoVFMADD_VFPR16_M2_E16_MASK, PseudoVFMADD_VFPR16_M2_E16, 0x3 }, // 491 { PseudoVFMADD_VFPR16_M4_E16_MASK, PseudoVFMADD_VFPR16_M4_E16, 0x3 }, // 492 { PseudoVFMADD_VFPR16_M8_E16_MASK, PseudoVFMADD_VFPR16_M8_E16, 0x3 }, // 493 { PseudoVFMADD_VFPR16_MF2_E16_MASK, PseudoVFMADD_VFPR16_MF2_E16, 0x3 }, // 494 { PseudoVFMADD_VFPR16_MF4_E16_MASK, PseudoVFMADD_VFPR16_MF4_E16, 0x3 }, // 495 { PseudoVFMADD_VFPR32_M1_E32_MASK, PseudoVFMADD_VFPR32_M1_E32, 0x3 }, // 496 { PseudoVFMADD_VFPR32_M2_E32_MASK, PseudoVFMADD_VFPR32_M2_E32, 0x3 }, // 497 { PseudoVFMADD_VFPR32_M4_E32_MASK, PseudoVFMADD_VFPR32_M4_E32, 0x3 }, // 498 { PseudoVFMADD_VFPR32_M8_E32_MASK, PseudoVFMADD_VFPR32_M8_E32, 0x3 }, // 499 { PseudoVFMADD_VFPR32_MF2_E32_MASK, PseudoVFMADD_VFPR32_MF2_E32, 0x3 }, // 500 { PseudoVFMADD_VFPR64_M1_E64_MASK, PseudoVFMADD_VFPR64_M1_E64, 0x3 }, // 501 { PseudoVFMADD_VFPR64_M2_E64_MASK, PseudoVFMADD_VFPR64_M2_E64, 0x3 }, // 502 { PseudoVFMADD_VFPR64_M4_E64_MASK, PseudoVFMADD_VFPR64_M4_E64, 0x3 }, // 503 { PseudoVFMADD_VFPR64_M8_E64_MASK, PseudoVFMADD_VFPR64_M8_E64, 0x3 }, // 504 { PseudoVFMADD_VV_M1_E16_MASK, PseudoVFMADD_VV_M1_E16, 0x3 }, // 505 { PseudoVFMADD_VV_M1_E32_MASK, PseudoVFMADD_VV_M1_E32, 0x3 }, // 506 { PseudoVFMADD_VV_M1_E64_MASK, PseudoVFMADD_VV_M1_E64, 0x3 }, // 507 { PseudoVFMADD_VV_M2_E16_MASK, PseudoVFMADD_VV_M2_E16, 0x3 }, // 508 { PseudoVFMADD_VV_M2_E32_MASK, PseudoVFMADD_VV_M2_E32, 0x3 }, // 509 { PseudoVFMADD_VV_M2_E64_MASK, PseudoVFMADD_VV_M2_E64, 0x3 }, // 510 { PseudoVFMADD_VV_M4_E16_MASK, PseudoVFMADD_VV_M4_E16, 0x3 }, // 511 { PseudoVFMADD_VV_M4_E32_MASK, PseudoVFMADD_VV_M4_E32, 0x3 }, // 512 { PseudoVFMADD_VV_M4_E64_MASK, PseudoVFMADD_VV_M4_E64, 0x3 }, // 513 { PseudoVFMADD_VV_M8_E16_MASK, PseudoVFMADD_VV_M8_E16, 0x3 }, // 514 { PseudoVFMADD_VV_M8_E32_MASK, PseudoVFMADD_VV_M8_E32, 0x3 }, // 515 { PseudoVFMADD_VV_M8_E64_MASK, PseudoVFMADD_VV_M8_E64, 0x3 }, // 516 { PseudoVFMADD_VV_MF2_E16_MASK, PseudoVFMADD_VV_MF2_E16, 0x3 }, // 517 { PseudoVFMADD_VV_MF2_E32_MASK, PseudoVFMADD_VV_MF2_E32, 0x3 }, // 518 { PseudoVFMADD_VV_MF4_E16_MASK, PseudoVFMADD_VV_MF4_E16, 0x3 }, // 519 { PseudoVFMAX_VFPR16_M1_E16_MASK, PseudoVFMAX_VFPR16_M1_E16, 0x3 }, // 520 { PseudoVFMAX_VFPR16_M2_E16_MASK, PseudoVFMAX_VFPR16_M2_E16, 0x3 }, // 521 { PseudoVFMAX_VFPR16_M4_E16_MASK, PseudoVFMAX_VFPR16_M4_E16, 0x3 }, // 522 { PseudoVFMAX_VFPR16_M8_E16_MASK, PseudoVFMAX_VFPR16_M8_E16, 0x3 }, // 523 { PseudoVFMAX_VFPR16_MF2_E16_MASK, PseudoVFMAX_VFPR16_MF2_E16, 0x3 }, // 524 { PseudoVFMAX_VFPR16_MF4_E16_MASK, PseudoVFMAX_VFPR16_MF4_E16, 0x3 }, // 525 { PseudoVFMAX_VFPR32_M1_E32_MASK, PseudoVFMAX_VFPR32_M1_E32, 0x3 }, // 526 { PseudoVFMAX_VFPR32_M2_E32_MASK, PseudoVFMAX_VFPR32_M2_E32, 0x3 }, // 527 { PseudoVFMAX_VFPR32_M4_E32_MASK, PseudoVFMAX_VFPR32_M4_E32, 0x3 }, // 528 { PseudoVFMAX_VFPR32_M8_E32_MASK, PseudoVFMAX_VFPR32_M8_E32, 0x3 }, // 529 { PseudoVFMAX_VFPR32_MF2_E32_MASK, PseudoVFMAX_VFPR32_MF2_E32, 0x3 }, // 530 { PseudoVFMAX_VFPR64_M1_E64_MASK, PseudoVFMAX_VFPR64_M1_E64, 0x3 }, // 531 { PseudoVFMAX_VFPR64_M2_E64_MASK, PseudoVFMAX_VFPR64_M2_E64, 0x3 }, // 532 { PseudoVFMAX_VFPR64_M4_E64_MASK, PseudoVFMAX_VFPR64_M4_E64, 0x3 }, // 533 { PseudoVFMAX_VFPR64_M8_E64_MASK, PseudoVFMAX_VFPR64_M8_E64, 0x3 }, // 534 { PseudoVFMAX_VV_M1_E16_MASK, PseudoVFMAX_VV_M1_E16, 0x3 }, // 535 { PseudoVFMAX_VV_M1_E32_MASK, PseudoVFMAX_VV_M1_E32, 0x3 }, // 536 { PseudoVFMAX_VV_M1_E64_MASK, PseudoVFMAX_VV_M1_E64, 0x3 }, // 537 { PseudoVFMAX_VV_M2_E16_MASK, PseudoVFMAX_VV_M2_E16, 0x3 }, // 538 { PseudoVFMAX_VV_M2_E32_MASK, PseudoVFMAX_VV_M2_E32, 0x3 }, // 539 { PseudoVFMAX_VV_M2_E64_MASK, PseudoVFMAX_VV_M2_E64, 0x3 }, // 540 { PseudoVFMAX_VV_M4_E16_MASK, PseudoVFMAX_VV_M4_E16, 0x3 }, // 541 { PseudoVFMAX_VV_M4_E32_MASK, PseudoVFMAX_VV_M4_E32, 0x3 }, // 542 { PseudoVFMAX_VV_M4_E64_MASK, PseudoVFMAX_VV_M4_E64, 0x3 }, // 543 { PseudoVFMAX_VV_M8_E16_MASK, PseudoVFMAX_VV_M8_E16, 0x3 }, // 544 { PseudoVFMAX_VV_M8_E32_MASK, PseudoVFMAX_VV_M8_E32, 0x3 }, // 545 { PseudoVFMAX_VV_M8_E64_MASK, PseudoVFMAX_VV_M8_E64, 0x3 }, // 546 { PseudoVFMAX_VV_MF2_E16_MASK, PseudoVFMAX_VV_MF2_E16, 0x3 }, // 547 { PseudoVFMAX_VV_MF2_E32_MASK, PseudoVFMAX_VV_MF2_E32, 0x3 }, // 548 { PseudoVFMAX_VV_MF4_E16_MASK, PseudoVFMAX_VV_MF4_E16, 0x3 }, // 549 { PseudoVFMIN_VFPR16_M1_E16_MASK, PseudoVFMIN_VFPR16_M1_E16, 0x3 }, // 550 { PseudoVFMIN_VFPR16_M2_E16_MASK, PseudoVFMIN_VFPR16_M2_E16, 0x3 }, // 551 { PseudoVFMIN_VFPR16_M4_E16_MASK, PseudoVFMIN_VFPR16_M4_E16, 0x3 }, // 552 { PseudoVFMIN_VFPR16_M8_E16_MASK, PseudoVFMIN_VFPR16_M8_E16, 0x3 }, // 553 { PseudoVFMIN_VFPR16_MF2_E16_MASK, PseudoVFMIN_VFPR16_MF2_E16, 0x3 }, // 554 { PseudoVFMIN_VFPR16_MF4_E16_MASK, PseudoVFMIN_VFPR16_MF4_E16, 0x3 }, // 555 { PseudoVFMIN_VFPR32_M1_E32_MASK, PseudoVFMIN_VFPR32_M1_E32, 0x3 }, // 556 { PseudoVFMIN_VFPR32_M2_E32_MASK, PseudoVFMIN_VFPR32_M2_E32, 0x3 }, // 557 { PseudoVFMIN_VFPR32_M4_E32_MASK, PseudoVFMIN_VFPR32_M4_E32, 0x3 }, // 558 { PseudoVFMIN_VFPR32_M8_E32_MASK, PseudoVFMIN_VFPR32_M8_E32, 0x3 }, // 559 { PseudoVFMIN_VFPR32_MF2_E32_MASK, PseudoVFMIN_VFPR32_MF2_E32, 0x3 }, // 560 { PseudoVFMIN_VFPR64_M1_E64_MASK, PseudoVFMIN_VFPR64_M1_E64, 0x3 }, // 561 { PseudoVFMIN_VFPR64_M2_E64_MASK, PseudoVFMIN_VFPR64_M2_E64, 0x3 }, // 562 { PseudoVFMIN_VFPR64_M4_E64_MASK, PseudoVFMIN_VFPR64_M4_E64, 0x3 }, // 563 { PseudoVFMIN_VFPR64_M8_E64_MASK, PseudoVFMIN_VFPR64_M8_E64, 0x3 }, // 564 { PseudoVFMIN_VV_M1_E16_MASK, PseudoVFMIN_VV_M1_E16, 0x3 }, // 565 { PseudoVFMIN_VV_M1_E32_MASK, PseudoVFMIN_VV_M1_E32, 0x3 }, // 566 { PseudoVFMIN_VV_M1_E64_MASK, PseudoVFMIN_VV_M1_E64, 0x3 }, // 567 { PseudoVFMIN_VV_M2_E16_MASK, PseudoVFMIN_VV_M2_E16, 0x3 }, // 568 { PseudoVFMIN_VV_M2_E32_MASK, PseudoVFMIN_VV_M2_E32, 0x3 }, // 569 { PseudoVFMIN_VV_M2_E64_MASK, PseudoVFMIN_VV_M2_E64, 0x3 }, // 570 { PseudoVFMIN_VV_M4_E16_MASK, PseudoVFMIN_VV_M4_E16, 0x3 }, // 571 { PseudoVFMIN_VV_M4_E32_MASK, PseudoVFMIN_VV_M4_E32, 0x3 }, // 572 { PseudoVFMIN_VV_M4_E64_MASK, PseudoVFMIN_VV_M4_E64, 0x3 }, // 573 { PseudoVFMIN_VV_M8_E16_MASK, PseudoVFMIN_VV_M8_E16, 0x3 }, // 574 { PseudoVFMIN_VV_M8_E32_MASK, PseudoVFMIN_VV_M8_E32, 0x3 }, // 575 { PseudoVFMIN_VV_M8_E64_MASK, PseudoVFMIN_VV_M8_E64, 0x3 }, // 576 { PseudoVFMIN_VV_MF2_E16_MASK, PseudoVFMIN_VV_MF2_E16, 0x3 }, // 577 { PseudoVFMIN_VV_MF2_E32_MASK, PseudoVFMIN_VV_MF2_E32, 0x3 }, // 578 { PseudoVFMIN_VV_MF4_E16_MASK, PseudoVFMIN_VV_MF4_E16, 0x3 }, // 579 { PseudoVFMSAC_VFPR16_M1_E16_MASK, PseudoVFMSAC_VFPR16_M1_E16, 0x3 }, // 580 { PseudoVFMSAC_VFPR16_M2_E16_MASK, PseudoVFMSAC_VFPR16_M2_E16, 0x3 }, // 581 { PseudoVFMSAC_VFPR16_M4_E16_MASK, PseudoVFMSAC_VFPR16_M4_E16, 0x3 }, // 582 { PseudoVFMSAC_VFPR16_M8_E16_MASK, PseudoVFMSAC_VFPR16_M8_E16, 0x3 }, // 583 { PseudoVFMSAC_VFPR16_MF2_E16_MASK, PseudoVFMSAC_VFPR16_MF2_E16, 0x3 }, // 584 { PseudoVFMSAC_VFPR16_MF4_E16_MASK, PseudoVFMSAC_VFPR16_MF4_E16, 0x3 }, // 585 { PseudoVFMSAC_VFPR32_M1_E32_MASK, PseudoVFMSAC_VFPR32_M1_E32, 0x3 }, // 586 { PseudoVFMSAC_VFPR32_M2_E32_MASK, PseudoVFMSAC_VFPR32_M2_E32, 0x3 }, // 587 { PseudoVFMSAC_VFPR32_M4_E32_MASK, PseudoVFMSAC_VFPR32_M4_E32, 0x3 }, // 588 { PseudoVFMSAC_VFPR32_M8_E32_MASK, PseudoVFMSAC_VFPR32_M8_E32, 0x3 }, // 589 { PseudoVFMSAC_VFPR32_MF2_E32_MASK, PseudoVFMSAC_VFPR32_MF2_E32, 0x3 }, // 590 { PseudoVFMSAC_VFPR64_M1_E64_MASK, PseudoVFMSAC_VFPR64_M1_E64, 0x3 }, // 591 { PseudoVFMSAC_VFPR64_M2_E64_MASK, PseudoVFMSAC_VFPR64_M2_E64, 0x3 }, // 592 { PseudoVFMSAC_VFPR64_M4_E64_MASK, PseudoVFMSAC_VFPR64_M4_E64, 0x3 }, // 593 { PseudoVFMSAC_VFPR64_M8_E64_MASK, PseudoVFMSAC_VFPR64_M8_E64, 0x3 }, // 594 { PseudoVFMSAC_VV_M1_E16_MASK, PseudoVFMSAC_VV_M1_E16, 0x3 }, // 595 { PseudoVFMSAC_VV_M1_E32_MASK, PseudoVFMSAC_VV_M1_E32, 0x3 }, // 596 { PseudoVFMSAC_VV_M1_E64_MASK, PseudoVFMSAC_VV_M1_E64, 0x3 }, // 597 { PseudoVFMSAC_VV_M2_E16_MASK, PseudoVFMSAC_VV_M2_E16, 0x3 }, // 598 { PseudoVFMSAC_VV_M2_E32_MASK, PseudoVFMSAC_VV_M2_E32, 0x3 }, // 599 { PseudoVFMSAC_VV_M2_E64_MASK, PseudoVFMSAC_VV_M2_E64, 0x3 }, // 600 { PseudoVFMSAC_VV_M4_E16_MASK, PseudoVFMSAC_VV_M4_E16, 0x3 }, // 601 { PseudoVFMSAC_VV_M4_E32_MASK, PseudoVFMSAC_VV_M4_E32, 0x3 }, // 602 { PseudoVFMSAC_VV_M4_E64_MASK, PseudoVFMSAC_VV_M4_E64, 0x3 }, // 603 { PseudoVFMSAC_VV_M8_E16_MASK, PseudoVFMSAC_VV_M8_E16, 0x3 }, // 604 { PseudoVFMSAC_VV_M8_E32_MASK, PseudoVFMSAC_VV_M8_E32, 0x3 }, // 605 { PseudoVFMSAC_VV_M8_E64_MASK, PseudoVFMSAC_VV_M8_E64, 0x3 }, // 606 { PseudoVFMSAC_VV_MF2_E16_MASK, PseudoVFMSAC_VV_MF2_E16, 0x3 }, // 607 { PseudoVFMSAC_VV_MF2_E32_MASK, PseudoVFMSAC_VV_MF2_E32, 0x3 }, // 608 { PseudoVFMSAC_VV_MF4_E16_MASK, PseudoVFMSAC_VV_MF4_E16, 0x3 }, // 609 { PseudoVFMSUB_VFPR16_M1_E16_MASK, PseudoVFMSUB_VFPR16_M1_E16, 0x3 }, // 610 { PseudoVFMSUB_VFPR16_M2_E16_MASK, PseudoVFMSUB_VFPR16_M2_E16, 0x3 }, // 611 { PseudoVFMSUB_VFPR16_M4_E16_MASK, PseudoVFMSUB_VFPR16_M4_E16, 0x3 }, // 612 { PseudoVFMSUB_VFPR16_M8_E16_MASK, PseudoVFMSUB_VFPR16_M8_E16, 0x3 }, // 613 { PseudoVFMSUB_VFPR16_MF2_E16_MASK, PseudoVFMSUB_VFPR16_MF2_E16, 0x3 }, // 614 { PseudoVFMSUB_VFPR16_MF4_E16_MASK, PseudoVFMSUB_VFPR16_MF4_E16, 0x3 }, // 615 { PseudoVFMSUB_VFPR32_M1_E32_MASK, PseudoVFMSUB_VFPR32_M1_E32, 0x3 }, // 616 { PseudoVFMSUB_VFPR32_M2_E32_MASK, PseudoVFMSUB_VFPR32_M2_E32, 0x3 }, // 617 { PseudoVFMSUB_VFPR32_M4_E32_MASK, PseudoVFMSUB_VFPR32_M4_E32, 0x3 }, // 618 { PseudoVFMSUB_VFPR32_M8_E32_MASK, PseudoVFMSUB_VFPR32_M8_E32, 0x3 }, // 619 { PseudoVFMSUB_VFPR32_MF2_E32_MASK, PseudoVFMSUB_VFPR32_MF2_E32, 0x3 }, // 620 { PseudoVFMSUB_VFPR64_M1_E64_MASK, PseudoVFMSUB_VFPR64_M1_E64, 0x3 }, // 621 { PseudoVFMSUB_VFPR64_M2_E64_MASK, PseudoVFMSUB_VFPR64_M2_E64, 0x3 }, // 622 { PseudoVFMSUB_VFPR64_M4_E64_MASK, PseudoVFMSUB_VFPR64_M4_E64, 0x3 }, // 623 { PseudoVFMSUB_VFPR64_M8_E64_MASK, PseudoVFMSUB_VFPR64_M8_E64, 0x3 }, // 624 { PseudoVFMSUB_VV_M1_E16_MASK, PseudoVFMSUB_VV_M1_E16, 0x3 }, // 625 { PseudoVFMSUB_VV_M1_E32_MASK, PseudoVFMSUB_VV_M1_E32, 0x3 }, // 626 { PseudoVFMSUB_VV_M1_E64_MASK, PseudoVFMSUB_VV_M1_E64, 0x3 }, // 627 { PseudoVFMSUB_VV_M2_E16_MASK, PseudoVFMSUB_VV_M2_E16, 0x3 }, // 628 { PseudoVFMSUB_VV_M2_E32_MASK, PseudoVFMSUB_VV_M2_E32, 0x3 }, // 629 { PseudoVFMSUB_VV_M2_E64_MASK, PseudoVFMSUB_VV_M2_E64, 0x3 }, // 630 { PseudoVFMSUB_VV_M4_E16_MASK, PseudoVFMSUB_VV_M4_E16, 0x3 }, // 631 { PseudoVFMSUB_VV_M4_E32_MASK, PseudoVFMSUB_VV_M4_E32, 0x3 }, // 632 { PseudoVFMSUB_VV_M4_E64_MASK, PseudoVFMSUB_VV_M4_E64, 0x3 }, // 633 { PseudoVFMSUB_VV_M8_E16_MASK, PseudoVFMSUB_VV_M8_E16, 0x3 }, // 634 { PseudoVFMSUB_VV_M8_E32_MASK, PseudoVFMSUB_VV_M8_E32, 0x3 }, // 635 { PseudoVFMSUB_VV_M8_E64_MASK, PseudoVFMSUB_VV_M8_E64, 0x3 }, // 636 { PseudoVFMSUB_VV_MF2_E16_MASK, PseudoVFMSUB_VV_MF2_E16, 0x3 }, // 637 { PseudoVFMSUB_VV_MF2_E32_MASK, PseudoVFMSUB_VV_MF2_E32, 0x3 }, // 638 { PseudoVFMSUB_VV_MF4_E16_MASK, PseudoVFMSUB_VV_MF4_E16, 0x3 }, // 639 { PseudoVFMUL_VFPR16_M1_E16_MASK, PseudoVFMUL_VFPR16_M1_E16, 0x3 }, // 640 { PseudoVFMUL_VFPR16_M2_E16_MASK, PseudoVFMUL_VFPR16_M2_E16, 0x3 }, // 641 { PseudoVFMUL_VFPR16_M4_E16_MASK, PseudoVFMUL_VFPR16_M4_E16, 0x3 }, // 642 { PseudoVFMUL_VFPR16_M8_E16_MASK, PseudoVFMUL_VFPR16_M8_E16, 0x3 }, // 643 { PseudoVFMUL_VFPR16_MF2_E16_MASK, PseudoVFMUL_VFPR16_MF2_E16, 0x3 }, // 644 { PseudoVFMUL_VFPR16_MF4_E16_MASK, PseudoVFMUL_VFPR16_MF4_E16, 0x3 }, // 645 { PseudoVFMUL_VFPR32_M1_E32_MASK, PseudoVFMUL_VFPR32_M1_E32, 0x3 }, // 646 { PseudoVFMUL_VFPR32_M2_E32_MASK, PseudoVFMUL_VFPR32_M2_E32, 0x3 }, // 647 { PseudoVFMUL_VFPR32_M4_E32_MASK, PseudoVFMUL_VFPR32_M4_E32, 0x3 }, // 648 { PseudoVFMUL_VFPR32_M8_E32_MASK, PseudoVFMUL_VFPR32_M8_E32, 0x3 }, // 649 { PseudoVFMUL_VFPR32_MF2_E32_MASK, PseudoVFMUL_VFPR32_MF2_E32, 0x3 }, // 650 { PseudoVFMUL_VFPR64_M1_E64_MASK, PseudoVFMUL_VFPR64_M1_E64, 0x3 }, // 651 { PseudoVFMUL_VFPR64_M2_E64_MASK, PseudoVFMUL_VFPR64_M2_E64, 0x3 }, // 652 { PseudoVFMUL_VFPR64_M4_E64_MASK, PseudoVFMUL_VFPR64_M4_E64, 0x3 }, // 653 { PseudoVFMUL_VFPR64_M8_E64_MASK, PseudoVFMUL_VFPR64_M8_E64, 0x3 }, // 654 { PseudoVFMUL_VV_M1_E16_MASK, PseudoVFMUL_VV_M1_E16, 0x3 }, // 655 { PseudoVFMUL_VV_M1_E32_MASK, PseudoVFMUL_VV_M1_E32, 0x3 }, // 656 { PseudoVFMUL_VV_M1_E64_MASK, PseudoVFMUL_VV_M1_E64, 0x3 }, // 657 { PseudoVFMUL_VV_M2_E16_MASK, PseudoVFMUL_VV_M2_E16, 0x3 }, // 658 { PseudoVFMUL_VV_M2_E32_MASK, PseudoVFMUL_VV_M2_E32, 0x3 }, // 659 { PseudoVFMUL_VV_M2_E64_MASK, PseudoVFMUL_VV_M2_E64, 0x3 }, // 660 { PseudoVFMUL_VV_M4_E16_MASK, PseudoVFMUL_VV_M4_E16, 0x3 }, // 661 { PseudoVFMUL_VV_M4_E32_MASK, PseudoVFMUL_VV_M4_E32, 0x3 }, // 662 { PseudoVFMUL_VV_M4_E64_MASK, PseudoVFMUL_VV_M4_E64, 0x3 }, // 663 { PseudoVFMUL_VV_M8_E16_MASK, PseudoVFMUL_VV_M8_E16, 0x3 }, // 664 { PseudoVFMUL_VV_M8_E32_MASK, PseudoVFMUL_VV_M8_E32, 0x3 }, // 665 { PseudoVFMUL_VV_M8_E64_MASK, PseudoVFMUL_VV_M8_E64, 0x3 }, // 666 { PseudoVFMUL_VV_MF2_E16_MASK, PseudoVFMUL_VV_MF2_E16, 0x3 }, // 667 { PseudoVFMUL_VV_MF2_E32_MASK, PseudoVFMUL_VV_MF2_E32, 0x3 }, // 668 { PseudoVFMUL_VV_MF4_E16_MASK, PseudoVFMUL_VV_MF4_E16, 0x3 }, // 669 { PseudoVFNCVTBF16_F_F_W_M1_E16_MASK, PseudoVFNCVTBF16_F_F_W_M1_E16, 0x2 }, // 670 { PseudoVFNCVTBF16_F_F_W_M1_E32_MASK, PseudoVFNCVTBF16_F_F_W_M1_E32, 0x2 }, // 671 { PseudoVFNCVTBF16_F_F_W_M2_E16_MASK, PseudoVFNCVTBF16_F_F_W_M2_E16, 0x2 }, // 672 { PseudoVFNCVTBF16_F_F_W_M2_E32_MASK, PseudoVFNCVTBF16_F_F_W_M2_E32, 0x2 }, // 673 { PseudoVFNCVTBF16_F_F_W_M4_E16_MASK, PseudoVFNCVTBF16_F_F_W_M4_E16, 0x2 }, // 674 { PseudoVFNCVTBF16_F_F_W_M4_E32_MASK, PseudoVFNCVTBF16_F_F_W_M4_E32, 0x2 }, // 675 { PseudoVFNCVTBF16_F_F_W_MF2_E16_MASK, PseudoVFNCVTBF16_F_F_W_MF2_E16, 0x2 }, // 676 { PseudoVFNCVTBF16_F_F_W_MF2_E32_MASK, PseudoVFNCVTBF16_F_F_W_MF2_E32, 0x2 }, // 677 { PseudoVFNCVTBF16_F_F_W_MF4_E16_MASK, PseudoVFNCVTBF16_F_F_W_MF4_E16, 0x2 }, // 678 { PseudoVFNCVT_F_F_W_M1_E16_MASK, PseudoVFNCVT_F_F_W_M1_E16, 0x2 }, // 679 { PseudoVFNCVT_F_F_W_M1_E32_MASK, PseudoVFNCVT_F_F_W_M1_E32, 0x2 }, // 680 { PseudoVFNCVT_F_F_W_M2_E16_MASK, PseudoVFNCVT_F_F_W_M2_E16, 0x2 }, // 681 { PseudoVFNCVT_F_F_W_M2_E32_MASK, PseudoVFNCVT_F_F_W_M2_E32, 0x2 }, // 682 { PseudoVFNCVT_F_F_W_M4_E16_MASK, PseudoVFNCVT_F_F_W_M4_E16, 0x2 }, // 683 { PseudoVFNCVT_F_F_W_M4_E32_MASK, PseudoVFNCVT_F_F_W_M4_E32, 0x2 }, // 684 { PseudoVFNCVT_F_F_W_MF2_E16_MASK, PseudoVFNCVT_F_F_W_MF2_E16, 0x2 }, // 685 { PseudoVFNCVT_F_F_W_MF2_E32_MASK, PseudoVFNCVT_F_F_W_MF2_E32, 0x2 }, // 686 { PseudoVFNCVT_F_F_W_MF4_E16_MASK, PseudoVFNCVT_F_F_W_MF4_E16, 0x2 }, // 687 { PseudoVFNCVT_F_XU_W_M1_E16_MASK, PseudoVFNCVT_F_XU_W_M1_E16, 0x2 }, // 688 { PseudoVFNCVT_F_XU_W_M1_E32_MASK, PseudoVFNCVT_F_XU_W_M1_E32, 0x2 }, // 689 { PseudoVFNCVT_F_XU_W_M2_E16_MASK, PseudoVFNCVT_F_XU_W_M2_E16, 0x2 }, // 690 { PseudoVFNCVT_F_XU_W_M2_E32_MASK, PseudoVFNCVT_F_XU_W_M2_E32, 0x2 }, // 691 { PseudoVFNCVT_F_XU_W_M4_E16_MASK, PseudoVFNCVT_F_XU_W_M4_E16, 0x2 }, // 692 { PseudoVFNCVT_F_XU_W_M4_E32_MASK, PseudoVFNCVT_F_XU_W_M4_E32, 0x2 }, // 693 { PseudoVFNCVT_F_XU_W_MF2_E16_MASK, PseudoVFNCVT_F_XU_W_MF2_E16, 0x2 }, // 694 { PseudoVFNCVT_F_XU_W_MF2_E32_MASK, PseudoVFNCVT_F_XU_W_MF2_E32, 0x2 }, // 695 { PseudoVFNCVT_F_XU_W_MF4_E16_MASK, PseudoVFNCVT_F_XU_W_MF4_E16, 0x2 }, // 696 { PseudoVFNCVT_F_X_W_M1_E16_MASK, PseudoVFNCVT_F_X_W_M1_E16, 0x2 }, // 697 { PseudoVFNCVT_F_X_W_M1_E32_MASK, PseudoVFNCVT_F_X_W_M1_E32, 0x2 }, // 698 { PseudoVFNCVT_F_X_W_M2_E16_MASK, PseudoVFNCVT_F_X_W_M2_E16, 0x2 }, // 699 { PseudoVFNCVT_F_X_W_M2_E32_MASK, PseudoVFNCVT_F_X_W_M2_E32, 0x2 }, // 700 { PseudoVFNCVT_F_X_W_M4_E16_MASK, PseudoVFNCVT_F_X_W_M4_E16, 0x2 }, // 701 { PseudoVFNCVT_F_X_W_M4_E32_MASK, PseudoVFNCVT_F_X_W_M4_E32, 0x2 }, // 702 { PseudoVFNCVT_F_X_W_MF2_E16_MASK, PseudoVFNCVT_F_X_W_MF2_E16, 0x2 }, // 703 { PseudoVFNCVT_F_X_W_MF2_E32_MASK, PseudoVFNCVT_F_X_W_MF2_E32, 0x2 }, // 704 { PseudoVFNCVT_F_X_W_MF4_E16_MASK, PseudoVFNCVT_F_X_W_MF4_E16, 0x2 }, // 705 { PseudoVFNCVT_RM_F_XU_W_M1_E16_MASK, PseudoVFNCVT_RM_F_XU_W_M1_E16, 0x2 }, // 706 { PseudoVFNCVT_RM_F_XU_W_M1_E32_MASK, PseudoVFNCVT_RM_F_XU_W_M1_E32, 0x2 }, // 707 { PseudoVFNCVT_RM_F_XU_W_M2_E16_MASK, PseudoVFNCVT_RM_F_XU_W_M2_E16, 0x2 }, // 708 { PseudoVFNCVT_RM_F_XU_W_M2_E32_MASK, PseudoVFNCVT_RM_F_XU_W_M2_E32, 0x2 }, // 709 { PseudoVFNCVT_RM_F_XU_W_M4_E16_MASK, PseudoVFNCVT_RM_F_XU_W_M4_E16, 0x2 }, // 710 { PseudoVFNCVT_RM_F_XU_W_M4_E32_MASK, PseudoVFNCVT_RM_F_XU_W_M4_E32, 0x2 }, // 711 { PseudoVFNCVT_RM_F_XU_W_MF2_E16_MASK, PseudoVFNCVT_RM_F_XU_W_MF2_E16, 0x2 }, // 712 { PseudoVFNCVT_RM_F_XU_W_MF2_E32_MASK, PseudoVFNCVT_RM_F_XU_W_MF2_E32, 0x2 }, // 713 { PseudoVFNCVT_RM_F_XU_W_MF4_E16_MASK, PseudoVFNCVT_RM_F_XU_W_MF4_E16, 0x2 }, // 714 { PseudoVFNCVT_RM_F_X_W_M1_E16_MASK, PseudoVFNCVT_RM_F_X_W_M1_E16, 0x2 }, // 715 { PseudoVFNCVT_RM_F_X_W_M1_E32_MASK, PseudoVFNCVT_RM_F_X_W_M1_E32, 0x2 }, // 716 { PseudoVFNCVT_RM_F_X_W_M2_E16_MASK, PseudoVFNCVT_RM_F_X_W_M2_E16, 0x2 }, // 717 { PseudoVFNCVT_RM_F_X_W_M2_E32_MASK, PseudoVFNCVT_RM_F_X_W_M2_E32, 0x2 }, // 718 { PseudoVFNCVT_RM_F_X_W_M4_E16_MASK, PseudoVFNCVT_RM_F_X_W_M4_E16, 0x2 }, // 719 { PseudoVFNCVT_RM_F_X_W_M4_E32_MASK, PseudoVFNCVT_RM_F_X_W_M4_E32, 0x2 }, // 720 { PseudoVFNCVT_RM_F_X_W_MF2_E16_MASK, PseudoVFNCVT_RM_F_X_W_MF2_E16, 0x2 }, // 721 { PseudoVFNCVT_RM_F_X_W_MF2_E32_MASK, PseudoVFNCVT_RM_F_X_W_MF2_E32, 0x2 }, // 722 { PseudoVFNCVT_RM_F_X_W_MF4_E16_MASK, PseudoVFNCVT_RM_F_X_W_MF4_E16, 0x2 }, // 723 { PseudoVFNCVT_RM_XU_F_W_M1_MASK, PseudoVFNCVT_RM_XU_F_W_M1, 0x2 }, // 724 { PseudoVFNCVT_RM_XU_F_W_M2_MASK, PseudoVFNCVT_RM_XU_F_W_M2, 0x2 }, // 725 { PseudoVFNCVT_RM_XU_F_W_M4_MASK, PseudoVFNCVT_RM_XU_F_W_M4, 0x2 }, // 726 { PseudoVFNCVT_RM_XU_F_W_MF2_MASK, PseudoVFNCVT_RM_XU_F_W_MF2, 0x2 }, // 727 { PseudoVFNCVT_RM_XU_F_W_MF4_MASK, PseudoVFNCVT_RM_XU_F_W_MF4, 0x2 }, // 728 { PseudoVFNCVT_RM_XU_F_W_MF8_MASK, PseudoVFNCVT_RM_XU_F_W_MF8, 0x2 }, // 729 { PseudoVFNCVT_RM_X_F_W_M1_MASK, PseudoVFNCVT_RM_X_F_W_M1, 0x2 }, // 730 { PseudoVFNCVT_RM_X_F_W_M2_MASK, PseudoVFNCVT_RM_X_F_W_M2, 0x2 }, // 731 { PseudoVFNCVT_RM_X_F_W_M4_MASK, PseudoVFNCVT_RM_X_F_W_M4, 0x2 }, // 732 { PseudoVFNCVT_RM_X_F_W_MF2_MASK, PseudoVFNCVT_RM_X_F_W_MF2, 0x2 }, // 733 { PseudoVFNCVT_RM_X_F_W_MF4_MASK, PseudoVFNCVT_RM_X_F_W_MF4, 0x2 }, // 734 { PseudoVFNCVT_RM_X_F_W_MF8_MASK, PseudoVFNCVT_RM_X_F_W_MF8, 0x2 }, // 735 { PseudoVFNCVT_ROD_F_F_W_M1_E16_MASK, PseudoVFNCVT_ROD_F_F_W_M1_E16, 0x2 }, // 736 { PseudoVFNCVT_ROD_F_F_W_M1_E32_MASK, PseudoVFNCVT_ROD_F_F_W_M1_E32, 0x2 }, // 737 { PseudoVFNCVT_ROD_F_F_W_M2_E16_MASK, PseudoVFNCVT_ROD_F_F_W_M2_E16, 0x2 }, // 738 { PseudoVFNCVT_ROD_F_F_W_M2_E32_MASK, PseudoVFNCVT_ROD_F_F_W_M2_E32, 0x2 }, // 739 { PseudoVFNCVT_ROD_F_F_W_M4_E16_MASK, PseudoVFNCVT_ROD_F_F_W_M4_E16, 0x2 }, // 740 { PseudoVFNCVT_ROD_F_F_W_M4_E32_MASK, PseudoVFNCVT_ROD_F_F_W_M4_E32, 0x2 }, // 741 { PseudoVFNCVT_ROD_F_F_W_MF2_E16_MASK, PseudoVFNCVT_ROD_F_F_W_MF2_E16, 0x2 }, // 742 { PseudoVFNCVT_ROD_F_F_W_MF2_E32_MASK, PseudoVFNCVT_ROD_F_F_W_MF2_E32, 0x2 }, // 743 { PseudoVFNCVT_ROD_F_F_W_MF4_E16_MASK, PseudoVFNCVT_ROD_F_F_W_MF4_E16, 0x2 }, // 744 { PseudoVFNCVT_RTZ_XU_F_W_M1_MASK, PseudoVFNCVT_RTZ_XU_F_W_M1, 0x2 }, // 745 { PseudoVFNCVT_RTZ_XU_F_W_M2_MASK, PseudoVFNCVT_RTZ_XU_F_W_M2, 0x2 }, // 746 { PseudoVFNCVT_RTZ_XU_F_W_M4_MASK, PseudoVFNCVT_RTZ_XU_F_W_M4, 0x2 }, // 747 { PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK, PseudoVFNCVT_RTZ_XU_F_W_MF2, 0x2 }, // 748 { PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK, PseudoVFNCVT_RTZ_XU_F_W_MF4, 0x2 }, // 749 { PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK, PseudoVFNCVT_RTZ_XU_F_W_MF8, 0x2 }, // 750 { PseudoVFNCVT_RTZ_X_F_W_M1_MASK, PseudoVFNCVT_RTZ_X_F_W_M1, 0x2 }, // 751 { PseudoVFNCVT_RTZ_X_F_W_M2_MASK, PseudoVFNCVT_RTZ_X_F_W_M2, 0x2 }, // 752 { PseudoVFNCVT_RTZ_X_F_W_M4_MASK, PseudoVFNCVT_RTZ_X_F_W_M4, 0x2 }, // 753 { PseudoVFNCVT_RTZ_X_F_W_MF2_MASK, PseudoVFNCVT_RTZ_X_F_W_MF2, 0x2 }, // 754 { PseudoVFNCVT_RTZ_X_F_W_MF4_MASK, PseudoVFNCVT_RTZ_X_F_W_MF4, 0x2 }, // 755 { PseudoVFNCVT_RTZ_X_F_W_MF8_MASK, PseudoVFNCVT_RTZ_X_F_W_MF8, 0x2 }, // 756 { PseudoVFNCVT_XU_F_W_M1_MASK, PseudoVFNCVT_XU_F_W_M1, 0x2 }, // 757 { PseudoVFNCVT_XU_F_W_M2_MASK, PseudoVFNCVT_XU_F_W_M2, 0x2 }, // 758 { PseudoVFNCVT_XU_F_W_M4_MASK, PseudoVFNCVT_XU_F_W_M4, 0x2 }, // 759 { PseudoVFNCVT_XU_F_W_MF2_MASK, PseudoVFNCVT_XU_F_W_MF2, 0x2 }, // 760 { PseudoVFNCVT_XU_F_W_MF4_MASK, PseudoVFNCVT_XU_F_W_MF4, 0x2 }, // 761 { PseudoVFNCVT_XU_F_W_MF8_MASK, PseudoVFNCVT_XU_F_W_MF8, 0x2 }, // 762 { PseudoVFNCVT_X_F_W_M1_MASK, PseudoVFNCVT_X_F_W_M1, 0x2 }, // 763 { PseudoVFNCVT_X_F_W_M2_MASK, PseudoVFNCVT_X_F_W_M2, 0x2 }, // 764 { PseudoVFNCVT_X_F_W_M4_MASK, PseudoVFNCVT_X_F_W_M4, 0x2 }, // 765 { PseudoVFNCVT_X_F_W_MF2_MASK, PseudoVFNCVT_X_F_W_MF2, 0x2 }, // 766 { PseudoVFNCVT_X_F_W_MF4_MASK, PseudoVFNCVT_X_F_W_MF4, 0x2 }, // 767 { PseudoVFNCVT_X_F_W_MF8_MASK, PseudoVFNCVT_X_F_W_MF8, 0x2 }, // 768 { PseudoVFNMACC_VFPR16_M1_E16_MASK, PseudoVFNMACC_VFPR16_M1_E16, 0x3 }, // 769 { PseudoVFNMACC_VFPR16_M2_E16_MASK, PseudoVFNMACC_VFPR16_M2_E16, 0x3 }, // 770 { PseudoVFNMACC_VFPR16_M4_E16_MASK, PseudoVFNMACC_VFPR16_M4_E16, 0x3 }, // 771 { PseudoVFNMACC_VFPR16_M8_E16_MASK, PseudoVFNMACC_VFPR16_M8_E16, 0x3 }, // 772 { PseudoVFNMACC_VFPR16_MF2_E16_MASK, PseudoVFNMACC_VFPR16_MF2_E16, 0x3 }, // 773 { PseudoVFNMACC_VFPR16_MF4_E16_MASK, PseudoVFNMACC_VFPR16_MF4_E16, 0x3 }, // 774 { PseudoVFNMACC_VFPR32_M1_E32_MASK, PseudoVFNMACC_VFPR32_M1_E32, 0x3 }, // 775 { PseudoVFNMACC_VFPR32_M2_E32_MASK, PseudoVFNMACC_VFPR32_M2_E32, 0x3 }, // 776 { PseudoVFNMACC_VFPR32_M4_E32_MASK, PseudoVFNMACC_VFPR32_M4_E32, 0x3 }, // 777 { PseudoVFNMACC_VFPR32_M8_E32_MASK, PseudoVFNMACC_VFPR32_M8_E32, 0x3 }, // 778 { PseudoVFNMACC_VFPR32_MF2_E32_MASK, PseudoVFNMACC_VFPR32_MF2_E32, 0x3 }, // 779 { PseudoVFNMACC_VFPR64_M1_E64_MASK, PseudoVFNMACC_VFPR64_M1_E64, 0x3 }, // 780 { PseudoVFNMACC_VFPR64_M2_E64_MASK, PseudoVFNMACC_VFPR64_M2_E64, 0x3 }, // 781 { PseudoVFNMACC_VFPR64_M4_E64_MASK, PseudoVFNMACC_VFPR64_M4_E64, 0x3 }, // 782 { PseudoVFNMACC_VFPR64_M8_E64_MASK, PseudoVFNMACC_VFPR64_M8_E64, 0x3 }, // 783 { PseudoVFNMACC_VV_M1_E16_MASK, PseudoVFNMACC_VV_M1_E16, 0x3 }, // 784 { PseudoVFNMACC_VV_M1_E32_MASK, PseudoVFNMACC_VV_M1_E32, 0x3 }, // 785 { PseudoVFNMACC_VV_M1_E64_MASK, PseudoVFNMACC_VV_M1_E64, 0x3 }, // 786 { PseudoVFNMACC_VV_M2_E16_MASK, PseudoVFNMACC_VV_M2_E16, 0x3 }, // 787 { PseudoVFNMACC_VV_M2_E32_MASK, PseudoVFNMACC_VV_M2_E32, 0x3 }, // 788 { PseudoVFNMACC_VV_M2_E64_MASK, PseudoVFNMACC_VV_M2_E64, 0x3 }, // 789 { PseudoVFNMACC_VV_M4_E16_MASK, PseudoVFNMACC_VV_M4_E16, 0x3 }, // 790 { PseudoVFNMACC_VV_M4_E32_MASK, PseudoVFNMACC_VV_M4_E32, 0x3 }, // 791 { PseudoVFNMACC_VV_M4_E64_MASK, PseudoVFNMACC_VV_M4_E64, 0x3 }, // 792 { PseudoVFNMACC_VV_M8_E16_MASK, PseudoVFNMACC_VV_M8_E16, 0x3 }, // 793 { PseudoVFNMACC_VV_M8_E32_MASK, PseudoVFNMACC_VV_M8_E32, 0x3 }, // 794 { PseudoVFNMACC_VV_M8_E64_MASK, PseudoVFNMACC_VV_M8_E64, 0x3 }, // 795 { PseudoVFNMACC_VV_MF2_E16_MASK, PseudoVFNMACC_VV_MF2_E16, 0x3 }, // 796 { PseudoVFNMACC_VV_MF2_E32_MASK, PseudoVFNMACC_VV_MF2_E32, 0x3 }, // 797 { PseudoVFNMACC_VV_MF4_E16_MASK, PseudoVFNMACC_VV_MF4_E16, 0x3 }, // 798 { PseudoVFNMADD_VFPR16_M1_E16_MASK, PseudoVFNMADD_VFPR16_M1_E16, 0x3 }, // 799 { PseudoVFNMADD_VFPR16_M2_E16_MASK, PseudoVFNMADD_VFPR16_M2_E16, 0x3 }, // 800 { PseudoVFNMADD_VFPR16_M4_E16_MASK, PseudoVFNMADD_VFPR16_M4_E16, 0x3 }, // 801 { PseudoVFNMADD_VFPR16_M8_E16_MASK, PseudoVFNMADD_VFPR16_M8_E16, 0x3 }, // 802 { PseudoVFNMADD_VFPR16_MF2_E16_MASK, PseudoVFNMADD_VFPR16_MF2_E16, 0x3 }, // 803 { PseudoVFNMADD_VFPR16_MF4_E16_MASK, PseudoVFNMADD_VFPR16_MF4_E16, 0x3 }, // 804 { PseudoVFNMADD_VFPR32_M1_E32_MASK, PseudoVFNMADD_VFPR32_M1_E32, 0x3 }, // 805 { PseudoVFNMADD_VFPR32_M2_E32_MASK, PseudoVFNMADD_VFPR32_M2_E32, 0x3 }, // 806 { PseudoVFNMADD_VFPR32_M4_E32_MASK, PseudoVFNMADD_VFPR32_M4_E32, 0x3 }, // 807 { PseudoVFNMADD_VFPR32_M8_E32_MASK, PseudoVFNMADD_VFPR32_M8_E32, 0x3 }, // 808 { PseudoVFNMADD_VFPR32_MF2_E32_MASK, PseudoVFNMADD_VFPR32_MF2_E32, 0x3 }, // 809 { PseudoVFNMADD_VFPR64_M1_E64_MASK, PseudoVFNMADD_VFPR64_M1_E64, 0x3 }, // 810 { PseudoVFNMADD_VFPR64_M2_E64_MASK, PseudoVFNMADD_VFPR64_M2_E64, 0x3 }, // 811 { PseudoVFNMADD_VFPR64_M4_E64_MASK, PseudoVFNMADD_VFPR64_M4_E64, 0x3 }, // 812 { PseudoVFNMADD_VFPR64_M8_E64_MASK, PseudoVFNMADD_VFPR64_M8_E64, 0x3 }, // 813 { PseudoVFNMADD_VV_M1_E16_MASK, PseudoVFNMADD_VV_M1_E16, 0x3 }, // 814 { PseudoVFNMADD_VV_M1_E32_MASK, PseudoVFNMADD_VV_M1_E32, 0x3 }, // 815 { PseudoVFNMADD_VV_M1_E64_MASK, PseudoVFNMADD_VV_M1_E64, 0x3 }, // 816 { PseudoVFNMADD_VV_M2_E16_MASK, PseudoVFNMADD_VV_M2_E16, 0x3 }, // 817 { PseudoVFNMADD_VV_M2_E32_MASK, PseudoVFNMADD_VV_M2_E32, 0x3 }, // 818 { PseudoVFNMADD_VV_M2_E64_MASK, PseudoVFNMADD_VV_M2_E64, 0x3 }, // 819 { PseudoVFNMADD_VV_M4_E16_MASK, PseudoVFNMADD_VV_M4_E16, 0x3 }, // 820 { PseudoVFNMADD_VV_M4_E32_MASK, PseudoVFNMADD_VV_M4_E32, 0x3 }, // 821 { PseudoVFNMADD_VV_M4_E64_MASK, PseudoVFNMADD_VV_M4_E64, 0x3 }, // 822 { PseudoVFNMADD_VV_M8_E16_MASK, PseudoVFNMADD_VV_M8_E16, 0x3 }, // 823 { PseudoVFNMADD_VV_M8_E32_MASK, PseudoVFNMADD_VV_M8_E32, 0x3 }, // 824 { PseudoVFNMADD_VV_M8_E64_MASK, PseudoVFNMADD_VV_M8_E64, 0x3 }, // 825 { PseudoVFNMADD_VV_MF2_E16_MASK, PseudoVFNMADD_VV_MF2_E16, 0x3 }, // 826 { PseudoVFNMADD_VV_MF2_E32_MASK, PseudoVFNMADD_VV_MF2_E32, 0x3 }, // 827 { PseudoVFNMADD_VV_MF4_E16_MASK, PseudoVFNMADD_VV_MF4_E16, 0x3 }, // 828 { PseudoVFNMSAC_VFPR16_M1_E16_MASK, PseudoVFNMSAC_VFPR16_M1_E16, 0x3 }, // 829 { PseudoVFNMSAC_VFPR16_M2_E16_MASK, PseudoVFNMSAC_VFPR16_M2_E16, 0x3 }, // 830 { PseudoVFNMSAC_VFPR16_M4_E16_MASK, PseudoVFNMSAC_VFPR16_M4_E16, 0x3 }, // 831 { PseudoVFNMSAC_VFPR16_M8_E16_MASK, PseudoVFNMSAC_VFPR16_M8_E16, 0x3 }, // 832 { PseudoVFNMSAC_VFPR16_MF2_E16_MASK, PseudoVFNMSAC_VFPR16_MF2_E16, 0x3 }, // 833 { PseudoVFNMSAC_VFPR16_MF4_E16_MASK, PseudoVFNMSAC_VFPR16_MF4_E16, 0x3 }, // 834 { PseudoVFNMSAC_VFPR32_M1_E32_MASK, PseudoVFNMSAC_VFPR32_M1_E32, 0x3 }, // 835 { PseudoVFNMSAC_VFPR32_M2_E32_MASK, PseudoVFNMSAC_VFPR32_M2_E32, 0x3 }, // 836 { PseudoVFNMSAC_VFPR32_M4_E32_MASK, PseudoVFNMSAC_VFPR32_M4_E32, 0x3 }, // 837 { PseudoVFNMSAC_VFPR32_M8_E32_MASK, PseudoVFNMSAC_VFPR32_M8_E32, 0x3 }, // 838 { PseudoVFNMSAC_VFPR32_MF2_E32_MASK, PseudoVFNMSAC_VFPR32_MF2_E32, 0x3 }, // 839 { PseudoVFNMSAC_VFPR64_M1_E64_MASK, PseudoVFNMSAC_VFPR64_M1_E64, 0x3 }, // 840 { PseudoVFNMSAC_VFPR64_M2_E64_MASK, PseudoVFNMSAC_VFPR64_M2_E64, 0x3 }, // 841 { PseudoVFNMSAC_VFPR64_M4_E64_MASK, PseudoVFNMSAC_VFPR64_M4_E64, 0x3 }, // 842 { PseudoVFNMSAC_VFPR64_M8_E64_MASK, PseudoVFNMSAC_VFPR64_M8_E64, 0x3 }, // 843 { PseudoVFNMSAC_VV_M1_E16_MASK, PseudoVFNMSAC_VV_M1_E16, 0x3 }, // 844 { PseudoVFNMSAC_VV_M1_E32_MASK, PseudoVFNMSAC_VV_M1_E32, 0x3 }, // 845 { PseudoVFNMSAC_VV_M1_E64_MASK, PseudoVFNMSAC_VV_M1_E64, 0x3 }, // 846 { PseudoVFNMSAC_VV_M2_E16_MASK, PseudoVFNMSAC_VV_M2_E16, 0x3 }, // 847 { PseudoVFNMSAC_VV_M2_E32_MASK, PseudoVFNMSAC_VV_M2_E32, 0x3 }, // 848 { PseudoVFNMSAC_VV_M2_E64_MASK, PseudoVFNMSAC_VV_M2_E64, 0x3 }, // 849 { PseudoVFNMSAC_VV_M4_E16_MASK, PseudoVFNMSAC_VV_M4_E16, 0x3 }, // 850 { PseudoVFNMSAC_VV_M4_E32_MASK, PseudoVFNMSAC_VV_M4_E32, 0x3 }, // 851 { PseudoVFNMSAC_VV_M4_E64_MASK, PseudoVFNMSAC_VV_M4_E64, 0x3 }, // 852 { PseudoVFNMSAC_VV_M8_E16_MASK, PseudoVFNMSAC_VV_M8_E16, 0x3 }, // 853 { PseudoVFNMSAC_VV_M8_E32_MASK, PseudoVFNMSAC_VV_M8_E32, 0x3 }, // 854 { PseudoVFNMSAC_VV_M8_E64_MASK, PseudoVFNMSAC_VV_M8_E64, 0x3 }, // 855 { PseudoVFNMSAC_VV_MF2_E16_MASK, PseudoVFNMSAC_VV_MF2_E16, 0x3 }, // 856 { PseudoVFNMSAC_VV_MF2_E32_MASK, PseudoVFNMSAC_VV_MF2_E32, 0x3 }, // 857 { PseudoVFNMSAC_VV_MF4_E16_MASK, PseudoVFNMSAC_VV_MF4_E16, 0x3 }, // 858 { PseudoVFNMSUB_VFPR16_M1_E16_MASK, PseudoVFNMSUB_VFPR16_M1_E16, 0x3 }, // 859 { PseudoVFNMSUB_VFPR16_M2_E16_MASK, PseudoVFNMSUB_VFPR16_M2_E16, 0x3 }, // 860 { PseudoVFNMSUB_VFPR16_M4_E16_MASK, PseudoVFNMSUB_VFPR16_M4_E16, 0x3 }, // 861 { PseudoVFNMSUB_VFPR16_M8_E16_MASK, PseudoVFNMSUB_VFPR16_M8_E16, 0x3 }, // 862 { PseudoVFNMSUB_VFPR16_MF2_E16_MASK, PseudoVFNMSUB_VFPR16_MF2_E16, 0x3 }, // 863 { PseudoVFNMSUB_VFPR16_MF4_E16_MASK, PseudoVFNMSUB_VFPR16_MF4_E16, 0x3 }, // 864 { PseudoVFNMSUB_VFPR32_M1_E32_MASK, PseudoVFNMSUB_VFPR32_M1_E32, 0x3 }, // 865 { PseudoVFNMSUB_VFPR32_M2_E32_MASK, PseudoVFNMSUB_VFPR32_M2_E32, 0x3 }, // 866 { PseudoVFNMSUB_VFPR32_M4_E32_MASK, PseudoVFNMSUB_VFPR32_M4_E32, 0x3 }, // 867 { PseudoVFNMSUB_VFPR32_M8_E32_MASK, PseudoVFNMSUB_VFPR32_M8_E32, 0x3 }, // 868 { PseudoVFNMSUB_VFPR32_MF2_E32_MASK, PseudoVFNMSUB_VFPR32_MF2_E32, 0x3 }, // 869 { PseudoVFNMSUB_VFPR64_M1_E64_MASK, PseudoVFNMSUB_VFPR64_M1_E64, 0x3 }, // 870 { PseudoVFNMSUB_VFPR64_M2_E64_MASK, PseudoVFNMSUB_VFPR64_M2_E64, 0x3 }, // 871 { PseudoVFNMSUB_VFPR64_M4_E64_MASK, PseudoVFNMSUB_VFPR64_M4_E64, 0x3 }, // 872 { PseudoVFNMSUB_VFPR64_M8_E64_MASK, PseudoVFNMSUB_VFPR64_M8_E64, 0x3 }, // 873 { PseudoVFNMSUB_VV_M1_E16_MASK, PseudoVFNMSUB_VV_M1_E16, 0x3 }, // 874 { PseudoVFNMSUB_VV_M1_E32_MASK, PseudoVFNMSUB_VV_M1_E32, 0x3 }, // 875 { PseudoVFNMSUB_VV_M1_E64_MASK, PseudoVFNMSUB_VV_M1_E64, 0x3 }, // 876 { PseudoVFNMSUB_VV_M2_E16_MASK, PseudoVFNMSUB_VV_M2_E16, 0x3 }, // 877 { PseudoVFNMSUB_VV_M2_E32_MASK, PseudoVFNMSUB_VV_M2_E32, 0x3 }, // 878 { PseudoVFNMSUB_VV_M2_E64_MASK, PseudoVFNMSUB_VV_M2_E64, 0x3 }, // 879 { PseudoVFNMSUB_VV_M4_E16_MASK, PseudoVFNMSUB_VV_M4_E16, 0x3 }, // 880 { PseudoVFNMSUB_VV_M4_E32_MASK, PseudoVFNMSUB_VV_M4_E32, 0x3 }, // 881 { PseudoVFNMSUB_VV_M4_E64_MASK, PseudoVFNMSUB_VV_M4_E64, 0x3 }, // 882 { PseudoVFNMSUB_VV_M8_E16_MASK, PseudoVFNMSUB_VV_M8_E16, 0x3 }, // 883 { PseudoVFNMSUB_VV_M8_E32_MASK, PseudoVFNMSUB_VV_M8_E32, 0x3 }, // 884 { PseudoVFNMSUB_VV_M8_E64_MASK, PseudoVFNMSUB_VV_M8_E64, 0x3 }, // 885 { PseudoVFNMSUB_VV_MF2_E16_MASK, PseudoVFNMSUB_VV_MF2_E16, 0x3 }, // 886 { PseudoVFNMSUB_VV_MF2_E32_MASK, PseudoVFNMSUB_VV_MF2_E32, 0x3 }, // 887 { PseudoVFNMSUB_VV_MF4_E16_MASK, PseudoVFNMSUB_VV_MF4_E16, 0x3 }, // 888 { PseudoVFNRCLIP_XU_F_QF_M1_MASK, PseudoVFNRCLIP_XU_F_QF_M1, 0x3 }, // 889 { PseudoVFNRCLIP_XU_F_QF_M2_MASK, PseudoVFNRCLIP_XU_F_QF_M2, 0x3 }, // 890 { PseudoVFNRCLIP_XU_F_QF_MF2_MASK, PseudoVFNRCLIP_XU_F_QF_MF2, 0x3 }, // 891 { PseudoVFNRCLIP_XU_F_QF_MF4_MASK, PseudoVFNRCLIP_XU_F_QF_MF4, 0x3 }, // 892 { PseudoVFNRCLIP_XU_F_QF_MF8_MASK, PseudoVFNRCLIP_XU_F_QF_MF8, 0x3 }, // 893 { PseudoVFNRCLIP_X_F_QF_M1_MASK, PseudoVFNRCLIP_X_F_QF_M1, 0x3 }, // 894 { PseudoVFNRCLIP_X_F_QF_M2_MASK, PseudoVFNRCLIP_X_F_QF_M2, 0x3 }, // 895 { PseudoVFNRCLIP_X_F_QF_MF2_MASK, PseudoVFNRCLIP_X_F_QF_MF2, 0x3 }, // 896 { PseudoVFNRCLIP_X_F_QF_MF4_MASK, PseudoVFNRCLIP_X_F_QF_MF4, 0x3 }, // 897 { PseudoVFNRCLIP_X_F_QF_MF8_MASK, PseudoVFNRCLIP_X_F_QF_MF8, 0x3 }, // 898 { PseudoVFRDIV_VFPR16_M1_E16_MASK, PseudoVFRDIV_VFPR16_M1_E16, 0x3 }, // 899 { PseudoVFRDIV_VFPR16_M2_E16_MASK, PseudoVFRDIV_VFPR16_M2_E16, 0x3 }, // 900 { PseudoVFRDIV_VFPR16_M4_E16_MASK, PseudoVFRDIV_VFPR16_M4_E16, 0x3 }, // 901 { PseudoVFRDIV_VFPR16_M8_E16_MASK, PseudoVFRDIV_VFPR16_M8_E16, 0x3 }, // 902 { PseudoVFRDIV_VFPR16_MF2_E16_MASK, PseudoVFRDIV_VFPR16_MF2_E16, 0x3 }, // 903 { PseudoVFRDIV_VFPR16_MF4_E16_MASK, PseudoVFRDIV_VFPR16_MF4_E16, 0x3 }, // 904 { PseudoVFRDIV_VFPR32_M1_E32_MASK, PseudoVFRDIV_VFPR32_M1_E32, 0x3 }, // 905 { PseudoVFRDIV_VFPR32_M2_E32_MASK, PseudoVFRDIV_VFPR32_M2_E32, 0x3 }, // 906 { PseudoVFRDIV_VFPR32_M4_E32_MASK, PseudoVFRDIV_VFPR32_M4_E32, 0x3 }, // 907 { PseudoVFRDIV_VFPR32_M8_E32_MASK, PseudoVFRDIV_VFPR32_M8_E32, 0x3 }, // 908 { PseudoVFRDIV_VFPR32_MF2_E32_MASK, PseudoVFRDIV_VFPR32_MF2_E32, 0x3 }, // 909 { PseudoVFRDIV_VFPR64_M1_E64_MASK, PseudoVFRDIV_VFPR64_M1_E64, 0x3 }, // 910 { PseudoVFRDIV_VFPR64_M2_E64_MASK, PseudoVFRDIV_VFPR64_M2_E64, 0x3 }, // 911 { PseudoVFRDIV_VFPR64_M4_E64_MASK, PseudoVFRDIV_VFPR64_M4_E64, 0x3 }, // 912 { PseudoVFRDIV_VFPR64_M8_E64_MASK, PseudoVFRDIV_VFPR64_M8_E64, 0x3 }, // 913 { PseudoVFREC7_V_M1_E16_MASK, PseudoVFREC7_V_M1_E16, 0x2 }, // 914 { PseudoVFREC7_V_M1_E32_MASK, PseudoVFREC7_V_M1_E32, 0x2 }, // 915 { PseudoVFREC7_V_M1_E64_MASK, PseudoVFREC7_V_M1_E64, 0x2 }, // 916 { PseudoVFREC7_V_M2_E16_MASK, PseudoVFREC7_V_M2_E16, 0x2 }, // 917 { PseudoVFREC7_V_M2_E32_MASK, PseudoVFREC7_V_M2_E32, 0x2 }, // 918 { PseudoVFREC7_V_M2_E64_MASK, PseudoVFREC7_V_M2_E64, 0x2 }, // 919 { PseudoVFREC7_V_M4_E16_MASK, PseudoVFREC7_V_M4_E16, 0x2 }, // 920 { PseudoVFREC7_V_M4_E32_MASK, PseudoVFREC7_V_M4_E32, 0x2 }, // 921 { PseudoVFREC7_V_M4_E64_MASK, PseudoVFREC7_V_M4_E64, 0x2 }, // 922 { PseudoVFREC7_V_M8_E16_MASK, PseudoVFREC7_V_M8_E16, 0x2 }, // 923 { PseudoVFREC7_V_M8_E32_MASK, PseudoVFREC7_V_M8_E32, 0x2 }, // 924 { PseudoVFREC7_V_M8_E64_MASK, PseudoVFREC7_V_M8_E64, 0x2 }, // 925 { PseudoVFREC7_V_MF2_E16_MASK, PseudoVFREC7_V_MF2_E16, 0x2 }, // 926 { PseudoVFREC7_V_MF2_E32_MASK, PseudoVFREC7_V_MF2_E32, 0x2 }, // 927 { PseudoVFREC7_V_MF4_E16_MASK, PseudoVFREC7_V_MF4_E16, 0x2 }, // 928 { PseudoVFREDMAX_VS_M1_E16_MASK, PseudoVFREDMAX_VS_M1_E16, 0x3 }, // 929 { PseudoVFREDMAX_VS_M1_E32_MASK, PseudoVFREDMAX_VS_M1_E32, 0x3 }, // 930 { PseudoVFREDMAX_VS_M1_E64_MASK, PseudoVFREDMAX_VS_M1_E64, 0x3 }, // 931 { PseudoVFREDMAX_VS_M2_E16_MASK, PseudoVFREDMAX_VS_M2_E16, 0x3 }, // 932 { PseudoVFREDMAX_VS_M2_E32_MASK, PseudoVFREDMAX_VS_M2_E32, 0x3 }, // 933 { PseudoVFREDMAX_VS_M2_E64_MASK, PseudoVFREDMAX_VS_M2_E64, 0x3 }, // 934 { PseudoVFREDMAX_VS_M4_E16_MASK, PseudoVFREDMAX_VS_M4_E16, 0x3 }, // 935 { PseudoVFREDMAX_VS_M4_E32_MASK, PseudoVFREDMAX_VS_M4_E32, 0x3 }, // 936 { PseudoVFREDMAX_VS_M4_E64_MASK, PseudoVFREDMAX_VS_M4_E64, 0x3 }, // 937 { PseudoVFREDMAX_VS_M8_E16_MASK, PseudoVFREDMAX_VS_M8_E16, 0x3 }, // 938 { PseudoVFREDMAX_VS_M8_E32_MASK, PseudoVFREDMAX_VS_M8_E32, 0x3 }, // 939 { PseudoVFREDMAX_VS_M8_E64_MASK, PseudoVFREDMAX_VS_M8_E64, 0x3 }, // 940 { PseudoVFREDMAX_VS_MF2_E16_MASK, PseudoVFREDMAX_VS_MF2_E16, 0x3 }, // 941 { PseudoVFREDMAX_VS_MF2_E32_MASK, PseudoVFREDMAX_VS_MF2_E32, 0x3 }, // 942 { PseudoVFREDMAX_VS_MF4_E16_MASK, PseudoVFREDMAX_VS_MF4_E16, 0x3 }, // 943 { PseudoVFREDMIN_VS_M1_E16_MASK, PseudoVFREDMIN_VS_M1_E16, 0x3 }, // 944 { PseudoVFREDMIN_VS_M1_E32_MASK, PseudoVFREDMIN_VS_M1_E32, 0x3 }, // 945 { PseudoVFREDMIN_VS_M1_E64_MASK, PseudoVFREDMIN_VS_M1_E64, 0x3 }, // 946 { PseudoVFREDMIN_VS_M2_E16_MASK, PseudoVFREDMIN_VS_M2_E16, 0x3 }, // 947 { PseudoVFREDMIN_VS_M2_E32_MASK, PseudoVFREDMIN_VS_M2_E32, 0x3 }, // 948 { PseudoVFREDMIN_VS_M2_E64_MASK, PseudoVFREDMIN_VS_M2_E64, 0x3 }, // 949 { PseudoVFREDMIN_VS_M4_E16_MASK, PseudoVFREDMIN_VS_M4_E16, 0x3 }, // 950 { PseudoVFREDMIN_VS_M4_E32_MASK, PseudoVFREDMIN_VS_M4_E32, 0x3 }, // 951 { PseudoVFREDMIN_VS_M4_E64_MASK, PseudoVFREDMIN_VS_M4_E64, 0x3 }, // 952 { PseudoVFREDMIN_VS_M8_E16_MASK, PseudoVFREDMIN_VS_M8_E16, 0x3 }, // 953 { PseudoVFREDMIN_VS_M8_E32_MASK, PseudoVFREDMIN_VS_M8_E32, 0x3 }, // 954 { PseudoVFREDMIN_VS_M8_E64_MASK, PseudoVFREDMIN_VS_M8_E64, 0x3 }, // 955 { PseudoVFREDMIN_VS_MF2_E16_MASK, PseudoVFREDMIN_VS_MF2_E16, 0x3 }, // 956 { PseudoVFREDMIN_VS_MF2_E32_MASK, PseudoVFREDMIN_VS_MF2_E32, 0x3 }, // 957 { PseudoVFREDMIN_VS_MF4_E16_MASK, PseudoVFREDMIN_VS_MF4_E16, 0x3 }, // 958 { PseudoVFREDOSUM_VS_M1_E16_MASK, PseudoVFREDOSUM_VS_M1_E16, 0x3 }, // 959 { PseudoVFREDOSUM_VS_M1_E32_MASK, PseudoVFREDOSUM_VS_M1_E32, 0x3 }, // 960 { PseudoVFREDOSUM_VS_M1_E64_MASK, PseudoVFREDOSUM_VS_M1_E64, 0x3 }, // 961 { PseudoVFREDOSUM_VS_M2_E16_MASK, PseudoVFREDOSUM_VS_M2_E16, 0x3 }, // 962 { PseudoVFREDOSUM_VS_M2_E32_MASK, PseudoVFREDOSUM_VS_M2_E32, 0x3 }, // 963 { PseudoVFREDOSUM_VS_M2_E64_MASK, PseudoVFREDOSUM_VS_M2_E64, 0x3 }, // 964 { PseudoVFREDOSUM_VS_M4_E16_MASK, PseudoVFREDOSUM_VS_M4_E16, 0x3 }, // 965 { PseudoVFREDOSUM_VS_M4_E32_MASK, PseudoVFREDOSUM_VS_M4_E32, 0x3 }, // 966 { PseudoVFREDOSUM_VS_M4_E64_MASK, PseudoVFREDOSUM_VS_M4_E64, 0x3 }, // 967 { PseudoVFREDOSUM_VS_M8_E16_MASK, PseudoVFREDOSUM_VS_M8_E16, 0x3 }, // 968 { PseudoVFREDOSUM_VS_M8_E32_MASK, PseudoVFREDOSUM_VS_M8_E32, 0x3 }, // 969 { PseudoVFREDOSUM_VS_M8_E64_MASK, PseudoVFREDOSUM_VS_M8_E64, 0x3 }, // 970 { PseudoVFREDOSUM_VS_MF2_E16_MASK, PseudoVFREDOSUM_VS_MF2_E16, 0x3 }, // 971 { PseudoVFREDOSUM_VS_MF2_E32_MASK, PseudoVFREDOSUM_VS_MF2_E32, 0x3 }, // 972 { PseudoVFREDOSUM_VS_MF4_E16_MASK, PseudoVFREDOSUM_VS_MF4_E16, 0x3 }, // 973 { PseudoVFREDUSUM_VS_M1_E16_MASK, PseudoVFREDUSUM_VS_M1_E16, 0x3 }, // 974 { PseudoVFREDUSUM_VS_M1_E32_MASK, PseudoVFREDUSUM_VS_M1_E32, 0x3 }, // 975 { PseudoVFREDUSUM_VS_M1_E64_MASK, PseudoVFREDUSUM_VS_M1_E64, 0x3 }, // 976 { PseudoVFREDUSUM_VS_M2_E16_MASK, PseudoVFREDUSUM_VS_M2_E16, 0x3 }, // 977 { PseudoVFREDUSUM_VS_M2_E32_MASK, PseudoVFREDUSUM_VS_M2_E32, 0x3 }, // 978 { PseudoVFREDUSUM_VS_M2_E64_MASK, PseudoVFREDUSUM_VS_M2_E64, 0x3 }, // 979 { PseudoVFREDUSUM_VS_M4_E16_MASK, PseudoVFREDUSUM_VS_M4_E16, 0x3 }, // 980 { PseudoVFREDUSUM_VS_M4_E32_MASK, PseudoVFREDUSUM_VS_M4_E32, 0x3 }, // 981 { PseudoVFREDUSUM_VS_M4_E64_MASK, PseudoVFREDUSUM_VS_M4_E64, 0x3 }, // 982 { PseudoVFREDUSUM_VS_M8_E16_MASK, PseudoVFREDUSUM_VS_M8_E16, 0x3 }, // 983 { PseudoVFREDUSUM_VS_M8_E32_MASK, PseudoVFREDUSUM_VS_M8_E32, 0x3 }, // 984 { PseudoVFREDUSUM_VS_M8_E64_MASK, PseudoVFREDUSUM_VS_M8_E64, 0x3 }, // 985 { PseudoVFREDUSUM_VS_MF2_E16_MASK, PseudoVFREDUSUM_VS_MF2_E16, 0x3 }, // 986 { PseudoVFREDUSUM_VS_MF2_E32_MASK, PseudoVFREDUSUM_VS_MF2_E32, 0x3 }, // 987 { PseudoVFREDUSUM_VS_MF4_E16_MASK, PseudoVFREDUSUM_VS_MF4_E16, 0x3 }, // 988 { PseudoVFRSQRT7_V_M1_E16_MASK, PseudoVFRSQRT7_V_M1_E16, 0x2 }, // 989 { PseudoVFRSQRT7_V_M1_E32_MASK, PseudoVFRSQRT7_V_M1_E32, 0x2 }, // 990 { PseudoVFRSQRT7_V_M1_E64_MASK, PseudoVFRSQRT7_V_M1_E64, 0x2 }, // 991 { PseudoVFRSQRT7_V_M2_E16_MASK, PseudoVFRSQRT7_V_M2_E16, 0x2 }, // 992 { PseudoVFRSQRT7_V_M2_E32_MASK, PseudoVFRSQRT7_V_M2_E32, 0x2 }, // 993 { PseudoVFRSQRT7_V_M2_E64_MASK, PseudoVFRSQRT7_V_M2_E64, 0x2 }, // 994 { PseudoVFRSQRT7_V_M4_E16_MASK, PseudoVFRSQRT7_V_M4_E16, 0x2 }, // 995 { PseudoVFRSQRT7_V_M4_E32_MASK, PseudoVFRSQRT7_V_M4_E32, 0x2 }, // 996 { PseudoVFRSQRT7_V_M4_E64_MASK, PseudoVFRSQRT7_V_M4_E64, 0x2 }, // 997 { PseudoVFRSQRT7_V_M8_E16_MASK, PseudoVFRSQRT7_V_M8_E16, 0x2 }, // 998 { PseudoVFRSQRT7_V_M8_E32_MASK, PseudoVFRSQRT7_V_M8_E32, 0x2 }, // 999 { PseudoVFRSQRT7_V_M8_E64_MASK, PseudoVFRSQRT7_V_M8_E64, 0x2 }, // 1000 { PseudoVFRSQRT7_V_MF2_E16_MASK, PseudoVFRSQRT7_V_MF2_E16, 0x2 }, // 1001 { PseudoVFRSQRT7_V_MF2_E32_MASK, PseudoVFRSQRT7_V_MF2_E32, 0x2 }, // 1002 { PseudoVFRSQRT7_V_MF4_E16_MASK, PseudoVFRSQRT7_V_MF4_E16, 0x2 }, // 1003 { PseudoVFRSUB_VFPR16_M1_E16_MASK, PseudoVFRSUB_VFPR16_M1_E16, 0x3 }, // 1004 { PseudoVFRSUB_VFPR16_M2_E16_MASK, PseudoVFRSUB_VFPR16_M2_E16, 0x3 }, // 1005 { PseudoVFRSUB_VFPR16_M4_E16_MASK, PseudoVFRSUB_VFPR16_M4_E16, 0x3 }, // 1006 { PseudoVFRSUB_VFPR16_M8_E16_MASK, PseudoVFRSUB_VFPR16_M8_E16, 0x3 }, // 1007 { PseudoVFRSUB_VFPR16_MF2_E16_MASK, PseudoVFRSUB_VFPR16_MF2_E16, 0x3 }, // 1008 { PseudoVFRSUB_VFPR16_MF4_E16_MASK, PseudoVFRSUB_VFPR16_MF4_E16, 0x3 }, // 1009 { PseudoVFRSUB_VFPR32_M1_E32_MASK, PseudoVFRSUB_VFPR32_M1_E32, 0x3 }, // 1010 { PseudoVFRSUB_VFPR32_M2_E32_MASK, PseudoVFRSUB_VFPR32_M2_E32, 0x3 }, // 1011 { PseudoVFRSUB_VFPR32_M4_E32_MASK, PseudoVFRSUB_VFPR32_M4_E32, 0x3 }, // 1012 { PseudoVFRSUB_VFPR32_M8_E32_MASK, PseudoVFRSUB_VFPR32_M8_E32, 0x3 }, // 1013 { PseudoVFRSUB_VFPR32_MF2_E32_MASK, PseudoVFRSUB_VFPR32_MF2_E32, 0x3 }, // 1014 { PseudoVFRSUB_VFPR64_M1_E64_MASK, PseudoVFRSUB_VFPR64_M1_E64, 0x3 }, // 1015 { PseudoVFRSUB_VFPR64_M2_E64_MASK, PseudoVFRSUB_VFPR64_M2_E64, 0x3 }, // 1016 { PseudoVFRSUB_VFPR64_M4_E64_MASK, PseudoVFRSUB_VFPR64_M4_E64, 0x3 }, // 1017 { PseudoVFRSUB_VFPR64_M8_E64_MASK, PseudoVFRSUB_VFPR64_M8_E64, 0x3 }, // 1018 { PseudoVFSGNJN_VFPR16_M1_E16_MASK, PseudoVFSGNJN_VFPR16_M1_E16, 0x3 }, // 1019 { PseudoVFSGNJN_VFPR16_M2_E16_MASK, PseudoVFSGNJN_VFPR16_M2_E16, 0x3 }, // 1020 { PseudoVFSGNJN_VFPR16_M4_E16_MASK, PseudoVFSGNJN_VFPR16_M4_E16, 0x3 }, // 1021 { PseudoVFSGNJN_VFPR16_M8_E16_MASK, PseudoVFSGNJN_VFPR16_M8_E16, 0x3 }, // 1022 { PseudoVFSGNJN_VFPR16_MF2_E16_MASK, PseudoVFSGNJN_VFPR16_MF2_E16, 0x3 }, // 1023 { PseudoVFSGNJN_VFPR16_MF4_E16_MASK, PseudoVFSGNJN_VFPR16_MF4_E16, 0x3 }, // 1024 { PseudoVFSGNJN_VFPR32_M1_E32_MASK, PseudoVFSGNJN_VFPR32_M1_E32, 0x3 }, // 1025 { PseudoVFSGNJN_VFPR32_M2_E32_MASK, PseudoVFSGNJN_VFPR32_M2_E32, 0x3 }, // 1026 { PseudoVFSGNJN_VFPR32_M4_E32_MASK, PseudoVFSGNJN_VFPR32_M4_E32, 0x3 }, // 1027 { PseudoVFSGNJN_VFPR32_M8_E32_MASK, PseudoVFSGNJN_VFPR32_M8_E32, 0x3 }, // 1028 { PseudoVFSGNJN_VFPR32_MF2_E32_MASK, PseudoVFSGNJN_VFPR32_MF2_E32, 0x3 }, // 1029 { PseudoVFSGNJN_VFPR64_M1_E64_MASK, PseudoVFSGNJN_VFPR64_M1_E64, 0x3 }, // 1030 { PseudoVFSGNJN_VFPR64_M2_E64_MASK, PseudoVFSGNJN_VFPR64_M2_E64, 0x3 }, // 1031 { PseudoVFSGNJN_VFPR64_M4_E64_MASK, PseudoVFSGNJN_VFPR64_M4_E64, 0x3 }, // 1032 { PseudoVFSGNJN_VFPR64_M8_E64_MASK, PseudoVFSGNJN_VFPR64_M8_E64, 0x3 }, // 1033 { PseudoVFSGNJN_VV_M1_E16_MASK, PseudoVFSGNJN_VV_M1_E16, 0x3 }, // 1034 { PseudoVFSGNJN_VV_M1_E32_MASK, PseudoVFSGNJN_VV_M1_E32, 0x3 }, // 1035 { PseudoVFSGNJN_VV_M1_E64_MASK, PseudoVFSGNJN_VV_M1_E64, 0x3 }, // 1036 { PseudoVFSGNJN_VV_M2_E16_MASK, PseudoVFSGNJN_VV_M2_E16, 0x3 }, // 1037 { PseudoVFSGNJN_VV_M2_E32_MASK, PseudoVFSGNJN_VV_M2_E32, 0x3 }, // 1038 { PseudoVFSGNJN_VV_M2_E64_MASK, PseudoVFSGNJN_VV_M2_E64, 0x3 }, // 1039 { PseudoVFSGNJN_VV_M4_E16_MASK, PseudoVFSGNJN_VV_M4_E16, 0x3 }, // 1040 { PseudoVFSGNJN_VV_M4_E32_MASK, PseudoVFSGNJN_VV_M4_E32, 0x3 }, // 1041 { PseudoVFSGNJN_VV_M4_E64_MASK, PseudoVFSGNJN_VV_M4_E64, 0x3 }, // 1042 { PseudoVFSGNJN_VV_M8_E16_MASK, PseudoVFSGNJN_VV_M8_E16, 0x3 }, // 1043 { PseudoVFSGNJN_VV_M8_E32_MASK, PseudoVFSGNJN_VV_M8_E32, 0x3 }, // 1044 { PseudoVFSGNJN_VV_M8_E64_MASK, PseudoVFSGNJN_VV_M8_E64, 0x3 }, // 1045 { PseudoVFSGNJN_VV_MF2_E16_MASK, PseudoVFSGNJN_VV_MF2_E16, 0x3 }, // 1046 { PseudoVFSGNJN_VV_MF2_E32_MASK, PseudoVFSGNJN_VV_MF2_E32, 0x3 }, // 1047 { PseudoVFSGNJN_VV_MF4_E16_MASK, PseudoVFSGNJN_VV_MF4_E16, 0x3 }, // 1048 { PseudoVFSGNJX_VFPR16_M1_E16_MASK, PseudoVFSGNJX_VFPR16_M1_E16, 0x3 }, // 1049 { PseudoVFSGNJX_VFPR16_M2_E16_MASK, PseudoVFSGNJX_VFPR16_M2_E16, 0x3 }, // 1050 { PseudoVFSGNJX_VFPR16_M4_E16_MASK, PseudoVFSGNJX_VFPR16_M4_E16, 0x3 }, // 1051 { PseudoVFSGNJX_VFPR16_M8_E16_MASK, PseudoVFSGNJX_VFPR16_M8_E16, 0x3 }, // 1052 { PseudoVFSGNJX_VFPR16_MF2_E16_MASK, PseudoVFSGNJX_VFPR16_MF2_E16, 0x3 }, // 1053 { PseudoVFSGNJX_VFPR16_MF4_E16_MASK, PseudoVFSGNJX_VFPR16_MF4_E16, 0x3 }, // 1054 { PseudoVFSGNJX_VFPR32_M1_E32_MASK, PseudoVFSGNJX_VFPR32_M1_E32, 0x3 }, // 1055 { PseudoVFSGNJX_VFPR32_M2_E32_MASK, PseudoVFSGNJX_VFPR32_M2_E32, 0x3 }, // 1056 { PseudoVFSGNJX_VFPR32_M4_E32_MASK, PseudoVFSGNJX_VFPR32_M4_E32, 0x3 }, // 1057 { PseudoVFSGNJX_VFPR32_M8_E32_MASK, PseudoVFSGNJX_VFPR32_M8_E32, 0x3 }, // 1058 { PseudoVFSGNJX_VFPR32_MF2_E32_MASK, PseudoVFSGNJX_VFPR32_MF2_E32, 0x3 }, // 1059 { PseudoVFSGNJX_VFPR64_M1_E64_MASK, PseudoVFSGNJX_VFPR64_M1_E64, 0x3 }, // 1060 { PseudoVFSGNJX_VFPR64_M2_E64_MASK, PseudoVFSGNJX_VFPR64_M2_E64, 0x3 }, // 1061 { PseudoVFSGNJX_VFPR64_M4_E64_MASK, PseudoVFSGNJX_VFPR64_M4_E64, 0x3 }, // 1062 { PseudoVFSGNJX_VFPR64_M8_E64_MASK, PseudoVFSGNJX_VFPR64_M8_E64, 0x3 }, // 1063 { PseudoVFSGNJX_VV_M1_E16_MASK, PseudoVFSGNJX_VV_M1_E16, 0x3 }, // 1064 { PseudoVFSGNJX_VV_M1_E32_MASK, PseudoVFSGNJX_VV_M1_E32, 0x3 }, // 1065 { PseudoVFSGNJX_VV_M1_E64_MASK, PseudoVFSGNJX_VV_M1_E64, 0x3 }, // 1066 { PseudoVFSGNJX_VV_M2_E16_MASK, PseudoVFSGNJX_VV_M2_E16, 0x3 }, // 1067 { PseudoVFSGNJX_VV_M2_E32_MASK, PseudoVFSGNJX_VV_M2_E32, 0x3 }, // 1068 { PseudoVFSGNJX_VV_M2_E64_MASK, PseudoVFSGNJX_VV_M2_E64, 0x3 }, // 1069 { PseudoVFSGNJX_VV_M4_E16_MASK, PseudoVFSGNJX_VV_M4_E16, 0x3 }, // 1070 { PseudoVFSGNJX_VV_M4_E32_MASK, PseudoVFSGNJX_VV_M4_E32, 0x3 }, // 1071 { PseudoVFSGNJX_VV_M4_E64_MASK, PseudoVFSGNJX_VV_M4_E64, 0x3 }, // 1072 { PseudoVFSGNJX_VV_M8_E16_MASK, PseudoVFSGNJX_VV_M8_E16, 0x3 }, // 1073 { PseudoVFSGNJX_VV_M8_E32_MASK, PseudoVFSGNJX_VV_M8_E32, 0x3 }, // 1074 { PseudoVFSGNJX_VV_M8_E64_MASK, PseudoVFSGNJX_VV_M8_E64, 0x3 }, // 1075 { PseudoVFSGNJX_VV_MF2_E16_MASK, PseudoVFSGNJX_VV_MF2_E16, 0x3 }, // 1076 { PseudoVFSGNJX_VV_MF2_E32_MASK, PseudoVFSGNJX_VV_MF2_E32, 0x3 }, // 1077 { PseudoVFSGNJX_VV_MF4_E16_MASK, PseudoVFSGNJX_VV_MF4_E16, 0x3 }, // 1078 { PseudoVFSGNJ_VFPR16_M1_E16_MASK, PseudoVFSGNJ_VFPR16_M1_E16, 0x3 }, // 1079 { PseudoVFSGNJ_VFPR16_M2_E16_MASK, PseudoVFSGNJ_VFPR16_M2_E16, 0x3 }, // 1080 { PseudoVFSGNJ_VFPR16_M4_E16_MASK, PseudoVFSGNJ_VFPR16_M4_E16, 0x3 }, // 1081 { PseudoVFSGNJ_VFPR16_M8_E16_MASK, PseudoVFSGNJ_VFPR16_M8_E16, 0x3 }, // 1082 { PseudoVFSGNJ_VFPR16_MF2_E16_MASK, PseudoVFSGNJ_VFPR16_MF2_E16, 0x3 }, // 1083 { PseudoVFSGNJ_VFPR16_MF4_E16_MASK, PseudoVFSGNJ_VFPR16_MF4_E16, 0x3 }, // 1084 { PseudoVFSGNJ_VFPR32_M1_E32_MASK, PseudoVFSGNJ_VFPR32_M1_E32, 0x3 }, // 1085 { PseudoVFSGNJ_VFPR32_M2_E32_MASK, PseudoVFSGNJ_VFPR32_M2_E32, 0x3 }, // 1086 { PseudoVFSGNJ_VFPR32_M4_E32_MASK, PseudoVFSGNJ_VFPR32_M4_E32, 0x3 }, // 1087 { PseudoVFSGNJ_VFPR32_M8_E32_MASK, PseudoVFSGNJ_VFPR32_M8_E32, 0x3 }, // 1088 { PseudoVFSGNJ_VFPR32_MF2_E32_MASK, PseudoVFSGNJ_VFPR32_MF2_E32, 0x3 }, // 1089 { PseudoVFSGNJ_VFPR64_M1_E64_MASK, PseudoVFSGNJ_VFPR64_M1_E64, 0x3 }, // 1090 { PseudoVFSGNJ_VFPR64_M2_E64_MASK, PseudoVFSGNJ_VFPR64_M2_E64, 0x3 }, // 1091 { PseudoVFSGNJ_VFPR64_M4_E64_MASK, PseudoVFSGNJ_VFPR64_M4_E64, 0x3 }, // 1092 { PseudoVFSGNJ_VFPR64_M8_E64_MASK, PseudoVFSGNJ_VFPR64_M8_E64, 0x3 }, // 1093 { PseudoVFSGNJ_VV_M1_E16_MASK, PseudoVFSGNJ_VV_M1_E16, 0x3 }, // 1094 { PseudoVFSGNJ_VV_M1_E32_MASK, PseudoVFSGNJ_VV_M1_E32, 0x3 }, // 1095 { PseudoVFSGNJ_VV_M1_E64_MASK, PseudoVFSGNJ_VV_M1_E64, 0x3 }, // 1096 { PseudoVFSGNJ_VV_M2_E16_MASK, PseudoVFSGNJ_VV_M2_E16, 0x3 }, // 1097 { PseudoVFSGNJ_VV_M2_E32_MASK, PseudoVFSGNJ_VV_M2_E32, 0x3 }, // 1098 { PseudoVFSGNJ_VV_M2_E64_MASK, PseudoVFSGNJ_VV_M2_E64, 0x3 }, // 1099 { PseudoVFSGNJ_VV_M4_E16_MASK, PseudoVFSGNJ_VV_M4_E16, 0x3 }, // 1100 { PseudoVFSGNJ_VV_M4_E32_MASK, PseudoVFSGNJ_VV_M4_E32, 0x3 }, // 1101 { PseudoVFSGNJ_VV_M4_E64_MASK, PseudoVFSGNJ_VV_M4_E64, 0x3 }, // 1102 { PseudoVFSGNJ_VV_M8_E16_MASK, PseudoVFSGNJ_VV_M8_E16, 0x3 }, // 1103 { PseudoVFSGNJ_VV_M8_E32_MASK, PseudoVFSGNJ_VV_M8_E32, 0x3 }, // 1104 { PseudoVFSGNJ_VV_M8_E64_MASK, PseudoVFSGNJ_VV_M8_E64, 0x3 }, // 1105 { PseudoVFSGNJ_VV_MF2_E16_MASK, PseudoVFSGNJ_VV_MF2_E16, 0x3 }, // 1106 { PseudoVFSGNJ_VV_MF2_E32_MASK, PseudoVFSGNJ_VV_MF2_E32, 0x3 }, // 1107 { PseudoVFSGNJ_VV_MF4_E16_MASK, PseudoVFSGNJ_VV_MF4_E16, 0x3 }, // 1108 { PseudoVFSLIDE1DOWN_VFPR16_M1_MASK, PseudoVFSLIDE1DOWN_VFPR16_M1, 0x3 }, // 1109 { PseudoVFSLIDE1DOWN_VFPR16_M2_MASK, PseudoVFSLIDE1DOWN_VFPR16_M2, 0x3 }, // 1110 { PseudoVFSLIDE1DOWN_VFPR16_M4_MASK, PseudoVFSLIDE1DOWN_VFPR16_M4, 0x3 }, // 1111 { PseudoVFSLIDE1DOWN_VFPR16_M8_MASK, PseudoVFSLIDE1DOWN_VFPR16_M8, 0x3 }, // 1112 { PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK, PseudoVFSLIDE1DOWN_VFPR16_MF2, 0x3 }, // 1113 { PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK, PseudoVFSLIDE1DOWN_VFPR16_MF4, 0x3 }, // 1114 { PseudoVFSLIDE1DOWN_VFPR32_M1_MASK, PseudoVFSLIDE1DOWN_VFPR32_M1, 0x3 }, // 1115 { PseudoVFSLIDE1DOWN_VFPR32_M2_MASK, PseudoVFSLIDE1DOWN_VFPR32_M2, 0x3 }, // 1116 { PseudoVFSLIDE1DOWN_VFPR32_M4_MASK, PseudoVFSLIDE1DOWN_VFPR32_M4, 0x3 }, // 1117 { PseudoVFSLIDE1DOWN_VFPR32_M8_MASK, PseudoVFSLIDE1DOWN_VFPR32_M8, 0x3 }, // 1118 { PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK, PseudoVFSLIDE1DOWN_VFPR32_MF2, 0x3 }, // 1119 { PseudoVFSLIDE1DOWN_VFPR64_M1_MASK, PseudoVFSLIDE1DOWN_VFPR64_M1, 0x3 }, // 1120 { PseudoVFSLIDE1DOWN_VFPR64_M2_MASK, PseudoVFSLIDE1DOWN_VFPR64_M2, 0x3 }, // 1121 { PseudoVFSLIDE1DOWN_VFPR64_M4_MASK, PseudoVFSLIDE1DOWN_VFPR64_M4, 0x3 }, // 1122 { PseudoVFSLIDE1DOWN_VFPR64_M8_MASK, PseudoVFSLIDE1DOWN_VFPR64_M8, 0x3 }, // 1123 { PseudoVFSLIDE1UP_VFPR16_M1_MASK, PseudoVFSLIDE1UP_VFPR16_M1, 0x3 }, // 1124 { PseudoVFSLIDE1UP_VFPR16_M2_MASK, PseudoVFSLIDE1UP_VFPR16_M2, 0x3 }, // 1125 { PseudoVFSLIDE1UP_VFPR16_M4_MASK, PseudoVFSLIDE1UP_VFPR16_M4, 0x3 }, // 1126 { PseudoVFSLIDE1UP_VFPR16_M8_MASK, PseudoVFSLIDE1UP_VFPR16_M8, 0x3 }, // 1127 { PseudoVFSLIDE1UP_VFPR16_MF2_MASK, PseudoVFSLIDE1UP_VFPR16_MF2, 0x3 }, // 1128 { PseudoVFSLIDE1UP_VFPR16_MF4_MASK, PseudoVFSLIDE1UP_VFPR16_MF4, 0x3 }, // 1129 { PseudoVFSLIDE1UP_VFPR32_M1_MASK, PseudoVFSLIDE1UP_VFPR32_M1, 0x3 }, // 1130 { PseudoVFSLIDE1UP_VFPR32_M2_MASK, PseudoVFSLIDE1UP_VFPR32_M2, 0x3 }, // 1131 { PseudoVFSLIDE1UP_VFPR32_M4_MASK, PseudoVFSLIDE1UP_VFPR32_M4, 0x3 }, // 1132 { PseudoVFSLIDE1UP_VFPR32_M8_MASK, PseudoVFSLIDE1UP_VFPR32_M8, 0x3 }, // 1133 { PseudoVFSLIDE1UP_VFPR32_MF2_MASK, PseudoVFSLIDE1UP_VFPR32_MF2, 0x3 }, // 1134 { PseudoVFSLIDE1UP_VFPR64_M1_MASK, PseudoVFSLIDE1UP_VFPR64_M1, 0x3 }, // 1135 { PseudoVFSLIDE1UP_VFPR64_M2_MASK, PseudoVFSLIDE1UP_VFPR64_M2, 0x3 }, // 1136 { PseudoVFSLIDE1UP_VFPR64_M4_MASK, PseudoVFSLIDE1UP_VFPR64_M4, 0x3 }, // 1137 { PseudoVFSLIDE1UP_VFPR64_M8_MASK, PseudoVFSLIDE1UP_VFPR64_M8, 0x3 }, // 1138 { PseudoVFSQRT_V_M1_E16_MASK, PseudoVFSQRT_V_M1_E16, 0x2 }, // 1139 { PseudoVFSQRT_V_M1_E32_MASK, PseudoVFSQRT_V_M1_E32, 0x2 }, // 1140 { PseudoVFSQRT_V_M1_E64_MASK, PseudoVFSQRT_V_M1_E64, 0x2 }, // 1141 { PseudoVFSQRT_V_M2_E16_MASK, PseudoVFSQRT_V_M2_E16, 0x2 }, // 1142 { PseudoVFSQRT_V_M2_E32_MASK, PseudoVFSQRT_V_M2_E32, 0x2 }, // 1143 { PseudoVFSQRT_V_M2_E64_MASK, PseudoVFSQRT_V_M2_E64, 0x2 }, // 1144 { PseudoVFSQRT_V_M4_E16_MASK, PseudoVFSQRT_V_M4_E16, 0x2 }, // 1145 { PseudoVFSQRT_V_M4_E32_MASK, PseudoVFSQRT_V_M4_E32, 0x2 }, // 1146 { PseudoVFSQRT_V_M4_E64_MASK, PseudoVFSQRT_V_M4_E64, 0x2 }, // 1147 { PseudoVFSQRT_V_M8_E16_MASK, PseudoVFSQRT_V_M8_E16, 0x2 }, // 1148 { PseudoVFSQRT_V_M8_E32_MASK, PseudoVFSQRT_V_M8_E32, 0x2 }, // 1149 { PseudoVFSQRT_V_M8_E64_MASK, PseudoVFSQRT_V_M8_E64, 0x2 }, // 1150 { PseudoVFSQRT_V_MF2_E16_MASK, PseudoVFSQRT_V_MF2_E16, 0x2 }, // 1151 { PseudoVFSQRT_V_MF2_E32_MASK, PseudoVFSQRT_V_MF2_E32, 0x2 }, // 1152 { PseudoVFSQRT_V_MF4_E16_MASK, PseudoVFSQRT_V_MF4_E16, 0x2 }, // 1153 { PseudoVFSUB_VFPR16_M1_E16_MASK, PseudoVFSUB_VFPR16_M1_E16, 0x3 }, // 1154 { PseudoVFSUB_VFPR16_M2_E16_MASK, PseudoVFSUB_VFPR16_M2_E16, 0x3 }, // 1155 { PseudoVFSUB_VFPR16_M4_E16_MASK, PseudoVFSUB_VFPR16_M4_E16, 0x3 }, // 1156 { PseudoVFSUB_VFPR16_M8_E16_MASK, PseudoVFSUB_VFPR16_M8_E16, 0x3 }, // 1157 { PseudoVFSUB_VFPR16_MF2_E16_MASK, PseudoVFSUB_VFPR16_MF2_E16, 0x3 }, // 1158 { PseudoVFSUB_VFPR16_MF4_E16_MASK, PseudoVFSUB_VFPR16_MF4_E16, 0x3 }, // 1159 { PseudoVFSUB_VFPR32_M1_E32_MASK, PseudoVFSUB_VFPR32_M1_E32, 0x3 }, // 1160 { PseudoVFSUB_VFPR32_M2_E32_MASK, PseudoVFSUB_VFPR32_M2_E32, 0x3 }, // 1161 { PseudoVFSUB_VFPR32_M4_E32_MASK, PseudoVFSUB_VFPR32_M4_E32, 0x3 }, // 1162 { PseudoVFSUB_VFPR32_M8_E32_MASK, PseudoVFSUB_VFPR32_M8_E32, 0x3 }, // 1163 { PseudoVFSUB_VFPR32_MF2_E32_MASK, PseudoVFSUB_VFPR32_MF2_E32, 0x3 }, // 1164 { PseudoVFSUB_VFPR64_M1_E64_MASK, PseudoVFSUB_VFPR64_M1_E64, 0x3 }, // 1165 { PseudoVFSUB_VFPR64_M2_E64_MASK, PseudoVFSUB_VFPR64_M2_E64, 0x3 }, // 1166 { PseudoVFSUB_VFPR64_M4_E64_MASK, PseudoVFSUB_VFPR64_M4_E64, 0x3 }, // 1167 { PseudoVFSUB_VFPR64_M8_E64_MASK, PseudoVFSUB_VFPR64_M8_E64, 0x3 }, // 1168 { PseudoVFSUB_VV_M1_E16_MASK, PseudoVFSUB_VV_M1_E16, 0x3 }, // 1169 { PseudoVFSUB_VV_M1_E32_MASK, PseudoVFSUB_VV_M1_E32, 0x3 }, // 1170 { PseudoVFSUB_VV_M1_E64_MASK, PseudoVFSUB_VV_M1_E64, 0x3 }, // 1171 { PseudoVFSUB_VV_M2_E16_MASK, PseudoVFSUB_VV_M2_E16, 0x3 }, // 1172 { PseudoVFSUB_VV_M2_E32_MASK, PseudoVFSUB_VV_M2_E32, 0x3 }, // 1173 { PseudoVFSUB_VV_M2_E64_MASK, PseudoVFSUB_VV_M2_E64, 0x3 }, // 1174 { PseudoVFSUB_VV_M4_E16_MASK, PseudoVFSUB_VV_M4_E16, 0x3 }, // 1175 { PseudoVFSUB_VV_M4_E32_MASK, PseudoVFSUB_VV_M4_E32, 0x3 }, // 1176 { PseudoVFSUB_VV_M4_E64_MASK, PseudoVFSUB_VV_M4_E64, 0x3 }, // 1177 { PseudoVFSUB_VV_M8_E16_MASK, PseudoVFSUB_VV_M8_E16, 0x3 }, // 1178 { PseudoVFSUB_VV_M8_E32_MASK, PseudoVFSUB_VV_M8_E32, 0x3 }, // 1179 { PseudoVFSUB_VV_M8_E64_MASK, PseudoVFSUB_VV_M8_E64, 0x3 }, // 1180 { PseudoVFSUB_VV_MF2_E16_MASK, PseudoVFSUB_VV_MF2_E16, 0x3 }, // 1181 { PseudoVFSUB_VV_MF2_E32_MASK, PseudoVFSUB_VV_MF2_E32, 0x3 }, // 1182 { PseudoVFSUB_VV_MF4_E16_MASK, PseudoVFSUB_VV_MF4_E16, 0x3 }, // 1183 { PseudoVFWADD_VFPR16_M1_E16_MASK, PseudoVFWADD_VFPR16_M1_E16, 0x3 }, // 1184 { PseudoVFWADD_VFPR16_M2_E16_MASK, PseudoVFWADD_VFPR16_M2_E16, 0x3 }, // 1185 { PseudoVFWADD_VFPR16_M4_E16_MASK, PseudoVFWADD_VFPR16_M4_E16, 0x3 }, // 1186 { PseudoVFWADD_VFPR16_MF2_E16_MASK, PseudoVFWADD_VFPR16_MF2_E16, 0x3 }, // 1187 { PseudoVFWADD_VFPR16_MF4_E16_MASK, PseudoVFWADD_VFPR16_MF4_E16, 0x3 }, // 1188 { PseudoVFWADD_VFPR32_M1_E32_MASK, PseudoVFWADD_VFPR32_M1_E32, 0x3 }, // 1189 { PseudoVFWADD_VFPR32_M2_E32_MASK, PseudoVFWADD_VFPR32_M2_E32, 0x3 }, // 1190 { PseudoVFWADD_VFPR32_M4_E32_MASK, PseudoVFWADD_VFPR32_M4_E32, 0x3 }, // 1191 { PseudoVFWADD_VFPR32_MF2_E32_MASK, PseudoVFWADD_VFPR32_MF2_E32, 0x3 }, // 1192 { PseudoVFWADD_VV_M1_E16_MASK, PseudoVFWADD_VV_M1_E16, 0x3 }, // 1193 { PseudoVFWADD_VV_M1_E32_MASK, PseudoVFWADD_VV_M1_E32, 0x3 }, // 1194 { PseudoVFWADD_VV_M2_E16_MASK, PseudoVFWADD_VV_M2_E16, 0x3 }, // 1195 { PseudoVFWADD_VV_M2_E32_MASK, PseudoVFWADD_VV_M2_E32, 0x3 }, // 1196 { PseudoVFWADD_VV_M4_E16_MASK, PseudoVFWADD_VV_M4_E16, 0x3 }, // 1197 { PseudoVFWADD_VV_M4_E32_MASK, PseudoVFWADD_VV_M4_E32, 0x3 }, // 1198 { PseudoVFWADD_VV_MF2_E16_MASK, PseudoVFWADD_VV_MF2_E16, 0x3 }, // 1199 { PseudoVFWADD_VV_MF2_E32_MASK, PseudoVFWADD_VV_MF2_E32, 0x3 }, // 1200 { PseudoVFWADD_VV_MF4_E16_MASK, PseudoVFWADD_VV_MF4_E16, 0x3 }, // 1201 { PseudoVFWADD_WFPR16_M1_E16_MASK, PseudoVFWADD_WFPR16_M1_E16, 0x3 }, // 1202 { PseudoVFWADD_WFPR16_M2_E16_MASK, PseudoVFWADD_WFPR16_M2_E16, 0x3 }, // 1203 { PseudoVFWADD_WFPR16_M4_E16_MASK, PseudoVFWADD_WFPR16_M4_E16, 0x3 }, // 1204 { PseudoVFWADD_WFPR16_MF2_E16_MASK, PseudoVFWADD_WFPR16_MF2_E16, 0x3 }, // 1205 { PseudoVFWADD_WFPR16_MF4_E16_MASK, PseudoVFWADD_WFPR16_MF4_E16, 0x3 }, // 1206 { PseudoVFWADD_WFPR32_M1_E32_MASK, PseudoVFWADD_WFPR32_M1_E32, 0x3 }, // 1207 { PseudoVFWADD_WFPR32_M2_E32_MASK, PseudoVFWADD_WFPR32_M2_E32, 0x3 }, // 1208 { PseudoVFWADD_WFPR32_M4_E32_MASK, PseudoVFWADD_WFPR32_M4_E32, 0x3 }, // 1209 { PseudoVFWADD_WFPR32_MF2_E32_MASK, PseudoVFWADD_WFPR32_MF2_E32, 0x3 }, // 1210 { PseudoVFWADD_WV_M1_E16_MASK, PseudoVFWADD_WV_M1_E16, 0x3 }, // 1211 { PseudoVFWADD_WV_M1_E16_MASK_TIED, PseudoVFWADD_WV_M1_E16_TIED, 0x2 }, // 1212 { PseudoVFWADD_WV_M1_E32_MASK, PseudoVFWADD_WV_M1_E32, 0x3 }, // 1213 { PseudoVFWADD_WV_M1_E32_MASK_TIED, PseudoVFWADD_WV_M1_E32_TIED, 0x2 }, // 1214 { PseudoVFWADD_WV_M2_E16_MASK, PseudoVFWADD_WV_M2_E16, 0x3 }, // 1215 { PseudoVFWADD_WV_M2_E16_MASK_TIED, PseudoVFWADD_WV_M2_E16_TIED, 0x2 }, // 1216 { PseudoVFWADD_WV_M2_E32_MASK, PseudoVFWADD_WV_M2_E32, 0x3 }, // 1217 { PseudoVFWADD_WV_M2_E32_MASK_TIED, PseudoVFWADD_WV_M2_E32_TIED, 0x2 }, // 1218 { PseudoVFWADD_WV_M4_E16_MASK, PseudoVFWADD_WV_M4_E16, 0x3 }, // 1219 { PseudoVFWADD_WV_M4_E16_MASK_TIED, PseudoVFWADD_WV_M4_E16_TIED, 0x2 }, // 1220 { PseudoVFWADD_WV_M4_E32_MASK, PseudoVFWADD_WV_M4_E32, 0x3 }, // 1221 { PseudoVFWADD_WV_M4_E32_MASK_TIED, PseudoVFWADD_WV_M4_E32_TIED, 0x2 }, // 1222 { PseudoVFWADD_WV_MF2_E16_MASK, PseudoVFWADD_WV_MF2_E16, 0x3 }, // 1223 { PseudoVFWADD_WV_MF2_E16_MASK_TIED, PseudoVFWADD_WV_MF2_E16_TIED, 0x2 }, // 1224 { PseudoVFWADD_WV_MF2_E32_MASK, PseudoVFWADD_WV_MF2_E32, 0x3 }, // 1225 { PseudoVFWADD_WV_MF2_E32_MASK_TIED, PseudoVFWADD_WV_MF2_E32_TIED, 0x2 }, // 1226 { PseudoVFWADD_WV_MF4_E16_MASK, PseudoVFWADD_WV_MF4_E16, 0x3 }, // 1227 { PseudoVFWADD_WV_MF4_E16_MASK_TIED, PseudoVFWADD_WV_MF4_E16_TIED, 0x2 }, // 1228 { PseudoVFWCVTBF16_F_F_V_M1_E16_MASK, PseudoVFWCVTBF16_F_F_V_M1_E16, 0x2 }, // 1229 { PseudoVFWCVTBF16_F_F_V_M1_E32_MASK, PseudoVFWCVTBF16_F_F_V_M1_E32, 0x2 }, // 1230 { PseudoVFWCVTBF16_F_F_V_M2_E16_MASK, PseudoVFWCVTBF16_F_F_V_M2_E16, 0x2 }, // 1231 { PseudoVFWCVTBF16_F_F_V_M2_E32_MASK, PseudoVFWCVTBF16_F_F_V_M2_E32, 0x2 }, // 1232 { PseudoVFWCVTBF16_F_F_V_M4_E16_MASK, PseudoVFWCVTBF16_F_F_V_M4_E16, 0x2 }, // 1233 { PseudoVFWCVTBF16_F_F_V_M4_E32_MASK, PseudoVFWCVTBF16_F_F_V_M4_E32, 0x2 }, // 1234 { PseudoVFWCVTBF16_F_F_V_MF2_E16_MASK, PseudoVFWCVTBF16_F_F_V_MF2_E16, 0x2 }, // 1235 { PseudoVFWCVTBF16_F_F_V_MF2_E32_MASK, PseudoVFWCVTBF16_F_F_V_MF2_E32, 0x2 }, // 1236 { PseudoVFWCVTBF16_F_F_V_MF4_E16_MASK, PseudoVFWCVTBF16_F_F_V_MF4_E16, 0x2 }, // 1237 { PseudoVFWCVT_F_F_V_M1_E16_MASK, PseudoVFWCVT_F_F_V_M1_E16, 0x2 }, // 1238 { PseudoVFWCVT_F_F_V_M1_E32_MASK, PseudoVFWCVT_F_F_V_M1_E32, 0x2 }, // 1239 { PseudoVFWCVT_F_F_V_M2_E16_MASK, PseudoVFWCVT_F_F_V_M2_E16, 0x2 }, // 1240 { PseudoVFWCVT_F_F_V_M2_E32_MASK, PseudoVFWCVT_F_F_V_M2_E32, 0x2 }, // 1241 { PseudoVFWCVT_F_F_V_M4_E16_MASK, PseudoVFWCVT_F_F_V_M4_E16, 0x2 }, // 1242 { PseudoVFWCVT_F_F_V_M4_E32_MASK, PseudoVFWCVT_F_F_V_M4_E32, 0x2 }, // 1243 { PseudoVFWCVT_F_F_V_MF2_E16_MASK, PseudoVFWCVT_F_F_V_MF2_E16, 0x2 }, // 1244 { PseudoVFWCVT_F_F_V_MF2_E32_MASK, PseudoVFWCVT_F_F_V_MF2_E32, 0x2 }, // 1245 { PseudoVFWCVT_F_F_V_MF4_E16_MASK, PseudoVFWCVT_F_F_V_MF4_E16, 0x2 }, // 1246 { PseudoVFWCVT_F_XU_V_M1_E16_MASK, PseudoVFWCVT_F_XU_V_M1_E16, 0x2 }, // 1247 { PseudoVFWCVT_F_XU_V_M1_E32_MASK, PseudoVFWCVT_F_XU_V_M1_E32, 0x2 }, // 1248 { PseudoVFWCVT_F_XU_V_M1_E8_MASK, PseudoVFWCVT_F_XU_V_M1_E8, 0x2 }, // 1249 { PseudoVFWCVT_F_XU_V_M2_E16_MASK, PseudoVFWCVT_F_XU_V_M2_E16, 0x2 }, // 1250 { PseudoVFWCVT_F_XU_V_M2_E32_MASK, PseudoVFWCVT_F_XU_V_M2_E32, 0x2 }, // 1251 { PseudoVFWCVT_F_XU_V_M2_E8_MASK, PseudoVFWCVT_F_XU_V_M2_E8, 0x2 }, // 1252 { PseudoVFWCVT_F_XU_V_M4_E16_MASK, PseudoVFWCVT_F_XU_V_M4_E16, 0x2 }, // 1253 { PseudoVFWCVT_F_XU_V_M4_E32_MASK, PseudoVFWCVT_F_XU_V_M4_E32, 0x2 }, // 1254 { PseudoVFWCVT_F_XU_V_M4_E8_MASK, PseudoVFWCVT_F_XU_V_M4_E8, 0x2 }, // 1255 { PseudoVFWCVT_F_XU_V_MF2_E16_MASK, PseudoVFWCVT_F_XU_V_MF2_E16, 0x2 }, // 1256 { PseudoVFWCVT_F_XU_V_MF2_E32_MASK, PseudoVFWCVT_F_XU_V_MF2_E32, 0x2 }, // 1257 { PseudoVFWCVT_F_XU_V_MF2_E8_MASK, PseudoVFWCVT_F_XU_V_MF2_E8, 0x2 }, // 1258 { PseudoVFWCVT_F_XU_V_MF4_E16_MASK, PseudoVFWCVT_F_XU_V_MF4_E16, 0x2 }, // 1259 { PseudoVFWCVT_F_XU_V_MF4_E8_MASK, PseudoVFWCVT_F_XU_V_MF4_E8, 0x2 }, // 1260 { PseudoVFWCVT_F_XU_V_MF8_E8_MASK, PseudoVFWCVT_F_XU_V_MF8_E8, 0x2 }, // 1261 { PseudoVFWCVT_F_X_V_M1_E16_MASK, PseudoVFWCVT_F_X_V_M1_E16, 0x2 }, // 1262 { PseudoVFWCVT_F_X_V_M1_E32_MASK, PseudoVFWCVT_F_X_V_M1_E32, 0x2 }, // 1263 { PseudoVFWCVT_F_X_V_M1_E8_MASK, PseudoVFWCVT_F_X_V_M1_E8, 0x2 }, // 1264 { PseudoVFWCVT_F_X_V_M2_E16_MASK, PseudoVFWCVT_F_X_V_M2_E16, 0x2 }, // 1265 { PseudoVFWCVT_F_X_V_M2_E32_MASK, PseudoVFWCVT_F_X_V_M2_E32, 0x2 }, // 1266 { PseudoVFWCVT_F_X_V_M2_E8_MASK, PseudoVFWCVT_F_X_V_M2_E8, 0x2 }, // 1267 { PseudoVFWCVT_F_X_V_M4_E16_MASK, PseudoVFWCVT_F_X_V_M4_E16, 0x2 }, // 1268 { PseudoVFWCVT_F_X_V_M4_E32_MASK, PseudoVFWCVT_F_X_V_M4_E32, 0x2 }, // 1269 { PseudoVFWCVT_F_X_V_M4_E8_MASK, PseudoVFWCVT_F_X_V_M4_E8, 0x2 }, // 1270 { PseudoVFWCVT_F_X_V_MF2_E16_MASK, PseudoVFWCVT_F_X_V_MF2_E16, 0x2 }, // 1271 { PseudoVFWCVT_F_X_V_MF2_E32_MASK, PseudoVFWCVT_F_X_V_MF2_E32, 0x2 }, // 1272 { PseudoVFWCVT_F_X_V_MF2_E8_MASK, PseudoVFWCVT_F_X_V_MF2_E8, 0x2 }, // 1273 { PseudoVFWCVT_F_X_V_MF4_E16_MASK, PseudoVFWCVT_F_X_V_MF4_E16, 0x2 }, // 1274 { PseudoVFWCVT_F_X_V_MF4_E8_MASK, PseudoVFWCVT_F_X_V_MF4_E8, 0x2 }, // 1275 { PseudoVFWCVT_F_X_V_MF8_E8_MASK, PseudoVFWCVT_F_X_V_MF8_E8, 0x2 }, // 1276 { PseudoVFWCVT_RM_XU_F_V_M1_MASK, PseudoVFWCVT_RM_XU_F_V_M1, 0x2 }, // 1277 { PseudoVFWCVT_RM_XU_F_V_M2_MASK, PseudoVFWCVT_RM_XU_F_V_M2, 0x2 }, // 1278 { PseudoVFWCVT_RM_XU_F_V_M4_MASK, PseudoVFWCVT_RM_XU_F_V_M4, 0x2 }, // 1279 { PseudoVFWCVT_RM_XU_F_V_MF2_MASK, PseudoVFWCVT_RM_XU_F_V_MF2, 0x2 }, // 1280 { PseudoVFWCVT_RM_XU_F_V_MF4_MASK, PseudoVFWCVT_RM_XU_F_V_MF4, 0x2 }, // 1281 { PseudoVFWCVT_RM_X_F_V_M1_MASK, PseudoVFWCVT_RM_X_F_V_M1, 0x2 }, // 1282 { PseudoVFWCVT_RM_X_F_V_M2_MASK, PseudoVFWCVT_RM_X_F_V_M2, 0x2 }, // 1283 { PseudoVFWCVT_RM_X_F_V_M4_MASK, PseudoVFWCVT_RM_X_F_V_M4, 0x2 }, // 1284 { PseudoVFWCVT_RM_X_F_V_MF2_MASK, PseudoVFWCVT_RM_X_F_V_MF2, 0x2 }, // 1285 { PseudoVFWCVT_RM_X_F_V_MF4_MASK, PseudoVFWCVT_RM_X_F_V_MF4, 0x2 }, // 1286 { PseudoVFWCVT_RTZ_XU_F_V_M1_MASK, PseudoVFWCVT_RTZ_XU_F_V_M1, 0x2 }, // 1287 { PseudoVFWCVT_RTZ_XU_F_V_M2_MASK, PseudoVFWCVT_RTZ_XU_F_V_M2, 0x2 }, // 1288 { PseudoVFWCVT_RTZ_XU_F_V_M4_MASK, PseudoVFWCVT_RTZ_XU_F_V_M4, 0x2 }, // 1289 { PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK, PseudoVFWCVT_RTZ_XU_F_V_MF2, 0x2 }, // 1290 { PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK, PseudoVFWCVT_RTZ_XU_F_V_MF4, 0x2 }, // 1291 { PseudoVFWCVT_RTZ_X_F_V_M1_MASK, PseudoVFWCVT_RTZ_X_F_V_M1, 0x2 }, // 1292 { PseudoVFWCVT_RTZ_X_F_V_M2_MASK, PseudoVFWCVT_RTZ_X_F_V_M2, 0x2 }, // 1293 { PseudoVFWCVT_RTZ_X_F_V_M4_MASK, PseudoVFWCVT_RTZ_X_F_V_M4, 0x2 }, // 1294 { PseudoVFWCVT_RTZ_X_F_V_MF2_MASK, PseudoVFWCVT_RTZ_X_F_V_MF2, 0x2 }, // 1295 { PseudoVFWCVT_RTZ_X_F_V_MF4_MASK, PseudoVFWCVT_RTZ_X_F_V_MF4, 0x2 }, // 1296 { PseudoVFWCVT_XU_F_V_M1_MASK, PseudoVFWCVT_XU_F_V_M1, 0x2 }, // 1297 { PseudoVFWCVT_XU_F_V_M2_MASK, PseudoVFWCVT_XU_F_V_M2, 0x2 }, // 1298 { PseudoVFWCVT_XU_F_V_M4_MASK, PseudoVFWCVT_XU_F_V_M4, 0x2 }, // 1299 { PseudoVFWCVT_XU_F_V_MF2_MASK, PseudoVFWCVT_XU_F_V_MF2, 0x2 }, // 1300 { PseudoVFWCVT_XU_F_V_MF4_MASK, PseudoVFWCVT_XU_F_V_MF4, 0x2 }, // 1301 { PseudoVFWCVT_X_F_V_M1_MASK, PseudoVFWCVT_X_F_V_M1, 0x2 }, // 1302 { PseudoVFWCVT_X_F_V_M2_MASK, PseudoVFWCVT_X_F_V_M2, 0x2 }, // 1303 { PseudoVFWCVT_X_F_V_M4_MASK, PseudoVFWCVT_X_F_V_M4, 0x2 }, // 1304 { PseudoVFWCVT_X_F_V_MF2_MASK, PseudoVFWCVT_X_F_V_MF2, 0x2 }, // 1305 { PseudoVFWCVT_X_F_V_MF4_MASK, PseudoVFWCVT_X_F_V_MF4, 0x2 }, // 1306 { PseudoVFWMACCBF16_VFPR16_M1_E16_MASK, PseudoVFWMACCBF16_VFPR16_M1_E16, 0x3 }, // 1307 { PseudoVFWMACCBF16_VFPR16_M2_E16_MASK, PseudoVFWMACCBF16_VFPR16_M2_E16, 0x3 }, // 1308 { PseudoVFWMACCBF16_VFPR16_M4_E16_MASK, PseudoVFWMACCBF16_VFPR16_M4_E16, 0x3 }, // 1309 { PseudoVFWMACCBF16_VFPR16_MF2_E16_MASK, PseudoVFWMACCBF16_VFPR16_MF2_E16, 0x3 }, // 1310 { PseudoVFWMACCBF16_VFPR16_MF4_E16_MASK, PseudoVFWMACCBF16_VFPR16_MF4_E16, 0x3 }, // 1311 { PseudoVFWMACCBF16_VV_M1_E16_MASK, PseudoVFWMACCBF16_VV_M1_E16, 0x3 }, // 1312 { PseudoVFWMACCBF16_VV_M1_E32_MASK, PseudoVFWMACCBF16_VV_M1_E32, 0x3 }, // 1313 { PseudoVFWMACCBF16_VV_M2_E16_MASK, PseudoVFWMACCBF16_VV_M2_E16, 0x3 }, // 1314 { PseudoVFWMACCBF16_VV_M2_E32_MASK, PseudoVFWMACCBF16_VV_M2_E32, 0x3 }, // 1315 { PseudoVFWMACCBF16_VV_M4_E16_MASK, PseudoVFWMACCBF16_VV_M4_E16, 0x3 }, // 1316 { PseudoVFWMACCBF16_VV_M4_E32_MASK, PseudoVFWMACCBF16_VV_M4_E32, 0x3 }, // 1317 { PseudoVFWMACCBF16_VV_MF2_E16_MASK, PseudoVFWMACCBF16_VV_MF2_E16, 0x3 }, // 1318 { PseudoVFWMACCBF16_VV_MF2_E32_MASK, PseudoVFWMACCBF16_VV_MF2_E32, 0x3 }, // 1319 { PseudoVFWMACCBF16_VV_MF4_E16_MASK, PseudoVFWMACCBF16_VV_MF4_E16, 0x3 }, // 1320 { PseudoVFWMACC_VFPR16_M1_E16_MASK, PseudoVFWMACC_VFPR16_M1_E16, 0x3 }, // 1321 { PseudoVFWMACC_VFPR16_M2_E16_MASK, PseudoVFWMACC_VFPR16_M2_E16, 0x3 }, // 1322 { PseudoVFWMACC_VFPR16_M4_E16_MASK, PseudoVFWMACC_VFPR16_M4_E16, 0x3 }, // 1323 { PseudoVFWMACC_VFPR16_MF2_E16_MASK, PseudoVFWMACC_VFPR16_MF2_E16, 0x3 }, // 1324 { PseudoVFWMACC_VFPR16_MF4_E16_MASK, PseudoVFWMACC_VFPR16_MF4_E16, 0x3 }, // 1325 { PseudoVFWMACC_VFPR32_M1_E32_MASK, PseudoVFWMACC_VFPR32_M1_E32, 0x3 }, // 1326 { PseudoVFWMACC_VFPR32_M2_E32_MASK, PseudoVFWMACC_VFPR32_M2_E32, 0x3 }, // 1327 { PseudoVFWMACC_VFPR32_M4_E32_MASK, PseudoVFWMACC_VFPR32_M4_E32, 0x3 }, // 1328 { PseudoVFWMACC_VFPR32_MF2_E32_MASK, PseudoVFWMACC_VFPR32_MF2_E32, 0x3 }, // 1329 { PseudoVFWMACC_VV_M1_E16_MASK, PseudoVFWMACC_VV_M1_E16, 0x3 }, // 1330 { PseudoVFWMACC_VV_M1_E32_MASK, PseudoVFWMACC_VV_M1_E32, 0x3 }, // 1331 { PseudoVFWMACC_VV_M2_E16_MASK, PseudoVFWMACC_VV_M2_E16, 0x3 }, // 1332 { PseudoVFWMACC_VV_M2_E32_MASK, PseudoVFWMACC_VV_M2_E32, 0x3 }, // 1333 { PseudoVFWMACC_VV_M4_E16_MASK, PseudoVFWMACC_VV_M4_E16, 0x3 }, // 1334 { PseudoVFWMACC_VV_M4_E32_MASK, PseudoVFWMACC_VV_M4_E32, 0x3 }, // 1335 { PseudoVFWMACC_VV_MF2_E16_MASK, PseudoVFWMACC_VV_MF2_E16, 0x3 }, // 1336 { PseudoVFWMACC_VV_MF2_E32_MASK, PseudoVFWMACC_VV_MF2_E32, 0x3 }, // 1337 { PseudoVFWMACC_VV_MF4_E16_MASK, PseudoVFWMACC_VV_MF4_E16, 0x3 }, // 1338 { PseudoVFWMSAC_VFPR16_M1_E16_MASK, PseudoVFWMSAC_VFPR16_M1_E16, 0x3 }, // 1339 { PseudoVFWMSAC_VFPR16_M2_E16_MASK, PseudoVFWMSAC_VFPR16_M2_E16, 0x3 }, // 1340 { PseudoVFWMSAC_VFPR16_M4_E16_MASK, PseudoVFWMSAC_VFPR16_M4_E16, 0x3 }, // 1341 { PseudoVFWMSAC_VFPR16_MF2_E16_MASK, PseudoVFWMSAC_VFPR16_MF2_E16, 0x3 }, // 1342 { PseudoVFWMSAC_VFPR16_MF4_E16_MASK, PseudoVFWMSAC_VFPR16_MF4_E16, 0x3 }, // 1343 { PseudoVFWMSAC_VFPR32_M1_E32_MASK, PseudoVFWMSAC_VFPR32_M1_E32, 0x3 }, // 1344 { PseudoVFWMSAC_VFPR32_M2_E32_MASK, PseudoVFWMSAC_VFPR32_M2_E32, 0x3 }, // 1345 { PseudoVFWMSAC_VFPR32_M4_E32_MASK, PseudoVFWMSAC_VFPR32_M4_E32, 0x3 }, // 1346 { PseudoVFWMSAC_VFPR32_MF2_E32_MASK, PseudoVFWMSAC_VFPR32_MF2_E32, 0x3 }, // 1347 { PseudoVFWMSAC_VV_M1_E16_MASK, PseudoVFWMSAC_VV_M1_E16, 0x3 }, // 1348 { PseudoVFWMSAC_VV_M1_E32_MASK, PseudoVFWMSAC_VV_M1_E32, 0x3 }, // 1349 { PseudoVFWMSAC_VV_M2_E16_MASK, PseudoVFWMSAC_VV_M2_E16, 0x3 }, // 1350 { PseudoVFWMSAC_VV_M2_E32_MASK, PseudoVFWMSAC_VV_M2_E32, 0x3 }, // 1351 { PseudoVFWMSAC_VV_M4_E16_MASK, PseudoVFWMSAC_VV_M4_E16, 0x3 }, // 1352 { PseudoVFWMSAC_VV_M4_E32_MASK, PseudoVFWMSAC_VV_M4_E32, 0x3 }, // 1353 { PseudoVFWMSAC_VV_MF2_E16_MASK, PseudoVFWMSAC_VV_MF2_E16, 0x3 }, // 1354 { PseudoVFWMSAC_VV_MF2_E32_MASK, PseudoVFWMSAC_VV_MF2_E32, 0x3 }, // 1355 { PseudoVFWMSAC_VV_MF4_E16_MASK, PseudoVFWMSAC_VV_MF4_E16, 0x3 }, // 1356 { PseudoVFWMUL_VFPR16_M1_E16_MASK, PseudoVFWMUL_VFPR16_M1_E16, 0x3 }, // 1357 { PseudoVFWMUL_VFPR16_M2_E16_MASK, PseudoVFWMUL_VFPR16_M2_E16, 0x3 }, // 1358 { PseudoVFWMUL_VFPR16_M4_E16_MASK, PseudoVFWMUL_VFPR16_M4_E16, 0x3 }, // 1359 { PseudoVFWMUL_VFPR16_MF2_E16_MASK, PseudoVFWMUL_VFPR16_MF2_E16, 0x3 }, // 1360 { PseudoVFWMUL_VFPR16_MF4_E16_MASK, PseudoVFWMUL_VFPR16_MF4_E16, 0x3 }, // 1361 { PseudoVFWMUL_VFPR32_M1_E32_MASK, PseudoVFWMUL_VFPR32_M1_E32, 0x3 }, // 1362 { PseudoVFWMUL_VFPR32_M2_E32_MASK, PseudoVFWMUL_VFPR32_M2_E32, 0x3 }, // 1363 { PseudoVFWMUL_VFPR32_M4_E32_MASK, PseudoVFWMUL_VFPR32_M4_E32, 0x3 }, // 1364 { PseudoVFWMUL_VFPR32_MF2_E32_MASK, PseudoVFWMUL_VFPR32_MF2_E32, 0x3 }, // 1365 { PseudoVFWMUL_VV_M1_E16_MASK, PseudoVFWMUL_VV_M1_E16, 0x3 }, // 1366 { PseudoVFWMUL_VV_M1_E32_MASK, PseudoVFWMUL_VV_M1_E32, 0x3 }, // 1367 { PseudoVFWMUL_VV_M2_E16_MASK, PseudoVFWMUL_VV_M2_E16, 0x3 }, // 1368 { PseudoVFWMUL_VV_M2_E32_MASK, PseudoVFWMUL_VV_M2_E32, 0x3 }, // 1369 { PseudoVFWMUL_VV_M4_E16_MASK, PseudoVFWMUL_VV_M4_E16, 0x3 }, // 1370 { PseudoVFWMUL_VV_M4_E32_MASK, PseudoVFWMUL_VV_M4_E32, 0x3 }, // 1371 { PseudoVFWMUL_VV_MF2_E16_MASK, PseudoVFWMUL_VV_MF2_E16, 0x3 }, // 1372 { PseudoVFWMUL_VV_MF2_E32_MASK, PseudoVFWMUL_VV_MF2_E32, 0x3 }, // 1373 { PseudoVFWMUL_VV_MF4_E16_MASK, PseudoVFWMUL_VV_MF4_E16, 0x3 }, // 1374 { PseudoVFWNMACC_VFPR16_M1_E16_MASK, PseudoVFWNMACC_VFPR16_M1_E16, 0x3 }, // 1375 { PseudoVFWNMACC_VFPR16_M2_E16_MASK, PseudoVFWNMACC_VFPR16_M2_E16, 0x3 }, // 1376 { PseudoVFWNMACC_VFPR16_M4_E16_MASK, PseudoVFWNMACC_VFPR16_M4_E16, 0x3 }, // 1377 { PseudoVFWNMACC_VFPR16_MF2_E16_MASK, PseudoVFWNMACC_VFPR16_MF2_E16, 0x3 }, // 1378 { PseudoVFWNMACC_VFPR16_MF4_E16_MASK, PseudoVFWNMACC_VFPR16_MF4_E16, 0x3 }, // 1379 { PseudoVFWNMACC_VFPR32_M1_E32_MASK, PseudoVFWNMACC_VFPR32_M1_E32, 0x3 }, // 1380 { PseudoVFWNMACC_VFPR32_M2_E32_MASK, PseudoVFWNMACC_VFPR32_M2_E32, 0x3 }, // 1381 { PseudoVFWNMACC_VFPR32_M4_E32_MASK, PseudoVFWNMACC_VFPR32_M4_E32, 0x3 }, // 1382 { PseudoVFWNMACC_VFPR32_MF2_E32_MASK, PseudoVFWNMACC_VFPR32_MF2_E32, 0x3 }, // 1383 { PseudoVFWNMACC_VV_M1_E16_MASK, PseudoVFWNMACC_VV_M1_E16, 0x3 }, // 1384 { PseudoVFWNMACC_VV_M1_E32_MASK, PseudoVFWNMACC_VV_M1_E32, 0x3 }, // 1385 { PseudoVFWNMACC_VV_M2_E16_MASK, PseudoVFWNMACC_VV_M2_E16, 0x3 }, // 1386 { PseudoVFWNMACC_VV_M2_E32_MASK, PseudoVFWNMACC_VV_M2_E32, 0x3 }, // 1387 { PseudoVFWNMACC_VV_M4_E16_MASK, PseudoVFWNMACC_VV_M4_E16, 0x3 }, // 1388 { PseudoVFWNMACC_VV_M4_E32_MASK, PseudoVFWNMACC_VV_M4_E32, 0x3 }, // 1389 { PseudoVFWNMACC_VV_MF2_E16_MASK, PseudoVFWNMACC_VV_MF2_E16, 0x3 }, // 1390 { PseudoVFWNMACC_VV_MF2_E32_MASK, PseudoVFWNMACC_VV_MF2_E32, 0x3 }, // 1391 { PseudoVFWNMACC_VV_MF4_E16_MASK, PseudoVFWNMACC_VV_MF4_E16, 0x3 }, // 1392 { PseudoVFWNMSAC_VFPR16_M1_E16_MASK, PseudoVFWNMSAC_VFPR16_M1_E16, 0x3 }, // 1393 { PseudoVFWNMSAC_VFPR16_M2_E16_MASK, PseudoVFWNMSAC_VFPR16_M2_E16, 0x3 }, // 1394 { PseudoVFWNMSAC_VFPR16_M4_E16_MASK, PseudoVFWNMSAC_VFPR16_M4_E16, 0x3 }, // 1395 { PseudoVFWNMSAC_VFPR16_MF2_E16_MASK, PseudoVFWNMSAC_VFPR16_MF2_E16, 0x3 }, // 1396 { PseudoVFWNMSAC_VFPR16_MF4_E16_MASK, PseudoVFWNMSAC_VFPR16_MF4_E16, 0x3 }, // 1397 { PseudoVFWNMSAC_VFPR32_M1_E32_MASK, PseudoVFWNMSAC_VFPR32_M1_E32, 0x3 }, // 1398 { PseudoVFWNMSAC_VFPR32_M2_E32_MASK, PseudoVFWNMSAC_VFPR32_M2_E32, 0x3 }, // 1399 { PseudoVFWNMSAC_VFPR32_M4_E32_MASK, PseudoVFWNMSAC_VFPR32_M4_E32, 0x3 }, // 1400 { PseudoVFWNMSAC_VFPR32_MF2_E32_MASK, PseudoVFWNMSAC_VFPR32_MF2_E32, 0x3 }, // 1401 { PseudoVFWNMSAC_VV_M1_E16_MASK, PseudoVFWNMSAC_VV_M1_E16, 0x3 }, // 1402 { PseudoVFWNMSAC_VV_M1_E32_MASK, PseudoVFWNMSAC_VV_M1_E32, 0x3 }, // 1403 { PseudoVFWNMSAC_VV_M2_E16_MASK, PseudoVFWNMSAC_VV_M2_E16, 0x3 }, // 1404 { PseudoVFWNMSAC_VV_M2_E32_MASK, PseudoVFWNMSAC_VV_M2_E32, 0x3 }, // 1405 { PseudoVFWNMSAC_VV_M4_E16_MASK, PseudoVFWNMSAC_VV_M4_E16, 0x3 }, // 1406 { PseudoVFWNMSAC_VV_M4_E32_MASK, PseudoVFWNMSAC_VV_M4_E32, 0x3 }, // 1407 { PseudoVFWNMSAC_VV_MF2_E16_MASK, PseudoVFWNMSAC_VV_MF2_E16, 0x3 }, // 1408 { PseudoVFWNMSAC_VV_MF2_E32_MASK, PseudoVFWNMSAC_VV_MF2_E32, 0x3 }, // 1409 { PseudoVFWNMSAC_VV_MF4_E16_MASK, PseudoVFWNMSAC_VV_MF4_E16, 0x3 }, // 1410 { PseudoVFWREDOSUM_VS_M1_E16_MASK, PseudoVFWREDOSUM_VS_M1_E16, 0x3 }, // 1411 { PseudoVFWREDOSUM_VS_M1_E32_MASK, PseudoVFWREDOSUM_VS_M1_E32, 0x3 }, // 1412 { PseudoVFWREDOSUM_VS_M2_E16_MASK, PseudoVFWREDOSUM_VS_M2_E16, 0x3 }, // 1413 { PseudoVFWREDOSUM_VS_M2_E32_MASK, PseudoVFWREDOSUM_VS_M2_E32, 0x3 }, // 1414 { PseudoVFWREDOSUM_VS_M4_E16_MASK, PseudoVFWREDOSUM_VS_M4_E16, 0x3 }, // 1415 { PseudoVFWREDOSUM_VS_M4_E32_MASK, PseudoVFWREDOSUM_VS_M4_E32, 0x3 }, // 1416 { PseudoVFWREDOSUM_VS_M8_E16_MASK, PseudoVFWREDOSUM_VS_M8_E16, 0x3 }, // 1417 { PseudoVFWREDOSUM_VS_M8_E32_MASK, PseudoVFWREDOSUM_VS_M8_E32, 0x3 }, // 1418 { PseudoVFWREDOSUM_VS_MF2_E16_MASK, PseudoVFWREDOSUM_VS_MF2_E16, 0x3 }, // 1419 { PseudoVFWREDOSUM_VS_MF2_E32_MASK, PseudoVFWREDOSUM_VS_MF2_E32, 0x3 }, // 1420 { PseudoVFWREDOSUM_VS_MF4_E16_MASK, PseudoVFWREDOSUM_VS_MF4_E16, 0x3 }, // 1421 { PseudoVFWREDUSUM_VS_M1_E16_MASK, PseudoVFWREDUSUM_VS_M1_E16, 0x3 }, // 1422 { PseudoVFWREDUSUM_VS_M1_E32_MASK, PseudoVFWREDUSUM_VS_M1_E32, 0x3 }, // 1423 { PseudoVFWREDUSUM_VS_M2_E16_MASK, PseudoVFWREDUSUM_VS_M2_E16, 0x3 }, // 1424 { PseudoVFWREDUSUM_VS_M2_E32_MASK, PseudoVFWREDUSUM_VS_M2_E32, 0x3 }, // 1425 { PseudoVFWREDUSUM_VS_M4_E16_MASK, PseudoVFWREDUSUM_VS_M4_E16, 0x3 }, // 1426 { PseudoVFWREDUSUM_VS_M4_E32_MASK, PseudoVFWREDUSUM_VS_M4_E32, 0x3 }, // 1427 { PseudoVFWREDUSUM_VS_M8_E16_MASK, PseudoVFWREDUSUM_VS_M8_E16, 0x3 }, // 1428 { PseudoVFWREDUSUM_VS_M8_E32_MASK, PseudoVFWREDUSUM_VS_M8_E32, 0x3 }, // 1429 { PseudoVFWREDUSUM_VS_MF2_E16_MASK, PseudoVFWREDUSUM_VS_MF2_E16, 0x3 }, // 1430 { PseudoVFWREDUSUM_VS_MF2_E32_MASK, PseudoVFWREDUSUM_VS_MF2_E32, 0x3 }, // 1431 { PseudoVFWREDUSUM_VS_MF4_E16_MASK, PseudoVFWREDUSUM_VS_MF4_E16, 0x3 }, // 1432 { PseudoVFWSUB_VFPR16_M1_E16_MASK, PseudoVFWSUB_VFPR16_M1_E16, 0x3 }, // 1433 { PseudoVFWSUB_VFPR16_M2_E16_MASK, PseudoVFWSUB_VFPR16_M2_E16, 0x3 }, // 1434 { PseudoVFWSUB_VFPR16_M4_E16_MASK, PseudoVFWSUB_VFPR16_M4_E16, 0x3 }, // 1435 { PseudoVFWSUB_VFPR16_MF2_E16_MASK, PseudoVFWSUB_VFPR16_MF2_E16, 0x3 }, // 1436 { PseudoVFWSUB_VFPR16_MF4_E16_MASK, PseudoVFWSUB_VFPR16_MF4_E16, 0x3 }, // 1437 { PseudoVFWSUB_VFPR32_M1_E32_MASK, PseudoVFWSUB_VFPR32_M1_E32, 0x3 }, // 1438 { PseudoVFWSUB_VFPR32_M2_E32_MASK, PseudoVFWSUB_VFPR32_M2_E32, 0x3 }, // 1439 { PseudoVFWSUB_VFPR32_M4_E32_MASK, PseudoVFWSUB_VFPR32_M4_E32, 0x3 }, // 1440 { PseudoVFWSUB_VFPR32_MF2_E32_MASK, PseudoVFWSUB_VFPR32_MF2_E32, 0x3 }, // 1441 { PseudoVFWSUB_VV_M1_E16_MASK, PseudoVFWSUB_VV_M1_E16, 0x3 }, // 1442 { PseudoVFWSUB_VV_M1_E32_MASK, PseudoVFWSUB_VV_M1_E32, 0x3 }, // 1443 { PseudoVFWSUB_VV_M2_E16_MASK, PseudoVFWSUB_VV_M2_E16, 0x3 }, // 1444 { PseudoVFWSUB_VV_M2_E32_MASK, PseudoVFWSUB_VV_M2_E32, 0x3 }, // 1445 { PseudoVFWSUB_VV_M4_E16_MASK, PseudoVFWSUB_VV_M4_E16, 0x3 }, // 1446 { PseudoVFWSUB_VV_M4_E32_MASK, PseudoVFWSUB_VV_M4_E32, 0x3 }, // 1447 { PseudoVFWSUB_VV_MF2_E16_MASK, PseudoVFWSUB_VV_MF2_E16, 0x3 }, // 1448 { PseudoVFWSUB_VV_MF2_E32_MASK, PseudoVFWSUB_VV_MF2_E32, 0x3 }, // 1449 { PseudoVFWSUB_VV_MF4_E16_MASK, PseudoVFWSUB_VV_MF4_E16, 0x3 }, // 1450 { PseudoVFWSUB_WFPR16_M1_E16_MASK, PseudoVFWSUB_WFPR16_M1_E16, 0x3 }, // 1451 { PseudoVFWSUB_WFPR16_M2_E16_MASK, PseudoVFWSUB_WFPR16_M2_E16, 0x3 }, // 1452 { PseudoVFWSUB_WFPR16_M4_E16_MASK, PseudoVFWSUB_WFPR16_M4_E16, 0x3 }, // 1453 { PseudoVFWSUB_WFPR16_MF2_E16_MASK, PseudoVFWSUB_WFPR16_MF2_E16, 0x3 }, // 1454 { PseudoVFWSUB_WFPR16_MF4_E16_MASK, PseudoVFWSUB_WFPR16_MF4_E16, 0x3 }, // 1455 { PseudoVFWSUB_WFPR32_M1_E32_MASK, PseudoVFWSUB_WFPR32_M1_E32, 0x3 }, // 1456 { PseudoVFWSUB_WFPR32_M2_E32_MASK, PseudoVFWSUB_WFPR32_M2_E32, 0x3 }, // 1457 { PseudoVFWSUB_WFPR32_M4_E32_MASK, PseudoVFWSUB_WFPR32_M4_E32, 0x3 }, // 1458 { PseudoVFWSUB_WFPR32_MF2_E32_MASK, PseudoVFWSUB_WFPR32_MF2_E32, 0x3 }, // 1459 { PseudoVFWSUB_WV_M1_E16_MASK, PseudoVFWSUB_WV_M1_E16, 0x3 }, // 1460 { PseudoVFWSUB_WV_M1_E16_MASK_TIED, PseudoVFWSUB_WV_M1_E16_TIED, 0x2 }, // 1461 { PseudoVFWSUB_WV_M1_E32_MASK, PseudoVFWSUB_WV_M1_E32, 0x3 }, // 1462 { PseudoVFWSUB_WV_M1_E32_MASK_TIED, PseudoVFWSUB_WV_M1_E32_TIED, 0x2 }, // 1463 { PseudoVFWSUB_WV_M2_E16_MASK, PseudoVFWSUB_WV_M2_E16, 0x3 }, // 1464 { PseudoVFWSUB_WV_M2_E16_MASK_TIED, PseudoVFWSUB_WV_M2_E16_TIED, 0x2 }, // 1465 { PseudoVFWSUB_WV_M2_E32_MASK, PseudoVFWSUB_WV_M2_E32, 0x3 }, // 1466 { PseudoVFWSUB_WV_M2_E32_MASK_TIED, PseudoVFWSUB_WV_M2_E32_TIED, 0x2 }, // 1467 { PseudoVFWSUB_WV_M4_E16_MASK, PseudoVFWSUB_WV_M4_E16, 0x3 }, // 1468 { PseudoVFWSUB_WV_M4_E16_MASK_TIED, PseudoVFWSUB_WV_M4_E16_TIED, 0x2 }, // 1469 { PseudoVFWSUB_WV_M4_E32_MASK, PseudoVFWSUB_WV_M4_E32, 0x3 }, // 1470 { PseudoVFWSUB_WV_M4_E32_MASK_TIED, PseudoVFWSUB_WV_M4_E32_TIED, 0x2 }, // 1471 { PseudoVFWSUB_WV_MF2_E16_MASK, PseudoVFWSUB_WV_MF2_E16, 0x3 }, // 1472 { PseudoVFWSUB_WV_MF2_E16_MASK_TIED, PseudoVFWSUB_WV_MF2_E16_TIED, 0x2 }, // 1473 { PseudoVFWSUB_WV_MF2_E32_MASK, PseudoVFWSUB_WV_MF2_E32, 0x3 }, // 1474 { PseudoVFWSUB_WV_MF2_E32_MASK_TIED, PseudoVFWSUB_WV_MF2_E32_TIED, 0x2 }, // 1475 { PseudoVFWSUB_WV_MF4_E16_MASK, PseudoVFWSUB_WV_MF4_E16, 0x3 }, // 1476 { PseudoVFWSUB_WV_MF4_E16_MASK_TIED, PseudoVFWSUB_WV_MF4_E16_TIED, 0x2 }, // 1477 { PseudoVID_V_M1_MASK, PseudoVID_V_M1, 0x1 }, // 1478 { PseudoVID_V_M2_MASK, PseudoVID_V_M2, 0x1 }, // 1479 { PseudoVID_V_M4_MASK, PseudoVID_V_M4, 0x1 }, // 1480 { PseudoVID_V_M8_MASK, PseudoVID_V_M8, 0x1 }, // 1481 { PseudoVID_V_MF2_MASK, PseudoVID_V_MF2, 0x1 }, // 1482 { PseudoVID_V_MF4_MASK, PseudoVID_V_MF4, 0x1 }, // 1483 { PseudoVID_V_MF8_MASK, PseudoVID_V_MF8, 0x1 }, // 1484 { PseudoVIOTA_M_M1_MASK, PseudoVIOTA_M_M1, 0x2 }, // 1485 { PseudoVIOTA_M_M2_MASK, PseudoVIOTA_M_M2, 0x2 }, // 1486 { PseudoVIOTA_M_M4_MASK, PseudoVIOTA_M_M4, 0x2 }, // 1487 { PseudoVIOTA_M_M8_MASK, PseudoVIOTA_M_M8, 0x2 }, // 1488 { PseudoVIOTA_M_MF2_MASK, PseudoVIOTA_M_MF2, 0x2 }, // 1489 { PseudoVIOTA_M_MF4_MASK, PseudoVIOTA_M_MF4, 0x2 }, // 1490 { PseudoVIOTA_M_MF8_MASK, PseudoVIOTA_M_MF8, 0x2 }, // 1491 { PseudoVLE16FF_V_M1_MASK, PseudoVLE16FF_V_M1, 0x2 }, // 1492 { PseudoVLE16FF_V_M2_MASK, PseudoVLE16FF_V_M2, 0x2 }, // 1493 { PseudoVLE16FF_V_M4_MASK, PseudoVLE16FF_V_M4, 0x2 }, // 1494 { PseudoVLE16FF_V_M8_MASK, PseudoVLE16FF_V_M8, 0x2 }, // 1495 { PseudoVLE16FF_V_MF2_MASK, PseudoVLE16FF_V_MF2, 0x2 }, // 1496 { PseudoVLE16FF_V_MF4_MASK, PseudoVLE16FF_V_MF4, 0x2 }, // 1497 { PseudoVLE16_V_M1_MASK, PseudoVLE16_V_M1, 0x2 }, // 1498 { PseudoVLE16_V_M2_MASK, PseudoVLE16_V_M2, 0x2 }, // 1499 { PseudoVLE16_V_M4_MASK, PseudoVLE16_V_M4, 0x2 }, // 1500 { PseudoVLE16_V_M8_MASK, PseudoVLE16_V_M8, 0x2 }, // 1501 { PseudoVLE16_V_MF2_MASK, PseudoVLE16_V_MF2, 0x2 }, // 1502 { PseudoVLE16_V_MF4_MASK, PseudoVLE16_V_MF4, 0x2 }, // 1503 { PseudoVLE32FF_V_M1_MASK, PseudoVLE32FF_V_M1, 0x2 }, // 1504 { PseudoVLE32FF_V_M2_MASK, PseudoVLE32FF_V_M2, 0x2 }, // 1505 { PseudoVLE32FF_V_M4_MASK, PseudoVLE32FF_V_M4, 0x2 }, // 1506 { PseudoVLE32FF_V_M8_MASK, PseudoVLE32FF_V_M8, 0x2 }, // 1507 { PseudoVLE32FF_V_MF2_MASK, PseudoVLE32FF_V_MF2, 0x2 }, // 1508 { PseudoVLE32_V_M1_MASK, PseudoVLE32_V_M1, 0x2 }, // 1509 { PseudoVLE32_V_M2_MASK, PseudoVLE32_V_M2, 0x2 }, // 1510 { PseudoVLE32_V_M4_MASK, PseudoVLE32_V_M4, 0x2 }, // 1511 { PseudoVLE32_V_M8_MASK, PseudoVLE32_V_M8, 0x2 }, // 1512 { PseudoVLE32_V_MF2_MASK, PseudoVLE32_V_MF2, 0x2 }, // 1513 { PseudoVLE64FF_V_M1_MASK, PseudoVLE64FF_V_M1, 0x2 }, // 1514 { PseudoVLE64FF_V_M2_MASK, PseudoVLE64FF_V_M2, 0x2 }, // 1515 { PseudoVLE64FF_V_M4_MASK, PseudoVLE64FF_V_M4, 0x2 }, // 1516 { PseudoVLE64FF_V_M8_MASK, PseudoVLE64FF_V_M8, 0x2 }, // 1517 { PseudoVLE64_V_M1_MASK, PseudoVLE64_V_M1, 0x2 }, // 1518 { PseudoVLE64_V_M2_MASK, PseudoVLE64_V_M2, 0x2 }, // 1519 { PseudoVLE64_V_M4_MASK, PseudoVLE64_V_M4, 0x2 }, // 1520 { PseudoVLE64_V_M8_MASK, PseudoVLE64_V_M8, 0x2 }, // 1521 { PseudoVLE8FF_V_M1_MASK, PseudoVLE8FF_V_M1, 0x2 }, // 1522 { PseudoVLE8FF_V_M2_MASK, PseudoVLE8FF_V_M2, 0x2 }, // 1523 { PseudoVLE8FF_V_M4_MASK, PseudoVLE8FF_V_M4, 0x2 }, // 1524 { PseudoVLE8FF_V_M8_MASK, PseudoVLE8FF_V_M8, 0x2 }, // 1525 { PseudoVLE8FF_V_MF2_MASK, PseudoVLE8FF_V_MF2, 0x2 }, // 1526 { PseudoVLE8FF_V_MF4_MASK, PseudoVLE8FF_V_MF4, 0x2 }, // 1527 { PseudoVLE8FF_V_MF8_MASK, PseudoVLE8FF_V_MF8, 0x2 }, // 1528 { PseudoVLE8_V_M1_MASK, PseudoVLE8_V_M1, 0x2 }, // 1529 { PseudoVLE8_V_M2_MASK, PseudoVLE8_V_M2, 0x2 }, // 1530 { PseudoVLE8_V_M4_MASK, PseudoVLE8_V_M4, 0x2 }, // 1531 { PseudoVLE8_V_M8_MASK, PseudoVLE8_V_M8, 0x2 }, // 1532 { PseudoVLE8_V_MF2_MASK, PseudoVLE8_V_MF2, 0x2 }, // 1533 { PseudoVLE8_V_MF4_MASK, PseudoVLE8_V_MF4, 0x2 }, // 1534 { PseudoVLE8_V_MF8_MASK, PseudoVLE8_V_MF8, 0x2 }, // 1535 { PseudoVLOXEI16_V_M1_M1_MASK, PseudoVLOXEI16_V_M1_M1, 0x3 }, // 1536 { PseudoVLOXEI16_V_M1_M2_MASK, PseudoVLOXEI16_V_M1_M2, 0x3 }, // 1537 { PseudoVLOXEI16_V_M1_M4_MASK, PseudoVLOXEI16_V_M1_M4, 0x3 }, // 1538 { PseudoVLOXEI16_V_M1_MF2_MASK, PseudoVLOXEI16_V_M1_MF2, 0x3 }, // 1539 { PseudoVLOXEI16_V_M2_M1_MASK, PseudoVLOXEI16_V_M2_M1, 0x3 }, // 1540 { PseudoVLOXEI16_V_M2_M2_MASK, PseudoVLOXEI16_V_M2_M2, 0x3 }, // 1541 { PseudoVLOXEI16_V_M2_M4_MASK, PseudoVLOXEI16_V_M2_M4, 0x3 }, // 1542 { PseudoVLOXEI16_V_M2_M8_MASK, PseudoVLOXEI16_V_M2_M8, 0x3 }, // 1543 { PseudoVLOXEI16_V_M4_M2_MASK, PseudoVLOXEI16_V_M4_M2, 0x3 }, // 1544 { PseudoVLOXEI16_V_M4_M4_MASK, PseudoVLOXEI16_V_M4_M4, 0x3 }, // 1545 { PseudoVLOXEI16_V_M4_M8_MASK, PseudoVLOXEI16_V_M4_M8, 0x3 }, // 1546 { PseudoVLOXEI16_V_M8_M4_MASK, PseudoVLOXEI16_V_M8_M4, 0x3 }, // 1547 { PseudoVLOXEI16_V_M8_M8_MASK, PseudoVLOXEI16_V_M8_M8, 0x3 }, // 1548 { PseudoVLOXEI16_V_MF2_M1_MASK, PseudoVLOXEI16_V_MF2_M1, 0x3 }, // 1549 { PseudoVLOXEI16_V_MF2_M2_MASK, PseudoVLOXEI16_V_MF2_M2, 0x3 }, // 1550 { PseudoVLOXEI16_V_MF2_MF2_MASK, PseudoVLOXEI16_V_MF2_MF2, 0x3 }, // 1551 { PseudoVLOXEI16_V_MF2_MF4_MASK, PseudoVLOXEI16_V_MF2_MF4, 0x3 }, // 1552 { PseudoVLOXEI16_V_MF4_M1_MASK, PseudoVLOXEI16_V_MF4_M1, 0x3 }, // 1553 { PseudoVLOXEI16_V_MF4_MF2_MASK, PseudoVLOXEI16_V_MF4_MF2, 0x3 }, // 1554 { PseudoVLOXEI16_V_MF4_MF4_MASK, PseudoVLOXEI16_V_MF4_MF4, 0x3 }, // 1555 { PseudoVLOXEI16_V_MF4_MF8_MASK, PseudoVLOXEI16_V_MF4_MF8, 0x3 }, // 1556 { PseudoVLOXEI32_V_M1_M1_MASK, PseudoVLOXEI32_V_M1_M1, 0x3 }, // 1557 { PseudoVLOXEI32_V_M1_M2_MASK, PseudoVLOXEI32_V_M1_M2, 0x3 }, // 1558 { PseudoVLOXEI32_V_M1_MF2_MASK, PseudoVLOXEI32_V_M1_MF2, 0x3 }, // 1559 { PseudoVLOXEI32_V_M1_MF4_MASK, PseudoVLOXEI32_V_M1_MF4, 0x3 }, // 1560 { PseudoVLOXEI32_V_M2_M1_MASK, PseudoVLOXEI32_V_M2_M1, 0x3 }, // 1561 { PseudoVLOXEI32_V_M2_M2_MASK, PseudoVLOXEI32_V_M2_M2, 0x3 }, // 1562 { PseudoVLOXEI32_V_M2_M4_MASK, PseudoVLOXEI32_V_M2_M4, 0x3 }, // 1563 { PseudoVLOXEI32_V_M2_MF2_MASK, PseudoVLOXEI32_V_M2_MF2, 0x3 }, // 1564 { PseudoVLOXEI32_V_M4_M1_MASK, PseudoVLOXEI32_V_M4_M1, 0x3 }, // 1565 { PseudoVLOXEI32_V_M4_M2_MASK, PseudoVLOXEI32_V_M4_M2, 0x3 }, // 1566 { PseudoVLOXEI32_V_M4_M4_MASK, PseudoVLOXEI32_V_M4_M4, 0x3 }, // 1567 { PseudoVLOXEI32_V_M4_M8_MASK, PseudoVLOXEI32_V_M4_M8, 0x3 }, // 1568 { PseudoVLOXEI32_V_M8_M2_MASK, PseudoVLOXEI32_V_M8_M2, 0x3 }, // 1569 { PseudoVLOXEI32_V_M8_M4_MASK, PseudoVLOXEI32_V_M8_M4, 0x3 }, // 1570 { PseudoVLOXEI32_V_M8_M8_MASK, PseudoVLOXEI32_V_M8_M8, 0x3 }, // 1571 { PseudoVLOXEI32_V_MF2_M1_MASK, PseudoVLOXEI32_V_MF2_M1, 0x3 }, // 1572 { PseudoVLOXEI32_V_MF2_MF2_MASK, PseudoVLOXEI32_V_MF2_MF2, 0x3 }, // 1573 { PseudoVLOXEI32_V_MF2_MF4_MASK, PseudoVLOXEI32_V_MF2_MF4, 0x3 }, // 1574 { PseudoVLOXEI32_V_MF2_MF8_MASK, PseudoVLOXEI32_V_MF2_MF8, 0x3 }, // 1575 { PseudoVLOXEI64_V_M1_M1_MASK, PseudoVLOXEI64_V_M1_M1, 0x3 }, // 1576 { PseudoVLOXEI64_V_M1_MF2_MASK, PseudoVLOXEI64_V_M1_MF2, 0x3 }, // 1577 { PseudoVLOXEI64_V_M1_MF4_MASK, PseudoVLOXEI64_V_M1_MF4, 0x3 }, // 1578 { PseudoVLOXEI64_V_M1_MF8_MASK, PseudoVLOXEI64_V_M1_MF8, 0x3 }, // 1579 { PseudoVLOXEI64_V_M2_M1_MASK, PseudoVLOXEI64_V_M2_M1, 0x3 }, // 1580 { PseudoVLOXEI64_V_M2_M2_MASK, PseudoVLOXEI64_V_M2_M2, 0x3 }, // 1581 { PseudoVLOXEI64_V_M2_MF2_MASK, PseudoVLOXEI64_V_M2_MF2, 0x3 }, // 1582 { PseudoVLOXEI64_V_M2_MF4_MASK, PseudoVLOXEI64_V_M2_MF4, 0x3 }, // 1583 { PseudoVLOXEI64_V_M4_M1_MASK, PseudoVLOXEI64_V_M4_M1, 0x3 }, // 1584 { PseudoVLOXEI64_V_M4_M2_MASK, PseudoVLOXEI64_V_M4_M2, 0x3 }, // 1585 { PseudoVLOXEI64_V_M4_M4_MASK, PseudoVLOXEI64_V_M4_M4, 0x3 }, // 1586 { PseudoVLOXEI64_V_M4_MF2_MASK, PseudoVLOXEI64_V_M4_MF2, 0x3 }, // 1587 { PseudoVLOXEI64_V_M8_M1_MASK, PseudoVLOXEI64_V_M8_M1, 0x3 }, // 1588 { PseudoVLOXEI64_V_M8_M2_MASK, PseudoVLOXEI64_V_M8_M2, 0x3 }, // 1589 { PseudoVLOXEI64_V_M8_M4_MASK, PseudoVLOXEI64_V_M8_M4, 0x3 }, // 1590 { PseudoVLOXEI64_V_M8_M8_MASK, PseudoVLOXEI64_V_M8_M8, 0x3 }, // 1591 { PseudoVLOXEI8_V_M1_M1_MASK, PseudoVLOXEI8_V_M1_M1, 0x3 }, // 1592 { PseudoVLOXEI8_V_M1_M2_MASK, PseudoVLOXEI8_V_M1_M2, 0x3 }, // 1593 { PseudoVLOXEI8_V_M1_M4_MASK, PseudoVLOXEI8_V_M1_M4, 0x3 }, // 1594 { PseudoVLOXEI8_V_M1_M8_MASK, PseudoVLOXEI8_V_M1_M8, 0x3 }, // 1595 { PseudoVLOXEI8_V_M2_M2_MASK, PseudoVLOXEI8_V_M2_M2, 0x3 }, // 1596 { PseudoVLOXEI8_V_M2_M4_MASK, PseudoVLOXEI8_V_M2_M4, 0x3 }, // 1597 { PseudoVLOXEI8_V_M2_M8_MASK, PseudoVLOXEI8_V_M2_M8, 0x3 }, // 1598 { PseudoVLOXEI8_V_M4_M4_MASK, PseudoVLOXEI8_V_M4_M4, 0x3 }, // 1599 { PseudoVLOXEI8_V_M4_M8_MASK, PseudoVLOXEI8_V_M4_M8, 0x3 }, // 1600 { PseudoVLOXEI8_V_M8_M8_MASK, PseudoVLOXEI8_V_M8_M8, 0x3 }, // 1601 { PseudoVLOXEI8_V_MF2_M1_MASK, PseudoVLOXEI8_V_MF2_M1, 0x3 }, // 1602 { PseudoVLOXEI8_V_MF2_M2_MASK, PseudoVLOXEI8_V_MF2_M2, 0x3 }, // 1603 { PseudoVLOXEI8_V_MF2_M4_MASK, PseudoVLOXEI8_V_MF2_M4, 0x3 }, // 1604 { PseudoVLOXEI8_V_MF2_MF2_MASK, PseudoVLOXEI8_V_MF2_MF2, 0x3 }, // 1605 { PseudoVLOXEI8_V_MF4_M1_MASK, PseudoVLOXEI8_V_MF4_M1, 0x3 }, // 1606 { PseudoVLOXEI8_V_MF4_M2_MASK, PseudoVLOXEI8_V_MF4_M2, 0x3 }, // 1607 { PseudoVLOXEI8_V_MF4_MF2_MASK, PseudoVLOXEI8_V_MF4_MF2, 0x3 }, // 1608 { PseudoVLOXEI8_V_MF4_MF4_MASK, PseudoVLOXEI8_V_MF4_MF4, 0x3 }, // 1609 { PseudoVLOXEI8_V_MF8_M1_MASK, PseudoVLOXEI8_V_MF8_M1, 0x3 }, // 1610 { PseudoVLOXEI8_V_MF8_MF2_MASK, PseudoVLOXEI8_V_MF8_MF2, 0x3 }, // 1611 { PseudoVLOXEI8_V_MF8_MF4_MASK, PseudoVLOXEI8_V_MF8_MF4, 0x3 }, // 1612 { PseudoVLOXEI8_V_MF8_MF8_MASK, PseudoVLOXEI8_V_MF8_MF8, 0x3 }, // 1613 { PseudoVLSE16_V_M1_MASK, PseudoVLSE16_V_M1, 0x3 }, // 1614 { PseudoVLSE16_V_M2_MASK, PseudoVLSE16_V_M2, 0x3 }, // 1615 { PseudoVLSE16_V_M4_MASK, PseudoVLSE16_V_M4, 0x3 }, // 1616 { PseudoVLSE16_V_M8_MASK, PseudoVLSE16_V_M8, 0x3 }, // 1617 { PseudoVLSE16_V_MF2_MASK, PseudoVLSE16_V_MF2, 0x3 }, // 1618 { PseudoVLSE16_V_MF4_MASK, PseudoVLSE16_V_MF4, 0x3 }, // 1619 { PseudoVLSE32_V_M1_MASK, PseudoVLSE32_V_M1, 0x3 }, // 1620 { PseudoVLSE32_V_M2_MASK, PseudoVLSE32_V_M2, 0x3 }, // 1621 { PseudoVLSE32_V_M4_MASK, PseudoVLSE32_V_M4, 0x3 }, // 1622 { PseudoVLSE32_V_M8_MASK, PseudoVLSE32_V_M8, 0x3 }, // 1623 { PseudoVLSE32_V_MF2_MASK, PseudoVLSE32_V_MF2, 0x3 }, // 1624 { PseudoVLSE64_V_M1_MASK, PseudoVLSE64_V_M1, 0x3 }, // 1625 { PseudoVLSE64_V_M2_MASK, PseudoVLSE64_V_M2, 0x3 }, // 1626 { PseudoVLSE64_V_M4_MASK, PseudoVLSE64_V_M4, 0x3 }, // 1627 { PseudoVLSE64_V_M8_MASK, PseudoVLSE64_V_M8, 0x3 }, // 1628 { PseudoVLSE8_V_M1_MASK, PseudoVLSE8_V_M1, 0x3 }, // 1629 { PseudoVLSE8_V_M2_MASK, PseudoVLSE8_V_M2, 0x3 }, // 1630 { PseudoVLSE8_V_M4_MASK, PseudoVLSE8_V_M4, 0x3 }, // 1631 { PseudoVLSE8_V_M8_MASK, PseudoVLSE8_V_M8, 0x3 }, // 1632 { PseudoVLSE8_V_MF2_MASK, PseudoVLSE8_V_MF2, 0x3 }, // 1633 { PseudoVLSE8_V_MF4_MASK, PseudoVLSE8_V_MF4, 0x3 }, // 1634 { PseudoVLSE8_V_MF8_MASK, PseudoVLSE8_V_MF8, 0x3 }, // 1635 { PseudoVLUXEI16_V_M1_M1_MASK, PseudoVLUXEI16_V_M1_M1, 0x3 }, // 1636 { PseudoVLUXEI16_V_M1_M2_MASK, PseudoVLUXEI16_V_M1_M2, 0x3 }, // 1637 { PseudoVLUXEI16_V_M1_M4_MASK, PseudoVLUXEI16_V_M1_M4, 0x3 }, // 1638 { PseudoVLUXEI16_V_M1_MF2_MASK, PseudoVLUXEI16_V_M1_MF2, 0x3 }, // 1639 { PseudoVLUXEI16_V_M2_M1_MASK, PseudoVLUXEI16_V_M2_M1, 0x3 }, // 1640 { PseudoVLUXEI16_V_M2_M2_MASK, PseudoVLUXEI16_V_M2_M2, 0x3 }, // 1641 { PseudoVLUXEI16_V_M2_M4_MASK, PseudoVLUXEI16_V_M2_M4, 0x3 }, // 1642 { PseudoVLUXEI16_V_M2_M8_MASK, PseudoVLUXEI16_V_M2_M8, 0x3 }, // 1643 { PseudoVLUXEI16_V_M4_M2_MASK, PseudoVLUXEI16_V_M4_M2, 0x3 }, // 1644 { PseudoVLUXEI16_V_M4_M4_MASK, PseudoVLUXEI16_V_M4_M4, 0x3 }, // 1645 { PseudoVLUXEI16_V_M4_M8_MASK, PseudoVLUXEI16_V_M4_M8, 0x3 }, // 1646 { PseudoVLUXEI16_V_M8_M4_MASK, PseudoVLUXEI16_V_M8_M4, 0x3 }, // 1647 { PseudoVLUXEI16_V_M8_M8_MASK, PseudoVLUXEI16_V_M8_M8, 0x3 }, // 1648 { PseudoVLUXEI16_V_MF2_M1_MASK, PseudoVLUXEI16_V_MF2_M1, 0x3 }, // 1649 { PseudoVLUXEI16_V_MF2_M2_MASK, PseudoVLUXEI16_V_MF2_M2, 0x3 }, // 1650 { PseudoVLUXEI16_V_MF2_MF2_MASK, PseudoVLUXEI16_V_MF2_MF2, 0x3 }, // 1651 { PseudoVLUXEI16_V_MF2_MF4_MASK, PseudoVLUXEI16_V_MF2_MF4, 0x3 }, // 1652 { PseudoVLUXEI16_V_MF4_M1_MASK, PseudoVLUXEI16_V_MF4_M1, 0x3 }, // 1653 { PseudoVLUXEI16_V_MF4_MF2_MASK, PseudoVLUXEI16_V_MF4_MF2, 0x3 }, // 1654 { PseudoVLUXEI16_V_MF4_MF4_MASK, PseudoVLUXEI16_V_MF4_MF4, 0x3 }, // 1655 { PseudoVLUXEI16_V_MF4_MF8_MASK, PseudoVLUXEI16_V_MF4_MF8, 0x3 }, // 1656 { PseudoVLUXEI32_V_M1_M1_MASK, PseudoVLUXEI32_V_M1_M1, 0x3 }, // 1657 { PseudoVLUXEI32_V_M1_M2_MASK, PseudoVLUXEI32_V_M1_M2, 0x3 }, // 1658 { PseudoVLUXEI32_V_M1_MF2_MASK, PseudoVLUXEI32_V_M1_MF2, 0x3 }, // 1659 { PseudoVLUXEI32_V_M1_MF4_MASK, PseudoVLUXEI32_V_M1_MF4, 0x3 }, // 1660 { PseudoVLUXEI32_V_M2_M1_MASK, PseudoVLUXEI32_V_M2_M1, 0x3 }, // 1661 { PseudoVLUXEI32_V_M2_M2_MASK, PseudoVLUXEI32_V_M2_M2, 0x3 }, // 1662 { PseudoVLUXEI32_V_M2_M4_MASK, PseudoVLUXEI32_V_M2_M4, 0x3 }, // 1663 { PseudoVLUXEI32_V_M2_MF2_MASK, PseudoVLUXEI32_V_M2_MF2, 0x3 }, // 1664 { PseudoVLUXEI32_V_M4_M1_MASK, PseudoVLUXEI32_V_M4_M1, 0x3 }, // 1665 { PseudoVLUXEI32_V_M4_M2_MASK, PseudoVLUXEI32_V_M4_M2, 0x3 }, // 1666 { PseudoVLUXEI32_V_M4_M4_MASK, PseudoVLUXEI32_V_M4_M4, 0x3 }, // 1667 { PseudoVLUXEI32_V_M4_M8_MASK, PseudoVLUXEI32_V_M4_M8, 0x3 }, // 1668 { PseudoVLUXEI32_V_M8_M2_MASK, PseudoVLUXEI32_V_M8_M2, 0x3 }, // 1669 { PseudoVLUXEI32_V_M8_M4_MASK, PseudoVLUXEI32_V_M8_M4, 0x3 }, // 1670 { PseudoVLUXEI32_V_M8_M8_MASK, PseudoVLUXEI32_V_M8_M8, 0x3 }, // 1671 { PseudoVLUXEI32_V_MF2_M1_MASK, PseudoVLUXEI32_V_MF2_M1, 0x3 }, // 1672 { PseudoVLUXEI32_V_MF2_MF2_MASK, PseudoVLUXEI32_V_MF2_MF2, 0x3 }, // 1673 { PseudoVLUXEI32_V_MF2_MF4_MASK, PseudoVLUXEI32_V_MF2_MF4, 0x3 }, // 1674 { PseudoVLUXEI32_V_MF2_MF8_MASK, PseudoVLUXEI32_V_MF2_MF8, 0x3 }, // 1675 { PseudoVLUXEI64_V_M1_M1_MASK, PseudoVLUXEI64_V_M1_M1, 0x3 }, // 1676 { PseudoVLUXEI64_V_M1_MF2_MASK, PseudoVLUXEI64_V_M1_MF2, 0x3 }, // 1677 { PseudoVLUXEI64_V_M1_MF4_MASK, PseudoVLUXEI64_V_M1_MF4, 0x3 }, // 1678 { PseudoVLUXEI64_V_M1_MF8_MASK, PseudoVLUXEI64_V_M1_MF8, 0x3 }, // 1679 { PseudoVLUXEI64_V_M2_M1_MASK, PseudoVLUXEI64_V_M2_M1, 0x3 }, // 1680 { PseudoVLUXEI64_V_M2_M2_MASK, PseudoVLUXEI64_V_M2_M2, 0x3 }, // 1681 { PseudoVLUXEI64_V_M2_MF2_MASK, PseudoVLUXEI64_V_M2_MF2, 0x3 }, // 1682 { PseudoVLUXEI64_V_M2_MF4_MASK, PseudoVLUXEI64_V_M2_MF4, 0x3 }, // 1683 { PseudoVLUXEI64_V_M4_M1_MASK, PseudoVLUXEI64_V_M4_M1, 0x3 }, // 1684 { PseudoVLUXEI64_V_M4_M2_MASK, PseudoVLUXEI64_V_M4_M2, 0x3 }, // 1685 { PseudoVLUXEI64_V_M4_M4_MASK, PseudoVLUXEI64_V_M4_M4, 0x3 }, // 1686 { PseudoVLUXEI64_V_M4_MF2_MASK, PseudoVLUXEI64_V_M4_MF2, 0x3 }, // 1687 { PseudoVLUXEI64_V_M8_M1_MASK, PseudoVLUXEI64_V_M8_M1, 0x3 }, // 1688 { PseudoVLUXEI64_V_M8_M2_MASK, PseudoVLUXEI64_V_M8_M2, 0x3 }, // 1689 { PseudoVLUXEI64_V_M8_M4_MASK, PseudoVLUXEI64_V_M8_M4, 0x3 }, // 1690 { PseudoVLUXEI64_V_M8_M8_MASK, PseudoVLUXEI64_V_M8_M8, 0x3 }, // 1691 { PseudoVLUXEI8_V_M1_M1_MASK, PseudoVLUXEI8_V_M1_M1, 0x3 }, // 1692 { PseudoVLUXEI8_V_M1_M2_MASK, PseudoVLUXEI8_V_M1_M2, 0x3 }, // 1693 { PseudoVLUXEI8_V_M1_M4_MASK, PseudoVLUXEI8_V_M1_M4, 0x3 }, // 1694 { PseudoVLUXEI8_V_M1_M8_MASK, PseudoVLUXEI8_V_M1_M8, 0x3 }, // 1695 { PseudoVLUXEI8_V_M2_M2_MASK, PseudoVLUXEI8_V_M2_M2, 0x3 }, // 1696 { PseudoVLUXEI8_V_M2_M4_MASK, PseudoVLUXEI8_V_M2_M4, 0x3 }, // 1697 { PseudoVLUXEI8_V_M2_M8_MASK, PseudoVLUXEI8_V_M2_M8, 0x3 }, // 1698 { PseudoVLUXEI8_V_M4_M4_MASK, PseudoVLUXEI8_V_M4_M4, 0x3 }, // 1699 { PseudoVLUXEI8_V_M4_M8_MASK, PseudoVLUXEI8_V_M4_M8, 0x3 }, // 1700 { PseudoVLUXEI8_V_M8_M8_MASK, PseudoVLUXEI8_V_M8_M8, 0x3 }, // 1701 { PseudoVLUXEI8_V_MF2_M1_MASK, PseudoVLUXEI8_V_MF2_M1, 0x3 }, // 1702 { PseudoVLUXEI8_V_MF2_M2_MASK, PseudoVLUXEI8_V_MF2_M2, 0x3 }, // 1703 { PseudoVLUXEI8_V_MF2_M4_MASK, PseudoVLUXEI8_V_MF2_M4, 0x3 }, // 1704 { PseudoVLUXEI8_V_MF2_MF2_MASK, PseudoVLUXEI8_V_MF2_MF2, 0x3 }, // 1705 { PseudoVLUXEI8_V_MF4_M1_MASK, PseudoVLUXEI8_V_MF4_M1, 0x3 }, // 1706 { PseudoVLUXEI8_V_MF4_M2_MASK, PseudoVLUXEI8_V_MF4_M2, 0x3 }, // 1707 { PseudoVLUXEI8_V_MF4_MF2_MASK, PseudoVLUXEI8_V_MF4_MF2, 0x3 }, // 1708 { PseudoVLUXEI8_V_MF4_MF4_MASK, PseudoVLUXEI8_V_MF4_MF4, 0x3 }, // 1709 { PseudoVLUXEI8_V_MF8_M1_MASK, PseudoVLUXEI8_V_MF8_M1, 0x3 }, // 1710 { PseudoVLUXEI8_V_MF8_MF2_MASK, PseudoVLUXEI8_V_MF8_MF2, 0x3 }, // 1711 { PseudoVLUXEI8_V_MF8_MF4_MASK, PseudoVLUXEI8_V_MF8_MF4, 0x3 }, // 1712 { PseudoVLUXEI8_V_MF8_MF8_MASK, PseudoVLUXEI8_V_MF8_MF8, 0x3 }, // 1713 { PseudoVMACC_VV_M1_MASK, PseudoVMACC_VV_M1, 0x3 }, // 1714 { PseudoVMACC_VV_M2_MASK, PseudoVMACC_VV_M2, 0x3 }, // 1715 { PseudoVMACC_VV_M4_MASK, PseudoVMACC_VV_M4, 0x3 }, // 1716 { PseudoVMACC_VV_M8_MASK, PseudoVMACC_VV_M8, 0x3 }, // 1717 { PseudoVMACC_VV_MF2_MASK, PseudoVMACC_VV_MF2, 0x3 }, // 1718 { PseudoVMACC_VV_MF4_MASK, PseudoVMACC_VV_MF4, 0x3 }, // 1719 { PseudoVMACC_VV_MF8_MASK, PseudoVMACC_VV_MF8, 0x3 }, // 1720 { PseudoVMACC_VX_M1_MASK, PseudoVMACC_VX_M1, 0x3 }, // 1721 { PseudoVMACC_VX_M2_MASK, PseudoVMACC_VX_M2, 0x3 }, // 1722 { PseudoVMACC_VX_M4_MASK, PseudoVMACC_VX_M4, 0x3 }, // 1723 { PseudoVMACC_VX_M8_MASK, PseudoVMACC_VX_M8, 0x3 }, // 1724 { PseudoVMACC_VX_MF2_MASK, PseudoVMACC_VX_MF2, 0x3 }, // 1725 { PseudoVMACC_VX_MF4_MASK, PseudoVMACC_VX_MF4, 0x3 }, // 1726 { PseudoVMACC_VX_MF8_MASK, PseudoVMACC_VX_MF8, 0x3 }, // 1727 { PseudoVMADD_VV_M1_MASK, PseudoVMADD_VV_M1, 0x3 }, // 1728 { PseudoVMADD_VV_M2_MASK, PseudoVMADD_VV_M2, 0x3 }, // 1729 { PseudoVMADD_VV_M4_MASK, PseudoVMADD_VV_M4, 0x3 }, // 1730 { PseudoVMADD_VV_M8_MASK, PseudoVMADD_VV_M8, 0x3 }, // 1731 { PseudoVMADD_VV_MF2_MASK, PseudoVMADD_VV_MF2, 0x3 }, // 1732 { PseudoVMADD_VV_MF4_MASK, PseudoVMADD_VV_MF4, 0x3 }, // 1733 { PseudoVMADD_VV_MF8_MASK, PseudoVMADD_VV_MF8, 0x3 }, // 1734 { PseudoVMADD_VX_M1_MASK, PseudoVMADD_VX_M1, 0x3 }, // 1735 { PseudoVMADD_VX_M2_MASK, PseudoVMADD_VX_M2, 0x3 }, // 1736 { PseudoVMADD_VX_M4_MASK, PseudoVMADD_VX_M4, 0x3 }, // 1737 { PseudoVMADD_VX_M8_MASK, PseudoVMADD_VX_M8, 0x3 }, // 1738 { PseudoVMADD_VX_MF2_MASK, PseudoVMADD_VX_MF2, 0x3 }, // 1739 { PseudoVMADD_VX_MF4_MASK, PseudoVMADD_VX_MF4, 0x3 }, // 1740 { PseudoVMADD_VX_MF8_MASK, PseudoVMADD_VX_MF8, 0x3 }, // 1741 { PseudoVMAXU_VV_M1_MASK, PseudoVMAXU_VV_M1, 0x3 }, // 1742 { PseudoVMAXU_VV_M2_MASK, PseudoVMAXU_VV_M2, 0x3 }, // 1743 { PseudoVMAXU_VV_M4_MASK, PseudoVMAXU_VV_M4, 0x3 }, // 1744 { PseudoVMAXU_VV_M8_MASK, PseudoVMAXU_VV_M8, 0x3 }, // 1745 { PseudoVMAXU_VV_MF2_MASK, PseudoVMAXU_VV_MF2, 0x3 }, // 1746 { PseudoVMAXU_VV_MF4_MASK, PseudoVMAXU_VV_MF4, 0x3 }, // 1747 { PseudoVMAXU_VV_MF8_MASK, PseudoVMAXU_VV_MF8, 0x3 }, // 1748 { PseudoVMAXU_VX_M1_MASK, PseudoVMAXU_VX_M1, 0x3 }, // 1749 { PseudoVMAXU_VX_M2_MASK, PseudoVMAXU_VX_M2, 0x3 }, // 1750 { PseudoVMAXU_VX_M4_MASK, PseudoVMAXU_VX_M4, 0x3 }, // 1751 { PseudoVMAXU_VX_M8_MASK, PseudoVMAXU_VX_M8, 0x3 }, // 1752 { PseudoVMAXU_VX_MF2_MASK, PseudoVMAXU_VX_MF2, 0x3 }, // 1753 { PseudoVMAXU_VX_MF4_MASK, PseudoVMAXU_VX_MF4, 0x3 }, // 1754 { PseudoVMAXU_VX_MF8_MASK, PseudoVMAXU_VX_MF8, 0x3 }, // 1755 { PseudoVMAX_VV_M1_MASK, PseudoVMAX_VV_M1, 0x3 }, // 1756 { PseudoVMAX_VV_M2_MASK, PseudoVMAX_VV_M2, 0x3 }, // 1757 { PseudoVMAX_VV_M4_MASK, PseudoVMAX_VV_M4, 0x3 }, // 1758 { PseudoVMAX_VV_M8_MASK, PseudoVMAX_VV_M8, 0x3 }, // 1759 { PseudoVMAX_VV_MF2_MASK, PseudoVMAX_VV_MF2, 0x3 }, // 1760 { PseudoVMAX_VV_MF4_MASK, PseudoVMAX_VV_MF4, 0x3 }, // 1761 { PseudoVMAX_VV_MF8_MASK, PseudoVMAX_VV_MF8, 0x3 }, // 1762 { PseudoVMAX_VX_M1_MASK, PseudoVMAX_VX_M1, 0x3 }, // 1763 { PseudoVMAX_VX_M2_MASK, PseudoVMAX_VX_M2, 0x3 }, // 1764 { PseudoVMAX_VX_M4_MASK, PseudoVMAX_VX_M4, 0x3 }, // 1765 { PseudoVMAX_VX_M8_MASK, PseudoVMAX_VX_M8, 0x3 }, // 1766 { PseudoVMAX_VX_MF2_MASK, PseudoVMAX_VX_MF2, 0x3 }, // 1767 { PseudoVMAX_VX_MF4_MASK, PseudoVMAX_VX_MF4, 0x3 }, // 1768 { PseudoVMAX_VX_MF8_MASK, PseudoVMAX_VX_MF8, 0x3 }, // 1769 { PseudoVMFEQ_VFPR16_M1_MASK, PseudoVMFEQ_VFPR16_M1, 0x3 }, // 1770 { PseudoVMFEQ_VFPR16_M2_MASK, PseudoVMFEQ_VFPR16_M2, 0x3 }, // 1771 { PseudoVMFEQ_VFPR16_M4_MASK, PseudoVMFEQ_VFPR16_M4, 0x3 }, // 1772 { PseudoVMFEQ_VFPR16_M8_MASK, PseudoVMFEQ_VFPR16_M8, 0x3 }, // 1773 { PseudoVMFEQ_VFPR16_MF2_MASK, PseudoVMFEQ_VFPR16_MF2, 0x3 }, // 1774 { PseudoVMFEQ_VFPR16_MF4_MASK, PseudoVMFEQ_VFPR16_MF4, 0x3 }, // 1775 { PseudoVMFEQ_VFPR32_M1_MASK, PseudoVMFEQ_VFPR32_M1, 0x3 }, // 1776 { PseudoVMFEQ_VFPR32_M2_MASK, PseudoVMFEQ_VFPR32_M2, 0x3 }, // 1777 { PseudoVMFEQ_VFPR32_M4_MASK, PseudoVMFEQ_VFPR32_M4, 0x3 }, // 1778 { PseudoVMFEQ_VFPR32_M8_MASK, PseudoVMFEQ_VFPR32_M8, 0x3 }, // 1779 { PseudoVMFEQ_VFPR32_MF2_MASK, PseudoVMFEQ_VFPR32_MF2, 0x3 }, // 1780 { PseudoVMFEQ_VFPR64_M1_MASK, PseudoVMFEQ_VFPR64_M1, 0x3 }, // 1781 { PseudoVMFEQ_VFPR64_M2_MASK, PseudoVMFEQ_VFPR64_M2, 0x3 }, // 1782 { PseudoVMFEQ_VFPR64_M4_MASK, PseudoVMFEQ_VFPR64_M4, 0x3 }, // 1783 { PseudoVMFEQ_VFPR64_M8_MASK, PseudoVMFEQ_VFPR64_M8, 0x3 }, // 1784 { PseudoVMFEQ_VV_M1_MASK, PseudoVMFEQ_VV_M1, 0x3 }, // 1785 { PseudoVMFEQ_VV_M2_MASK, PseudoVMFEQ_VV_M2, 0x3 }, // 1786 { PseudoVMFEQ_VV_M4_MASK, PseudoVMFEQ_VV_M4, 0x3 }, // 1787 { PseudoVMFEQ_VV_M8_MASK, PseudoVMFEQ_VV_M8, 0x3 }, // 1788 { PseudoVMFEQ_VV_MF2_MASK, PseudoVMFEQ_VV_MF2, 0x3 }, // 1789 { PseudoVMFEQ_VV_MF4_MASK, PseudoVMFEQ_VV_MF4, 0x3 }, // 1790 { PseudoVMFGE_VFPR16_M1_MASK, PseudoVMFGE_VFPR16_M1, 0x3 }, // 1791 { PseudoVMFGE_VFPR16_M2_MASK, PseudoVMFGE_VFPR16_M2, 0x3 }, // 1792 { PseudoVMFGE_VFPR16_M4_MASK, PseudoVMFGE_VFPR16_M4, 0x3 }, // 1793 { PseudoVMFGE_VFPR16_M8_MASK, PseudoVMFGE_VFPR16_M8, 0x3 }, // 1794 { PseudoVMFGE_VFPR16_MF2_MASK, PseudoVMFGE_VFPR16_MF2, 0x3 }, // 1795 { PseudoVMFGE_VFPR16_MF4_MASK, PseudoVMFGE_VFPR16_MF4, 0x3 }, // 1796 { PseudoVMFGE_VFPR32_M1_MASK, PseudoVMFGE_VFPR32_M1, 0x3 }, // 1797 { PseudoVMFGE_VFPR32_M2_MASK, PseudoVMFGE_VFPR32_M2, 0x3 }, // 1798 { PseudoVMFGE_VFPR32_M4_MASK, PseudoVMFGE_VFPR32_M4, 0x3 }, // 1799 { PseudoVMFGE_VFPR32_M8_MASK, PseudoVMFGE_VFPR32_M8, 0x3 }, // 1800 { PseudoVMFGE_VFPR32_MF2_MASK, PseudoVMFGE_VFPR32_MF2, 0x3 }, // 1801 { PseudoVMFGE_VFPR64_M1_MASK, PseudoVMFGE_VFPR64_M1, 0x3 }, // 1802 { PseudoVMFGE_VFPR64_M2_MASK, PseudoVMFGE_VFPR64_M2, 0x3 }, // 1803 { PseudoVMFGE_VFPR64_M4_MASK, PseudoVMFGE_VFPR64_M4, 0x3 }, // 1804 { PseudoVMFGE_VFPR64_M8_MASK, PseudoVMFGE_VFPR64_M8, 0x3 }, // 1805 { PseudoVMFGT_VFPR16_M1_MASK, PseudoVMFGT_VFPR16_M1, 0x3 }, // 1806 { PseudoVMFGT_VFPR16_M2_MASK, PseudoVMFGT_VFPR16_M2, 0x3 }, // 1807 { PseudoVMFGT_VFPR16_M4_MASK, PseudoVMFGT_VFPR16_M4, 0x3 }, // 1808 { PseudoVMFGT_VFPR16_M8_MASK, PseudoVMFGT_VFPR16_M8, 0x3 }, // 1809 { PseudoVMFGT_VFPR16_MF2_MASK, PseudoVMFGT_VFPR16_MF2, 0x3 }, // 1810 { PseudoVMFGT_VFPR16_MF4_MASK, PseudoVMFGT_VFPR16_MF4, 0x3 }, // 1811 { PseudoVMFGT_VFPR32_M1_MASK, PseudoVMFGT_VFPR32_M1, 0x3 }, // 1812 { PseudoVMFGT_VFPR32_M2_MASK, PseudoVMFGT_VFPR32_M2, 0x3 }, // 1813 { PseudoVMFGT_VFPR32_M4_MASK, PseudoVMFGT_VFPR32_M4, 0x3 }, // 1814 { PseudoVMFGT_VFPR32_M8_MASK, PseudoVMFGT_VFPR32_M8, 0x3 }, // 1815 { PseudoVMFGT_VFPR32_MF2_MASK, PseudoVMFGT_VFPR32_MF2, 0x3 }, // 1816 { PseudoVMFGT_VFPR64_M1_MASK, PseudoVMFGT_VFPR64_M1, 0x3 }, // 1817 { PseudoVMFGT_VFPR64_M2_MASK, PseudoVMFGT_VFPR64_M2, 0x3 }, // 1818 { PseudoVMFGT_VFPR64_M4_MASK, PseudoVMFGT_VFPR64_M4, 0x3 }, // 1819 { PseudoVMFGT_VFPR64_M8_MASK, PseudoVMFGT_VFPR64_M8, 0x3 }, // 1820 { PseudoVMFLE_VFPR16_M1_MASK, PseudoVMFLE_VFPR16_M1, 0x3 }, // 1821 { PseudoVMFLE_VFPR16_M2_MASK, PseudoVMFLE_VFPR16_M2, 0x3 }, // 1822 { PseudoVMFLE_VFPR16_M4_MASK, PseudoVMFLE_VFPR16_M4, 0x3 }, // 1823 { PseudoVMFLE_VFPR16_M8_MASK, PseudoVMFLE_VFPR16_M8, 0x3 }, // 1824 { PseudoVMFLE_VFPR16_MF2_MASK, PseudoVMFLE_VFPR16_MF2, 0x3 }, // 1825 { PseudoVMFLE_VFPR16_MF4_MASK, PseudoVMFLE_VFPR16_MF4, 0x3 }, // 1826 { PseudoVMFLE_VFPR32_M1_MASK, PseudoVMFLE_VFPR32_M1, 0x3 }, // 1827 { PseudoVMFLE_VFPR32_M2_MASK, PseudoVMFLE_VFPR32_M2, 0x3 }, // 1828 { PseudoVMFLE_VFPR32_M4_MASK, PseudoVMFLE_VFPR32_M4, 0x3 }, // 1829 { PseudoVMFLE_VFPR32_M8_MASK, PseudoVMFLE_VFPR32_M8, 0x3 }, // 1830 { PseudoVMFLE_VFPR32_MF2_MASK, PseudoVMFLE_VFPR32_MF2, 0x3 }, // 1831 { PseudoVMFLE_VFPR64_M1_MASK, PseudoVMFLE_VFPR64_M1, 0x3 }, // 1832 { PseudoVMFLE_VFPR64_M2_MASK, PseudoVMFLE_VFPR64_M2, 0x3 }, // 1833 { PseudoVMFLE_VFPR64_M4_MASK, PseudoVMFLE_VFPR64_M4, 0x3 }, // 1834 { PseudoVMFLE_VFPR64_M8_MASK, PseudoVMFLE_VFPR64_M8, 0x3 }, // 1835 { PseudoVMFLE_VV_M1_MASK, PseudoVMFLE_VV_M1, 0x3 }, // 1836 { PseudoVMFLE_VV_M2_MASK, PseudoVMFLE_VV_M2, 0x3 }, // 1837 { PseudoVMFLE_VV_M4_MASK, PseudoVMFLE_VV_M4, 0x3 }, // 1838 { PseudoVMFLE_VV_M8_MASK, PseudoVMFLE_VV_M8, 0x3 }, // 1839 { PseudoVMFLE_VV_MF2_MASK, PseudoVMFLE_VV_MF2, 0x3 }, // 1840 { PseudoVMFLE_VV_MF4_MASK, PseudoVMFLE_VV_MF4, 0x3 }, // 1841 { PseudoVMFLT_VFPR16_M1_MASK, PseudoVMFLT_VFPR16_M1, 0x3 }, // 1842 { PseudoVMFLT_VFPR16_M2_MASK, PseudoVMFLT_VFPR16_M2, 0x3 }, // 1843 { PseudoVMFLT_VFPR16_M4_MASK, PseudoVMFLT_VFPR16_M4, 0x3 }, // 1844 { PseudoVMFLT_VFPR16_M8_MASK, PseudoVMFLT_VFPR16_M8, 0x3 }, // 1845 { PseudoVMFLT_VFPR16_MF2_MASK, PseudoVMFLT_VFPR16_MF2, 0x3 }, // 1846 { PseudoVMFLT_VFPR16_MF4_MASK, PseudoVMFLT_VFPR16_MF4, 0x3 }, // 1847 { PseudoVMFLT_VFPR32_M1_MASK, PseudoVMFLT_VFPR32_M1, 0x3 }, // 1848 { PseudoVMFLT_VFPR32_M2_MASK, PseudoVMFLT_VFPR32_M2, 0x3 }, // 1849 { PseudoVMFLT_VFPR32_M4_MASK, PseudoVMFLT_VFPR32_M4, 0x3 }, // 1850 { PseudoVMFLT_VFPR32_M8_MASK, PseudoVMFLT_VFPR32_M8, 0x3 }, // 1851 { PseudoVMFLT_VFPR32_MF2_MASK, PseudoVMFLT_VFPR32_MF2, 0x3 }, // 1852 { PseudoVMFLT_VFPR64_M1_MASK, PseudoVMFLT_VFPR64_M1, 0x3 }, // 1853 { PseudoVMFLT_VFPR64_M2_MASK, PseudoVMFLT_VFPR64_M2, 0x3 }, // 1854 { PseudoVMFLT_VFPR64_M4_MASK, PseudoVMFLT_VFPR64_M4, 0x3 }, // 1855 { PseudoVMFLT_VFPR64_M8_MASK, PseudoVMFLT_VFPR64_M8, 0x3 }, // 1856 { PseudoVMFLT_VV_M1_MASK, PseudoVMFLT_VV_M1, 0x3 }, // 1857 { PseudoVMFLT_VV_M2_MASK, PseudoVMFLT_VV_M2, 0x3 }, // 1858 { PseudoVMFLT_VV_M4_MASK, PseudoVMFLT_VV_M4, 0x3 }, // 1859 { PseudoVMFLT_VV_M8_MASK, PseudoVMFLT_VV_M8, 0x3 }, // 1860 { PseudoVMFLT_VV_MF2_MASK, PseudoVMFLT_VV_MF2, 0x3 }, // 1861 { PseudoVMFLT_VV_MF4_MASK, PseudoVMFLT_VV_MF4, 0x3 }, // 1862 { PseudoVMFNE_VFPR16_M1_MASK, PseudoVMFNE_VFPR16_M1, 0x3 }, // 1863 { PseudoVMFNE_VFPR16_M2_MASK, PseudoVMFNE_VFPR16_M2, 0x3 }, // 1864 { PseudoVMFNE_VFPR16_M4_MASK, PseudoVMFNE_VFPR16_M4, 0x3 }, // 1865 { PseudoVMFNE_VFPR16_M8_MASK, PseudoVMFNE_VFPR16_M8, 0x3 }, // 1866 { PseudoVMFNE_VFPR16_MF2_MASK, PseudoVMFNE_VFPR16_MF2, 0x3 }, // 1867 { PseudoVMFNE_VFPR16_MF4_MASK, PseudoVMFNE_VFPR16_MF4, 0x3 }, // 1868 { PseudoVMFNE_VFPR32_M1_MASK, PseudoVMFNE_VFPR32_M1, 0x3 }, // 1869 { PseudoVMFNE_VFPR32_M2_MASK, PseudoVMFNE_VFPR32_M2, 0x3 }, // 1870 { PseudoVMFNE_VFPR32_M4_MASK, PseudoVMFNE_VFPR32_M4, 0x3 }, // 1871 { PseudoVMFNE_VFPR32_M8_MASK, PseudoVMFNE_VFPR32_M8, 0x3 }, // 1872 { PseudoVMFNE_VFPR32_MF2_MASK, PseudoVMFNE_VFPR32_MF2, 0x3 }, // 1873 { PseudoVMFNE_VFPR64_M1_MASK, PseudoVMFNE_VFPR64_M1, 0x3 }, // 1874 { PseudoVMFNE_VFPR64_M2_MASK, PseudoVMFNE_VFPR64_M2, 0x3 }, // 1875 { PseudoVMFNE_VFPR64_M4_MASK, PseudoVMFNE_VFPR64_M4, 0x3 }, // 1876 { PseudoVMFNE_VFPR64_M8_MASK, PseudoVMFNE_VFPR64_M8, 0x3 }, // 1877 { PseudoVMFNE_VV_M1_MASK, PseudoVMFNE_VV_M1, 0x3 }, // 1878 { PseudoVMFNE_VV_M2_MASK, PseudoVMFNE_VV_M2, 0x3 }, // 1879 { PseudoVMFNE_VV_M4_MASK, PseudoVMFNE_VV_M4, 0x3 }, // 1880 { PseudoVMFNE_VV_M8_MASK, PseudoVMFNE_VV_M8, 0x3 }, // 1881 { PseudoVMFNE_VV_MF2_MASK, PseudoVMFNE_VV_MF2, 0x3 }, // 1882 { PseudoVMFNE_VV_MF4_MASK, PseudoVMFNE_VV_MF4, 0x3 }, // 1883 { PseudoVMINU_VV_M1_MASK, PseudoVMINU_VV_M1, 0x3 }, // 1884 { PseudoVMINU_VV_M2_MASK, PseudoVMINU_VV_M2, 0x3 }, // 1885 { PseudoVMINU_VV_M4_MASK, PseudoVMINU_VV_M4, 0x3 }, // 1886 { PseudoVMINU_VV_M8_MASK, PseudoVMINU_VV_M8, 0x3 }, // 1887 { PseudoVMINU_VV_MF2_MASK, PseudoVMINU_VV_MF2, 0x3 }, // 1888 { PseudoVMINU_VV_MF4_MASK, PseudoVMINU_VV_MF4, 0x3 }, // 1889 { PseudoVMINU_VV_MF8_MASK, PseudoVMINU_VV_MF8, 0x3 }, // 1890 { PseudoVMINU_VX_M1_MASK, PseudoVMINU_VX_M1, 0x3 }, // 1891 { PseudoVMINU_VX_M2_MASK, PseudoVMINU_VX_M2, 0x3 }, // 1892 { PseudoVMINU_VX_M4_MASK, PseudoVMINU_VX_M4, 0x3 }, // 1893 { PseudoVMINU_VX_M8_MASK, PseudoVMINU_VX_M8, 0x3 }, // 1894 { PseudoVMINU_VX_MF2_MASK, PseudoVMINU_VX_MF2, 0x3 }, // 1895 { PseudoVMINU_VX_MF4_MASK, PseudoVMINU_VX_MF4, 0x3 }, // 1896 { PseudoVMINU_VX_MF8_MASK, PseudoVMINU_VX_MF8, 0x3 }, // 1897 { PseudoVMIN_VV_M1_MASK, PseudoVMIN_VV_M1, 0x3 }, // 1898 { PseudoVMIN_VV_M2_MASK, PseudoVMIN_VV_M2, 0x3 }, // 1899 { PseudoVMIN_VV_M4_MASK, PseudoVMIN_VV_M4, 0x3 }, // 1900 { PseudoVMIN_VV_M8_MASK, PseudoVMIN_VV_M8, 0x3 }, // 1901 { PseudoVMIN_VV_MF2_MASK, PseudoVMIN_VV_MF2, 0x3 }, // 1902 { PseudoVMIN_VV_MF4_MASK, PseudoVMIN_VV_MF4, 0x3 }, // 1903 { PseudoVMIN_VV_MF8_MASK, PseudoVMIN_VV_MF8, 0x3 }, // 1904 { PseudoVMIN_VX_M1_MASK, PseudoVMIN_VX_M1, 0x3 }, // 1905 { PseudoVMIN_VX_M2_MASK, PseudoVMIN_VX_M2, 0x3 }, // 1906 { PseudoVMIN_VX_M4_MASK, PseudoVMIN_VX_M4, 0x3 }, // 1907 { PseudoVMIN_VX_M8_MASK, PseudoVMIN_VX_M8, 0x3 }, // 1908 { PseudoVMIN_VX_MF2_MASK, PseudoVMIN_VX_MF2, 0x3 }, // 1909 { PseudoVMIN_VX_MF4_MASK, PseudoVMIN_VX_MF4, 0x3 }, // 1910 { PseudoVMIN_VX_MF8_MASK, PseudoVMIN_VX_MF8, 0x3 }, // 1911 { PseudoVMSEQ_VI_M1_MASK, PseudoVMSEQ_VI_M1, 0x3 }, // 1912 { PseudoVMSEQ_VI_M2_MASK, PseudoVMSEQ_VI_M2, 0x3 }, // 1913 { PseudoVMSEQ_VI_M4_MASK, PseudoVMSEQ_VI_M4, 0x3 }, // 1914 { PseudoVMSEQ_VI_M8_MASK, PseudoVMSEQ_VI_M8, 0x3 }, // 1915 { PseudoVMSEQ_VI_MF2_MASK, PseudoVMSEQ_VI_MF2, 0x3 }, // 1916 { PseudoVMSEQ_VI_MF4_MASK, PseudoVMSEQ_VI_MF4, 0x3 }, // 1917 { PseudoVMSEQ_VI_MF8_MASK, PseudoVMSEQ_VI_MF8, 0x3 }, // 1918 { PseudoVMSEQ_VV_M1_MASK, PseudoVMSEQ_VV_M1, 0x3 }, // 1919 { PseudoVMSEQ_VV_M2_MASK, PseudoVMSEQ_VV_M2, 0x3 }, // 1920 { PseudoVMSEQ_VV_M4_MASK, PseudoVMSEQ_VV_M4, 0x3 }, // 1921 { PseudoVMSEQ_VV_M8_MASK, PseudoVMSEQ_VV_M8, 0x3 }, // 1922 { PseudoVMSEQ_VV_MF2_MASK, PseudoVMSEQ_VV_MF2, 0x3 }, // 1923 { PseudoVMSEQ_VV_MF4_MASK, PseudoVMSEQ_VV_MF4, 0x3 }, // 1924 { PseudoVMSEQ_VV_MF8_MASK, PseudoVMSEQ_VV_MF8, 0x3 }, // 1925 { PseudoVMSEQ_VX_M1_MASK, PseudoVMSEQ_VX_M1, 0x3 }, // 1926 { PseudoVMSEQ_VX_M2_MASK, PseudoVMSEQ_VX_M2, 0x3 }, // 1927 { PseudoVMSEQ_VX_M4_MASK, PseudoVMSEQ_VX_M4, 0x3 }, // 1928 { PseudoVMSEQ_VX_M8_MASK, PseudoVMSEQ_VX_M8, 0x3 }, // 1929 { PseudoVMSEQ_VX_MF2_MASK, PseudoVMSEQ_VX_MF2, 0x3 }, // 1930 { PseudoVMSEQ_VX_MF4_MASK, PseudoVMSEQ_VX_MF4, 0x3 }, // 1931 { PseudoVMSEQ_VX_MF8_MASK, PseudoVMSEQ_VX_MF8, 0x3 }, // 1932 { PseudoVMSGTU_VI_M1_MASK, PseudoVMSGTU_VI_M1, 0x3 }, // 1933 { PseudoVMSGTU_VI_M2_MASK, PseudoVMSGTU_VI_M2, 0x3 }, // 1934 { PseudoVMSGTU_VI_M4_MASK, PseudoVMSGTU_VI_M4, 0x3 }, // 1935 { PseudoVMSGTU_VI_M8_MASK, PseudoVMSGTU_VI_M8, 0x3 }, // 1936 { PseudoVMSGTU_VI_MF2_MASK, PseudoVMSGTU_VI_MF2, 0x3 }, // 1937 { PseudoVMSGTU_VI_MF4_MASK, PseudoVMSGTU_VI_MF4, 0x3 }, // 1938 { PseudoVMSGTU_VI_MF8_MASK, PseudoVMSGTU_VI_MF8, 0x3 }, // 1939 { PseudoVMSGTU_VX_M1_MASK, PseudoVMSGTU_VX_M1, 0x3 }, // 1940 { PseudoVMSGTU_VX_M2_MASK, PseudoVMSGTU_VX_M2, 0x3 }, // 1941 { PseudoVMSGTU_VX_M4_MASK, PseudoVMSGTU_VX_M4, 0x3 }, // 1942 { PseudoVMSGTU_VX_M8_MASK, PseudoVMSGTU_VX_M8, 0x3 }, // 1943 { PseudoVMSGTU_VX_MF2_MASK, PseudoVMSGTU_VX_MF2, 0x3 }, // 1944 { PseudoVMSGTU_VX_MF4_MASK, PseudoVMSGTU_VX_MF4, 0x3 }, // 1945 { PseudoVMSGTU_VX_MF8_MASK, PseudoVMSGTU_VX_MF8, 0x3 }, // 1946 { PseudoVMSGT_VI_M1_MASK, PseudoVMSGT_VI_M1, 0x3 }, // 1947 { PseudoVMSGT_VI_M2_MASK, PseudoVMSGT_VI_M2, 0x3 }, // 1948 { PseudoVMSGT_VI_M4_MASK, PseudoVMSGT_VI_M4, 0x3 }, // 1949 { PseudoVMSGT_VI_M8_MASK, PseudoVMSGT_VI_M8, 0x3 }, // 1950 { PseudoVMSGT_VI_MF2_MASK, PseudoVMSGT_VI_MF2, 0x3 }, // 1951 { PseudoVMSGT_VI_MF4_MASK, PseudoVMSGT_VI_MF4, 0x3 }, // 1952 { PseudoVMSGT_VI_MF8_MASK, PseudoVMSGT_VI_MF8, 0x3 }, // 1953 { PseudoVMSGT_VX_M1_MASK, PseudoVMSGT_VX_M1, 0x3 }, // 1954 { PseudoVMSGT_VX_M2_MASK, PseudoVMSGT_VX_M2, 0x3 }, // 1955 { PseudoVMSGT_VX_M4_MASK, PseudoVMSGT_VX_M4, 0x3 }, // 1956 { PseudoVMSGT_VX_M8_MASK, PseudoVMSGT_VX_M8, 0x3 }, // 1957 { PseudoVMSGT_VX_MF2_MASK, PseudoVMSGT_VX_MF2, 0x3 }, // 1958 { PseudoVMSGT_VX_MF4_MASK, PseudoVMSGT_VX_MF4, 0x3 }, // 1959 { PseudoVMSGT_VX_MF8_MASK, PseudoVMSGT_VX_MF8, 0x3 }, // 1960 { PseudoVMSLEU_VI_M1_MASK, PseudoVMSLEU_VI_M1, 0x3 }, // 1961 { PseudoVMSLEU_VI_M2_MASK, PseudoVMSLEU_VI_M2, 0x3 }, // 1962 { PseudoVMSLEU_VI_M4_MASK, PseudoVMSLEU_VI_M4, 0x3 }, // 1963 { PseudoVMSLEU_VI_M8_MASK, PseudoVMSLEU_VI_M8, 0x3 }, // 1964 { PseudoVMSLEU_VI_MF2_MASK, PseudoVMSLEU_VI_MF2, 0x3 }, // 1965 { PseudoVMSLEU_VI_MF4_MASK, PseudoVMSLEU_VI_MF4, 0x3 }, // 1966 { PseudoVMSLEU_VI_MF8_MASK, PseudoVMSLEU_VI_MF8, 0x3 }, // 1967 { PseudoVMSLEU_VV_M1_MASK, PseudoVMSLEU_VV_M1, 0x3 }, // 1968 { PseudoVMSLEU_VV_M2_MASK, PseudoVMSLEU_VV_M2, 0x3 }, // 1969 { PseudoVMSLEU_VV_M4_MASK, PseudoVMSLEU_VV_M4, 0x3 }, // 1970 { PseudoVMSLEU_VV_M8_MASK, PseudoVMSLEU_VV_M8, 0x3 }, // 1971 { PseudoVMSLEU_VV_MF2_MASK, PseudoVMSLEU_VV_MF2, 0x3 }, // 1972 { PseudoVMSLEU_VV_MF4_MASK, PseudoVMSLEU_VV_MF4, 0x3 }, // 1973 { PseudoVMSLEU_VV_MF8_MASK, PseudoVMSLEU_VV_MF8, 0x3 }, // 1974 { PseudoVMSLEU_VX_M1_MASK, PseudoVMSLEU_VX_M1, 0x3 }, // 1975 { PseudoVMSLEU_VX_M2_MASK, PseudoVMSLEU_VX_M2, 0x3 }, // 1976 { PseudoVMSLEU_VX_M4_MASK, PseudoVMSLEU_VX_M4, 0x3 }, // 1977 { PseudoVMSLEU_VX_M8_MASK, PseudoVMSLEU_VX_M8, 0x3 }, // 1978 { PseudoVMSLEU_VX_MF2_MASK, PseudoVMSLEU_VX_MF2, 0x3 }, // 1979 { PseudoVMSLEU_VX_MF4_MASK, PseudoVMSLEU_VX_MF4, 0x3 }, // 1980 { PseudoVMSLEU_VX_MF8_MASK, PseudoVMSLEU_VX_MF8, 0x3 }, // 1981 { PseudoVMSLE_VI_M1_MASK, PseudoVMSLE_VI_M1, 0x3 }, // 1982 { PseudoVMSLE_VI_M2_MASK, PseudoVMSLE_VI_M2, 0x3 }, // 1983 { PseudoVMSLE_VI_M4_MASK, PseudoVMSLE_VI_M4, 0x3 }, // 1984 { PseudoVMSLE_VI_M8_MASK, PseudoVMSLE_VI_M8, 0x3 }, // 1985 { PseudoVMSLE_VI_MF2_MASK, PseudoVMSLE_VI_MF2, 0x3 }, // 1986 { PseudoVMSLE_VI_MF4_MASK, PseudoVMSLE_VI_MF4, 0x3 }, // 1987 { PseudoVMSLE_VI_MF8_MASK, PseudoVMSLE_VI_MF8, 0x3 }, // 1988 { PseudoVMSLE_VV_M1_MASK, PseudoVMSLE_VV_M1, 0x3 }, // 1989 { PseudoVMSLE_VV_M2_MASK, PseudoVMSLE_VV_M2, 0x3 }, // 1990 { PseudoVMSLE_VV_M4_MASK, PseudoVMSLE_VV_M4, 0x3 }, // 1991 { PseudoVMSLE_VV_M8_MASK, PseudoVMSLE_VV_M8, 0x3 }, // 1992 { PseudoVMSLE_VV_MF2_MASK, PseudoVMSLE_VV_MF2, 0x3 }, // 1993 { PseudoVMSLE_VV_MF4_MASK, PseudoVMSLE_VV_MF4, 0x3 }, // 1994 { PseudoVMSLE_VV_MF8_MASK, PseudoVMSLE_VV_MF8, 0x3 }, // 1995 { PseudoVMSLE_VX_M1_MASK, PseudoVMSLE_VX_M1, 0x3 }, // 1996 { PseudoVMSLE_VX_M2_MASK, PseudoVMSLE_VX_M2, 0x3 }, // 1997 { PseudoVMSLE_VX_M4_MASK, PseudoVMSLE_VX_M4, 0x3 }, // 1998 { PseudoVMSLE_VX_M8_MASK, PseudoVMSLE_VX_M8, 0x3 }, // 1999 { PseudoVMSLE_VX_MF2_MASK, PseudoVMSLE_VX_MF2, 0x3 }, // 2000 { PseudoVMSLE_VX_MF4_MASK, PseudoVMSLE_VX_MF4, 0x3 }, // 2001 { PseudoVMSLE_VX_MF8_MASK, PseudoVMSLE_VX_MF8, 0x3 }, // 2002 { PseudoVMSLTU_VV_M1_MASK, PseudoVMSLTU_VV_M1, 0x3 }, // 2003 { PseudoVMSLTU_VV_M2_MASK, PseudoVMSLTU_VV_M2, 0x3 }, // 2004 { PseudoVMSLTU_VV_M4_MASK, PseudoVMSLTU_VV_M4, 0x3 }, // 2005 { PseudoVMSLTU_VV_M8_MASK, PseudoVMSLTU_VV_M8, 0x3 }, // 2006 { PseudoVMSLTU_VV_MF2_MASK, PseudoVMSLTU_VV_MF2, 0x3 }, // 2007 { PseudoVMSLTU_VV_MF4_MASK, PseudoVMSLTU_VV_MF4, 0x3 }, // 2008 { PseudoVMSLTU_VV_MF8_MASK, PseudoVMSLTU_VV_MF8, 0x3 }, // 2009 { PseudoVMSLTU_VX_M1_MASK, PseudoVMSLTU_VX_M1, 0x3 }, // 2010 { PseudoVMSLTU_VX_M2_MASK, PseudoVMSLTU_VX_M2, 0x3 }, // 2011 { PseudoVMSLTU_VX_M4_MASK, PseudoVMSLTU_VX_M4, 0x3 }, // 2012 { PseudoVMSLTU_VX_M8_MASK, PseudoVMSLTU_VX_M8, 0x3 }, // 2013 { PseudoVMSLTU_VX_MF2_MASK, PseudoVMSLTU_VX_MF2, 0x3 }, // 2014 { PseudoVMSLTU_VX_MF4_MASK, PseudoVMSLTU_VX_MF4, 0x3 }, // 2015 { PseudoVMSLTU_VX_MF8_MASK, PseudoVMSLTU_VX_MF8, 0x3 }, // 2016 { PseudoVMSLT_VV_M1_MASK, PseudoVMSLT_VV_M1, 0x3 }, // 2017 { PseudoVMSLT_VV_M2_MASK, PseudoVMSLT_VV_M2, 0x3 }, // 2018 { PseudoVMSLT_VV_M4_MASK, PseudoVMSLT_VV_M4, 0x3 }, // 2019 { PseudoVMSLT_VV_M8_MASK, PseudoVMSLT_VV_M8, 0x3 }, // 2020 { PseudoVMSLT_VV_MF2_MASK, PseudoVMSLT_VV_MF2, 0x3 }, // 2021 { PseudoVMSLT_VV_MF4_MASK, PseudoVMSLT_VV_MF4, 0x3 }, // 2022 { PseudoVMSLT_VV_MF8_MASK, PseudoVMSLT_VV_MF8, 0x3 }, // 2023 { PseudoVMSLT_VX_M1_MASK, PseudoVMSLT_VX_M1, 0x3 }, // 2024 { PseudoVMSLT_VX_M2_MASK, PseudoVMSLT_VX_M2, 0x3 }, // 2025 { PseudoVMSLT_VX_M4_MASK, PseudoVMSLT_VX_M4, 0x3 }, // 2026 { PseudoVMSLT_VX_M8_MASK, PseudoVMSLT_VX_M8, 0x3 }, // 2027 { PseudoVMSLT_VX_MF2_MASK, PseudoVMSLT_VX_MF2, 0x3 }, // 2028 { PseudoVMSLT_VX_MF4_MASK, PseudoVMSLT_VX_MF4, 0x3 }, // 2029 { PseudoVMSLT_VX_MF8_MASK, PseudoVMSLT_VX_MF8, 0x3 }, // 2030 { PseudoVMSNE_VI_M1_MASK, PseudoVMSNE_VI_M1, 0x3 }, // 2031 { PseudoVMSNE_VI_M2_MASK, PseudoVMSNE_VI_M2, 0x3 }, // 2032 { PseudoVMSNE_VI_M4_MASK, PseudoVMSNE_VI_M4, 0x3 }, // 2033 { PseudoVMSNE_VI_M8_MASK, PseudoVMSNE_VI_M8, 0x3 }, // 2034 { PseudoVMSNE_VI_MF2_MASK, PseudoVMSNE_VI_MF2, 0x3 }, // 2035 { PseudoVMSNE_VI_MF4_MASK, PseudoVMSNE_VI_MF4, 0x3 }, // 2036 { PseudoVMSNE_VI_MF8_MASK, PseudoVMSNE_VI_MF8, 0x3 }, // 2037 { PseudoVMSNE_VV_M1_MASK, PseudoVMSNE_VV_M1, 0x3 }, // 2038 { PseudoVMSNE_VV_M2_MASK, PseudoVMSNE_VV_M2, 0x3 }, // 2039 { PseudoVMSNE_VV_M4_MASK, PseudoVMSNE_VV_M4, 0x3 }, // 2040 { PseudoVMSNE_VV_M8_MASK, PseudoVMSNE_VV_M8, 0x3 }, // 2041 { PseudoVMSNE_VV_MF2_MASK, PseudoVMSNE_VV_MF2, 0x3 }, // 2042 { PseudoVMSNE_VV_MF4_MASK, PseudoVMSNE_VV_MF4, 0x3 }, // 2043 { PseudoVMSNE_VV_MF8_MASK, PseudoVMSNE_VV_MF8, 0x3 }, // 2044 { PseudoVMSNE_VX_M1_MASK, PseudoVMSNE_VX_M1, 0x3 }, // 2045 { PseudoVMSNE_VX_M2_MASK, PseudoVMSNE_VX_M2, 0x3 }, // 2046 { PseudoVMSNE_VX_M4_MASK, PseudoVMSNE_VX_M4, 0x3 }, // 2047 { PseudoVMSNE_VX_M8_MASK, PseudoVMSNE_VX_M8, 0x3 }, // 2048 { PseudoVMSNE_VX_MF2_MASK, PseudoVMSNE_VX_MF2, 0x3 }, // 2049 { PseudoVMSNE_VX_MF4_MASK, PseudoVMSNE_VX_MF4, 0x3 }, // 2050 { PseudoVMSNE_VX_MF8_MASK, PseudoVMSNE_VX_MF8, 0x3 }, // 2051 { PseudoVMULHSU_VV_M1_MASK, PseudoVMULHSU_VV_M1, 0x3 }, // 2052 { PseudoVMULHSU_VV_M2_MASK, PseudoVMULHSU_VV_M2, 0x3 }, // 2053 { PseudoVMULHSU_VV_M4_MASK, PseudoVMULHSU_VV_M4, 0x3 }, // 2054 { PseudoVMULHSU_VV_M8_MASK, PseudoVMULHSU_VV_M8, 0x3 }, // 2055 { PseudoVMULHSU_VV_MF2_MASK, PseudoVMULHSU_VV_MF2, 0x3 }, // 2056 { PseudoVMULHSU_VV_MF4_MASK, PseudoVMULHSU_VV_MF4, 0x3 }, // 2057 { PseudoVMULHSU_VV_MF8_MASK, PseudoVMULHSU_VV_MF8, 0x3 }, // 2058 { PseudoVMULHSU_VX_M1_MASK, PseudoVMULHSU_VX_M1, 0x3 }, // 2059 { PseudoVMULHSU_VX_M2_MASK, PseudoVMULHSU_VX_M2, 0x3 }, // 2060 { PseudoVMULHSU_VX_M4_MASK, PseudoVMULHSU_VX_M4, 0x3 }, // 2061 { PseudoVMULHSU_VX_M8_MASK, PseudoVMULHSU_VX_M8, 0x3 }, // 2062 { PseudoVMULHSU_VX_MF2_MASK, PseudoVMULHSU_VX_MF2, 0x3 }, // 2063 { PseudoVMULHSU_VX_MF4_MASK, PseudoVMULHSU_VX_MF4, 0x3 }, // 2064 { PseudoVMULHSU_VX_MF8_MASK, PseudoVMULHSU_VX_MF8, 0x3 }, // 2065 { PseudoVMULHU_VV_M1_MASK, PseudoVMULHU_VV_M1, 0x3 }, // 2066 { PseudoVMULHU_VV_M2_MASK, PseudoVMULHU_VV_M2, 0x3 }, // 2067 { PseudoVMULHU_VV_M4_MASK, PseudoVMULHU_VV_M4, 0x3 }, // 2068 { PseudoVMULHU_VV_M8_MASK, PseudoVMULHU_VV_M8, 0x3 }, // 2069 { PseudoVMULHU_VV_MF2_MASK, PseudoVMULHU_VV_MF2, 0x3 }, // 2070 { PseudoVMULHU_VV_MF4_MASK, PseudoVMULHU_VV_MF4, 0x3 }, // 2071 { PseudoVMULHU_VV_MF8_MASK, PseudoVMULHU_VV_MF8, 0x3 }, // 2072 { PseudoVMULHU_VX_M1_MASK, PseudoVMULHU_VX_M1, 0x3 }, // 2073 { PseudoVMULHU_VX_M2_MASK, PseudoVMULHU_VX_M2, 0x3 }, // 2074 { PseudoVMULHU_VX_M4_MASK, PseudoVMULHU_VX_M4, 0x3 }, // 2075 { PseudoVMULHU_VX_M8_MASK, PseudoVMULHU_VX_M8, 0x3 }, // 2076 { PseudoVMULHU_VX_MF2_MASK, PseudoVMULHU_VX_MF2, 0x3 }, // 2077 { PseudoVMULHU_VX_MF4_MASK, PseudoVMULHU_VX_MF4, 0x3 }, // 2078 { PseudoVMULHU_VX_MF8_MASK, PseudoVMULHU_VX_MF8, 0x3 }, // 2079 { PseudoVMULH_VV_M1_MASK, PseudoVMULH_VV_M1, 0x3 }, // 2080 { PseudoVMULH_VV_M2_MASK, PseudoVMULH_VV_M2, 0x3 }, // 2081 { PseudoVMULH_VV_M4_MASK, PseudoVMULH_VV_M4, 0x3 }, // 2082 { PseudoVMULH_VV_M8_MASK, PseudoVMULH_VV_M8, 0x3 }, // 2083 { PseudoVMULH_VV_MF2_MASK, PseudoVMULH_VV_MF2, 0x3 }, // 2084 { PseudoVMULH_VV_MF4_MASK, PseudoVMULH_VV_MF4, 0x3 }, // 2085 { PseudoVMULH_VV_MF8_MASK, PseudoVMULH_VV_MF8, 0x3 }, // 2086 { PseudoVMULH_VX_M1_MASK, PseudoVMULH_VX_M1, 0x3 }, // 2087 { PseudoVMULH_VX_M2_MASK, PseudoVMULH_VX_M2, 0x3 }, // 2088 { PseudoVMULH_VX_M4_MASK, PseudoVMULH_VX_M4, 0x3 }, // 2089 { PseudoVMULH_VX_M8_MASK, PseudoVMULH_VX_M8, 0x3 }, // 2090 { PseudoVMULH_VX_MF2_MASK, PseudoVMULH_VX_MF2, 0x3 }, // 2091 { PseudoVMULH_VX_MF4_MASK, PseudoVMULH_VX_MF4, 0x3 }, // 2092 { PseudoVMULH_VX_MF8_MASK, PseudoVMULH_VX_MF8, 0x3 }, // 2093 { PseudoVMUL_VV_M1_MASK, PseudoVMUL_VV_M1, 0x3 }, // 2094 { PseudoVMUL_VV_M2_MASK, PseudoVMUL_VV_M2, 0x3 }, // 2095 { PseudoVMUL_VV_M4_MASK, PseudoVMUL_VV_M4, 0x3 }, // 2096 { PseudoVMUL_VV_M8_MASK, PseudoVMUL_VV_M8, 0x3 }, // 2097 { PseudoVMUL_VV_MF2_MASK, PseudoVMUL_VV_MF2, 0x3 }, // 2098 { PseudoVMUL_VV_MF4_MASK, PseudoVMUL_VV_MF4, 0x3 }, // 2099 { PseudoVMUL_VV_MF8_MASK, PseudoVMUL_VV_MF8, 0x3 }, // 2100 { PseudoVMUL_VX_M1_MASK, PseudoVMUL_VX_M1, 0x3 }, // 2101 { PseudoVMUL_VX_M2_MASK, PseudoVMUL_VX_M2, 0x3 }, // 2102 { PseudoVMUL_VX_M4_MASK, PseudoVMUL_VX_M4, 0x3 }, // 2103 { PseudoVMUL_VX_M8_MASK, PseudoVMUL_VX_M8, 0x3 }, // 2104 { PseudoVMUL_VX_MF2_MASK, PseudoVMUL_VX_MF2, 0x3 }, // 2105 { PseudoVMUL_VX_MF4_MASK, PseudoVMUL_VX_MF4, 0x3 }, // 2106 { PseudoVMUL_VX_MF8_MASK, PseudoVMUL_VX_MF8, 0x3 }, // 2107 { PseudoVNCLIPU_WI_M1_MASK, PseudoVNCLIPU_WI_M1, 0x3 }, // 2108 { PseudoVNCLIPU_WI_M2_MASK, PseudoVNCLIPU_WI_M2, 0x3 }, // 2109 { PseudoVNCLIPU_WI_M4_MASK, PseudoVNCLIPU_WI_M4, 0x3 }, // 2110 { PseudoVNCLIPU_WI_MF2_MASK, PseudoVNCLIPU_WI_MF2, 0x3 }, // 2111 { PseudoVNCLIPU_WI_MF4_MASK, PseudoVNCLIPU_WI_MF4, 0x3 }, // 2112 { PseudoVNCLIPU_WI_MF8_MASK, PseudoVNCLIPU_WI_MF8, 0x3 }, // 2113 { PseudoVNCLIPU_WV_M1_MASK, PseudoVNCLIPU_WV_M1, 0x3 }, // 2114 { PseudoVNCLIPU_WV_M2_MASK, PseudoVNCLIPU_WV_M2, 0x3 }, // 2115 { PseudoVNCLIPU_WV_M4_MASK, PseudoVNCLIPU_WV_M4, 0x3 }, // 2116 { PseudoVNCLIPU_WV_MF2_MASK, PseudoVNCLIPU_WV_MF2, 0x3 }, // 2117 { PseudoVNCLIPU_WV_MF4_MASK, PseudoVNCLIPU_WV_MF4, 0x3 }, // 2118 { PseudoVNCLIPU_WV_MF8_MASK, PseudoVNCLIPU_WV_MF8, 0x3 }, // 2119 { PseudoVNCLIPU_WX_M1_MASK, PseudoVNCLIPU_WX_M1, 0x3 }, // 2120 { PseudoVNCLIPU_WX_M2_MASK, PseudoVNCLIPU_WX_M2, 0x3 }, // 2121 { PseudoVNCLIPU_WX_M4_MASK, PseudoVNCLIPU_WX_M4, 0x3 }, // 2122 { PseudoVNCLIPU_WX_MF2_MASK, PseudoVNCLIPU_WX_MF2, 0x3 }, // 2123 { PseudoVNCLIPU_WX_MF4_MASK, PseudoVNCLIPU_WX_MF4, 0x3 }, // 2124 { PseudoVNCLIPU_WX_MF8_MASK, PseudoVNCLIPU_WX_MF8, 0x3 }, // 2125 { PseudoVNCLIP_WI_M1_MASK, PseudoVNCLIP_WI_M1, 0x3 }, // 2126 { PseudoVNCLIP_WI_M2_MASK, PseudoVNCLIP_WI_M2, 0x3 }, // 2127 { PseudoVNCLIP_WI_M4_MASK, PseudoVNCLIP_WI_M4, 0x3 }, // 2128 { PseudoVNCLIP_WI_MF2_MASK, PseudoVNCLIP_WI_MF2, 0x3 }, // 2129 { PseudoVNCLIP_WI_MF4_MASK, PseudoVNCLIP_WI_MF4, 0x3 }, // 2130 { PseudoVNCLIP_WI_MF8_MASK, PseudoVNCLIP_WI_MF8, 0x3 }, // 2131 { PseudoVNCLIP_WV_M1_MASK, PseudoVNCLIP_WV_M1, 0x3 }, // 2132 { PseudoVNCLIP_WV_M2_MASK, PseudoVNCLIP_WV_M2, 0x3 }, // 2133 { PseudoVNCLIP_WV_M4_MASK, PseudoVNCLIP_WV_M4, 0x3 }, // 2134 { PseudoVNCLIP_WV_MF2_MASK, PseudoVNCLIP_WV_MF2, 0x3 }, // 2135 { PseudoVNCLIP_WV_MF4_MASK, PseudoVNCLIP_WV_MF4, 0x3 }, // 2136 { PseudoVNCLIP_WV_MF8_MASK, PseudoVNCLIP_WV_MF8, 0x3 }, // 2137 { PseudoVNCLIP_WX_M1_MASK, PseudoVNCLIP_WX_M1, 0x3 }, // 2138 { PseudoVNCLIP_WX_M2_MASK, PseudoVNCLIP_WX_M2, 0x3 }, // 2139 { PseudoVNCLIP_WX_M4_MASK, PseudoVNCLIP_WX_M4, 0x3 }, // 2140 { PseudoVNCLIP_WX_MF2_MASK, PseudoVNCLIP_WX_MF2, 0x3 }, // 2141 { PseudoVNCLIP_WX_MF4_MASK, PseudoVNCLIP_WX_MF4, 0x3 }, // 2142 { PseudoVNCLIP_WX_MF8_MASK, PseudoVNCLIP_WX_MF8, 0x3 }, // 2143 { PseudoVNMSAC_VV_M1_MASK, PseudoVNMSAC_VV_M1, 0x3 }, // 2144 { PseudoVNMSAC_VV_M2_MASK, PseudoVNMSAC_VV_M2, 0x3 }, // 2145 { PseudoVNMSAC_VV_M4_MASK, PseudoVNMSAC_VV_M4, 0x3 }, // 2146 { PseudoVNMSAC_VV_M8_MASK, PseudoVNMSAC_VV_M8, 0x3 }, // 2147 { PseudoVNMSAC_VV_MF2_MASK, PseudoVNMSAC_VV_MF2, 0x3 }, // 2148 { PseudoVNMSAC_VV_MF4_MASK, PseudoVNMSAC_VV_MF4, 0x3 }, // 2149 { PseudoVNMSAC_VV_MF8_MASK, PseudoVNMSAC_VV_MF8, 0x3 }, // 2150 { PseudoVNMSAC_VX_M1_MASK, PseudoVNMSAC_VX_M1, 0x3 }, // 2151 { PseudoVNMSAC_VX_M2_MASK, PseudoVNMSAC_VX_M2, 0x3 }, // 2152 { PseudoVNMSAC_VX_M4_MASK, PseudoVNMSAC_VX_M4, 0x3 }, // 2153 { PseudoVNMSAC_VX_M8_MASK, PseudoVNMSAC_VX_M8, 0x3 }, // 2154 { PseudoVNMSAC_VX_MF2_MASK, PseudoVNMSAC_VX_MF2, 0x3 }, // 2155 { PseudoVNMSAC_VX_MF4_MASK, PseudoVNMSAC_VX_MF4, 0x3 }, // 2156 { PseudoVNMSAC_VX_MF8_MASK, PseudoVNMSAC_VX_MF8, 0x3 }, // 2157 { PseudoVNMSUB_VV_M1_MASK, PseudoVNMSUB_VV_M1, 0x3 }, // 2158 { PseudoVNMSUB_VV_M2_MASK, PseudoVNMSUB_VV_M2, 0x3 }, // 2159 { PseudoVNMSUB_VV_M4_MASK, PseudoVNMSUB_VV_M4, 0x3 }, // 2160 { PseudoVNMSUB_VV_M8_MASK, PseudoVNMSUB_VV_M8, 0x3 }, // 2161 { PseudoVNMSUB_VV_MF2_MASK, PseudoVNMSUB_VV_MF2, 0x3 }, // 2162 { PseudoVNMSUB_VV_MF4_MASK, PseudoVNMSUB_VV_MF4, 0x3 }, // 2163 { PseudoVNMSUB_VV_MF8_MASK, PseudoVNMSUB_VV_MF8, 0x3 }, // 2164 { PseudoVNMSUB_VX_M1_MASK, PseudoVNMSUB_VX_M1, 0x3 }, // 2165 { PseudoVNMSUB_VX_M2_MASK, PseudoVNMSUB_VX_M2, 0x3 }, // 2166 { PseudoVNMSUB_VX_M4_MASK, PseudoVNMSUB_VX_M4, 0x3 }, // 2167 { PseudoVNMSUB_VX_M8_MASK, PseudoVNMSUB_VX_M8, 0x3 }, // 2168 { PseudoVNMSUB_VX_MF2_MASK, PseudoVNMSUB_VX_MF2, 0x3 }, // 2169 { PseudoVNMSUB_VX_MF4_MASK, PseudoVNMSUB_VX_MF4, 0x3 }, // 2170 { PseudoVNMSUB_VX_MF8_MASK, PseudoVNMSUB_VX_MF8, 0x3 }, // 2171 { PseudoVNSRA_WI_M1_MASK, PseudoVNSRA_WI_M1, 0x3 }, // 2172 { PseudoVNSRA_WI_M2_MASK, PseudoVNSRA_WI_M2, 0x3 }, // 2173 { PseudoVNSRA_WI_M4_MASK, PseudoVNSRA_WI_M4, 0x3 }, // 2174 { PseudoVNSRA_WI_MF2_MASK, PseudoVNSRA_WI_MF2, 0x3 }, // 2175 { PseudoVNSRA_WI_MF4_MASK, PseudoVNSRA_WI_MF4, 0x3 }, // 2176 { PseudoVNSRA_WI_MF8_MASK, PseudoVNSRA_WI_MF8, 0x3 }, // 2177 { PseudoVNSRA_WV_M1_MASK, PseudoVNSRA_WV_M1, 0x3 }, // 2178 { PseudoVNSRA_WV_M2_MASK, PseudoVNSRA_WV_M2, 0x3 }, // 2179 { PseudoVNSRA_WV_M4_MASK, PseudoVNSRA_WV_M4, 0x3 }, // 2180 { PseudoVNSRA_WV_MF2_MASK, PseudoVNSRA_WV_MF2, 0x3 }, // 2181 { PseudoVNSRA_WV_MF4_MASK, PseudoVNSRA_WV_MF4, 0x3 }, // 2182 { PseudoVNSRA_WV_MF8_MASK, PseudoVNSRA_WV_MF8, 0x3 }, // 2183 { PseudoVNSRA_WX_M1_MASK, PseudoVNSRA_WX_M1, 0x3 }, // 2184 { PseudoVNSRA_WX_M2_MASK, PseudoVNSRA_WX_M2, 0x3 }, // 2185 { PseudoVNSRA_WX_M4_MASK, PseudoVNSRA_WX_M4, 0x3 }, // 2186 { PseudoVNSRA_WX_MF2_MASK, PseudoVNSRA_WX_MF2, 0x3 }, // 2187 { PseudoVNSRA_WX_MF4_MASK, PseudoVNSRA_WX_MF4, 0x3 }, // 2188 { PseudoVNSRA_WX_MF8_MASK, PseudoVNSRA_WX_MF8, 0x3 }, // 2189 { PseudoVNSRL_WI_M1_MASK, PseudoVNSRL_WI_M1, 0x3 }, // 2190 { PseudoVNSRL_WI_M2_MASK, PseudoVNSRL_WI_M2, 0x3 }, // 2191 { PseudoVNSRL_WI_M4_MASK, PseudoVNSRL_WI_M4, 0x3 }, // 2192 { PseudoVNSRL_WI_MF2_MASK, PseudoVNSRL_WI_MF2, 0x3 }, // 2193 { PseudoVNSRL_WI_MF4_MASK, PseudoVNSRL_WI_MF4, 0x3 }, // 2194 { PseudoVNSRL_WI_MF8_MASK, PseudoVNSRL_WI_MF8, 0x3 }, // 2195 { PseudoVNSRL_WV_M1_MASK, PseudoVNSRL_WV_M1, 0x3 }, // 2196 { PseudoVNSRL_WV_M2_MASK, PseudoVNSRL_WV_M2, 0x3 }, // 2197 { PseudoVNSRL_WV_M4_MASK, PseudoVNSRL_WV_M4, 0x3 }, // 2198 { PseudoVNSRL_WV_MF2_MASK, PseudoVNSRL_WV_MF2, 0x3 }, // 2199 { PseudoVNSRL_WV_MF4_MASK, PseudoVNSRL_WV_MF4, 0x3 }, // 2200 { PseudoVNSRL_WV_MF8_MASK, PseudoVNSRL_WV_MF8, 0x3 }, // 2201 { PseudoVNSRL_WX_M1_MASK, PseudoVNSRL_WX_M1, 0x3 }, // 2202 { PseudoVNSRL_WX_M2_MASK, PseudoVNSRL_WX_M2, 0x3 }, // 2203 { PseudoVNSRL_WX_M4_MASK, PseudoVNSRL_WX_M4, 0x3 }, // 2204 { PseudoVNSRL_WX_MF2_MASK, PseudoVNSRL_WX_MF2, 0x3 }, // 2205 { PseudoVNSRL_WX_MF4_MASK, PseudoVNSRL_WX_MF4, 0x3 }, // 2206 { PseudoVNSRL_WX_MF8_MASK, PseudoVNSRL_WX_MF8, 0x3 }, // 2207 { PseudoVOR_VI_M1_MASK, PseudoVOR_VI_M1, 0x3 }, // 2208 { PseudoVOR_VI_M2_MASK, PseudoVOR_VI_M2, 0x3 }, // 2209 { PseudoVOR_VI_M4_MASK, PseudoVOR_VI_M4, 0x3 }, // 2210 { PseudoVOR_VI_M8_MASK, PseudoVOR_VI_M8, 0x3 }, // 2211 { PseudoVOR_VI_MF2_MASK, PseudoVOR_VI_MF2, 0x3 }, // 2212 { PseudoVOR_VI_MF4_MASK, PseudoVOR_VI_MF4, 0x3 }, // 2213 { PseudoVOR_VI_MF8_MASK, PseudoVOR_VI_MF8, 0x3 }, // 2214 { PseudoVOR_VV_M1_MASK, PseudoVOR_VV_M1, 0x3 }, // 2215 { PseudoVOR_VV_M2_MASK, PseudoVOR_VV_M2, 0x3 }, // 2216 { PseudoVOR_VV_M4_MASK, PseudoVOR_VV_M4, 0x3 }, // 2217 { PseudoVOR_VV_M8_MASK, PseudoVOR_VV_M8, 0x3 }, // 2218 { PseudoVOR_VV_MF2_MASK, PseudoVOR_VV_MF2, 0x3 }, // 2219 { PseudoVOR_VV_MF4_MASK, PseudoVOR_VV_MF4, 0x3 }, // 2220 { PseudoVOR_VV_MF8_MASK, PseudoVOR_VV_MF8, 0x3 }, // 2221 { PseudoVOR_VX_M1_MASK, PseudoVOR_VX_M1, 0x3 }, // 2222 { PseudoVOR_VX_M2_MASK, PseudoVOR_VX_M2, 0x3 }, // 2223 { PseudoVOR_VX_M4_MASK, PseudoVOR_VX_M4, 0x3 }, // 2224 { PseudoVOR_VX_M8_MASK, PseudoVOR_VX_M8, 0x3 }, // 2225 { PseudoVOR_VX_MF2_MASK, PseudoVOR_VX_MF2, 0x3 }, // 2226 { PseudoVOR_VX_MF4_MASK, PseudoVOR_VX_MF4, 0x3 }, // 2227 { PseudoVOR_VX_MF8_MASK, PseudoVOR_VX_MF8, 0x3 }, // 2228 { PseudoVREDAND_VS_M1_E16_MASK, PseudoVREDAND_VS_M1_E16, 0x3 }, // 2229 { PseudoVREDAND_VS_M1_E32_MASK, PseudoVREDAND_VS_M1_E32, 0x3 }, // 2230 { PseudoVREDAND_VS_M1_E64_MASK, PseudoVREDAND_VS_M1_E64, 0x3 }, // 2231 { PseudoVREDAND_VS_M1_E8_MASK, PseudoVREDAND_VS_M1_E8, 0x3 }, // 2232 { PseudoVREDAND_VS_M2_E16_MASK, PseudoVREDAND_VS_M2_E16, 0x3 }, // 2233 { PseudoVREDAND_VS_M2_E32_MASK, PseudoVREDAND_VS_M2_E32, 0x3 }, // 2234 { PseudoVREDAND_VS_M2_E64_MASK, PseudoVREDAND_VS_M2_E64, 0x3 }, // 2235 { PseudoVREDAND_VS_M2_E8_MASK, PseudoVREDAND_VS_M2_E8, 0x3 }, // 2236 { PseudoVREDAND_VS_M4_E16_MASK, PseudoVREDAND_VS_M4_E16, 0x3 }, // 2237 { PseudoVREDAND_VS_M4_E32_MASK, PseudoVREDAND_VS_M4_E32, 0x3 }, // 2238 { PseudoVREDAND_VS_M4_E64_MASK, PseudoVREDAND_VS_M4_E64, 0x3 }, // 2239 { PseudoVREDAND_VS_M4_E8_MASK, PseudoVREDAND_VS_M4_E8, 0x3 }, // 2240 { PseudoVREDAND_VS_M8_E16_MASK, PseudoVREDAND_VS_M8_E16, 0x3 }, // 2241 { PseudoVREDAND_VS_M8_E32_MASK, PseudoVREDAND_VS_M8_E32, 0x3 }, // 2242 { PseudoVREDAND_VS_M8_E64_MASK, PseudoVREDAND_VS_M8_E64, 0x3 }, // 2243 { PseudoVREDAND_VS_M8_E8_MASK, PseudoVREDAND_VS_M8_E8, 0x3 }, // 2244 { PseudoVREDAND_VS_MF2_E16_MASK, PseudoVREDAND_VS_MF2_E16, 0x3 }, // 2245 { PseudoVREDAND_VS_MF2_E32_MASK, PseudoVREDAND_VS_MF2_E32, 0x3 }, // 2246 { PseudoVREDAND_VS_MF2_E8_MASK, PseudoVREDAND_VS_MF2_E8, 0x3 }, // 2247 { PseudoVREDAND_VS_MF4_E16_MASK, PseudoVREDAND_VS_MF4_E16, 0x3 }, // 2248 { PseudoVREDAND_VS_MF4_E8_MASK, PseudoVREDAND_VS_MF4_E8, 0x3 }, // 2249 { PseudoVREDAND_VS_MF8_E8_MASK, PseudoVREDAND_VS_MF8_E8, 0x3 }, // 2250 { PseudoVREDMAXU_VS_M1_E16_MASK, PseudoVREDMAXU_VS_M1_E16, 0x3 }, // 2251 { PseudoVREDMAXU_VS_M1_E32_MASK, PseudoVREDMAXU_VS_M1_E32, 0x3 }, // 2252 { PseudoVREDMAXU_VS_M1_E64_MASK, PseudoVREDMAXU_VS_M1_E64, 0x3 }, // 2253 { PseudoVREDMAXU_VS_M1_E8_MASK, PseudoVREDMAXU_VS_M1_E8, 0x3 }, // 2254 { PseudoVREDMAXU_VS_M2_E16_MASK, PseudoVREDMAXU_VS_M2_E16, 0x3 }, // 2255 { PseudoVREDMAXU_VS_M2_E32_MASK, PseudoVREDMAXU_VS_M2_E32, 0x3 }, // 2256 { PseudoVREDMAXU_VS_M2_E64_MASK, PseudoVREDMAXU_VS_M2_E64, 0x3 }, // 2257 { PseudoVREDMAXU_VS_M2_E8_MASK, PseudoVREDMAXU_VS_M2_E8, 0x3 }, // 2258 { PseudoVREDMAXU_VS_M4_E16_MASK, PseudoVREDMAXU_VS_M4_E16, 0x3 }, // 2259 { PseudoVREDMAXU_VS_M4_E32_MASK, PseudoVREDMAXU_VS_M4_E32, 0x3 }, // 2260 { PseudoVREDMAXU_VS_M4_E64_MASK, PseudoVREDMAXU_VS_M4_E64, 0x3 }, // 2261 { PseudoVREDMAXU_VS_M4_E8_MASK, PseudoVREDMAXU_VS_M4_E8, 0x3 }, // 2262 { PseudoVREDMAXU_VS_M8_E16_MASK, PseudoVREDMAXU_VS_M8_E16, 0x3 }, // 2263 { PseudoVREDMAXU_VS_M8_E32_MASK, PseudoVREDMAXU_VS_M8_E32, 0x3 }, // 2264 { PseudoVREDMAXU_VS_M8_E64_MASK, PseudoVREDMAXU_VS_M8_E64, 0x3 }, // 2265 { PseudoVREDMAXU_VS_M8_E8_MASK, PseudoVREDMAXU_VS_M8_E8, 0x3 }, // 2266 { PseudoVREDMAXU_VS_MF2_E16_MASK, PseudoVREDMAXU_VS_MF2_E16, 0x3 }, // 2267 { PseudoVREDMAXU_VS_MF2_E32_MASK, PseudoVREDMAXU_VS_MF2_E32, 0x3 }, // 2268 { PseudoVREDMAXU_VS_MF2_E8_MASK, PseudoVREDMAXU_VS_MF2_E8, 0x3 }, // 2269 { PseudoVREDMAXU_VS_MF4_E16_MASK, PseudoVREDMAXU_VS_MF4_E16, 0x3 }, // 2270 { PseudoVREDMAXU_VS_MF4_E8_MASK, PseudoVREDMAXU_VS_MF4_E8, 0x3 }, // 2271 { PseudoVREDMAXU_VS_MF8_E8_MASK, PseudoVREDMAXU_VS_MF8_E8, 0x3 }, // 2272 { PseudoVREDMAX_VS_M1_E16_MASK, PseudoVREDMAX_VS_M1_E16, 0x3 }, // 2273 { PseudoVREDMAX_VS_M1_E32_MASK, PseudoVREDMAX_VS_M1_E32, 0x3 }, // 2274 { PseudoVREDMAX_VS_M1_E64_MASK, PseudoVREDMAX_VS_M1_E64, 0x3 }, // 2275 { PseudoVREDMAX_VS_M1_E8_MASK, PseudoVREDMAX_VS_M1_E8, 0x3 }, // 2276 { PseudoVREDMAX_VS_M2_E16_MASK, PseudoVREDMAX_VS_M2_E16, 0x3 }, // 2277 { PseudoVREDMAX_VS_M2_E32_MASK, PseudoVREDMAX_VS_M2_E32, 0x3 }, // 2278 { PseudoVREDMAX_VS_M2_E64_MASK, PseudoVREDMAX_VS_M2_E64, 0x3 }, // 2279 { PseudoVREDMAX_VS_M2_E8_MASK, PseudoVREDMAX_VS_M2_E8, 0x3 }, // 2280 { PseudoVREDMAX_VS_M4_E16_MASK, PseudoVREDMAX_VS_M4_E16, 0x3 }, // 2281 { PseudoVREDMAX_VS_M4_E32_MASK, PseudoVREDMAX_VS_M4_E32, 0x3 }, // 2282 { PseudoVREDMAX_VS_M4_E64_MASK, PseudoVREDMAX_VS_M4_E64, 0x3 }, // 2283 { PseudoVREDMAX_VS_M4_E8_MASK, PseudoVREDMAX_VS_M4_E8, 0x3 }, // 2284 { PseudoVREDMAX_VS_M8_E16_MASK, PseudoVREDMAX_VS_M8_E16, 0x3 }, // 2285 { PseudoVREDMAX_VS_M8_E32_MASK, PseudoVREDMAX_VS_M8_E32, 0x3 }, // 2286 { PseudoVREDMAX_VS_M8_E64_MASK, PseudoVREDMAX_VS_M8_E64, 0x3 }, // 2287 { PseudoVREDMAX_VS_M8_E8_MASK, PseudoVREDMAX_VS_M8_E8, 0x3 }, // 2288 { PseudoVREDMAX_VS_MF2_E16_MASK, PseudoVREDMAX_VS_MF2_E16, 0x3 }, // 2289 { PseudoVREDMAX_VS_MF2_E32_MASK, PseudoVREDMAX_VS_MF2_E32, 0x3 }, // 2290 { PseudoVREDMAX_VS_MF2_E8_MASK, PseudoVREDMAX_VS_MF2_E8, 0x3 }, // 2291 { PseudoVREDMAX_VS_MF4_E16_MASK, PseudoVREDMAX_VS_MF4_E16, 0x3 }, // 2292 { PseudoVREDMAX_VS_MF4_E8_MASK, PseudoVREDMAX_VS_MF4_E8, 0x3 }, // 2293 { PseudoVREDMAX_VS_MF8_E8_MASK, PseudoVREDMAX_VS_MF8_E8, 0x3 }, // 2294 { PseudoVREDMINU_VS_M1_E16_MASK, PseudoVREDMINU_VS_M1_E16, 0x3 }, // 2295 { PseudoVREDMINU_VS_M1_E32_MASK, PseudoVREDMINU_VS_M1_E32, 0x3 }, // 2296 { PseudoVREDMINU_VS_M1_E64_MASK, PseudoVREDMINU_VS_M1_E64, 0x3 }, // 2297 { PseudoVREDMINU_VS_M1_E8_MASK, PseudoVREDMINU_VS_M1_E8, 0x3 }, // 2298 { PseudoVREDMINU_VS_M2_E16_MASK, PseudoVREDMINU_VS_M2_E16, 0x3 }, // 2299 { PseudoVREDMINU_VS_M2_E32_MASK, PseudoVREDMINU_VS_M2_E32, 0x3 }, // 2300 { PseudoVREDMINU_VS_M2_E64_MASK, PseudoVREDMINU_VS_M2_E64, 0x3 }, // 2301 { PseudoVREDMINU_VS_M2_E8_MASK, PseudoVREDMINU_VS_M2_E8, 0x3 }, // 2302 { PseudoVREDMINU_VS_M4_E16_MASK, PseudoVREDMINU_VS_M4_E16, 0x3 }, // 2303 { PseudoVREDMINU_VS_M4_E32_MASK, PseudoVREDMINU_VS_M4_E32, 0x3 }, // 2304 { PseudoVREDMINU_VS_M4_E64_MASK, PseudoVREDMINU_VS_M4_E64, 0x3 }, // 2305 { PseudoVREDMINU_VS_M4_E8_MASK, PseudoVREDMINU_VS_M4_E8, 0x3 }, // 2306 { PseudoVREDMINU_VS_M8_E16_MASK, PseudoVREDMINU_VS_M8_E16, 0x3 }, // 2307 { PseudoVREDMINU_VS_M8_E32_MASK, PseudoVREDMINU_VS_M8_E32, 0x3 }, // 2308 { PseudoVREDMINU_VS_M8_E64_MASK, PseudoVREDMINU_VS_M8_E64, 0x3 }, // 2309 { PseudoVREDMINU_VS_M8_E8_MASK, PseudoVREDMINU_VS_M8_E8, 0x3 }, // 2310 { PseudoVREDMINU_VS_MF2_E16_MASK, PseudoVREDMINU_VS_MF2_E16, 0x3 }, // 2311 { PseudoVREDMINU_VS_MF2_E32_MASK, PseudoVREDMINU_VS_MF2_E32, 0x3 }, // 2312 { PseudoVREDMINU_VS_MF2_E8_MASK, PseudoVREDMINU_VS_MF2_E8, 0x3 }, // 2313 { PseudoVREDMINU_VS_MF4_E16_MASK, PseudoVREDMINU_VS_MF4_E16, 0x3 }, // 2314 { PseudoVREDMINU_VS_MF4_E8_MASK, PseudoVREDMINU_VS_MF4_E8, 0x3 }, // 2315 { PseudoVREDMINU_VS_MF8_E8_MASK, PseudoVREDMINU_VS_MF8_E8, 0x3 }, // 2316 { PseudoVREDMIN_VS_M1_E16_MASK, PseudoVREDMIN_VS_M1_E16, 0x3 }, // 2317 { PseudoVREDMIN_VS_M1_E32_MASK, PseudoVREDMIN_VS_M1_E32, 0x3 }, // 2318 { PseudoVREDMIN_VS_M1_E64_MASK, PseudoVREDMIN_VS_M1_E64, 0x3 }, // 2319 { PseudoVREDMIN_VS_M1_E8_MASK, PseudoVREDMIN_VS_M1_E8, 0x3 }, // 2320 { PseudoVREDMIN_VS_M2_E16_MASK, PseudoVREDMIN_VS_M2_E16, 0x3 }, // 2321 { PseudoVREDMIN_VS_M2_E32_MASK, PseudoVREDMIN_VS_M2_E32, 0x3 }, // 2322 { PseudoVREDMIN_VS_M2_E64_MASK, PseudoVREDMIN_VS_M2_E64, 0x3 }, // 2323 { PseudoVREDMIN_VS_M2_E8_MASK, PseudoVREDMIN_VS_M2_E8, 0x3 }, // 2324 { PseudoVREDMIN_VS_M4_E16_MASK, PseudoVREDMIN_VS_M4_E16, 0x3 }, // 2325 { PseudoVREDMIN_VS_M4_E32_MASK, PseudoVREDMIN_VS_M4_E32, 0x3 }, // 2326 { PseudoVREDMIN_VS_M4_E64_MASK, PseudoVREDMIN_VS_M4_E64, 0x3 }, // 2327 { PseudoVREDMIN_VS_M4_E8_MASK, PseudoVREDMIN_VS_M4_E8, 0x3 }, // 2328 { PseudoVREDMIN_VS_M8_E16_MASK, PseudoVREDMIN_VS_M8_E16, 0x3 }, // 2329 { PseudoVREDMIN_VS_M8_E32_MASK, PseudoVREDMIN_VS_M8_E32, 0x3 }, // 2330 { PseudoVREDMIN_VS_M8_E64_MASK, PseudoVREDMIN_VS_M8_E64, 0x3 }, // 2331 { PseudoVREDMIN_VS_M8_E8_MASK, PseudoVREDMIN_VS_M8_E8, 0x3 }, // 2332 { PseudoVREDMIN_VS_MF2_E16_MASK, PseudoVREDMIN_VS_MF2_E16, 0x3 }, // 2333 { PseudoVREDMIN_VS_MF2_E32_MASK, PseudoVREDMIN_VS_MF2_E32, 0x3 }, // 2334 { PseudoVREDMIN_VS_MF2_E8_MASK, PseudoVREDMIN_VS_MF2_E8, 0x3 }, // 2335 { PseudoVREDMIN_VS_MF4_E16_MASK, PseudoVREDMIN_VS_MF4_E16, 0x3 }, // 2336 { PseudoVREDMIN_VS_MF4_E8_MASK, PseudoVREDMIN_VS_MF4_E8, 0x3 }, // 2337 { PseudoVREDMIN_VS_MF8_E8_MASK, PseudoVREDMIN_VS_MF8_E8, 0x3 }, // 2338 { PseudoVREDOR_VS_M1_E16_MASK, PseudoVREDOR_VS_M1_E16, 0x3 }, // 2339 { PseudoVREDOR_VS_M1_E32_MASK, PseudoVREDOR_VS_M1_E32, 0x3 }, // 2340 { PseudoVREDOR_VS_M1_E64_MASK, PseudoVREDOR_VS_M1_E64, 0x3 }, // 2341 { PseudoVREDOR_VS_M1_E8_MASK, PseudoVREDOR_VS_M1_E8, 0x3 }, // 2342 { PseudoVREDOR_VS_M2_E16_MASK, PseudoVREDOR_VS_M2_E16, 0x3 }, // 2343 { PseudoVREDOR_VS_M2_E32_MASK, PseudoVREDOR_VS_M2_E32, 0x3 }, // 2344 { PseudoVREDOR_VS_M2_E64_MASK, PseudoVREDOR_VS_M2_E64, 0x3 }, // 2345 { PseudoVREDOR_VS_M2_E8_MASK, PseudoVREDOR_VS_M2_E8, 0x3 }, // 2346 { PseudoVREDOR_VS_M4_E16_MASK, PseudoVREDOR_VS_M4_E16, 0x3 }, // 2347 { PseudoVREDOR_VS_M4_E32_MASK, PseudoVREDOR_VS_M4_E32, 0x3 }, // 2348 { PseudoVREDOR_VS_M4_E64_MASK, PseudoVREDOR_VS_M4_E64, 0x3 }, // 2349 { PseudoVREDOR_VS_M4_E8_MASK, PseudoVREDOR_VS_M4_E8, 0x3 }, // 2350 { PseudoVREDOR_VS_M8_E16_MASK, PseudoVREDOR_VS_M8_E16, 0x3 }, // 2351 { PseudoVREDOR_VS_M8_E32_MASK, PseudoVREDOR_VS_M8_E32, 0x3 }, // 2352 { PseudoVREDOR_VS_M8_E64_MASK, PseudoVREDOR_VS_M8_E64, 0x3 }, // 2353 { PseudoVREDOR_VS_M8_E8_MASK, PseudoVREDOR_VS_M8_E8, 0x3 }, // 2354 { PseudoVREDOR_VS_MF2_E16_MASK, PseudoVREDOR_VS_MF2_E16, 0x3 }, // 2355 { PseudoVREDOR_VS_MF2_E32_MASK, PseudoVREDOR_VS_MF2_E32, 0x3 }, // 2356 { PseudoVREDOR_VS_MF2_E8_MASK, PseudoVREDOR_VS_MF2_E8, 0x3 }, // 2357 { PseudoVREDOR_VS_MF4_E16_MASK, PseudoVREDOR_VS_MF4_E16, 0x3 }, // 2358 { PseudoVREDOR_VS_MF4_E8_MASK, PseudoVREDOR_VS_MF4_E8, 0x3 }, // 2359 { PseudoVREDOR_VS_MF8_E8_MASK, PseudoVREDOR_VS_MF8_E8, 0x3 }, // 2360 { PseudoVREDSUM_VS_M1_E16_MASK, PseudoVREDSUM_VS_M1_E16, 0x3 }, // 2361 { PseudoVREDSUM_VS_M1_E32_MASK, PseudoVREDSUM_VS_M1_E32, 0x3 }, // 2362 { PseudoVREDSUM_VS_M1_E64_MASK, PseudoVREDSUM_VS_M1_E64, 0x3 }, // 2363 { PseudoVREDSUM_VS_M1_E8_MASK, PseudoVREDSUM_VS_M1_E8, 0x3 }, // 2364 { PseudoVREDSUM_VS_M2_E16_MASK, PseudoVREDSUM_VS_M2_E16, 0x3 }, // 2365 { PseudoVREDSUM_VS_M2_E32_MASK, PseudoVREDSUM_VS_M2_E32, 0x3 }, // 2366 { PseudoVREDSUM_VS_M2_E64_MASK, PseudoVREDSUM_VS_M2_E64, 0x3 }, // 2367 { PseudoVREDSUM_VS_M2_E8_MASK, PseudoVREDSUM_VS_M2_E8, 0x3 }, // 2368 { PseudoVREDSUM_VS_M4_E16_MASK, PseudoVREDSUM_VS_M4_E16, 0x3 }, // 2369 { PseudoVREDSUM_VS_M4_E32_MASK, PseudoVREDSUM_VS_M4_E32, 0x3 }, // 2370 { PseudoVREDSUM_VS_M4_E64_MASK, PseudoVREDSUM_VS_M4_E64, 0x3 }, // 2371 { PseudoVREDSUM_VS_M4_E8_MASK, PseudoVREDSUM_VS_M4_E8, 0x3 }, // 2372 { PseudoVREDSUM_VS_M8_E16_MASK, PseudoVREDSUM_VS_M8_E16, 0x3 }, // 2373 { PseudoVREDSUM_VS_M8_E32_MASK, PseudoVREDSUM_VS_M8_E32, 0x3 }, // 2374 { PseudoVREDSUM_VS_M8_E64_MASK, PseudoVREDSUM_VS_M8_E64, 0x3 }, // 2375 { PseudoVREDSUM_VS_M8_E8_MASK, PseudoVREDSUM_VS_M8_E8, 0x3 }, // 2376 { PseudoVREDSUM_VS_MF2_E16_MASK, PseudoVREDSUM_VS_MF2_E16, 0x3 }, // 2377 { PseudoVREDSUM_VS_MF2_E32_MASK, PseudoVREDSUM_VS_MF2_E32, 0x3 }, // 2378 { PseudoVREDSUM_VS_MF2_E8_MASK, PseudoVREDSUM_VS_MF2_E8, 0x3 }, // 2379 { PseudoVREDSUM_VS_MF4_E16_MASK, PseudoVREDSUM_VS_MF4_E16, 0x3 }, // 2380 { PseudoVREDSUM_VS_MF4_E8_MASK, PseudoVREDSUM_VS_MF4_E8, 0x3 }, // 2381 { PseudoVREDSUM_VS_MF8_E8_MASK, PseudoVREDSUM_VS_MF8_E8, 0x3 }, // 2382 { PseudoVREDXOR_VS_M1_E16_MASK, PseudoVREDXOR_VS_M1_E16, 0x3 }, // 2383 { PseudoVREDXOR_VS_M1_E32_MASK, PseudoVREDXOR_VS_M1_E32, 0x3 }, // 2384 { PseudoVREDXOR_VS_M1_E64_MASK, PseudoVREDXOR_VS_M1_E64, 0x3 }, // 2385 { PseudoVREDXOR_VS_M1_E8_MASK, PseudoVREDXOR_VS_M1_E8, 0x3 }, // 2386 { PseudoVREDXOR_VS_M2_E16_MASK, PseudoVREDXOR_VS_M2_E16, 0x3 }, // 2387 { PseudoVREDXOR_VS_M2_E32_MASK, PseudoVREDXOR_VS_M2_E32, 0x3 }, // 2388 { PseudoVREDXOR_VS_M2_E64_MASK, PseudoVREDXOR_VS_M2_E64, 0x3 }, // 2389 { PseudoVREDXOR_VS_M2_E8_MASK, PseudoVREDXOR_VS_M2_E8, 0x3 }, // 2390 { PseudoVREDXOR_VS_M4_E16_MASK, PseudoVREDXOR_VS_M4_E16, 0x3 }, // 2391 { PseudoVREDXOR_VS_M4_E32_MASK, PseudoVREDXOR_VS_M4_E32, 0x3 }, // 2392 { PseudoVREDXOR_VS_M4_E64_MASK, PseudoVREDXOR_VS_M4_E64, 0x3 }, // 2393 { PseudoVREDXOR_VS_M4_E8_MASK, PseudoVREDXOR_VS_M4_E8, 0x3 }, // 2394 { PseudoVREDXOR_VS_M8_E16_MASK, PseudoVREDXOR_VS_M8_E16, 0x3 }, // 2395 { PseudoVREDXOR_VS_M8_E32_MASK, PseudoVREDXOR_VS_M8_E32, 0x3 }, // 2396 { PseudoVREDXOR_VS_M8_E64_MASK, PseudoVREDXOR_VS_M8_E64, 0x3 }, // 2397 { PseudoVREDXOR_VS_M8_E8_MASK, PseudoVREDXOR_VS_M8_E8, 0x3 }, // 2398 { PseudoVREDXOR_VS_MF2_E16_MASK, PseudoVREDXOR_VS_MF2_E16, 0x3 }, // 2399 { PseudoVREDXOR_VS_MF2_E32_MASK, PseudoVREDXOR_VS_MF2_E32, 0x3 }, // 2400 { PseudoVREDXOR_VS_MF2_E8_MASK, PseudoVREDXOR_VS_MF2_E8, 0x3 }, // 2401 { PseudoVREDXOR_VS_MF4_E16_MASK, PseudoVREDXOR_VS_MF4_E16, 0x3 }, // 2402 { PseudoVREDXOR_VS_MF4_E8_MASK, PseudoVREDXOR_VS_MF4_E8, 0x3 }, // 2403 { PseudoVREDXOR_VS_MF8_E8_MASK, PseudoVREDXOR_VS_MF8_E8, 0x3 }, // 2404 { PseudoVREMU_VV_M1_E16_MASK, PseudoVREMU_VV_M1_E16, 0x3 }, // 2405 { PseudoVREMU_VV_M1_E32_MASK, PseudoVREMU_VV_M1_E32, 0x3 }, // 2406 { PseudoVREMU_VV_M1_E64_MASK, PseudoVREMU_VV_M1_E64, 0x3 }, // 2407 { PseudoVREMU_VV_M1_E8_MASK, PseudoVREMU_VV_M1_E8, 0x3 }, // 2408 { PseudoVREMU_VV_M2_E16_MASK, PseudoVREMU_VV_M2_E16, 0x3 }, // 2409 { PseudoVREMU_VV_M2_E32_MASK, PseudoVREMU_VV_M2_E32, 0x3 }, // 2410 { PseudoVREMU_VV_M2_E64_MASK, PseudoVREMU_VV_M2_E64, 0x3 }, // 2411 { PseudoVREMU_VV_M2_E8_MASK, PseudoVREMU_VV_M2_E8, 0x3 }, // 2412 { PseudoVREMU_VV_M4_E16_MASK, PseudoVREMU_VV_M4_E16, 0x3 }, // 2413 { PseudoVREMU_VV_M4_E32_MASK, PseudoVREMU_VV_M4_E32, 0x3 }, // 2414 { PseudoVREMU_VV_M4_E64_MASK, PseudoVREMU_VV_M4_E64, 0x3 }, // 2415 { PseudoVREMU_VV_M4_E8_MASK, PseudoVREMU_VV_M4_E8, 0x3 }, // 2416 { PseudoVREMU_VV_M8_E16_MASK, PseudoVREMU_VV_M8_E16, 0x3 }, // 2417 { PseudoVREMU_VV_M8_E32_MASK, PseudoVREMU_VV_M8_E32, 0x3 }, // 2418 { PseudoVREMU_VV_M8_E64_MASK, PseudoVREMU_VV_M8_E64, 0x3 }, // 2419 { PseudoVREMU_VV_M8_E8_MASK, PseudoVREMU_VV_M8_E8, 0x3 }, // 2420 { PseudoVREMU_VV_MF2_E16_MASK, PseudoVREMU_VV_MF2_E16, 0x3 }, // 2421 { PseudoVREMU_VV_MF2_E32_MASK, PseudoVREMU_VV_MF2_E32, 0x3 }, // 2422 { PseudoVREMU_VV_MF2_E8_MASK, PseudoVREMU_VV_MF2_E8, 0x3 }, // 2423 { PseudoVREMU_VV_MF4_E16_MASK, PseudoVREMU_VV_MF4_E16, 0x3 }, // 2424 { PseudoVREMU_VV_MF4_E8_MASK, PseudoVREMU_VV_MF4_E8, 0x3 }, // 2425 { PseudoVREMU_VV_MF8_E8_MASK, PseudoVREMU_VV_MF8_E8, 0x3 }, // 2426 { PseudoVREMU_VX_M1_E16_MASK, PseudoVREMU_VX_M1_E16, 0x3 }, // 2427 { PseudoVREMU_VX_M1_E32_MASK, PseudoVREMU_VX_M1_E32, 0x3 }, // 2428 { PseudoVREMU_VX_M1_E64_MASK, PseudoVREMU_VX_M1_E64, 0x3 }, // 2429 { PseudoVREMU_VX_M1_E8_MASK, PseudoVREMU_VX_M1_E8, 0x3 }, // 2430 { PseudoVREMU_VX_M2_E16_MASK, PseudoVREMU_VX_M2_E16, 0x3 }, // 2431 { PseudoVREMU_VX_M2_E32_MASK, PseudoVREMU_VX_M2_E32, 0x3 }, // 2432 { PseudoVREMU_VX_M2_E64_MASK, PseudoVREMU_VX_M2_E64, 0x3 }, // 2433 { PseudoVREMU_VX_M2_E8_MASK, PseudoVREMU_VX_M2_E8, 0x3 }, // 2434 { PseudoVREMU_VX_M4_E16_MASK, PseudoVREMU_VX_M4_E16, 0x3 }, // 2435 { PseudoVREMU_VX_M4_E32_MASK, PseudoVREMU_VX_M4_E32, 0x3 }, // 2436 { PseudoVREMU_VX_M4_E64_MASK, PseudoVREMU_VX_M4_E64, 0x3 }, // 2437 { PseudoVREMU_VX_M4_E8_MASK, PseudoVREMU_VX_M4_E8, 0x3 }, // 2438 { PseudoVREMU_VX_M8_E16_MASK, PseudoVREMU_VX_M8_E16, 0x3 }, // 2439 { PseudoVREMU_VX_M8_E32_MASK, PseudoVREMU_VX_M8_E32, 0x3 }, // 2440 { PseudoVREMU_VX_M8_E64_MASK, PseudoVREMU_VX_M8_E64, 0x3 }, // 2441 { PseudoVREMU_VX_M8_E8_MASK, PseudoVREMU_VX_M8_E8, 0x3 }, // 2442 { PseudoVREMU_VX_MF2_E16_MASK, PseudoVREMU_VX_MF2_E16, 0x3 }, // 2443 { PseudoVREMU_VX_MF2_E32_MASK, PseudoVREMU_VX_MF2_E32, 0x3 }, // 2444 { PseudoVREMU_VX_MF2_E8_MASK, PseudoVREMU_VX_MF2_E8, 0x3 }, // 2445 { PseudoVREMU_VX_MF4_E16_MASK, PseudoVREMU_VX_MF4_E16, 0x3 }, // 2446 { PseudoVREMU_VX_MF4_E8_MASK, PseudoVREMU_VX_MF4_E8, 0x3 }, // 2447 { PseudoVREMU_VX_MF8_E8_MASK, PseudoVREMU_VX_MF8_E8, 0x3 }, // 2448 { PseudoVREM_VV_M1_E16_MASK, PseudoVREM_VV_M1_E16, 0x3 }, // 2449 { PseudoVREM_VV_M1_E32_MASK, PseudoVREM_VV_M1_E32, 0x3 }, // 2450 { PseudoVREM_VV_M1_E64_MASK, PseudoVREM_VV_M1_E64, 0x3 }, // 2451 { PseudoVREM_VV_M1_E8_MASK, PseudoVREM_VV_M1_E8, 0x3 }, // 2452 { PseudoVREM_VV_M2_E16_MASK, PseudoVREM_VV_M2_E16, 0x3 }, // 2453 { PseudoVREM_VV_M2_E32_MASK, PseudoVREM_VV_M2_E32, 0x3 }, // 2454 { PseudoVREM_VV_M2_E64_MASK, PseudoVREM_VV_M2_E64, 0x3 }, // 2455 { PseudoVREM_VV_M2_E8_MASK, PseudoVREM_VV_M2_E8, 0x3 }, // 2456 { PseudoVREM_VV_M4_E16_MASK, PseudoVREM_VV_M4_E16, 0x3 }, // 2457 { PseudoVREM_VV_M4_E32_MASK, PseudoVREM_VV_M4_E32, 0x3 }, // 2458 { PseudoVREM_VV_M4_E64_MASK, PseudoVREM_VV_M4_E64, 0x3 }, // 2459 { PseudoVREM_VV_M4_E8_MASK, PseudoVREM_VV_M4_E8, 0x3 }, // 2460 { PseudoVREM_VV_M8_E16_MASK, PseudoVREM_VV_M8_E16, 0x3 }, // 2461 { PseudoVREM_VV_M8_E32_MASK, PseudoVREM_VV_M8_E32, 0x3 }, // 2462 { PseudoVREM_VV_M8_E64_MASK, PseudoVREM_VV_M8_E64, 0x3 }, // 2463 { PseudoVREM_VV_M8_E8_MASK, PseudoVREM_VV_M8_E8, 0x3 }, // 2464 { PseudoVREM_VV_MF2_E16_MASK, PseudoVREM_VV_MF2_E16, 0x3 }, // 2465 { PseudoVREM_VV_MF2_E32_MASK, PseudoVREM_VV_MF2_E32, 0x3 }, // 2466 { PseudoVREM_VV_MF2_E8_MASK, PseudoVREM_VV_MF2_E8, 0x3 }, // 2467 { PseudoVREM_VV_MF4_E16_MASK, PseudoVREM_VV_MF4_E16, 0x3 }, // 2468 { PseudoVREM_VV_MF4_E8_MASK, PseudoVREM_VV_MF4_E8, 0x3 }, // 2469 { PseudoVREM_VV_MF8_E8_MASK, PseudoVREM_VV_MF8_E8, 0x3 }, // 2470 { PseudoVREM_VX_M1_E16_MASK, PseudoVREM_VX_M1_E16, 0x3 }, // 2471 { PseudoVREM_VX_M1_E32_MASK, PseudoVREM_VX_M1_E32, 0x3 }, // 2472 { PseudoVREM_VX_M1_E64_MASK, PseudoVREM_VX_M1_E64, 0x3 }, // 2473 { PseudoVREM_VX_M1_E8_MASK, PseudoVREM_VX_M1_E8, 0x3 }, // 2474 { PseudoVREM_VX_M2_E16_MASK, PseudoVREM_VX_M2_E16, 0x3 }, // 2475 { PseudoVREM_VX_M2_E32_MASK, PseudoVREM_VX_M2_E32, 0x3 }, // 2476 { PseudoVREM_VX_M2_E64_MASK, PseudoVREM_VX_M2_E64, 0x3 }, // 2477 { PseudoVREM_VX_M2_E8_MASK, PseudoVREM_VX_M2_E8, 0x3 }, // 2478 { PseudoVREM_VX_M4_E16_MASK, PseudoVREM_VX_M4_E16, 0x3 }, // 2479 { PseudoVREM_VX_M4_E32_MASK, PseudoVREM_VX_M4_E32, 0x3 }, // 2480 { PseudoVREM_VX_M4_E64_MASK, PseudoVREM_VX_M4_E64, 0x3 }, // 2481 { PseudoVREM_VX_M4_E8_MASK, PseudoVREM_VX_M4_E8, 0x3 }, // 2482 { PseudoVREM_VX_M8_E16_MASK, PseudoVREM_VX_M8_E16, 0x3 }, // 2483 { PseudoVREM_VX_M8_E32_MASK, PseudoVREM_VX_M8_E32, 0x3 }, // 2484 { PseudoVREM_VX_M8_E64_MASK, PseudoVREM_VX_M8_E64, 0x3 }, // 2485 { PseudoVREM_VX_M8_E8_MASK, PseudoVREM_VX_M8_E8, 0x3 }, // 2486 { PseudoVREM_VX_MF2_E16_MASK, PseudoVREM_VX_MF2_E16, 0x3 }, // 2487 { PseudoVREM_VX_MF2_E32_MASK, PseudoVREM_VX_MF2_E32, 0x3 }, // 2488 { PseudoVREM_VX_MF2_E8_MASK, PseudoVREM_VX_MF2_E8, 0x3 }, // 2489 { PseudoVREM_VX_MF4_E16_MASK, PseudoVREM_VX_MF4_E16, 0x3 }, // 2490 { PseudoVREM_VX_MF4_E8_MASK, PseudoVREM_VX_MF4_E8, 0x3 }, // 2491 { PseudoVREM_VX_MF8_E8_MASK, PseudoVREM_VX_MF8_E8, 0x3 }, // 2492 { PseudoVREV8_V_M1_MASK, PseudoVREV8_V_M1, 0x2 }, // 2493 { PseudoVREV8_V_M2_MASK, PseudoVREV8_V_M2, 0x2 }, // 2494 { PseudoVREV8_V_M4_MASK, PseudoVREV8_V_M4, 0x2 }, // 2495 { PseudoVREV8_V_M8_MASK, PseudoVREV8_V_M8, 0x2 }, // 2496 { PseudoVREV8_V_MF2_MASK, PseudoVREV8_V_MF2, 0x2 }, // 2497 { PseudoVREV8_V_MF4_MASK, PseudoVREV8_V_MF4, 0x2 }, // 2498 { PseudoVREV8_V_MF8_MASK, PseudoVREV8_V_MF8, 0x2 }, // 2499 { PseudoVRGATHEREI16_VV_M1_E16_M1_MASK, PseudoVRGATHEREI16_VV_M1_E16_M1, 0x3 }, // 2500 { PseudoVRGATHEREI16_VV_M1_E16_M2_MASK, PseudoVRGATHEREI16_VV_M1_E16_M2, 0x3 }, // 2501 { PseudoVRGATHEREI16_VV_M1_E16_MF2_MASK, PseudoVRGATHEREI16_VV_M1_E16_MF2, 0x3 }, // 2502 { PseudoVRGATHEREI16_VV_M1_E16_MF4_MASK, PseudoVRGATHEREI16_VV_M1_E16_MF4, 0x3 }, // 2503 { PseudoVRGATHEREI16_VV_M1_E32_M1_MASK, PseudoVRGATHEREI16_VV_M1_E32_M1, 0x3 }, // 2504 { PseudoVRGATHEREI16_VV_M1_E32_M2_MASK, PseudoVRGATHEREI16_VV_M1_E32_M2, 0x3 }, // 2505 { PseudoVRGATHEREI16_VV_M1_E32_MF2_MASK, PseudoVRGATHEREI16_VV_M1_E32_MF2, 0x3 }, // 2506 { PseudoVRGATHEREI16_VV_M1_E32_MF4_MASK, PseudoVRGATHEREI16_VV_M1_E32_MF4, 0x3 }, // 2507 { PseudoVRGATHEREI16_VV_M1_E64_M1_MASK, PseudoVRGATHEREI16_VV_M1_E64_M1, 0x3 }, // 2508 { PseudoVRGATHEREI16_VV_M1_E64_M2_MASK, PseudoVRGATHEREI16_VV_M1_E64_M2, 0x3 }, // 2509 { PseudoVRGATHEREI16_VV_M1_E64_MF2_MASK, PseudoVRGATHEREI16_VV_M1_E64_MF2, 0x3 }, // 2510 { PseudoVRGATHEREI16_VV_M1_E64_MF4_MASK, PseudoVRGATHEREI16_VV_M1_E64_MF4, 0x3 }, // 2511 { PseudoVRGATHEREI16_VV_M1_E8_M1_MASK, PseudoVRGATHEREI16_VV_M1_E8_M1, 0x3 }, // 2512 { PseudoVRGATHEREI16_VV_M1_E8_M2_MASK, PseudoVRGATHEREI16_VV_M1_E8_M2, 0x3 }, // 2513 { PseudoVRGATHEREI16_VV_M1_E8_MF2_MASK, PseudoVRGATHEREI16_VV_M1_E8_MF2, 0x3 }, // 2514 { PseudoVRGATHEREI16_VV_M1_E8_MF4_MASK, PseudoVRGATHEREI16_VV_M1_E8_MF4, 0x3 }, // 2515 { PseudoVRGATHEREI16_VV_M2_E16_M1_MASK, PseudoVRGATHEREI16_VV_M2_E16_M1, 0x3 }, // 2516 { PseudoVRGATHEREI16_VV_M2_E16_M2_MASK, PseudoVRGATHEREI16_VV_M2_E16_M2, 0x3 }, // 2517 { PseudoVRGATHEREI16_VV_M2_E16_M4_MASK, PseudoVRGATHEREI16_VV_M2_E16_M4, 0x3 }, // 2518 { PseudoVRGATHEREI16_VV_M2_E16_MF2_MASK, PseudoVRGATHEREI16_VV_M2_E16_MF2, 0x3 }, // 2519 { PseudoVRGATHEREI16_VV_M2_E32_M1_MASK, PseudoVRGATHEREI16_VV_M2_E32_M1, 0x3 }, // 2520 { PseudoVRGATHEREI16_VV_M2_E32_M2_MASK, PseudoVRGATHEREI16_VV_M2_E32_M2, 0x3 }, // 2521 { PseudoVRGATHEREI16_VV_M2_E32_M4_MASK, PseudoVRGATHEREI16_VV_M2_E32_M4, 0x3 }, // 2522 { PseudoVRGATHEREI16_VV_M2_E32_MF2_MASK, PseudoVRGATHEREI16_VV_M2_E32_MF2, 0x3 }, // 2523 { PseudoVRGATHEREI16_VV_M2_E64_M1_MASK, PseudoVRGATHEREI16_VV_M2_E64_M1, 0x3 }, // 2524 { PseudoVRGATHEREI16_VV_M2_E64_M2_MASK, PseudoVRGATHEREI16_VV_M2_E64_M2, 0x3 }, // 2525 { PseudoVRGATHEREI16_VV_M2_E64_M4_MASK, PseudoVRGATHEREI16_VV_M2_E64_M4, 0x3 }, // 2526 { PseudoVRGATHEREI16_VV_M2_E64_MF2_MASK, PseudoVRGATHEREI16_VV_M2_E64_MF2, 0x3 }, // 2527 { PseudoVRGATHEREI16_VV_M2_E8_M1_MASK, PseudoVRGATHEREI16_VV_M2_E8_M1, 0x3 }, // 2528 { PseudoVRGATHEREI16_VV_M2_E8_M2_MASK, PseudoVRGATHEREI16_VV_M2_E8_M2, 0x3 }, // 2529 { PseudoVRGATHEREI16_VV_M2_E8_M4_MASK, PseudoVRGATHEREI16_VV_M2_E8_M4, 0x3 }, // 2530 { PseudoVRGATHEREI16_VV_M2_E8_MF2_MASK, PseudoVRGATHEREI16_VV_M2_E8_MF2, 0x3 }, // 2531 { PseudoVRGATHEREI16_VV_M4_E16_M1_MASK, PseudoVRGATHEREI16_VV_M4_E16_M1, 0x3 }, // 2532 { PseudoVRGATHEREI16_VV_M4_E16_M2_MASK, PseudoVRGATHEREI16_VV_M4_E16_M2, 0x3 }, // 2533 { PseudoVRGATHEREI16_VV_M4_E16_M4_MASK, PseudoVRGATHEREI16_VV_M4_E16_M4, 0x3 }, // 2534 { PseudoVRGATHEREI16_VV_M4_E16_M8_MASK, PseudoVRGATHEREI16_VV_M4_E16_M8, 0x3 }, // 2535 { PseudoVRGATHEREI16_VV_M4_E32_M1_MASK, PseudoVRGATHEREI16_VV_M4_E32_M1, 0x3 }, // 2536 { PseudoVRGATHEREI16_VV_M4_E32_M2_MASK, PseudoVRGATHEREI16_VV_M4_E32_M2, 0x3 }, // 2537 { PseudoVRGATHEREI16_VV_M4_E32_M4_MASK, PseudoVRGATHEREI16_VV_M4_E32_M4, 0x3 }, // 2538 { PseudoVRGATHEREI16_VV_M4_E32_M8_MASK, PseudoVRGATHEREI16_VV_M4_E32_M8, 0x3 }, // 2539 { PseudoVRGATHEREI16_VV_M4_E64_M1_MASK, PseudoVRGATHEREI16_VV_M4_E64_M1, 0x3 }, // 2540 { PseudoVRGATHEREI16_VV_M4_E64_M2_MASK, PseudoVRGATHEREI16_VV_M4_E64_M2, 0x3 }, // 2541 { PseudoVRGATHEREI16_VV_M4_E64_M4_MASK, PseudoVRGATHEREI16_VV_M4_E64_M4, 0x3 }, // 2542 { PseudoVRGATHEREI16_VV_M4_E64_M8_MASK, PseudoVRGATHEREI16_VV_M4_E64_M8, 0x3 }, // 2543 { PseudoVRGATHEREI16_VV_M4_E8_M1_MASK, PseudoVRGATHEREI16_VV_M4_E8_M1, 0x3 }, // 2544 { PseudoVRGATHEREI16_VV_M4_E8_M2_MASK, PseudoVRGATHEREI16_VV_M4_E8_M2, 0x3 }, // 2545 { PseudoVRGATHEREI16_VV_M4_E8_M4_MASK, PseudoVRGATHEREI16_VV_M4_E8_M4, 0x3 }, // 2546 { PseudoVRGATHEREI16_VV_M4_E8_M8_MASK, PseudoVRGATHEREI16_VV_M4_E8_M8, 0x3 }, // 2547 { PseudoVRGATHEREI16_VV_M8_E16_M2_MASK, PseudoVRGATHEREI16_VV_M8_E16_M2, 0x3 }, // 2548 { PseudoVRGATHEREI16_VV_M8_E16_M4_MASK, PseudoVRGATHEREI16_VV_M8_E16_M4, 0x3 }, // 2549 { PseudoVRGATHEREI16_VV_M8_E16_M8_MASK, PseudoVRGATHEREI16_VV_M8_E16_M8, 0x3 }, // 2550 { PseudoVRGATHEREI16_VV_M8_E32_M2_MASK, PseudoVRGATHEREI16_VV_M8_E32_M2, 0x3 }, // 2551 { PseudoVRGATHEREI16_VV_M8_E32_M4_MASK, PseudoVRGATHEREI16_VV_M8_E32_M4, 0x3 }, // 2552 { PseudoVRGATHEREI16_VV_M8_E32_M8_MASK, PseudoVRGATHEREI16_VV_M8_E32_M8, 0x3 }, // 2553 { PseudoVRGATHEREI16_VV_M8_E64_M2_MASK, PseudoVRGATHEREI16_VV_M8_E64_M2, 0x3 }, // 2554 { PseudoVRGATHEREI16_VV_M8_E64_M4_MASK, PseudoVRGATHEREI16_VV_M8_E64_M4, 0x3 }, // 2555 { PseudoVRGATHEREI16_VV_M8_E64_M8_MASK, PseudoVRGATHEREI16_VV_M8_E64_M8, 0x3 }, // 2556 { PseudoVRGATHEREI16_VV_M8_E8_M2_MASK, PseudoVRGATHEREI16_VV_M8_E8_M2, 0x3 }, // 2557 { PseudoVRGATHEREI16_VV_M8_E8_M4_MASK, PseudoVRGATHEREI16_VV_M8_E8_M4, 0x3 }, // 2558 { PseudoVRGATHEREI16_VV_M8_E8_M8_MASK, PseudoVRGATHEREI16_VV_M8_E8_M8, 0x3 }, // 2559 { PseudoVRGATHEREI16_VV_MF2_E16_M1_MASK, PseudoVRGATHEREI16_VV_MF2_E16_M1, 0x3 }, // 2560 { PseudoVRGATHEREI16_VV_MF2_E16_MF2_MASK, PseudoVRGATHEREI16_VV_MF2_E16_MF2, 0x3 }, // 2561 { PseudoVRGATHEREI16_VV_MF2_E16_MF4_MASK, PseudoVRGATHEREI16_VV_MF2_E16_MF4, 0x3 }, // 2562 { PseudoVRGATHEREI16_VV_MF2_E16_MF8_MASK, PseudoVRGATHEREI16_VV_MF2_E16_MF8, 0x3 }, // 2563 { PseudoVRGATHEREI16_VV_MF2_E32_M1_MASK, PseudoVRGATHEREI16_VV_MF2_E32_M1, 0x3 }, // 2564 { PseudoVRGATHEREI16_VV_MF2_E32_MF2_MASK, PseudoVRGATHEREI16_VV_MF2_E32_MF2, 0x3 }, // 2565 { PseudoVRGATHEREI16_VV_MF2_E32_MF4_MASK, PseudoVRGATHEREI16_VV_MF2_E32_MF4, 0x3 }, // 2566 { PseudoVRGATHEREI16_VV_MF2_E32_MF8_MASK, PseudoVRGATHEREI16_VV_MF2_E32_MF8, 0x3 }, // 2567 { PseudoVRGATHEREI16_VV_MF2_E8_M1_MASK, PseudoVRGATHEREI16_VV_MF2_E8_M1, 0x3 }, // 2568 { PseudoVRGATHEREI16_VV_MF2_E8_MF2_MASK, PseudoVRGATHEREI16_VV_MF2_E8_MF2, 0x3 }, // 2569 { PseudoVRGATHEREI16_VV_MF2_E8_MF4_MASK, PseudoVRGATHEREI16_VV_MF2_E8_MF4, 0x3 }, // 2570 { PseudoVRGATHEREI16_VV_MF2_E8_MF8_MASK, PseudoVRGATHEREI16_VV_MF2_E8_MF8, 0x3 }, // 2571 { PseudoVRGATHEREI16_VV_MF4_E16_MF2_MASK, PseudoVRGATHEREI16_VV_MF4_E16_MF2, 0x3 }, // 2572 { PseudoVRGATHEREI16_VV_MF4_E16_MF4_MASK, PseudoVRGATHEREI16_VV_MF4_E16_MF4, 0x3 }, // 2573 { PseudoVRGATHEREI16_VV_MF4_E16_MF8_MASK, PseudoVRGATHEREI16_VV_MF4_E16_MF8, 0x3 }, // 2574 { PseudoVRGATHEREI16_VV_MF4_E8_MF2_MASK, PseudoVRGATHEREI16_VV_MF4_E8_MF2, 0x3 }, // 2575 { PseudoVRGATHEREI16_VV_MF4_E8_MF4_MASK, PseudoVRGATHEREI16_VV_MF4_E8_MF4, 0x3 }, // 2576 { PseudoVRGATHEREI16_VV_MF4_E8_MF8_MASK, PseudoVRGATHEREI16_VV_MF4_E8_MF8, 0x3 }, // 2577 { PseudoVRGATHEREI16_VV_MF8_E8_MF4_MASK, PseudoVRGATHEREI16_VV_MF8_E8_MF4, 0x3 }, // 2578 { PseudoVRGATHEREI16_VV_MF8_E8_MF8_MASK, PseudoVRGATHEREI16_VV_MF8_E8_MF8, 0x3 }, // 2579 { PseudoVRGATHER_VI_M1_MASK, PseudoVRGATHER_VI_M1, 0x3 }, // 2580 { PseudoVRGATHER_VI_M2_MASK, PseudoVRGATHER_VI_M2, 0x3 }, // 2581 { PseudoVRGATHER_VI_M4_MASK, PseudoVRGATHER_VI_M4, 0x3 }, // 2582 { PseudoVRGATHER_VI_M8_MASK, PseudoVRGATHER_VI_M8, 0x3 }, // 2583 { PseudoVRGATHER_VI_MF2_MASK, PseudoVRGATHER_VI_MF2, 0x3 }, // 2584 { PseudoVRGATHER_VI_MF4_MASK, PseudoVRGATHER_VI_MF4, 0x3 }, // 2585 { PseudoVRGATHER_VI_MF8_MASK, PseudoVRGATHER_VI_MF8, 0x3 }, // 2586 { PseudoVRGATHER_VV_M1_E16_MASK, PseudoVRGATHER_VV_M1_E16, 0x3 }, // 2587 { PseudoVRGATHER_VV_M1_E32_MASK, PseudoVRGATHER_VV_M1_E32, 0x3 }, // 2588 { PseudoVRGATHER_VV_M1_E64_MASK, PseudoVRGATHER_VV_M1_E64, 0x3 }, // 2589 { PseudoVRGATHER_VV_M1_E8_MASK, PseudoVRGATHER_VV_M1_E8, 0x3 }, // 2590 { PseudoVRGATHER_VV_M2_E16_MASK, PseudoVRGATHER_VV_M2_E16, 0x3 }, // 2591 { PseudoVRGATHER_VV_M2_E32_MASK, PseudoVRGATHER_VV_M2_E32, 0x3 }, // 2592 { PseudoVRGATHER_VV_M2_E64_MASK, PseudoVRGATHER_VV_M2_E64, 0x3 }, // 2593 { PseudoVRGATHER_VV_M2_E8_MASK, PseudoVRGATHER_VV_M2_E8, 0x3 }, // 2594 { PseudoVRGATHER_VV_M4_E16_MASK, PseudoVRGATHER_VV_M4_E16, 0x3 }, // 2595 { PseudoVRGATHER_VV_M4_E32_MASK, PseudoVRGATHER_VV_M4_E32, 0x3 }, // 2596 { PseudoVRGATHER_VV_M4_E64_MASK, PseudoVRGATHER_VV_M4_E64, 0x3 }, // 2597 { PseudoVRGATHER_VV_M4_E8_MASK, PseudoVRGATHER_VV_M4_E8, 0x3 }, // 2598 { PseudoVRGATHER_VV_M8_E16_MASK, PseudoVRGATHER_VV_M8_E16, 0x3 }, // 2599 { PseudoVRGATHER_VV_M8_E32_MASK, PseudoVRGATHER_VV_M8_E32, 0x3 }, // 2600 { PseudoVRGATHER_VV_M8_E64_MASK, PseudoVRGATHER_VV_M8_E64, 0x3 }, // 2601 { PseudoVRGATHER_VV_M8_E8_MASK, PseudoVRGATHER_VV_M8_E8, 0x3 }, // 2602 { PseudoVRGATHER_VV_MF2_E16_MASK, PseudoVRGATHER_VV_MF2_E16, 0x3 }, // 2603 { PseudoVRGATHER_VV_MF2_E32_MASK, PseudoVRGATHER_VV_MF2_E32, 0x3 }, // 2604 { PseudoVRGATHER_VV_MF2_E8_MASK, PseudoVRGATHER_VV_MF2_E8, 0x3 }, // 2605 { PseudoVRGATHER_VV_MF4_E16_MASK, PseudoVRGATHER_VV_MF4_E16, 0x3 }, // 2606 { PseudoVRGATHER_VV_MF4_E8_MASK, PseudoVRGATHER_VV_MF4_E8, 0x3 }, // 2607 { PseudoVRGATHER_VV_MF8_E8_MASK, PseudoVRGATHER_VV_MF8_E8, 0x3 }, // 2608 { PseudoVRGATHER_VX_M1_MASK, PseudoVRGATHER_VX_M1, 0x3 }, // 2609 { PseudoVRGATHER_VX_M2_MASK, PseudoVRGATHER_VX_M2, 0x3 }, // 2610 { PseudoVRGATHER_VX_M4_MASK, PseudoVRGATHER_VX_M4, 0x3 }, // 2611 { PseudoVRGATHER_VX_M8_MASK, PseudoVRGATHER_VX_M8, 0x3 }, // 2612 { PseudoVRGATHER_VX_MF2_MASK, PseudoVRGATHER_VX_MF2, 0x3 }, // 2613 { PseudoVRGATHER_VX_MF4_MASK, PseudoVRGATHER_VX_MF4, 0x3 }, // 2614 { PseudoVRGATHER_VX_MF8_MASK, PseudoVRGATHER_VX_MF8, 0x3 }, // 2615 { PseudoVROL_VV_M1_MASK, PseudoVROL_VV_M1, 0x3 }, // 2616 { PseudoVROL_VV_M2_MASK, PseudoVROL_VV_M2, 0x3 }, // 2617 { PseudoVROL_VV_M4_MASK, PseudoVROL_VV_M4, 0x3 }, // 2618 { PseudoVROL_VV_M8_MASK, PseudoVROL_VV_M8, 0x3 }, // 2619 { PseudoVROL_VV_MF2_MASK, PseudoVROL_VV_MF2, 0x3 }, // 2620 { PseudoVROL_VV_MF4_MASK, PseudoVROL_VV_MF4, 0x3 }, // 2621 { PseudoVROL_VV_MF8_MASK, PseudoVROL_VV_MF8, 0x3 }, // 2622 { PseudoVROL_VX_M1_MASK, PseudoVROL_VX_M1, 0x3 }, // 2623 { PseudoVROL_VX_M2_MASK, PseudoVROL_VX_M2, 0x3 }, // 2624 { PseudoVROL_VX_M4_MASK, PseudoVROL_VX_M4, 0x3 }, // 2625 { PseudoVROL_VX_M8_MASK, PseudoVROL_VX_M8, 0x3 }, // 2626 { PseudoVROL_VX_MF2_MASK, PseudoVROL_VX_MF2, 0x3 }, // 2627 { PseudoVROL_VX_MF4_MASK, PseudoVROL_VX_MF4, 0x3 }, // 2628 { PseudoVROL_VX_MF8_MASK, PseudoVROL_VX_MF8, 0x3 }, // 2629 { PseudoVROR_VI_M1_MASK, PseudoVROR_VI_M1, 0x3 }, // 2630 { PseudoVROR_VI_M2_MASK, PseudoVROR_VI_M2, 0x3 }, // 2631 { PseudoVROR_VI_M4_MASK, PseudoVROR_VI_M4, 0x3 }, // 2632 { PseudoVROR_VI_M8_MASK, PseudoVROR_VI_M8, 0x3 }, // 2633 { PseudoVROR_VI_MF2_MASK, PseudoVROR_VI_MF2, 0x3 }, // 2634 { PseudoVROR_VI_MF4_MASK, PseudoVROR_VI_MF4, 0x3 }, // 2635 { PseudoVROR_VI_MF8_MASK, PseudoVROR_VI_MF8, 0x3 }, // 2636 { PseudoVROR_VV_M1_MASK, PseudoVROR_VV_M1, 0x3 }, // 2637 { PseudoVROR_VV_M2_MASK, PseudoVROR_VV_M2, 0x3 }, // 2638 { PseudoVROR_VV_M4_MASK, PseudoVROR_VV_M4, 0x3 }, // 2639 { PseudoVROR_VV_M8_MASK, PseudoVROR_VV_M8, 0x3 }, // 2640 { PseudoVROR_VV_MF2_MASK, PseudoVROR_VV_MF2, 0x3 }, // 2641 { PseudoVROR_VV_MF4_MASK, PseudoVROR_VV_MF4, 0x3 }, // 2642 { PseudoVROR_VV_MF8_MASK, PseudoVROR_VV_MF8, 0x3 }, // 2643 { PseudoVROR_VX_M1_MASK, PseudoVROR_VX_M1, 0x3 }, // 2644 { PseudoVROR_VX_M2_MASK, PseudoVROR_VX_M2, 0x3 }, // 2645 { PseudoVROR_VX_M4_MASK, PseudoVROR_VX_M4, 0x3 }, // 2646 { PseudoVROR_VX_M8_MASK, PseudoVROR_VX_M8, 0x3 }, // 2647 { PseudoVROR_VX_MF2_MASK, PseudoVROR_VX_MF2, 0x3 }, // 2648 { PseudoVROR_VX_MF4_MASK, PseudoVROR_VX_MF4, 0x3 }, // 2649 { PseudoVROR_VX_MF8_MASK, PseudoVROR_VX_MF8, 0x3 }, // 2650 { PseudoVRSUB_VI_M1_MASK, PseudoVRSUB_VI_M1, 0x3 }, // 2651 { PseudoVRSUB_VI_M2_MASK, PseudoVRSUB_VI_M2, 0x3 }, // 2652 { PseudoVRSUB_VI_M4_MASK, PseudoVRSUB_VI_M4, 0x3 }, // 2653 { PseudoVRSUB_VI_M8_MASK, PseudoVRSUB_VI_M8, 0x3 }, // 2654 { PseudoVRSUB_VI_MF2_MASK, PseudoVRSUB_VI_MF2, 0x3 }, // 2655 { PseudoVRSUB_VI_MF4_MASK, PseudoVRSUB_VI_MF4, 0x3 }, // 2656 { PseudoVRSUB_VI_MF8_MASK, PseudoVRSUB_VI_MF8, 0x3 }, // 2657 { PseudoVRSUB_VX_M1_MASK, PseudoVRSUB_VX_M1, 0x3 }, // 2658 { PseudoVRSUB_VX_M2_MASK, PseudoVRSUB_VX_M2, 0x3 }, // 2659 { PseudoVRSUB_VX_M4_MASK, PseudoVRSUB_VX_M4, 0x3 }, // 2660 { PseudoVRSUB_VX_M8_MASK, PseudoVRSUB_VX_M8, 0x3 }, // 2661 { PseudoVRSUB_VX_MF2_MASK, PseudoVRSUB_VX_MF2, 0x3 }, // 2662 { PseudoVRSUB_VX_MF4_MASK, PseudoVRSUB_VX_MF4, 0x3 }, // 2663 { PseudoVRSUB_VX_MF8_MASK, PseudoVRSUB_VX_MF8, 0x3 }, // 2664 { PseudoVSADDU_VI_M1_MASK, PseudoVSADDU_VI_M1, 0x3 }, // 2665 { PseudoVSADDU_VI_M2_MASK, PseudoVSADDU_VI_M2, 0x3 }, // 2666 { PseudoVSADDU_VI_M4_MASK, PseudoVSADDU_VI_M4, 0x3 }, // 2667 { PseudoVSADDU_VI_M8_MASK, PseudoVSADDU_VI_M8, 0x3 }, // 2668 { PseudoVSADDU_VI_MF2_MASK, PseudoVSADDU_VI_MF2, 0x3 }, // 2669 { PseudoVSADDU_VI_MF4_MASK, PseudoVSADDU_VI_MF4, 0x3 }, // 2670 { PseudoVSADDU_VI_MF8_MASK, PseudoVSADDU_VI_MF8, 0x3 }, // 2671 { PseudoVSADDU_VV_M1_MASK, PseudoVSADDU_VV_M1, 0x3 }, // 2672 { PseudoVSADDU_VV_M2_MASK, PseudoVSADDU_VV_M2, 0x3 }, // 2673 { PseudoVSADDU_VV_M4_MASK, PseudoVSADDU_VV_M4, 0x3 }, // 2674 { PseudoVSADDU_VV_M8_MASK, PseudoVSADDU_VV_M8, 0x3 }, // 2675 { PseudoVSADDU_VV_MF2_MASK, PseudoVSADDU_VV_MF2, 0x3 }, // 2676 { PseudoVSADDU_VV_MF4_MASK, PseudoVSADDU_VV_MF4, 0x3 }, // 2677 { PseudoVSADDU_VV_MF8_MASK, PseudoVSADDU_VV_MF8, 0x3 }, // 2678 { PseudoVSADDU_VX_M1_MASK, PseudoVSADDU_VX_M1, 0x3 }, // 2679 { PseudoVSADDU_VX_M2_MASK, PseudoVSADDU_VX_M2, 0x3 }, // 2680 { PseudoVSADDU_VX_M4_MASK, PseudoVSADDU_VX_M4, 0x3 }, // 2681 { PseudoVSADDU_VX_M8_MASK, PseudoVSADDU_VX_M8, 0x3 }, // 2682 { PseudoVSADDU_VX_MF2_MASK, PseudoVSADDU_VX_MF2, 0x3 }, // 2683 { PseudoVSADDU_VX_MF4_MASK, PseudoVSADDU_VX_MF4, 0x3 }, // 2684 { PseudoVSADDU_VX_MF8_MASK, PseudoVSADDU_VX_MF8, 0x3 }, // 2685 { PseudoVSADD_VI_M1_MASK, PseudoVSADD_VI_M1, 0x3 }, // 2686 { PseudoVSADD_VI_M2_MASK, PseudoVSADD_VI_M2, 0x3 }, // 2687 { PseudoVSADD_VI_M4_MASK, PseudoVSADD_VI_M4, 0x3 }, // 2688 { PseudoVSADD_VI_M8_MASK, PseudoVSADD_VI_M8, 0x3 }, // 2689 { PseudoVSADD_VI_MF2_MASK, PseudoVSADD_VI_MF2, 0x3 }, // 2690 { PseudoVSADD_VI_MF4_MASK, PseudoVSADD_VI_MF4, 0x3 }, // 2691 { PseudoVSADD_VI_MF8_MASK, PseudoVSADD_VI_MF8, 0x3 }, // 2692 { PseudoVSADD_VV_M1_MASK, PseudoVSADD_VV_M1, 0x3 }, // 2693 { PseudoVSADD_VV_M2_MASK, PseudoVSADD_VV_M2, 0x3 }, // 2694 { PseudoVSADD_VV_M4_MASK, PseudoVSADD_VV_M4, 0x3 }, // 2695 { PseudoVSADD_VV_M8_MASK, PseudoVSADD_VV_M8, 0x3 }, // 2696 { PseudoVSADD_VV_MF2_MASK, PseudoVSADD_VV_MF2, 0x3 }, // 2697 { PseudoVSADD_VV_MF4_MASK, PseudoVSADD_VV_MF4, 0x3 }, // 2698 { PseudoVSADD_VV_MF8_MASK, PseudoVSADD_VV_MF8, 0x3 }, // 2699 { PseudoVSADD_VX_M1_MASK, PseudoVSADD_VX_M1, 0x3 }, // 2700 { PseudoVSADD_VX_M2_MASK, PseudoVSADD_VX_M2, 0x3 }, // 2701 { PseudoVSADD_VX_M4_MASK, PseudoVSADD_VX_M4, 0x3 }, // 2702 { PseudoVSADD_VX_M8_MASK, PseudoVSADD_VX_M8, 0x3 }, // 2703 { PseudoVSADD_VX_MF2_MASK, PseudoVSADD_VX_MF2, 0x3 }, // 2704 { PseudoVSADD_VX_MF4_MASK, PseudoVSADD_VX_MF4, 0x3 }, // 2705 { PseudoVSADD_VX_MF8_MASK, PseudoVSADD_VX_MF8, 0x3 }, // 2706 { PseudoVSEXT_VF2_M1_MASK, PseudoVSEXT_VF2_M1, 0x2 }, // 2707 { PseudoVSEXT_VF2_M2_MASK, PseudoVSEXT_VF2_M2, 0x2 }, // 2708 { PseudoVSEXT_VF2_M4_MASK, PseudoVSEXT_VF2_M4, 0x2 }, // 2709 { PseudoVSEXT_VF2_M8_MASK, PseudoVSEXT_VF2_M8, 0x2 }, // 2710 { PseudoVSEXT_VF2_MF2_MASK, PseudoVSEXT_VF2_MF2, 0x2 }, // 2711 { PseudoVSEXT_VF2_MF4_MASK, PseudoVSEXT_VF2_MF4, 0x2 }, // 2712 { PseudoVSEXT_VF4_M1_MASK, PseudoVSEXT_VF4_M1, 0x2 }, // 2713 { PseudoVSEXT_VF4_M2_MASK, PseudoVSEXT_VF4_M2, 0x2 }, // 2714 { PseudoVSEXT_VF4_M4_MASK, PseudoVSEXT_VF4_M4, 0x2 }, // 2715 { PseudoVSEXT_VF4_M8_MASK, PseudoVSEXT_VF4_M8, 0x2 }, // 2716 { PseudoVSEXT_VF4_MF2_MASK, PseudoVSEXT_VF4_MF2, 0x2 }, // 2717 { PseudoVSEXT_VF8_M1_MASK, PseudoVSEXT_VF8_M1, 0x2 }, // 2718 { PseudoVSEXT_VF8_M2_MASK, PseudoVSEXT_VF8_M2, 0x2 }, // 2719 { PseudoVSEXT_VF8_M4_MASK, PseudoVSEXT_VF8_M4, 0x2 }, // 2720 { PseudoVSEXT_VF8_M8_MASK, PseudoVSEXT_VF8_M8, 0x2 }, // 2721 { PseudoVSLIDE1DOWN_VX_M1_MASK, PseudoVSLIDE1DOWN_VX_M1, 0x3 }, // 2722 { PseudoVSLIDE1DOWN_VX_M2_MASK, PseudoVSLIDE1DOWN_VX_M2, 0x3 }, // 2723 { PseudoVSLIDE1DOWN_VX_M4_MASK, PseudoVSLIDE1DOWN_VX_M4, 0x3 }, // 2724 { PseudoVSLIDE1DOWN_VX_M8_MASK, PseudoVSLIDE1DOWN_VX_M8, 0x3 }, // 2725 { PseudoVSLIDE1DOWN_VX_MF2_MASK, PseudoVSLIDE1DOWN_VX_MF2, 0x3 }, // 2726 { PseudoVSLIDE1DOWN_VX_MF4_MASK, PseudoVSLIDE1DOWN_VX_MF4, 0x3 }, // 2727 { PseudoVSLIDE1DOWN_VX_MF8_MASK, PseudoVSLIDE1DOWN_VX_MF8, 0x3 }, // 2728 { PseudoVSLIDE1UP_VX_M1_MASK, PseudoVSLIDE1UP_VX_M1, 0x3 }, // 2729 { PseudoVSLIDE1UP_VX_M2_MASK, PseudoVSLIDE1UP_VX_M2, 0x3 }, // 2730 { PseudoVSLIDE1UP_VX_M4_MASK, PseudoVSLIDE1UP_VX_M4, 0x3 }, // 2731 { PseudoVSLIDE1UP_VX_M8_MASK, PseudoVSLIDE1UP_VX_M8, 0x3 }, // 2732 { PseudoVSLIDE1UP_VX_MF2_MASK, PseudoVSLIDE1UP_VX_MF2, 0x3 }, // 2733 { PseudoVSLIDE1UP_VX_MF4_MASK, PseudoVSLIDE1UP_VX_MF4, 0x3 }, // 2734 { PseudoVSLIDE1UP_VX_MF8_MASK, PseudoVSLIDE1UP_VX_MF8, 0x3 }, // 2735 { PseudoVSLIDEDOWN_VI_M1_MASK, PseudoVSLIDEDOWN_VI_M1, 0x3 }, // 2736 { PseudoVSLIDEDOWN_VI_M2_MASK, PseudoVSLIDEDOWN_VI_M2, 0x3 }, // 2737 { PseudoVSLIDEDOWN_VI_M4_MASK, PseudoVSLIDEDOWN_VI_M4, 0x3 }, // 2738 { PseudoVSLIDEDOWN_VI_M8_MASK, PseudoVSLIDEDOWN_VI_M8, 0x3 }, // 2739 { PseudoVSLIDEDOWN_VI_MF2_MASK, PseudoVSLIDEDOWN_VI_MF2, 0x3 }, // 2740 { PseudoVSLIDEDOWN_VI_MF4_MASK, PseudoVSLIDEDOWN_VI_MF4, 0x3 }, // 2741 { PseudoVSLIDEDOWN_VI_MF8_MASK, PseudoVSLIDEDOWN_VI_MF8, 0x3 }, // 2742 { PseudoVSLIDEDOWN_VX_M1_MASK, PseudoVSLIDEDOWN_VX_M1, 0x3 }, // 2743 { PseudoVSLIDEDOWN_VX_M2_MASK, PseudoVSLIDEDOWN_VX_M2, 0x3 }, // 2744 { PseudoVSLIDEDOWN_VX_M4_MASK, PseudoVSLIDEDOWN_VX_M4, 0x3 }, // 2745 { PseudoVSLIDEDOWN_VX_M8_MASK, PseudoVSLIDEDOWN_VX_M8, 0x3 }, // 2746 { PseudoVSLIDEDOWN_VX_MF2_MASK, PseudoVSLIDEDOWN_VX_MF2, 0x3 }, // 2747 { PseudoVSLIDEDOWN_VX_MF4_MASK, PseudoVSLIDEDOWN_VX_MF4, 0x3 }, // 2748 { PseudoVSLIDEDOWN_VX_MF8_MASK, PseudoVSLIDEDOWN_VX_MF8, 0x3 }, // 2749 { PseudoVSLIDEUP_VI_M1_MASK, PseudoVSLIDEUP_VI_M1, 0x3 }, // 2750 { PseudoVSLIDEUP_VI_M2_MASK, PseudoVSLIDEUP_VI_M2, 0x3 }, // 2751 { PseudoVSLIDEUP_VI_M4_MASK, PseudoVSLIDEUP_VI_M4, 0x3 }, // 2752 { PseudoVSLIDEUP_VI_M8_MASK, PseudoVSLIDEUP_VI_M8, 0x3 }, // 2753 { PseudoVSLIDEUP_VI_MF2_MASK, PseudoVSLIDEUP_VI_MF2, 0x3 }, // 2754 { PseudoVSLIDEUP_VI_MF4_MASK, PseudoVSLIDEUP_VI_MF4, 0x3 }, // 2755 { PseudoVSLIDEUP_VI_MF8_MASK, PseudoVSLIDEUP_VI_MF8, 0x3 }, // 2756 { PseudoVSLIDEUP_VX_M1_MASK, PseudoVSLIDEUP_VX_M1, 0x3 }, // 2757 { PseudoVSLIDEUP_VX_M2_MASK, PseudoVSLIDEUP_VX_M2, 0x3 }, // 2758 { PseudoVSLIDEUP_VX_M4_MASK, PseudoVSLIDEUP_VX_M4, 0x3 }, // 2759 { PseudoVSLIDEUP_VX_M8_MASK, PseudoVSLIDEUP_VX_M8, 0x3 }, // 2760 { PseudoVSLIDEUP_VX_MF2_MASK, PseudoVSLIDEUP_VX_MF2, 0x3 }, // 2761 { PseudoVSLIDEUP_VX_MF4_MASK, PseudoVSLIDEUP_VX_MF4, 0x3 }, // 2762 { PseudoVSLIDEUP_VX_MF8_MASK, PseudoVSLIDEUP_VX_MF8, 0x3 }, // 2763 { PseudoVSLL_VI_M1_MASK, PseudoVSLL_VI_M1, 0x3 }, // 2764 { PseudoVSLL_VI_M2_MASK, PseudoVSLL_VI_M2, 0x3 }, // 2765 { PseudoVSLL_VI_M4_MASK, PseudoVSLL_VI_M4, 0x3 }, // 2766 { PseudoVSLL_VI_M8_MASK, PseudoVSLL_VI_M8, 0x3 }, // 2767 { PseudoVSLL_VI_MF2_MASK, PseudoVSLL_VI_MF2, 0x3 }, // 2768 { PseudoVSLL_VI_MF4_MASK, PseudoVSLL_VI_MF4, 0x3 }, // 2769 { PseudoVSLL_VI_MF8_MASK, PseudoVSLL_VI_MF8, 0x3 }, // 2770 { PseudoVSLL_VV_M1_MASK, PseudoVSLL_VV_M1, 0x3 }, // 2771 { PseudoVSLL_VV_M2_MASK, PseudoVSLL_VV_M2, 0x3 }, // 2772 { PseudoVSLL_VV_M4_MASK, PseudoVSLL_VV_M4, 0x3 }, // 2773 { PseudoVSLL_VV_M8_MASK, PseudoVSLL_VV_M8, 0x3 }, // 2774 { PseudoVSLL_VV_MF2_MASK, PseudoVSLL_VV_MF2, 0x3 }, // 2775 { PseudoVSLL_VV_MF4_MASK, PseudoVSLL_VV_MF4, 0x3 }, // 2776 { PseudoVSLL_VV_MF8_MASK, PseudoVSLL_VV_MF8, 0x3 }, // 2777 { PseudoVSLL_VX_M1_MASK, PseudoVSLL_VX_M1, 0x3 }, // 2778 { PseudoVSLL_VX_M2_MASK, PseudoVSLL_VX_M2, 0x3 }, // 2779 { PseudoVSLL_VX_M4_MASK, PseudoVSLL_VX_M4, 0x3 }, // 2780 { PseudoVSLL_VX_M8_MASK, PseudoVSLL_VX_M8, 0x3 }, // 2781 { PseudoVSLL_VX_MF2_MASK, PseudoVSLL_VX_MF2, 0x3 }, // 2782 { PseudoVSLL_VX_MF4_MASK, PseudoVSLL_VX_MF4, 0x3 }, // 2783 { PseudoVSLL_VX_MF8_MASK, PseudoVSLL_VX_MF8, 0x3 }, // 2784 { PseudoVSMUL_VV_M1_MASK, PseudoVSMUL_VV_M1, 0x3 }, // 2785 { PseudoVSMUL_VV_M2_MASK, PseudoVSMUL_VV_M2, 0x3 }, // 2786 { PseudoVSMUL_VV_M4_MASK, PseudoVSMUL_VV_M4, 0x3 }, // 2787 { PseudoVSMUL_VV_M8_MASK, PseudoVSMUL_VV_M8, 0x3 }, // 2788 { PseudoVSMUL_VV_MF2_MASK, PseudoVSMUL_VV_MF2, 0x3 }, // 2789 { PseudoVSMUL_VV_MF4_MASK, PseudoVSMUL_VV_MF4, 0x3 }, // 2790 { PseudoVSMUL_VV_MF8_MASK, PseudoVSMUL_VV_MF8, 0x3 }, // 2791 { PseudoVSMUL_VX_M1_MASK, PseudoVSMUL_VX_M1, 0x3 }, // 2792 { PseudoVSMUL_VX_M2_MASK, PseudoVSMUL_VX_M2, 0x3 }, // 2793 { PseudoVSMUL_VX_M4_MASK, PseudoVSMUL_VX_M4, 0x3 }, // 2794 { PseudoVSMUL_VX_M8_MASK, PseudoVSMUL_VX_M8, 0x3 }, // 2795 { PseudoVSMUL_VX_MF2_MASK, PseudoVSMUL_VX_MF2, 0x3 }, // 2796 { PseudoVSMUL_VX_MF4_MASK, PseudoVSMUL_VX_MF4, 0x3 }, // 2797 { PseudoVSMUL_VX_MF8_MASK, PseudoVSMUL_VX_MF8, 0x3 }, // 2798 { PseudoVSRA_VI_M1_MASK, PseudoVSRA_VI_M1, 0x3 }, // 2799 { PseudoVSRA_VI_M2_MASK, PseudoVSRA_VI_M2, 0x3 }, // 2800 { PseudoVSRA_VI_M4_MASK, PseudoVSRA_VI_M4, 0x3 }, // 2801 { PseudoVSRA_VI_M8_MASK, PseudoVSRA_VI_M8, 0x3 }, // 2802 { PseudoVSRA_VI_MF2_MASK, PseudoVSRA_VI_MF2, 0x3 }, // 2803 { PseudoVSRA_VI_MF4_MASK, PseudoVSRA_VI_MF4, 0x3 }, // 2804 { PseudoVSRA_VI_MF8_MASK, PseudoVSRA_VI_MF8, 0x3 }, // 2805 { PseudoVSRA_VV_M1_MASK, PseudoVSRA_VV_M1, 0x3 }, // 2806 { PseudoVSRA_VV_M2_MASK, PseudoVSRA_VV_M2, 0x3 }, // 2807 { PseudoVSRA_VV_M4_MASK, PseudoVSRA_VV_M4, 0x3 }, // 2808 { PseudoVSRA_VV_M8_MASK, PseudoVSRA_VV_M8, 0x3 }, // 2809 { PseudoVSRA_VV_MF2_MASK, PseudoVSRA_VV_MF2, 0x3 }, // 2810 { PseudoVSRA_VV_MF4_MASK, PseudoVSRA_VV_MF4, 0x3 }, // 2811 { PseudoVSRA_VV_MF8_MASK, PseudoVSRA_VV_MF8, 0x3 }, // 2812 { PseudoVSRA_VX_M1_MASK, PseudoVSRA_VX_M1, 0x3 }, // 2813 { PseudoVSRA_VX_M2_MASK, PseudoVSRA_VX_M2, 0x3 }, // 2814 { PseudoVSRA_VX_M4_MASK, PseudoVSRA_VX_M4, 0x3 }, // 2815 { PseudoVSRA_VX_M8_MASK, PseudoVSRA_VX_M8, 0x3 }, // 2816 { PseudoVSRA_VX_MF2_MASK, PseudoVSRA_VX_MF2, 0x3 }, // 2817 { PseudoVSRA_VX_MF4_MASK, PseudoVSRA_VX_MF4, 0x3 }, // 2818 { PseudoVSRA_VX_MF8_MASK, PseudoVSRA_VX_MF8, 0x3 }, // 2819 { PseudoVSRL_VI_M1_MASK, PseudoVSRL_VI_M1, 0x3 }, // 2820 { PseudoVSRL_VI_M2_MASK, PseudoVSRL_VI_M2, 0x3 }, // 2821 { PseudoVSRL_VI_M4_MASK, PseudoVSRL_VI_M4, 0x3 }, // 2822 { PseudoVSRL_VI_M8_MASK, PseudoVSRL_VI_M8, 0x3 }, // 2823 { PseudoVSRL_VI_MF2_MASK, PseudoVSRL_VI_MF2, 0x3 }, // 2824 { PseudoVSRL_VI_MF4_MASK, PseudoVSRL_VI_MF4, 0x3 }, // 2825 { PseudoVSRL_VI_MF8_MASK, PseudoVSRL_VI_MF8, 0x3 }, // 2826 { PseudoVSRL_VV_M1_MASK, PseudoVSRL_VV_M1, 0x3 }, // 2827 { PseudoVSRL_VV_M2_MASK, PseudoVSRL_VV_M2, 0x3 }, // 2828 { PseudoVSRL_VV_M4_MASK, PseudoVSRL_VV_M4, 0x3 }, // 2829 { PseudoVSRL_VV_M8_MASK, PseudoVSRL_VV_M8, 0x3 }, // 2830 { PseudoVSRL_VV_MF2_MASK, PseudoVSRL_VV_MF2, 0x3 }, // 2831 { PseudoVSRL_VV_MF4_MASK, PseudoVSRL_VV_MF4, 0x3 }, // 2832 { PseudoVSRL_VV_MF8_MASK, PseudoVSRL_VV_MF8, 0x3 }, // 2833 { PseudoVSRL_VX_M1_MASK, PseudoVSRL_VX_M1, 0x3 }, // 2834 { PseudoVSRL_VX_M2_MASK, PseudoVSRL_VX_M2, 0x3 }, // 2835 { PseudoVSRL_VX_M4_MASK, PseudoVSRL_VX_M4, 0x3 }, // 2836 { PseudoVSRL_VX_M8_MASK, PseudoVSRL_VX_M8, 0x3 }, // 2837 { PseudoVSRL_VX_MF2_MASK, PseudoVSRL_VX_MF2, 0x3 }, // 2838 { PseudoVSRL_VX_MF4_MASK, PseudoVSRL_VX_MF4, 0x3 }, // 2839 { PseudoVSRL_VX_MF8_MASK, PseudoVSRL_VX_MF8, 0x3 }, // 2840 { PseudoVSSRA_VI_M1_MASK, PseudoVSSRA_VI_M1, 0x3 }, // 2841 { PseudoVSSRA_VI_M2_MASK, PseudoVSSRA_VI_M2, 0x3 }, // 2842 { PseudoVSSRA_VI_M4_MASK, PseudoVSSRA_VI_M4, 0x3 }, // 2843 { PseudoVSSRA_VI_M8_MASK, PseudoVSSRA_VI_M8, 0x3 }, // 2844 { PseudoVSSRA_VI_MF2_MASK, PseudoVSSRA_VI_MF2, 0x3 }, // 2845 { PseudoVSSRA_VI_MF4_MASK, PseudoVSSRA_VI_MF4, 0x3 }, // 2846 { PseudoVSSRA_VI_MF8_MASK, PseudoVSSRA_VI_MF8, 0x3 }, // 2847 { PseudoVSSRA_VV_M1_MASK, PseudoVSSRA_VV_M1, 0x3 }, // 2848 { PseudoVSSRA_VV_M2_MASK, PseudoVSSRA_VV_M2, 0x3 }, // 2849 { PseudoVSSRA_VV_M4_MASK, PseudoVSSRA_VV_M4, 0x3 }, // 2850 { PseudoVSSRA_VV_M8_MASK, PseudoVSSRA_VV_M8, 0x3 }, // 2851 { PseudoVSSRA_VV_MF2_MASK, PseudoVSSRA_VV_MF2, 0x3 }, // 2852 { PseudoVSSRA_VV_MF4_MASK, PseudoVSSRA_VV_MF4, 0x3 }, // 2853 { PseudoVSSRA_VV_MF8_MASK, PseudoVSSRA_VV_MF8, 0x3 }, // 2854 { PseudoVSSRA_VX_M1_MASK, PseudoVSSRA_VX_M1, 0x3 }, // 2855 { PseudoVSSRA_VX_M2_MASK, PseudoVSSRA_VX_M2, 0x3 }, // 2856 { PseudoVSSRA_VX_M4_MASK, PseudoVSSRA_VX_M4, 0x3 }, // 2857 { PseudoVSSRA_VX_M8_MASK, PseudoVSSRA_VX_M8, 0x3 }, // 2858 { PseudoVSSRA_VX_MF2_MASK, PseudoVSSRA_VX_MF2, 0x3 }, // 2859 { PseudoVSSRA_VX_MF4_MASK, PseudoVSSRA_VX_MF4, 0x3 }, // 2860 { PseudoVSSRA_VX_MF8_MASK, PseudoVSSRA_VX_MF8, 0x3 }, // 2861 { PseudoVSSRL_VI_M1_MASK, PseudoVSSRL_VI_M1, 0x3 }, // 2862 { PseudoVSSRL_VI_M2_MASK, PseudoVSSRL_VI_M2, 0x3 }, // 2863 { PseudoVSSRL_VI_M4_MASK, PseudoVSSRL_VI_M4, 0x3 }, // 2864 { PseudoVSSRL_VI_M8_MASK, PseudoVSSRL_VI_M8, 0x3 }, // 2865 { PseudoVSSRL_VI_MF2_MASK, PseudoVSSRL_VI_MF2, 0x3 }, // 2866 { PseudoVSSRL_VI_MF4_MASK, PseudoVSSRL_VI_MF4, 0x3 }, // 2867 { PseudoVSSRL_VI_MF8_MASK, PseudoVSSRL_VI_MF8, 0x3 }, // 2868 { PseudoVSSRL_VV_M1_MASK, PseudoVSSRL_VV_M1, 0x3 }, // 2869 { PseudoVSSRL_VV_M2_MASK, PseudoVSSRL_VV_M2, 0x3 }, // 2870 { PseudoVSSRL_VV_M4_MASK, PseudoVSSRL_VV_M4, 0x3 }, // 2871 { PseudoVSSRL_VV_M8_MASK, PseudoVSSRL_VV_M8, 0x3 }, // 2872 { PseudoVSSRL_VV_MF2_MASK, PseudoVSSRL_VV_MF2, 0x3 }, // 2873 { PseudoVSSRL_VV_MF4_MASK, PseudoVSSRL_VV_MF4, 0x3 }, // 2874 { PseudoVSSRL_VV_MF8_MASK, PseudoVSSRL_VV_MF8, 0x3 }, // 2875 { PseudoVSSRL_VX_M1_MASK, PseudoVSSRL_VX_M1, 0x3 }, // 2876 { PseudoVSSRL_VX_M2_MASK, PseudoVSSRL_VX_M2, 0x3 }, // 2877 { PseudoVSSRL_VX_M4_MASK, PseudoVSSRL_VX_M4, 0x3 }, // 2878 { PseudoVSSRL_VX_M8_MASK, PseudoVSSRL_VX_M8, 0x3 }, // 2879 { PseudoVSSRL_VX_MF2_MASK, PseudoVSSRL_VX_MF2, 0x3 }, // 2880 { PseudoVSSRL_VX_MF4_MASK, PseudoVSSRL_VX_MF4, 0x3 }, // 2881 { PseudoVSSRL_VX_MF8_MASK, PseudoVSSRL_VX_MF8, 0x3 }, // 2882 { PseudoVSSUBU_VV_M1_MASK, PseudoVSSUBU_VV_M1, 0x3 }, // 2883 { PseudoVSSUBU_VV_M2_MASK, PseudoVSSUBU_VV_M2, 0x3 }, // 2884 { PseudoVSSUBU_VV_M4_MASK, PseudoVSSUBU_VV_M4, 0x3 }, // 2885 { PseudoVSSUBU_VV_M8_MASK, PseudoVSSUBU_VV_M8, 0x3 }, // 2886 { PseudoVSSUBU_VV_MF2_MASK, PseudoVSSUBU_VV_MF2, 0x3 }, // 2887 { PseudoVSSUBU_VV_MF4_MASK, PseudoVSSUBU_VV_MF4, 0x3 }, // 2888 { PseudoVSSUBU_VV_MF8_MASK, PseudoVSSUBU_VV_MF8, 0x3 }, // 2889 { PseudoVSSUBU_VX_M1_MASK, PseudoVSSUBU_VX_M1, 0x3 }, // 2890 { PseudoVSSUBU_VX_M2_MASK, PseudoVSSUBU_VX_M2, 0x3 }, // 2891 { PseudoVSSUBU_VX_M4_MASK, PseudoVSSUBU_VX_M4, 0x3 }, // 2892 { PseudoVSSUBU_VX_M8_MASK, PseudoVSSUBU_VX_M8, 0x3 }, // 2893 { PseudoVSSUBU_VX_MF2_MASK, PseudoVSSUBU_VX_MF2, 0x3 }, // 2894 { PseudoVSSUBU_VX_MF4_MASK, PseudoVSSUBU_VX_MF4, 0x3 }, // 2895 { PseudoVSSUBU_VX_MF8_MASK, PseudoVSSUBU_VX_MF8, 0x3 }, // 2896 { PseudoVSSUB_VV_M1_MASK, PseudoVSSUB_VV_M1, 0x3 }, // 2897 { PseudoVSSUB_VV_M2_MASK, PseudoVSSUB_VV_M2, 0x3 }, // 2898 { PseudoVSSUB_VV_M4_MASK, PseudoVSSUB_VV_M4, 0x3 }, // 2899 { PseudoVSSUB_VV_M8_MASK, PseudoVSSUB_VV_M8, 0x3 }, // 2900 { PseudoVSSUB_VV_MF2_MASK, PseudoVSSUB_VV_MF2, 0x3 }, // 2901 { PseudoVSSUB_VV_MF4_MASK, PseudoVSSUB_VV_MF4, 0x3 }, // 2902 { PseudoVSSUB_VV_MF8_MASK, PseudoVSSUB_VV_MF8, 0x3 }, // 2903 { PseudoVSSUB_VX_M1_MASK, PseudoVSSUB_VX_M1, 0x3 }, // 2904 { PseudoVSSUB_VX_M2_MASK, PseudoVSSUB_VX_M2, 0x3 }, // 2905 { PseudoVSSUB_VX_M4_MASK, PseudoVSSUB_VX_M4, 0x3 }, // 2906 { PseudoVSSUB_VX_M8_MASK, PseudoVSSUB_VX_M8, 0x3 }, // 2907 { PseudoVSSUB_VX_MF2_MASK, PseudoVSSUB_VX_MF2, 0x3 }, // 2908 { PseudoVSSUB_VX_MF4_MASK, PseudoVSSUB_VX_MF4, 0x3 }, // 2909 { PseudoVSSUB_VX_MF8_MASK, PseudoVSSUB_VX_MF8, 0x3 }, // 2910 { PseudoVSUB_VV_M1_MASK, PseudoVSUB_VV_M1, 0x3 }, // 2911 { PseudoVSUB_VV_M2_MASK, PseudoVSUB_VV_M2, 0x3 }, // 2912 { PseudoVSUB_VV_M4_MASK, PseudoVSUB_VV_M4, 0x3 }, // 2913 { PseudoVSUB_VV_M8_MASK, PseudoVSUB_VV_M8, 0x3 }, // 2914 { PseudoVSUB_VV_MF2_MASK, PseudoVSUB_VV_MF2, 0x3 }, // 2915 { PseudoVSUB_VV_MF4_MASK, PseudoVSUB_VV_MF4, 0x3 }, // 2916 { PseudoVSUB_VV_MF8_MASK, PseudoVSUB_VV_MF8, 0x3 }, // 2917 { PseudoVSUB_VX_M1_MASK, PseudoVSUB_VX_M1, 0x3 }, // 2918 { PseudoVSUB_VX_M2_MASK, PseudoVSUB_VX_M2, 0x3 }, // 2919 { PseudoVSUB_VX_M4_MASK, PseudoVSUB_VX_M4, 0x3 }, // 2920 { PseudoVSUB_VX_M8_MASK, PseudoVSUB_VX_M8, 0x3 }, // 2921 { PseudoVSUB_VX_MF2_MASK, PseudoVSUB_VX_MF2, 0x3 }, // 2922 { PseudoVSUB_VX_MF4_MASK, PseudoVSUB_VX_MF4, 0x3 }, // 2923 { PseudoVSUB_VX_MF8_MASK, PseudoVSUB_VX_MF8, 0x3 }, // 2924 { PseudoVWADDU_VV_M1_MASK, PseudoVWADDU_VV_M1, 0x3 }, // 2925 { PseudoVWADDU_VV_M2_MASK, PseudoVWADDU_VV_M2, 0x3 }, // 2926 { PseudoVWADDU_VV_M4_MASK, PseudoVWADDU_VV_M4, 0x3 }, // 2927 { PseudoVWADDU_VV_MF2_MASK, PseudoVWADDU_VV_MF2, 0x3 }, // 2928 { PseudoVWADDU_VV_MF4_MASK, PseudoVWADDU_VV_MF4, 0x3 }, // 2929 { PseudoVWADDU_VV_MF8_MASK, PseudoVWADDU_VV_MF8, 0x3 }, // 2930 { PseudoVWADDU_VX_M1_MASK, PseudoVWADDU_VX_M1, 0x3 }, // 2931 { PseudoVWADDU_VX_M2_MASK, PseudoVWADDU_VX_M2, 0x3 }, // 2932 { PseudoVWADDU_VX_M4_MASK, PseudoVWADDU_VX_M4, 0x3 }, // 2933 { PseudoVWADDU_VX_MF2_MASK, PseudoVWADDU_VX_MF2, 0x3 }, // 2934 { PseudoVWADDU_VX_MF4_MASK, PseudoVWADDU_VX_MF4, 0x3 }, // 2935 { PseudoVWADDU_VX_MF8_MASK, PseudoVWADDU_VX_MF8, 0x3 }, // 2936 { PseudoVWADDU_WV_M1_MASK, PseudoVWADDU_WV_M1, 0x3 }, // 2937 { PseudoVWADDU_WV_M1_MASK_TIED, PseudoVWADDU_WV_M1_TIED, 0x2 }, // 2938 { PseudoVWADDU_WV_M2_MASK, PseudoVWADDU_WV_M2, 0x3 }, // 2939 { PseudoVWADDU_WV_M2_MASK_TIED, PseudoVWADDU_WV_M2_TIED, 0x2 }, // 2940 { PseudoVWADDU_WV_M4_MASK, PseudoVWADDU_WV_M4, 0x3 }, // 2941 { PseudoVWADDU_WV_M4_MASK_TIED, PseudoVWADDU_WV_M4_TIED, 0x2 }, // 2942 { PseudoVWADDU_WV_MF2_MASK, PseudoVWADDU_WV_MF2, 0x3 }, // 2943 { PseudoVWADDU_WV_MF2_MASK_TIED, PseudoVWADDU_WV_MF2_TIED, 0x2 }, // 2944 { PseudoVWADDU_WV_MF4_MASK, PseudoVWADDU_WV_MF4, 0x3 }, // 2945 { PseudoVWADDU_WV_MF4_MASK_TIED, PseudoVWADDU_WV_MF4_TIED, 0x2 }, // 2946 { PseudoVWADDU_WV_MF8_MASK, PseudoVWADDU_WV_MF8, 0x3 }, // 2947 { PseudoVWADDU_WV_MF8_MASK_TIED, PseudoVWADDU_WV_MF8_TIED, 0x2 }, // 2948 { PseudoVWADDU_WX_M1_MASK, PseudoVWADDU_WX_M1, 0x3 }, // 2949 { PseudoVWADDU_WX_M2_MASK, PseudoVWADDU_WX_M2, 0x3 }, // 2950 { PseudoVWADDU_WX_M4_MASK, PseudoVWADDU_WX_M4, 0x3 }, // 2951 { PseudoVWADDU_WX_MF2_MASK, PseudoVWADDU_WX_MF2, 0x3 }, // 2952 { PseudoVWADDU_WX_MF4_MASK, PseudoVWADDU_WX_MF4, 0x3 }, // 2953 { PseudoVWADDU_WX_MF8_MASK, PseudoVWADDU_WX_MF8, 0x3 }, // 2954 { PseudoVWADD_VV_M1_MASK, PseudoVWADD_VV_M1, 0x3 }, // 2955 { PseudoVWADD_VV_M2_MASK, PseudoVWADD_VV_M2, 0x3 }, // 2956 { PseudoVWADD_VV_M4_MASK, PseudoVWADD_VV_M4, 0x3 }, // 2957 { PseudoVWADD_VV_MF2_MASK, PseudoVWADD_VV_MF2, 0x3 }, // 2958 { PseudoVWADD_VV_MF4_MASK, PseudoVWADD_VV_MF4, 0x3 }, // 2959 { PseudoVWADD_VV_MF8_MASK, PseudoVWADD_VV_MF8, 0x3 }, // 2960 { PseudoVWADD_VX_M1_MASK, PseudoVWADD_VX_M1, 0x3 }, // 2961 { PseudoVWADD_VX_M2_MASK, PseudoVWADD_VX_M2, 0x3 }, // 2962 { PseudoVWADD_VX_M4_MASK, PseudoVWADD_VX_M4, 0x3 }, // 2963 { PseudoVWADD_VX_MF2_MASK, PseudoVWADD_VX_MF2, 0x3 }, // 2964 { PseudoVWADD_VX_MF4_MASK, PseudoVWADD_VX_MF4, 0x3 }, // 2965 { PseudoVWADD_VX_MF8_MASK, PseudoVWADD_VX_MF8, 0x3 }, // 2966 { PseudoVWADD_WV_M1_MASK, PseudoVWADD_WV_M1, 0x3 }, // 2967 { PseudoVWADD_WV_M1_MASK_TIED, PseudoVWADD_WV_M1_TIED, 0x2 }, // 2968 { PseudoVWADD_WV_M2_MASK, PseudoVWADD_WV_M2, 0x3 }, // 2969 { PseudoVWADD_WV_M2_MASK_TIED, PseudoVWADD_WV_M2_TIED, 0x2 }, // 2970 { PseudoVWADD_WV_M4_MASK, PseudoVWADD_WV_M4, 0x3 }, // 2971 { PseudoVWADD_WV_M4_MASK_TIED, PseudoVWADD_WV_M4_TIED, 0x2 }, // 2972 { PseudoVWADD_WV_MF2_MASK, PseudoVWADD_WV_MF2, 0x3 }, // 2973 { PseudoVWADD_WV_MF2_MASK_TIED, PseudoVWADD_WV_MF2_TIED, 0x2 }, // 2974 { PseudoVWADD_WV_MF4_MASK, PseudoVWADD_WV_MF4, 0x3 }, // 2975 { PseudoVWADD_WV_MF4_MASK_TIED, PseudoVWADD_WV_MF4_TIED, 0x2 }, // 2976 { PseudoVWADD_WV_MF8_MASK, PseudoVWADD_WV_MF8, 0x3 }, // 2977 { PseudoVWADD_WV_MF8_MASK_TIED, PseudoVWADD_WV_MF8_TIED, 0x2 }, // 2978 { PseudoVWADD_WX_M1_MASK, PseudoVWADD_WX_M1, 0x3 }, // 2979 { PseudoVWADD_WX_M2_MASK, PseudoVWADD_WX_M2, 0x3 }, // 2980 { PseudoVWADD_WX_M4_MASK, PseudoVWADD_WX_M4, 0x3 }, // 2981 { PseudoVWADD_WX_MF2_MASK, PseudoVWADD_WX_MF2, 0x3 }, // 2982 { PseudoVWADD_WX_MF4_MASK, PseudoVWADD_WX_MF4, 0x3 }, // 2983 { PseudoVWADD_WX_MF8_MASK, PseudoVWADD_WX_MF8, 0x3 }, // 2984 { PseudoVWMACCSU_VV_M1_MASK, PseudoVWMACCSU_VV_M1, 0x3 }, // 2985 { PseudoVWMACCSU_VV_M2_MASK, PseudoVWMACCSU_VV_M2, 0x3 }, // 2986 { PseudoVWMACCSU_VV_M4_MASK, PseudoVWMACCSU_VV_M4, 0x3 }, // 2987 { PseudoVWMACCSU_VV_MF2_MASK, PseudoVWMACCSU_VV_MF2, 0x3 }, // 2988 { PseudoVWMACCSU_VV_MF4_MASK, PseudoVWMACCSU_VV_MF4, 0x3 }, // 2989 { PseudoVWMACCSU_VV_MF8_MASK, PseudoVWMACCSU_VV_MF8, 0x3 }, // 2990 { PseudoVWMACCSU_VX_M1_MASK, PseudoVWMACCSU_VX_M1, 0x3 }, // 2991 { PseudoVWMACCSU_VX_M2_MASK, PseudoVWMACCSU_VX_M2, 0x3 }, // 2992 { PseudoVWMACCSU_VX_M4_MASK, PseudoVWMACCSU_VX_M4, 0x3 }, // 2993 { PseudoVWMACCSU_VX_MF2_MASK, PseudoVWMACCSU_VX_MF2, 0x3 }, // 2994 { PseudoVWMACCSU_VX_MF4_MASK, PseudoVWMACCSU_VX_MF4, 0x3 }, // 2995 { PseudoVWMACCSU_VX_MF8_MASK, PseudoVWMACCSU_VX_MF8, 0x3 }, // 2996 { PseudoVWMACCUS_VX_M1_MASK, PseudoVWMACCUS_VX_M1, 0x3 }, // 2997 { PseudoVWMACCUS_VX_M2_MASK, PseudoVWMACCUS_VX_M2, 0x3 }, // 2998 { PseudoVWMACCUS_VX_M4_MASK, PseudoVWMACCUS_VX_M4, 0x3 }, // 2999 { PseudoVWMACCUS_VX_MF2_MASK, PseudoVWMACCUS_VX_MF2, 0x3 }, // 3000 { PseudoVWMACCUS_VX_MF4_MASK, PseudoVWMACCUS_VX_MF4, 0x3 }, // 3001 { PseudoVWMACCUS_VX_MF8_MASK, PseudoVWMACCUS_VX_MF8, 0x3 }, // 3002 { PseudoVWMACCU_VV_M1_MASK, PseudoVWMACCU_VV_M1, 0x3 }, // 3003 { PseudoVWMACCU_VV_M2_MASK, PseudoVWMACCU_VV_M2, 0x3 }, // 3004 { PseudoVWMACCU_VV_M4_MASK, PseudoVWMACCU_VV_M4, 0x3 }, // 3005 { PseudoVWMACCU_VV_MF2_MASK, PseudoVWMACCU_VV_MF2, 0x3 }, // 3006 { PseudoVWMACCU_VV_MF4_MASK, PseudoVWMACCU_VV_MF4, 0x3 }, // 3007 { PseudoVWMACCU_VV_MF8_MASK, PseudoVWMACCU_VV_MF8, 0x3 }, // 3008 { PseudoVWMACCU_VX_M1_MASK, PseudoVWMACCU_VX_M1, 0x3 }, // 3009 { PseudoVWMACCU_VX_M2_MASK, PseudoVWMACCU_VX_M2, 0x3 }, // 3010 { PseudoVWMACCU_VX_M4_MASK, PseudoVWMACCU_VX_M4, 0x3 }, // 3011 { PseudoVWMACCU_VX_MF2_MASK, PseudoVWMACCU_VX_MF2, 0x3 }, // 3012 { PseudoVWMACCU_VX_MF4_MASK, PseudoVWMACCU_VX_MF4, 0x3 }, // 3013 { PseudoVWMACCU_VX_MF8_MASK, PseudoVWMACCU_VX_MF8, 0x3 }, // 3014 { PseudoVWMACC_VV_M1_MASK, PseudoVWMACC_VV_M1, 0x3 }, // 3015 { PseudoVWMACC_VV_M2_MASK, PseudoVWMACC_VV_M2, 0x3 }, // 3016 { PseudoVWMACC_VV_M4_MASK, PseudoVWMACC_VV_M4, 0x3 }, // 3017 { PseudoVWMACC_VV_MF2_MASK, PseudoVWMACC_VV_MF2, 0x3 }, // 3018 { PseudoVWMACC_VV_MF4_MASK, PseudoVWMACC_VV_MF4, 0x3 }, // 3019 { PseudoVWMACC_VV_MF8_MASK, PseudoVWMACC_VV_MF8, 0x3 }, // 3020 { PseudoVWMACC_VX_M1_MASK, PseudoVWMACC_VX_M1, 0x3 }, // 3021 { PseudoVWMACC_VX_M2_MASK, PseudoVWMACC_VX_M2, 0x3 }, // 3022 { PseudoVWMACC_VX_M4_MASK, PseudoVWMACC_VX_M4, 0x3 }, // 3023 { PseudoVWMACC_VX_MF2_MASK, PseudoVWMACC_VX_MF2, 0x3 }, // 3024 { PseudoVWMACC_VX_MF4_MASK, PseudoVWMACC_VX_MF4, 0x3 }, // 3025 { PseudoVWMACC_VX_MF8_MASK, PseudoVWMACC_VX_MF8, 0x3 }, // 3026 { PseudoVWMULSU_VV_M1_MASK, PseudoVWMULSU_VV_M1, 0x3 }, // 3027 { PseudoVWMULSU_VV_M2_MASK, PseudoVWMULSU_VV_M2, 0x3 }, // 3028 { PseudoVWMULSU_VV_M4_MASK, PseudoVWMULSU_VV_M4, 0x3 }, // 3029 { PseudoVWMULSU_VV_MF2_MASK, PseudoVWMULSU_VV_MF2, 0x3 }, // 3030 { PseudoVWMULSU_VV_MF4_MASK, PseudoVWMULSU_VV_MF4, 0x3 }, // 3031 { PseudoVWMULSU_VV_MF8_MASK, PseudoVWMULSU_VV_MF8, 0x3 }, // 3032 { PseudoVWMULSU_VX_M1_MASK, PseudoVWMULSU_VX_M1, 0x3 }, // 3033 { PseudoVWMULSU_VX_M2_MASK, PseudoVWMULSU_VX_M2, 0x3 }, // 3034 { PseudoVWMULSU_VX_M4_MASK, PseudoVWMULSU_VX_M4, 0x3 }, // 3035 { PseudoVWMULSU_VX_MF2_MASK, PseudoVWMULSU_VX_MF2, 0x3 }, // 3036 { PseudoVWMULSU_VX_MF4_MASK, PseudoVWMULSU_VX_MF4, 0x3 }, // 3037 { PseudoVWMULSU_VX_MF8_MASK, PseudoVWMULSU_VX_MF8, 0x3 }, // 3038 { PseudoVWMULU_VV_M1_MASK, PseudoVWMULU_VV_M1, 0x3 }, // 3039 { PseudoVWMULU_VV_M2_MASK, PseudoVWMULU_VV_M2, 0x3 }, // 3040 { PseudoVWMULU_VV_M4_MASK, PseudoVWMULU_VV_M4, 0x3 }, // 3041 { PseudoVWMULU_VV_MF2_MASK, PseudoVWMULU_VV_MF2, 0x3 }, // 3042 { PseudoVWMULU_VV_MF4_MASK, PseudoVWMULU_VV_MF4, 0x3 }, // 3043 { PseudoVWMULU_VV_MF8_MASK, PseudoVWMULU_VV_MF8, 0x3 }, // 3044 { PseudoVWMULU_VX_M1_MASK, PseudoVWMULU_VX_M1, 0x3 }, // 3045 { PseudoVWMULU_VX_M2_MASK, PseudoVWMULU_VX_M2, 0x3 }, // 3046 { PseudoVWMULU_VX_M4_MASK, PseudoVWMULU_VX_M4, 0x3 }, // 3047 { PseudoVWMULU_VX_MF2_MASK, PseudoVWMULU_VX_MF2, 0x3 }, // 3048 { PseudoVWMULU_VX_MF4_MASK, PseudoVWMULU_VX_MF4, 0x3 }, // 3049 { PseudoVWMULU_VX_MF8_MASK, PseudoVWMULU_VX_MF8, 0x3 }, // 3050 { PseudoVWMUL_VV_M1_MASK, PseudoVWMUL_VV_M1, 0x3 }, // 3051 { PseudoVWMUL_VV_M2_MASK, PseudoVWMUL_VV_M2, 0x3 }, // 3052 { PseudoVWMUL_VV_M4_MASK, PseudoVWMUL_VV_M4, 0x3 }, // 3053 { PseudoVWMUL_VV_MF2_MASK, PseudoVWMUL_VV_MF2, 0x3 }, // 3054 { PseudoVWMUL_VV_MF4_MASK, PseudoVWMUL_VV_MF4, 0x3 }, // 3055 { PseudoVWMUL_VV_MF8_MASK, PseudoVWMUL_VV_MF8, 0x3 }, // 3056 { PseudoVWMUL_VX_M1_MASK, PseudoVWMUL_VX_M1, 0x3 }, // 3057 { PseudoVWMUL_VX_M2_MASK, PseudoVWMUL_VX_M2, 0x3 }, // 3058 { PseudoVWMUL_VX_M4_MASK, PseudoVWMUL_VX_M4, 0x3 }, // 3059 { PseudoVWMUL_VX_MF2_MASK, PseudoVWMUL_VX_MF2, 0x3 }, // 3060 { PseudoVWMUL_VX_MF4_MASK, PseudoVWMUL_VX_MF4, 0x3 }, // 3061 { PseudoVWMUL_VX_MF8_MASK, PseudoVWMUL_VX_MF8, 0x3 }, // 3062 { PseudoVWREDSUMU_VS_M1_E16_MASK, PseudoVWREDSUMU_VS_M1_E16, 0x3 }, // 3063 { PseudoVWREDSUMU_VS_M1_E32_MASK, PseudoVWREDSUMU_VS_M1_E32, 0x3 }, // 3064 { PseudoVWREDSUMU_VS_M1_E8_MASK, PseudoVWREDSUMU_VS_M1_E8, 0x3 }, // 3065 { PseudoVWREDSUMU_VS_M2_E16_MASK, PseudoVWREDSUMU_VS_M2_E16, 0x3 }, // 3066 { PseudoVWREDSUMU_VS_M2_E32_MASK, PseudoVWREDSUMU_VS_M2_E32, 0x3 }, // 3067 { PseudoVWREDSUMU_VS_M2_E8_MASK, PseudoVWREDSUMU_VS_M2_E8, 0x3 }, // 3068 { PseudoVWREDSUMU_VS_M4_E16_MASK, PseudoVWREDSUMU_VS_M4_E16, 0x3 }, // 3069 { PseudoVWREDSUMU_VS_M4_E32_MASK, PseudoVWREDSUMU_VS_M4_E32, 0x3 }, // 3070 { PseudoVWREDSUMU_VS_M4_E8_MASK, PseudoVWREDSUMU_VS_M4_E8, 0x3 }, // 3071 { PseudoVWREDSUMU_VS_M8_E16_MASK, PseudoVWREDSUMU_VS_M8_E16, 0x3 }, // 3072 { PseudoVWREDSUMU_VS_M8_E32_MASK, PseudoVWREDSUMU_VS_M8_E32, 0x3 }, // 3073 { PseudoVWREDSUMU_VS_M8_E8_MASK, PseudoVWREDSUMU_VS_M8_E8, 0x3 }, // 3074 { PseudoVWREDSUMU_VS_MF2_E16_MASK, PseudoVWREDSUMU_VS_MF2_E16, 0x3 }, // 3075 { PseudoVWREDSUMU_VS_MF2_E32_MASK, PseudoVWREDSUMU_VS_MF2_E32, 0x3 }, // 3076 { PseudoVWREDSUMU_VS_MF2_E8_MASK, PseudoVWREDSUMU_VS_MF2_E8, 0x3 }, // 3077 { PseudoVWREDSUMU_VS_MF4_E16_MASK, PseudoVWREDSUMU_VS_MF4_E16, 0x3 }, // 3078 { PseudoVWREDSUMU_VS_MF4_E8_MASK, PseudoVWREDSUMU_VS_MF4_E8, 0x3 }, // 3079 { PseudoVWREDSUMU_VS_MF8_E8_MASK, PseudoVWREDSUMU_VS_MF8_E8, 0x3 }, // 3080 { PseudoVWREDSUM_VS_M1_E16_MASK, PseudoVWREDSUM_VS_M1_E16, 0x3 }, // 3081 { PseudoVWREDSUM_VS_M1_E32_MASK, PseudoVWREDSUM_VS_M1_E32, 0x3 }, // 3082 { PseudoVWREDSUM_VS_M1_E8_MASK, PseudoVWREDSUM_VS_M1_E8, 0x3 }, // 3083 { PseudoVWREDSUM_VS_M2_E16_MASK, PseudoVWREDSUM_VS_M2_E16, 0x3 }, // 3084 { PseudoVWREDSUM_VS_M2_E32_MASK, PseudoVWREDSUM_VS_M2_E32, 0x3 }, // 3085 { PseudoVWREDSUM_VS_M2_E8_MASK, PseudoVWREDSUM_VS_M2_E8, 0x3 }, // 3086 { PseudoVWREDSUM_VS_M4_E16_MASK, PseudoVWREDSUM_VS_M4_E16, 0x3 }, // 3087 { PseudoVWREDSUM_VS_M4_E32_MASK, PseudoVWREDSUM_VS_M4_E32, 0x3 }, // 3088 { PseudoVWREDSUM_VS_M4_E8_MASK, PseudoVWREDSUM_VS_M4_E8, 0x3 }, // 3089 { PseudoVWREDSUM_VS_M8_E16_MASK, PseudoVWREDSUM_VS_M8_E16, 0x3 }, // 3090 { PseudoVWREDSUM_VS_M8_E32_MASK, PseudoVWREDSUM_VS_M8_E32, 0x3 }, // 3091 { PseudoVWREDSUM_VS_M8_E8_MASK, PseudoVWREDSUM_VS_M8_E8, 0x3 }, // 3092 { PseudoVWREDSUM_VS_MF2_E16_MASK, PseudoVWREDSUM_VS_MF2_E16, 0x3 }, // 3093 { PseudoVWREDSUM_VS_MF2_E32_MASK, PseudoVWREDSUM_VS_MF2_E32, 0x3 }, // 3094 { PseudoVWREDSUM_VS_MF2_E8_MASK, PseudoVWREDSUM_VS_MF2_E8, 0x3 }, // 3095 { PseudoVWREDSUM_VS_MF4_E16_MASK, PseudoVWREDSUM_VS_MF4_E16, 0x3 }, // 3096 { PseudoVWREDSUM_VS_MF4_E8_MASK, PseudoVWREDSUM_VS_MF4_E8, 0x3 }, // 3097 { PseudoVWREDSUM_VS_MF8_E8_MASK, PseudoVWREDSUM_VS_MF8_E8, 0x3 }, // 3098 { PseudoVWSLL_VI_M1_MASK, PseudoVWSLL_VI_M1, 0x3 }, // 3099 { PseudoVWSLL_VI_M2_MASK, PseudoVWSLL_VI_M2, 0x3 }, // 3100 { PseudoVWSLL_VI_M4_MASK, PseudoVWSLL_VI_M4, 0x3 }, // 3101 { PseudoVWSLL_VI_MF2_MASK, PseudoVWSLL_VI_MF2, 0x3 }, // 3102 { PseudoVWSLL_VI_MF4_MASK, PseudoVWSLL_VI_MF4, 0x3 }, // 3103 { PseudoVWSLL_VI_MF8_MASK, PseudoVWSLL_VI_MF8, 0x3 }, // 3104 { PseudoVWSLL_VV_M1_MASK, PseudoVWSLL_VV_M1, 0x3 }, // 3105 { PseudoVWSLL_VV_M2_MASK, PseudoVWSLL_VV_M2, 0x3 }, // 3106 { PseudoVWSLL_VV_M4_MASK, PseudoVWSLL_VV_M4, 0x3 }, // 3107 { PseudoVWSLL_VV_MF2_MASK, PseudoVWSLL_VV_MF2, 0x3 }, // 3108 { PseudoVWSLL_VV_MF4_MASK, PseudoVWSLL_VV_MF4, 0x3 }, // 3109 { PseudoVWSLL_VV_MF8_MASK, PseudoVWSLL_VV_MF8, 0x3 }, // 3110 { PseudoVWSLL_VX_M1_MASK, PseudoVWSLL_VX_M1, 0x3 }, // 3111 { PseudoVWSLL_VX_M2_MASK, PseudoVWSLL_VX_M2, 0x3 }, // 3112 { PseudoVWSLL_VX_M4_MASK, PseudoVWSLL_VX_M4, 0x3 }, // 3113 { PseudoVWSLL_VX_MF2_MASK, PseudoVWSLL_VX_MF2, 0x3 }, // 3114 { PseudoVWSLL_VX_MF4_MASK, PseudoVWSLL_VX_MF4, 0x3 }, // 3115 { PseudoVWSLL_VX_MF8_MASK, PseudoVWSLL_VX_MF8, 0x3 }, // 3116 { PseudoVWSUBU_VV_M1_MASK, PseudoVWSUBU_VV_M1, 0x3 }, // 3117 { PseudoVWSUBU_VV_M2_MASK, PseudoVWSUBU_VV_M2, 0x3 }, // 3118 { PseudoVWSUBU_VV_M4_MASK, PseudoVWSUBU_VV_M4, 0x3 }, // 3119 { PseudoVWSUBU_VV_MF2_MASK, PseudoVWSUBU_VV_MF2, 0x3 }, // 3120 { PseudoVWSUBU_VV_MF4_MASK, PseudoVWSUBU_VV_MF4, 0x3 }, // 3121 { PseudoVWSUBU_VV_MF8_MASK, PseudoVWSUBU_VV_MF8, 0x3 }, // 3122 { PseudoVWSUBU_VX_M1_MASK, PseudoVWSUBU_VX_M1, 0x3 }, // 3123 { PseudoVWSUBU_VX_M2_MASK, PseudoVWSUBU_VX_M2, 0x3 }, // 3124 { PseudoVWSUBU_VX_M4_MASK, PseudoVWSUBU_VX_M4, 0x3 }, // 3125 { PseudoVWSUBU_VX_MF2_MASK, PseudoVWSUBU_VX_MF2, 0x3 }, // 3126 { PseudoVWSUBU_VX_MF4_MASK, PseudoVWSUBU_VX_MF4, 0x3 }, // 3127 { PseudoVWSUBU_VX_MF8_MASK, PseudoVWSUBU_VX_MF8, 0x3 }, // 3128 { PseudoVWSUBU_WV_M1_MASK, PseudoVWSUBU_WV_M1, 0x3 }, // 3129 { PseudoVWSUBU_WV_M1_MASK_TIED, PseudoVWSUBU_WV_M1_TIED, 0x2 }, // 3130 { PseudoVWSUBU_WV_M2_MASK, PseudoVWSUBU_WV_M2, 0x3 }, // 3131 { PseudoVWSUBU_WV_M2_MASK_TIED, PseudoVWSUBU_WV_M2_TIED, 0x2 }, // 3132 { PseudoVWSUBU_WV_M4_MASK, PseudoVWSUBU_WV_M4, 0x3 }, // 3133 { PseudoVWSUBU_WV_M4_MASK_TIED, PseudoVWSUBU_WV_M4_TIED, 0x2 }, // 3134 { PseudoVWSUBU_WV_MF2_MASK, PseudoVWSUBU_WV_MF2, 0x3 }, // 3135 { PseudoVWSUBU_WV_MF2_MASK_TIED, PseudoVWSUBU_WV_MF2_TIED, 0x2 }, // 3136 { PseudoVWSUBU_WV_MF4_MASK, PseudoVWSUBU_WV_MF4, 0x3 }, // 3137 { PseudoVWSUBU_WV_MF4_MASK_TIED, PseudoVWSUBU_WV_MF4_TIED, 0x2 }, // 3138 { PseudoVWSUBU_WV_MF8_MASK, PseudoVWSUBU_WV_MF8, 0x3 }, // 3139 { PseudoVWSUBU_WV_MF8_MASK_TIED, PseudoVWSUBU_WV_MF8_TIED, 0x2 }, // 3140 { PseudoVWSUBU_WX_M1_MASK, PseudoVWSUBU_WX_M1, 0x3 }, // 3141 { PseudoVWSUBU_WX_M2_MASK, PseudoVWSUBU_WX_M2, 0x3 }, // 3142 { PseudoVWSUBU_WX_M4_MASK, PseudoVWSUBU_WX_M4, 0x3 }, // 3143 { PseudoVWSUBU_WX_MF2_MASK, PseudoVWSUBU_WX_MF2, 0x3 }, // 3144 { PseudoVWSUBU_WX_MF4_MASK, PseudoVWSUBU_WX_MF4, 0x3 }, // 3145 { PseudoVWSUBU_WX_MF8_MASK, PseudoVWSUBU_WX_MF8, 0x3 }, // 3146 { PseudoVWSUB_VV_M1_MASK, PseudoVWSUB_VV_M1, 0x3 }, // 3147 { PseudoVWSUB_VV_M2_MASK, PseudoVWSUB_VV_M2, 0x3 }, // 3148 { PseudoVWSUB_VV_M4_MASK, PseudoVWSUB_VV_M4, 0x3 }, // 3149 { PseudoVWSUB_VV_MF2_MASK, PseudoVWSUB_VV_MF2, 0x3 }, // 3150 { PseudoVWSUB_VV_MF4_MASK, PseudoVWSUB_VV_MF4, 0x3 }, // 3151 { PseudoVWSUB_VV_MF8_MASK, PseudoVWSUB_VV_MF8, 0x3 }, // 3152 { PseudoVWSUB_VX_M1_MASK, PseudoVWSUB_VX_M1, 0x3 }, // 3153 { PseudoVWSUB_VX_M2_MASK, PseudoVWSUB_VX_M2, 0x3 }, // 3154 { PseudoVWSUB_VX_M4_MASK, PseudoVWSUB_VX_M4, 0x3 }, // 3155 { PseudoVWSUB_VX_MF2_MASK, PseudoVWSUB_VX_MF2, 0x3 }, // 3156 { PseudoVWSUB_VX_MF4_MASK, PseudoVWSUB_VX_MF4, 0x3 }, // 3157 { PseudoVWSUB_VX_MF8_MASK, PseudoVWSUB_VX_MF8, 0x3 }, // 3158 { PseudoVWSUB_WV_M1_MASK, PseudoVWSUB_WV_M1, 0x3 }, // 3159 { PseudoVWSUB_WV_M1_MASK_TIED, PseudoVWSUB_WV_M1_TIED, 0x2 }, // 3160 { PseudoVWSUB_WV_M2_MASK, PseudoVWSUB_WV_M2, 0x3 }, // 3161 { PseudoVWSUB_WV_M2_MASK_TIED, PseudoVWSUB_WV_M2_TIED, 0x2 }, // 3162 { PseudoVWSUB_WV_M4_MASK, PseudoVWSUB_WV_M4, 0x3 }, // 3163 { PseudoVWSUB_WV_M4_MASK_TIED, PseudoVWSUB_WV_M4_TIED, 0x2 }, // 3164 { PseudoVWSUB_WV_MF2_MASK, PseudoVWSUB_WV_MF2, 0x3 }, // 3165 { PseudoVWSUB_WV_MF2_MASK_TIED, PseudoVWSUB_WV_MF2_TIED, 0x2 }, // 3166 { PseudoVWSUB_WV_MF4_MASK, PseudoVWSUB_WV_MF4, 0x3 }, // 3167 { PseudoVWSUB_WV_MF4_MASK_TIED, PseudoVWSUB_WV_MF4_TIED, 0x2 }, // 3168 { PseudoVWSUB_WV_MF8_MASK, PseudoVWSUB_WV_MF8, 0x3 }, // 3169 { PseudoVWSUB_WV_MF8_MASK_TIED, PseudoVWSUB_WV_MF8_TIED, 0x2 }, // 3170 { PseudoVWSUB_WX_M1_MASK, PseudoVWSUB_WX_M1, 0x3 }, // 3171 { PseudoVWSUB_WX_M2_MASK, PseudoVWSUB_WX_M2, 0x3 }, // 3172 { PseudoVWSUB_WX_M4_MASK, PseudoVWSUB_WX_M4, 0x3 }, // 3173 { PseudoVWSUB_WX_MF2_MASK, PseudoVWSUB_WX_MF2, 0x3 }, // 3174 { PseudoVWSUB_WX_MF4_MASK, PseudoVWSUB_WX_MF4, 0x3 }, // 3175 { PseudoVWSUB_WX_MF8_MASK, PseudoVWSUB_WX_MF8, 0x3 }, // 3176 { PseudoVXOR_VI_M1_MASK, PseudoVXOR_VI_M1, 0x3 }, // 3177 { PseudoVXOR_VI_M2_MASK, PseudoVXOR_VI_M2, 0x3 }, // 3178 { PseudoVXOR_VI_M4_MASK, PseudoVXOR_VI_M4, 0x3 }, // 3179 { PseudoVXOR_VI_M8_MASK, PseudoVXOR_VI_M8, 0x3 }, // 3180 { PseudoVXOR_VI_MF2_MASK, PseudoVXOR_VI_MF2, 0x3 }, // 3181 { PseudoVXOR_VI_MF4_MASK, PseudoVXOR_VI_MF4, 0x3 }, // 3182 { PseudoVXOR_VI_MF8_MASK, PseudoVXOR_VI_MF8, 0x3 }, // 3183 { PseudoVXOR_VV_M1_MASK, PseudoVXOR_VV_M1, 0x3 }, // 3184 { PseudoVXOR_VV_M2_MASK, PseudoVXOR_VV_M2, 0x3 }, // 3185 { PseudoVXOR_VV_M4_MASK, PseudoVXOR_VV_M4, 0x3 }, // 3186 { PseudoVXOR_VV_M8_MASK, PseudoVXOR_VV_M8, 0x3 }, // 3187 { PseudoVXOR_VV_MF2_MASK, PseudoVXOR_VV_MF2, 0x3 }, // 3188 { PseudoVXOR_VV_MF4_MASK, PseudoVXOR_VV_MF4, 0x3 }, // 3189 { PseudoVXOR_VV_MF8_MASK, PseudoVXOR_VV_MF8, 0x3 }, // 3190 { PseudoVXOR_VX_M1_MASK, PseudoVXOR_VX_M1, 0x3 }, // 3191 { PseudoVXOR_VX_M2_MASK, PseudoVXOR_VX_M2, 0x3 }, // 3192 { PseudoVXOR_VX_M4_MASK, PseudoVXOR_VX_M4, 0x3 }, // 3193 { PseudoVXOR_VX_M8_MASK, PseudoVXOR_VX_M8, 0x3 }, // 3194 { PseudoVXOR_VX_MF2_MASK, PseudoVXOR_VX_MF2, 0x3 }, // 3195 { PseudoVXOR_VX_MF4_MASK, PseudoVXOR_VX_MF4, 0x3 }, // 3196 { PseudoVXOR_VX_MF8_MASK, PseudoVXOR_VX_MF8, 0x3 }, // 3197 { PseudoVZEXT_VF2_M1_MASK, PseudoVZEXT_VF2_M1, 0x2 }, // 3198 { PseudoVZEXT_VF2_M2_MASK, PseudoVZEXT_VF2_M2, 0x2 }, // 3199 { PseudoVZEXT_VF2_M4_MASK, PseudoVZEXT_VF2_M4, 0x2 }, // 3200 { PseudoVZEXT_VF2_M8_MASK, PseudoVZEXT_VF2_M8, 0x2 }, // 3201 { PseudoVZEXT_VF2_MF2_MASK, PseudoVZEXT_VF2_MF2, 0x2 }, // 3202 { PseudoVZEXT_VF2_MF4_MASK, PseudoVZEXT_VF2_MF4, 0x2 }, // 3203 { PseudoVZEXT_VF4_M1_MASK, PseudoVZEXT_VF4_M1, 0x2 }, // 3204 { PseudoVZEXT_VF4_M2_MASK, PseudoVZEXT_VF4_M2, 0x2 }, // 3205 { PseudoVZEXT_VF4_M4_MASK, PseudoVZEXT_VF4_M4, 0x2 }, // 3206 { PseudoVZEXT_VF4_M8_MASK, PseudoVZEXT_VF4_M8, 0x2 }, // 3207 { PseudoVZEXT_VF4_MF2_MASK, PseudoVZEXT_VF4_MF2, 0x2 }, // 3208 { PseudoVZEXT_VF8_M1_MASK, PseudoVZEXT_VF8_M1, 0x2 }, // 3209 { PseudoVZEXT_VF8_M2_MASK, PseudoVZEXT_VF8_M2, 0x2 }, // 3210 { PseudoVZEXT_VF8_M4_MASK, PseudoVZEXT_VF8_M4, 0x2 }, // 3211 { PseudoVZEXT_VF8_M8_MASK, PseudoVZEXT_VF8_M8, 0x2 }, // 3212 }; const RISCVMaskedPseudoInfo *getMaskedPseudoInfo(unsigned MaskedPseudo) { struct KeyType { unsigned MaskedPseudo; }; KeyType Key = {MaskedPseudo}; struct Comp { bool operator()(const RISCVMaskedPseudoInfo &LHS, const KeyType &RHS) const { if (LHS.MaskedPseudo < RHS.MaskedPseudo) return true; if (LHS.MaskedPseudo > RHS.MaskedPseudo) return false; return false; } }; auto Table = ArrayRef(RISCVMaskedPseudosTable); auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); if (Idx == Table.end() || Key.MaskedPseudo != Idx->MaskedPseudo) return nullptr; return &*Idx; } const RISCVMaskedPseudoInfo *lookupMaskedIntrinsicByUnmasked(unsigned UnmaskedPseudo) { struct IndexType { unsigned UnmaskedPseudo; unsigned _index; }; static const struct IndexType Index[] = { { PseudoTHVdotVMAQASU_VV_M1, 0 }, { PseudoTHVdotVMAQASU_VV_M2, 1 }, { PseudoTHVdotVMAQASU_VV_M4, 2 }, { PseudoTHVdotVMAQASU_VV_M8, 3 }, { PseudoTHVdotVMAQASU_VV_MF2, 4 }, { PseudoTHVdotVMAQASU_VX_M1, 5 }, { PseudoTHVdotVMAQASU_VX_M2, 6 }, { PseudoTHVdotVMAQASU_VX_M4, 7 }, { PseudoTHVdotVMAQASU_VX_M8, 8 }, { PseudoTHVdotVMAQASU_VX_MF2, 9 }, { PseudoTHVdotVMAQAUS_VX_M1, 10 }, { PseudoTHVdotVMAQAUS_VX_M2, 11 }, { PseudoTHVdotVMAQAUS_VX_M4, 12 }, { PseudoTHVdotVMAQAUS_VX_M8, 13 }, { PseudoTHVdotVMAQAUS_VX_MF2, 14 }, { PseudoTHVdotVMAQAU_VV_M1, 15 }, { PseudoTHVdotVMAQAU_VV_M2, 16 }, { PseudoTHVdotVMAQAU_VV_M4, 17 }, { PseudoTHVdotVMAQAU_VV_M8, 18 }, { PseudoTHVdotVMAQAU_VV_MF2, 19 }, { PseudoTHVdotVMAQAU_VX_M1, 20 }, { PseudoTHVdotVMAQAU_VX_M2, 21 }, { PseudoTHVdotVMAQAU_VX_M4, 22 }, { PseudoTHVdotVMAQAU_VX_M8, 23 }, { PseudoTHVdotVMAQAU_VX_MF2, 24 }, { PseudoTHVdotVMAQA_VV_M1, 25 }, { PseudoTHVdotVMAQA_VV_M2, 26 }, { PseudoTHVdotVMAQA_VV_M4, 27 }, { PseudoTHVdotVMAQA_VV_M8, 28 }, { PseudoTHVdotVMAQA_VV_MF2, 29 }, { PseudoTHVdotVMAQA_VX_M1, 30 }, { PseudoTHVdotVMAQA_VX_M2, 31 }, { PseudoTHVdotVMAQA_VX_M4, 32 }, { PseudoTHVdotVMAQA_VX_M8, 33 }, { PseudoTHVdotVMAQA_VX_MF2, 34 }, { PseudoVAADDU_VV_M1, 35 }, { PseudoVAADDU_VV_M2, 36 }, { PseudoVAADDU_VV_M4, 37 }, { PseudoVAADDU_VV_M8, 38 }, { PseudoVAADDU_VV_MF2, 39 }, { PseudoVAADDU_VV_MF4, 40 }, { PseudoVAADDU_VV_MF8, 41 }, { PseudoVAADDU_VX_M1, 42 }, { PseudoVAADDU_VX_M2, 43 }, { PseudoVAADDU_VX_M4, 44 }, { PseudoVAADDU_VX_M8, 45 }, { PseudoVAADDU_VX_MF2, 46 }, { PseudoVAADDU_VX_MF4, 47 }, { PseudoVAADDU_VX_MF8, 48 }, { PseudoVAADD_VV_M1, 49 }, { PseudoVAADD_VV_M2, 50 }, { PseudoVAADD_VV_M4, 51 }, { PseudoVAADD_VV_M8, 52 }, { PseudoVAADD_VV_MF2, 53 }, { PseudoVAADD_VV_MF4, 54 }, { PseudoVAADD_VV_MF8, 55 }, { PseudoVAADD_VX_M1, 56 }, { PseudoVAADD_VX_M2, 57 }, { PseudoVAADD_VX_M4, 58 }, { PseudoVAADD_VX_M8, 59 }, { PseudoVAADD_VX_MF2, 60 }, { PseudoVAADD_VX_MF4, 61 }, { PseudoVAADD_VX_MF8, 62 }, { PseudoVADD_VI_M1, 63 }, { PseudoVADD_VI_M2, 64 }, { PseudoVADD_VI_M4, 65 }, { PseudoVADD_VI_M8, 66 }, { PseudoVADD_VI_MF2, 67 }, { PseudoVADD_VI_MF4, 68 }, { PseudoVADD_VI_MF8, 69 }, { PseudoVADD_VV_M1, 70 }, { PseudoVADD_VV_M2, 71 }, { PseudoVADD_VV_M4, 72 }, { PseudoVADD_VV_M8, 73 }, { PseudoVADD_VV_MF2, 74 }, { PseudoVADD_VV_MF4, 75 }, { PseudoVADD_VV_MF8, 76 }, { PseudoVADD_VX_M1, 77 }, { PseudoVADD_VX_M2, 78 }, { PseudoVADD_VX_M4, 79 }, { PseudoVADD_VX_M8, 80 }, { PseudoVADD_VX_MF2, 81 }, { PseudoVADD_VX_MF4, 82 }, { PseudoVADD_VX_MF8, 83 }, { PseudoVANDN_VV_M1, 84 }, { PseudoVANDN_VV_M2, 85 }, { PseudoVANDN_VV_M4, 86 }, { PseudoVANDN_VV_M8, 87 }, { PseudoVANDN_VV_MF2, 88 }, { PseudoVANDN_VV_MF4, 89 }, { PseudoVANDN_VV_MF8, 90 }, { PseudoVANDN_VX_M1, 91 }, { PseudoVANDN_VX_M2, 92 }, { PseudoVANDN_VX_M4, 93 }, { PseudoVANDN_VX_M8, 94 }, { PseudoVANDN_VX_MF2, 95 }, { PseudoVANDN_VX_MF4, 96 }, { PseudoVANDN_VX_MF8, 97 }, { PseudoVAND_VI_M1, 98 }, { PseudoVAND_VI_M2, 99 }, { PseudoVAND_VI_M4, 100 }, { PseudoVAND_VI_M8, 101 }, { PseudoVAND_VI_MF2, 102 }, { PseudoVAND_VI_MF4, 103 }, { PseudoVAND_VI_MF8, 104 }, { PseudoVAND_VV_M1, 105 }, { PseudoVAND_VV_M2, 106 }, { PseudoVAND_VV_M4, 107 }, { PseudoVAND_VV_M8, 108 }, { PseudoVAND_VV_MF2, 109 }, { PseudoVAND_VV_MF4, 110 }, { PseudoVAND_VV_MF8, 111 }, { PseudoVAND_VX_M1, 112 }, { PseudoVAND_VX_M2, 113 }, { PseudoVAND_VX_M4, 114 }, { PseudoVAND_VX_M8, 115 }, { PseudoVAND_VX_MF2, 116 }, { PseudoVAND_VX_MF4, 117 }, { PseudoVAND_VX_MF8, 118 }, { PseudoVASUBU_VV_M1, 119 }, { PseudoVASUBU_VV_M2, 120 }, { PseudoVASUBU_VV_M4, 121 }, { PseudoVASUBU_VV_M8, 122 }, { PseudoVASUBU_VV_MF2, 123 }, { PseudoVASUBU_VV_MF4, 124 }, { PseudoVASUBU_VV_MF8, 125 }, { PseudoVASUBU_VX_M1, 126 }, { PseudoVASUBU_VX_M2, 127 }, { PseudoVASUBU_VX_M4, 128 }, { PseudoVASUBU_VX_M8, 129 }, { PseudoVASUBU_VX_MF2, 130 }, { PseudoVASUBU_VX_MF4, 131 }, { PseudoVASUBU_VX_MF8, 132 }, { PseudoVASUB_VV_M1, 133 }, { PseudoVASUB_VV_M2, 134 }, { PseudoVASUB_VV_M4, 135 }, { PseudoVASUB_VV_M8, 136 }, { PseudoVASUB_VV_MF2, 137 }, { PseudoVASUB_VV_MF4, 138 }, { PseudoVASUB_VV_MF8, 139 }, { PseudoVASUB_VX_M1, 140 }, { PseudoVASUB_VX_M2, 141 }, { PseudoVASUB_VX_M4, 142 }, { PseudoVASUB_VX_M8, 143 }, { PseudoVASUB_VX_MF2, 144 }, { PseudoVASUB_VX_MF4, 145 }, { PseudoVASUB_VX_MF8, 146 }, { PseudoVBREV8_V_M1, 147 }, { PseudoVBREV8_V_M2, 148 }, { PseudoVBREV8_V_M4, 149 }, { PseudoVBREV8_V_M8, 150 }, { PseudoVBREV8_V_MF2, 151 }, { PseudoVBREV8_V_MF4, 152 }, { PseudoVBREV8_V_MF8, 153 }, { PseudoVBREV_V_M1, 154 }, { PseudoVBREV_V_M2, 155 }, { PseudoVBREV_V_M4, 156 }, { PseudoVBREV_V_M8, 157 }, { PseudoVBREV_V_MF2, 158 }, { PseudoVBREV_V_MF4, 159 }, { PseudoVBREV_V_MF8, 160 }, { PseudoVCLMULH_VV_M1, 161 }, { PseudoVCLMULH_VV_M2, 162 }, { PseudoVCLMULH_VV_M4, 163 }, { PseudoVCLMULH_VV_M8, 164 }, { PseudoVCLMULH_VV_MF2, 165 }, { PseudoVCLMULH_VV_MF4, 166 }, { PseudoVCLMULH_VV_MF8, 167 }, { PseudoVCLMULH_VX_M1, 168 }, { PseudoVCLMULH_VX_M2, 169 }, { PseudoVCLMULH_VX_M4, 170 }, { PseudoVCLMULH_VX_M8, 171 }, { PseudoVCLMULH_VX_MF2, 172 }, { PseudoVCLMULH_VX_MF4, 173 }, { PseudoVCLMULH_VX_MF8, 174 }, { PseudoVCLMUL_VV_M1, 175 }, { PseudoVCLMUL_VV_M2, 176 }, { PseudoVCLMUL_VV_M4, 177 }, { PseudoVCLMUL_VV_M8, 178 }, { PseudoVCLMUL_VV_MF2, 179 }, { PseudoVCLMUL_VV_MF4, 180 }, { PseudoVCLMUL_VV_MF8, 181 }, { PseudoVCLMUL_VX_M1, 182 }, { PseudoVCLMUL_VX_M2, 183 }, { PseudoVCLMUL_VX_M4, 184 }, { PseudoVCLMUL_VX_M8, 185 }, { PseudoVCLMUL_VX_MF2, 186 }, { PseudoVCLMUL_VX_MF4, 187 }, { PseudoVCLMUL_VX_MF8, 188 }, { PseudoVCLZ_V_M1, 189 }, { PseudoVCLZ_V_M2, 190 }, { PseudoVCLZ_V_M4, 191 }, { PseudoVCLZ_V_M8, 192 }, { PseudoVCLZ_V_MF2, 193 }, { PseudoVCLZ_V_MF4, 194 }, { PseudoVCLZ_V_MF8, 195 }, { PseudoVCPOP_V_M1, 196 }, { PseudoVCPOP_V_M2, 197 }, { PseudoVCPOP_V_M4, 198 }, { PseudoVCPOP_V_M8, 199 }, { PseudoVCPOP_V_MF2, 200 }, { PseudoVCPOP_V_MF4, 201 }, { PseudoVCPOP_V_MF8, 202 }, { PseudoVCTZ_V_M1, 203 }, { PseudoVCTZ_V_M2, 204 }, { PseudoVCTZ_V_M4, 205 }, { PseudoVCTZ_V_M8, 206 }, { PseudoVCTZ_V_MF2, 207 }, { PseudoVCTZ_V_MF4, 208 }, { PseudoVCTZ_V_MF8, 209 }, { PseudoVDIVU_VV_M1_E16, 210 }, { PseudoVDIVU_VV_M1_E32, 211 }, { PseudoVDIVU_VV_M1_E64, 212 }, { PseudoVDIVU_VV_M1_E8, 213 }, { PseudoVDIVU_VV_M2_E16, 214 }, { PseudoVDIVU_VV_M2_E32, 215 }, { PseudoVDIVU_VV_M2_E64, 216 }, { PseudoVDIVU_VV_M2_E8, 217 }, { PseudoVDIVU_VV_M4_E16, 218 }, { PseudoVDIVU_VV_M4_E32, 219 }, { PseudoVDIVU_VV_M4_E64, 220 }, { PseudoVDIVU_VV_M4_E8, 221 }, { PseudoVDIVU_VV_M8_E16, 222 }, { PseudoVDIVU_VV_M8_E32, 223 }, { PseudoVDIVU_VV_M8_E64, 224 }, { PseudoVDIVU_VV_M8_E8, 225 }, { PseudoVDIVU_VV_MF2_E16, 226 }, { PseudoVDIVU_VV_MF2_E32, 227 }, { PseudoVDIVU_VV_MF2_E8, 228 }, { PseudoVDIVU_VV_MF4_E16, 229 }, { PseudoVDIVU_VV_MF4_E8, 230 }, { PseudoVDIVU_VV_MF8_E8, 231 }, { PseudoVDIVU_VX_M1_E16, 232 }, { PseudoVDIVU_VX_M1_E32, 233 }, { PseudoVDIVU_VX_M1_E64, 234 }, { PseudoVDIVU_VX_M1_E8, 235 }, { PseudoVDIVU_VX_M2_E16, 236 }, { PseudoVDIVU_VX_M2_E32, 237 }, { PseudoVDIVU_VX_M2_E64, 238 }, { PseudoVDIVU_VX_M2_E8, 239 }, { PseudoVDIVU_VX_M4_E16, 240 }, { PseudoVDIVU_VX_M4_E32, 241 }, { PseudoVDIVU_VX_M4_E64, 242 }, { PseudoVDIVU_VX_M4_E8, 243 }, { PseudoVDIVU_VX_M8_E16, 244 }, { PseudoVDIVU_VX_M8_E32, 245 }, { PseudoVDIVU_VX_M8_E64, 246 }, { PseudoVDIVU_VX_M8_E8, 247 }, { PseudoVDIVU_VX_MF2_E16, 248 }, { PseudoVDIVU_VX_MF2_E32, 249 }, { PseudoVDIVU_VX_MF2_E8, 250 }, { PseudoVDIVU_VX_MF4_E16, 251 }, { PseudoVDIVU_VX_MF4_E8, 252 }, { PseudoVDIVU_VX_MF8_E8, 253 }, { PseudoVDIV_VV_M1_E16, 254 }, { PseudoVDIV_VV_M1_E32, 255 }, { PseudoVDIV_VV_M1_E64, 256 }, { PseudoVDIV_VV_M1_E8, 257 }, { PseudoVDIV_VV_M2_E16, 258 }, { PseudoVDIV_VV_M2_E32, 259 }, { PseudoVDIV_VV_M2_E64, 260 }, { PseudoVDIV_VV_M2_E8, 261 }, { PseudoVDIV_VV_M4_E16, 262 }, { PseudoVDIV_VV_M4_E32, 263 }, { PseudoVDIV_VV_M4_E64, 264 }, { PseudoVDIV_VV_M4_E8, 265 }, { PseudoVDIV_VV_M8_E16, 266 }, { PseudoVDIV_VV_M8_E32, 267 }, { PseudoVDIV_VV_M8_E64, 268 }, { PseudoVDIV_VV_M8_E8, 269 }, { PseudoVDIV_VV_MF2_E16, 270 }, { PseudoVDIV_VV_MF2_E32, 271 }, { PseudoVDIV_VV_MF2_E8, 272 }, { PseudoVDIV_VV_MF4_E16, 273 }, { PseudoVDIV_VV_MF4_E8, 274 }, { PseudoVDIV_VV_MF8_E8, 275 }, { PseudoVDIV_VX_M1_E16, 276 }, { PseudoVDIV_VX_M1_E32, 277 }, { PseudoVDIV_VX_M1_E64, 278 }, { PseudoVDIV_VX_M1_E8, 279 }, { PseudoVDIV_VX_M2_E16, 280 }, { PseudoVDIV_VX_M2_E32, 281 }, { PseudoVDIV_VX_M2_E64, 282 }, { PseudoVDIV_VX_M2_E8, 283 }, { PseudoVDIV_VX_M4_E16, 284 }, { PseudoVDIV_VX_M4_E32, 285 }, { PseudoVDIV_VX_M4_E64, 286 }, { PseudoVDIV_VX_M4_E8, 287 }, { PseudoVDIV_VX_M8_E16, 288 }, { PseudoVDIV_VX_M8_E32, 289 }, { PseudoVDIV_VX_M8_E64, 290 }, { PseudoVDIV_VX_M8_E8, 291 }, { PseudoVDIV_VX_MF2_E16, 292 }, { PseudoVDIV_VX_MF2_E32, 293 }, { PseudoVDIV_VX_MF2_E8, 294 }, { PseudoVDIV_VX_MF4_E16, 295 }, { PseudoVDIV_VX_MF4_E8, 296 }, { PseudoVDIV_VX_MF8_E8, 297 }, { PseudoVFADD_VFPR16_M1_E16, 298 }, { PseudoVFADD_VFPR16_M2_E16, 299 }, { PseudoVFADD_VFPR16_M4_E16, 300 }, { PseudoVFADD_VFPR16_M8_E16, 301 }, { PseudoVFADD_VFPR16_MF2_E16, 302 }, { PseudoVFADD_VFPR16_MF4_E16, 303 }, { PseudoVFADD_VFPR32_M1_E32, 304 }, { PseudoVFADD_VFPR32_M2_E32, 305 }, { PseudoVFADD_VFPR32_M4_E32, 306 }, { PseudoVFADD_VFPR32_M8_E32, 307 }, { PseudoVFADD_VFPR32_MF2_E32, 308 }, { PseudoVFADD_VFPR64_M1_E64, 309 }, { PseudoVFADD_VFPR64_M2_E64, 310 }, { PseudoVFADD_VFPR64_M4_E64, 311 }, { PseudoVFADD_VFPR64_M8_E64, 312 }, { PseudoVFADD_VV_M1_E16, 313 }, { PseudoVFADD_VV_M1_E32, 314 }, { PseudoVFADD_VV_M1_E64, 315 }, { PseudoVFADD_VV_M2_E16, 316 }, { PseudoVFADD_VV_M2_E32, 317 }, { PseudoVFADD_VV_M2_E64, 318 }, { PseudoVFADD_VV_M4_E16, 319 }, { PseudoVFADD_VV_M4_E32, 320 }, { PseudoVFADD_VV_M4_E64, 321 }, { PseudoVFADD_VV_M8_E16, 322 }, { PseudoVFADD_VV_M8_E32, 323 }, { PseudoVFADD_VV_M8_E64, 324 }, { PseudoVFADD_VV_MF2_E16, 325 }, { PseudoVFADD_VV_MF2_E32, 326 }, { PseudoVFADD_VV_MF4_E16, 327 }, { PseudoVFCLASS_V_M1, 328 }, { PseudoVFCLASS_V_M2, 329 }, { PseudoVFCLASS_V_M4, 330 }, { PseudoVFCLASS_V_M8, 331 }, { PseudoVFCLASS_V_MF2, 332 }, { PseudoVFCLASS_V_MF4, 333 }, { PseudoVFCVT_F_XU_V_M1_E16, 334 }, { PseudoVFCVT_F_XU_V_M1_E32, 335 }, { PseudoVFCVT_F_XU_V_M1_E64, 336 }, { PseudoVFCVT_F_XU_V_M2_E16, 337 }, { PseudoVFCVT_F_XU_V_M2_E32, 338 }, { PseudoVFCVT_F_XU_V_M2_E64, 339 }, { PseudoVFCVT_F_XU_V_M4_E16, 340 }, { PseudoVFCVT_F_XU_V_M4_E32, 341 }, { PseudoVFCVT_F_XU_V_M4_E64, 342 }, { PseudoVFCVT_F_XU_V_M8_E16, 343 }, { PseudoVFCVT_F_XU_V_M8_E32, 344 }, { PseudoVFCVT_F_XU_V_M8_E64, 345 }, { PseudoVFCVT_F_XU_V_MF2_E16, 346 }, { PseudoVFCVT_F_XU_V_MF2_E32, 347 }, { PseudoVFCVT_F_XU_V_MF4_E16, 348 }, { PseudoVFCVT_F_X_V_M1_E16, 349 }, { PseudoVFCVT_F_X_V_M1_E32, 350 }, { PseudoVFCVT_F_X_V_M1_E64, 351 }, { PseudoVFCVT_F_X_V_M2_E16, 352 }, { PseudoVFCVT_F_X_V_M2_E32, 353 }, { PseudoVFCVT_F_X_V_M2_E64, 354 }, { PseudoVFCVT_F_X_V_M4_E16, 355 }, { PseudoVFCVT_F_X_V_M4_E32, 356 }, { PseudoVFCVT_F_X_V_M4_E64, 357 }, { PseudoVFCVT_F_X_V_M8_E16, 358 }, { PseudoVFCVT_F_X_V_M8_E32, 359 }, { PseudoVFCVT_F_X_V_M8_E64, 360 }, { PseudoVFCVT_F_X_V_MF2_E16, 361 }, { PseudoVFCVT_F_X_V_MF2_E32, 362 }, { PseudoVFCVT_F_X_V_MF4_E16, 363 }, { PseudoVFCVT_RM_F_XU_V_M1_E16, 364 }, { PseudoVFCVT_RM_F_XU_V_M1_E32, 365 }, { PseudoVFCVT_RM_F_XU_V_M1_E64, 366 }, { PseudoVFCVT_RM_F_XU_V_M2_E16, 367 }, { PseudoVFCVT_RM_F_XU_V_M2_E32, 368 }, { PseudoVFCVT_RM_F_XU_V_M2_E64, 369 }, { PseudoVFCVT_RM_F_XU_V_M4_E16, 370 }, { PseudoVFCVT_RM_F_XU_V_M4_E32, 371 }, { PseudoVFCVT_RM_F_XU_V_M4_E64, 372 }, { PseudoVFCVT_RM_F_XU_V_M8_E16, 373 }, { PseudoVFCVT_RM_F_XU_V_M8_E32, 374 }, { PseudoVFCVT_RM_F_XU_V_M8_E64, 375 }, { PseudoVFCVT_RM_F_XU_V_MF2_E16, 376 }, { PseudoVFCVT_RM_F_XU_V_MF2_E32, 377 }, { PseudoVFCVT_RM_F_XU_V_MF4_E16, 378 }, { PseudoVFCVT_RM_F_X_V_M1_E16, 379 }, { PseudoVFCVT_RM_F_X_V_M1_E32, 380 }, { PseudoVFCVT_RM_F_X_V_M1_E64, 381 }, { PseudoVFCVT_RM_F_X_V_M2_E16, 382 }, { PseudoVFCVT_RM_F_X_V_M2_E32, 383 }, { PseudoVFCVT_RM_F_X_V_M2_E64, 384 }, { PseudoVFCVT_RM_F_X_V_M4_E16, 385 }, { PseudoVFCVT_RM_F_X_V_M4_E32, 386 }, { PseudoVFCVT_RM_F_X_V_M4_E64, 387 }, { PseudoVFCVT_RM_F_X_V_M8_E16, 388 }, { PseudoVFCVT_RM_F_X_V_M8_E32, 389 }, { PseudoVFCVT_RM_F_X_V_M8_E64, 390 }, { PseudoVFCVT_RM_F_X_V_MF2_E16, 391 }, { PseudoVFCVT_RM_F_X_V_MF2_E32, 392 }, { PseudoVFCVT_RM_F_X_V_MF4_E16, 393 }, { PseudoVFCVT_RM_XU_F_V_M1, 394 }, { PseudoVFCVT_RM_XU_F_V_M2, 395 }, { PseudoVFCVT_RM_XU_F_V_M4, 396 }, { PseudoVFCVT_RM_XU_F_V_M8, 397 }, { PseudoVFCVT_RM_XU_F_V_MF2, 398 }, { PseudoVFCVT_RM_XU_F_V_MF4, 399 }, { PseudoVFCVT_RM_X_F_V_M1, 400 }, { PseudoVFCVT_RM_X_F_V_M2, 401 }, { PseudoVFCVT_RM_X_F_V_M4, 402 }, { PseudoVFCVT_RM_X_F_V_M8, 403 }, { PseudoVFCVT_RM_X_F_V_MF2, 404 }, { PseudoVFCVT_RM_X_F_V_MF4, 405 }, { PseudoVFCVT_RTZ_XU_F_V_M1, 406 }, { PseudoVFCVT_RTZ_XU_F_V_M2, 407 }, { PseudoVFCVT_RTZ_XU_F_V_M4, 408 }, { PseudoVFCVT_RTZ_XU_F_V_M8, 409 }, { PseudoVFCVT_RTZ_XU_F_V_MF2, 410 }, { PseudoVFCVT_RTZ_XU_F_V_MF4, 411 }, { PseudoVFCVT_RTZ_X_F_V_M1, 412 }, { PseudoVFCVT_RTZ_X_F_V_M2, 413 }, { PseudoVFCVT_RTZ_X_F_V_M4, 414 }, { PseudoVFCVT_RTZ_X_F_V_M8, 415 }, { PseudoVFCVT_RTZ_X_F_V_MF2, 416 }, { PseudoVFCVT_RTZ_X_F_V_MF4, 417 }, { PseudoVFCVT_XU_F_V_M1, 418 }, { PseudoVFCVT_XU_F_V_M2, 419 }, { PseudoVFCVT_XU_F_V_M4, 420 }, { PseudoVFCVT_XU_F_V_M8, 421 }, { PseudoVFCVT_XU_F_V_MF2, 422 }, { PseudoVFCVT_XU_F_V_MF4, 423 }, { PseudoVFCVT_X_F_V_M1, 424 }, { PseudoVFCVT_X_F_V_M2, 425 }, { PseudoVFCVT_X_F_V_M4, 426 }, { PseudoVFCVT_X_F_V_M8, 427 }, { PseudoVFCVT_X_F_V_MF2, 428 }, { PseudoVFCVT_X_F_V_MF4, 429 }, { PseudoVFDIV_VFPR16_M1_E16, 430 }, { PseudoVFDIV_VFPR16_M2_E16, 431 }, { PseudoVFDIV_VFPR16_M4_E16, 432 }, { PseudoVFDIV_VFPR16_M8_E16, 433 }, { PseudoVFDIV_VFPR16_MF2_E16, 434 }, { PseudoVFDIV_VFPR16_MF4_E16, 435 }, { PseudoVFDIV_VFPR32_M1_E32, 436 }, { PseudoVFDIV_VFPR32_M2_E32, 437 }, { PseudoVFDIV_VFPR32_M4_E32, 438 }, { PseudoVFDIV_VFPR32_M8_E32, 439 }, { PseudoVFDIV_VFPR32_MF2_E32, 440 }, { PseudoVFDIV_VFPR64_M1_E64, 441 }, { PseudoVFDIV_VFPR64_M2_E64, 442 }, { PseudoVFDIV_VFPR64_M4_E64, 443 }, { PseudoVFDIV_VFPR64_M8_E64, 444 }, { PseudoVFDIV_VV_M1_E16, 445 }, { PseudoVFDIV_VV_M1_E32, 446 }, { PseudoVFDIV_VV_M1_E64, 447 }, { PseudoVFDIV_VV_M2_E16, 448 }, { PseudoVFDIV_VV_M2_E32, 449 }, { PseudoVFDIV_VV_M2_E64, 450 }, { PseudoVFDIV_VV_M4_E16, 451 }, { PseudoVFDIV_VV_M4_E32, 452 }, { PseudoVFDIV_VV_M4_E64, 453 }, { PseudoVFDIV_VV_M8_E16, 454 }, { PseudoVFDIV_VV_M8_E32, 455 }, { PseudoVFDIV_VV_M8_E64, 456 }, { PseudoVFDIV_VV_MF2_E16, 457 }, { PseudoVFDIV_VV_MF2_E32, 458 }, { PseudoVFDIV_VV_MF4_E16, 459 }, { PseudoVFMACC_VFPR16_M1_E16, 460 }, { PseudoVFMACC_VFPR16_M2_E16, 461 }, { PseudoVFMACC_VFPR16_M4_E16, 462 }, { PseudoVFMACC_VFPR16_M8_E16, 463 }, { PseudoVFMACC_VFPR16_MF2_E16, 464 }, { PseudoVFMACC_VFPR16_MF4_E16, 465 }, { PseudoVFMACC_VFPR32_M1_E32, 466 }, { PseudoVFMACC_VFPR32_M2_E32, 467 }, { PseudoVFMACC_VFPR32_M4_E32, 468 }, { PseudoVFMACC_VFPR32_M8_E32, 469 }, { PseudoVFMACC_VFPR32_MF2_E32, 470 }, { PseudoVFMACC_VFPR64_M1_E64, 471 }, { PseudoVFMACC_VFPR64_M2_E64, 472 }, { PseudoVFMACC_VFPR64_M4_E64, 473 }, { PseudoVFMACC_VFPR64_M8_E64, 474 }, { PseudoVFMACC_VV_M1_E16, 475 }, { PseudoVFMACC_VV_M1_E32, 476 }, { PseudoVFMACC_VV_M1_E64, 477 }, { PseudoVFMACC_VV_M2_E16, 478 }, { PseudoVFMACC_VV_M2_E32, 479 }, { PseudoVFMACC_VV_M2_E64, 480 }, { PseudoVFMACC_VV_M4_E16, 481 }, { PseudoVFMACC_VV_M4_E32, 482 }, { PseudoVFMACC_VV_M4_E64, 483 }, { PseudoVFMACC_VV_M8_E16, 484 }, { PseudoVFMACC_VV_M8_E32, 485 }, { PseudoVFMACC_VV_M8_E64, 486 }, { PseudoVFMACC_VV_MF2_E16, 487 }, { PseudoVFMACC_VV_MF2_E32, 488 }, { PseudoVFMACC_VV_MF4_E16, 489 }, { PseudoVFMADD_VFPR16_M1_E16, 490 }, { PseudoVFMADD_VFPR16_M2_E16, 491 }, { PseudoVFMADD_VFPR16_M4_E16, 492 }, { PseudoVFMADD_VFPR16_M8_E16, 493 }, { PseudoVFMADD_VFPR16_MF2_E16, 494 }, { PseudoVFMADD_VFPR16_MF4_E16, 495 }, { PseudoVFMADD_VFPR32_M1_E32, 496 }, { PseudoVFMADD_VFPR32_M2_E32, 497 }, { PseudoVFMADD_VFPR32_M4_E32, 498 }, { PseudoVFMADD_VFPR32_M8_E32, 499 }, { PseudoVFMADD_VFPR32_MF2_E32, 500 }, { PseudoVFMADD_VFPR64_M1_E64, 501 }, { PseudoVFMADD_VFPR64_M2_E64, 502 }, { PseudoVFMADD_VFPR64_M4_E64, 503 }, { PseudoVFMADD_VFPR64_M8_E64, 504 }, { PseudoVFMADD_VV_M1_E16, 505 }, { PseudoVFMADD_VV_M1_E32, 506 }, { PseudoVFMADD_VV_M1_E64, 507 }, { PseudoVFMADD_VV_M2_E16, 508 }, { PseudoVFMADD_VV_M2_E32, 509 }, { PseudoVFMADD_VV_M2_E64, 510 }, { PseudoVFMADD_VV_M4_E16, 511 }, { PseudoVFMADD_VV_M4_E32, 512 }, { PseudoVFMADD_VV_M4_E64, 513 }, { PseudoVFMADD_VV_M8_E16, 514 }, { PseudoVFMADD_VV_M8_E32, 515 }, { PseudoVFMADD_VV_M8_E64, 516 }, { PseudoVFMADD_VV_MF2_E16, 517 }, { PseudoVFMADD_VV_MF2_E32, 518 }, { PseudoVFMADD_VV_MF4_E16, 519 }, { PseudoVFMAX_VFPR16_M1_E16, 520 }, { PseudoVFMAX_VFPR16_M2_E16, 521 }, { PseudoVFMAX_VFPR16_M4_E16, 522 }, { PseudoVFMAX_VFPR16_M8_E16, 523 }, { PseudoVFMAX_VFPR16_MF2_E16, 524 }, { PseudoVFMAX_VFPR16_MF4_E16, 525 }, { PseudoVFMAX_VFPR32_M1_E32, 526 }, { PseudoVFMAX_VFPR32_M2_E32, 527 }, { PseudoVFMAX_VFPR32_M4_E32, 528 }, { PseudoVFMAX_VFPR32_M8_E32, 529 }, { PseudoVFMAX_VFPR32_MF2_E32, 530 }, { PseudoVFMAX_VFPR64_M1_E64, 531 }, { PseudoVFMAX_VFPR64_M2_E64, 532 }, { PseudoVFMAX_VFPR64_M4_E64, 533 }, { PseudoVFMAX_VFPR64_M8_E64, 534 }, { PseudoVFMAX_VV_M1_E16, 535 }, { PseudoVFMAX_VV_M1_E32, 536 }, { PseudoVFMAX_VV_M1_E64, 537 }, { PseudoVFMAX_VV_M2_E16, 538 }, { PseudoVFMAX_VV_M2_E32, 539 }, { PseudoVFMAX_VV_M2_E64, 540 }, { PseudoVFMAX_VV_M4_E16, 541 }, { PseudoVFMAX_VV_M4_E32, 542 }, { PseudoVFMAX_VV_M4_E64, 543 }, { PseudoVFMAX_VV_M8_E16, 544 }, { PseudoVFMAX_VV_M8_E32, 545 }, { PseudoVFMAX_VV_M8_E64, 546 }, { PseudoVFMAX_VV_MF2_E16, 547 }, { PseudoVFMAX_VV_MF2_E32, 548 }, { PseudoVFMAX_VV_MF4_E16, 549 }, { PseudoVFMIN_VFPR16_M1_E16, 550 }, { PseudoVFMIN_VFPR16_M2_E16, 551 }, { PseudoVFMIN_VFPR16_M4_E16, 552 }, { PseudoVFMIN_VFPR16_M8_E16, 553 }, { PseudoVFMIN_VFPR16_MF2_E16, 554 }, { PseudoVFMIN_VFPR16_MF4_E16, 555 }, { PseudoVFMIN_VFPR32_M1_E32, 556 }, { PseudoVFMIN_VFPR32_M2_E32, 557 }, { PseudoVFMIN_VFPR32_M4_E32, 558 }, { PseudoVFMIN_VFPR32_M8_E32, 559 }, { PseudoVFMIN_VFPR32_MF2_E32, 560 }, { PseudoVFMIN_VFPR64_M1_E64, 561 }, { PseudoVFMIN_VFPR64_M2_E64, 562 }, { PseudoVFMIN_VFPR64_M4_E64, 563 }, { PseudoVFMIN_VFPR64_M8_E64, 564 }, { PseudoVFMIN_VV_M1_E16, 565 }, { PseudoVFMIN_VV_M1_E32, 566 }, { PseudoVFMIN_VV_M1_E64, 567 }, { PseudoVFMIN_VV_M2_E16, 568 }, { PseudoVFMIN_VV_M2_E32, 569 }, { PseudoVFMIN_VV_M2_E64, 570 }, { PseudoVFMIN_VV_M4_E16, 571 }, { PseudoVFMIN_VV_M4_E32, 572 }, { PseudoVFMIN_VV_M4_E64, 573 }, { PseudoVFMIN_VV_M8_E16, 574 }, { PseudoVFMIN_VV_M8_E32, 575 }, { PseudoVFMIN_VV_M8_E64, 576 }, { PseudoVFMIN_VV_MF2_E16, 577 }, { PseudoVFMIN_VV_MF2_E32, 578 }, { PseudoVFMIN_VV_MF4_E16, 579 }, { PseudoVFMSAC_VFPR16_M1_E16, 580 }, { PseudoVFMSAC_VFPR16_M2_E16, 581 }, { PseudoVFMSAC_VFPR16_M4_E16, 582 }, { PseudoVFMSAC_VFPR16_M8_E16, 583 }, { PseudoVFMSAC_VFPR16_MF2_E16, 584 }, { PseudoVFMSAC_VFPR16_MF4_E16, 585 }, { PseudoVFMSAC_VFPR32_M1_E32, 586 }, { PseudoVFMSAC_VFPR32_M2_E32, 587 }, { PseudoVFMSAC_VFPR32_M4_E32, 588 }, { PseudoVFMSAC_VFPR32_M8_E32, 589 }, { PseudoVFMSAC_VFPR32_MF2_E32, 590 }, { PseudoVFMSAC_VFPR64_M1_E64, 591 }, { PseudoVFMSAC_VFPR64_M2_E64, 592 }, { PseudoVFMSAC_VFPR64_M4_E64, 593 }, { PseudoVFMSAC_VFPR64_M8_E64, 594 }, { PseudoVFMSAC_VV_M1_E16, 595 }, { PseudoVFMSAC_VV_M1_E32, 596 }, { PseudoVFMSAC_VV_M1_E64, 597 }, { PseudoVFMSAC_VV_M2_E16, 598 }, { PseudoVFMSAC_VV_M2_E32, 599 }, { PseudoVFMSAC_VV_M2_E64, 600 }, { PseudoVFMSAC_VV_M4_E16, 601 }, { PseudoVFMSAC_VV_M4_E32, 602 }, { PseudoVFMSAC_VV_M4_E64, 603 }, { PseudoVFMSAC_VV_M8_E16, 604 }, { PseudoVFMSAC_VV_M8_E32, 605 }, { PseudoVFMSAC_VV_M8_E64, 606 }, { PseudoVFMSAC_VV_MF2_E16, 607 }, { PseudoVFMSAC_VV_MF2_E32, 608 }, { PseudoVFMSAC_VV_MF4_E16, 609 }, { PseudoVFMSUB_VFPR16_M1_E16, 610 }, { PseudoVFMSUB_VFPR16_M2_E16, 611 }, { PseudoVFMSUB_VFPR16_M4_E16, 612 }, { PseudoVFMSUB_VFPR16_M8_E16, 613 }, { PseudoVFMSUB_VFPR16_MF2_E16, 614 }, { PseudoVFMSUB_VFPR16_MF4_E16, 615 }, { PseudoVFMSUB_VFPR32_M1_E32, 616 }, { PseudoVFMSUB_VFPR32_M2_E32, 617 }, { PseudoVFMSUB_VFPR32_M4_E32, 618 }, { PseudoVFMSUB_VFPR32_M8_E32, 619 }, { PseudoVFMSUB_VFPR32_MF2_E32, 620 }, { PseudoVFMSUB_VFPR64_M1_E64, 621 }, { PseudoVFMSUB_VFPR64_M2_E64, 622 }, { PseudoVFMSUB_VFPR64_M4_E64, 623 }, { PseudoVFMSUB_VFPR64_M8_E64, 624 }, { PseudoVFMSUB_VV_M1_E16, 625 }, { PseudoVFMSUB_VV_M1_E32, 626 }, { PseudoVFMSUB_VV_M1_E64, 627 }, { PseudoVFMSUB_VV_M2_E16, 628 }, { PseudoVFMSUB_VV_M2_E32, 629 }, { PseudoVFMSUB_VV_M2_E64, 630 }, { PseudoVFMSUB_VV_M4_E16, 631 }, { PseudoVFMSUB_VV_M4_E32, 632 }, { PseudoVFMSUB_VV_M4_E64, 633 }, { PseudoVFMSUB_VV_M8_E16, 634 }, { PseudoVFMSUB_VV_M8_E32, 635 }, { PseudoVFMSUB_VV_M8_E64, 636 }, { PseudoVFMSUB_VV_MF2_E16, 637 }, { PseudoVFMSUB_VV_MF2_E32, 638 }, { PseudoVFMSUB_VV_MF4_E16, 639 }, { PseudoVFMUL_VFPR16_M1_E16, 640 }, { PseudoVFMUL_VFPR16_M2_E16, 641 }, { PseudoVFMUL_VFPR16_M4_E16, 642 }, { PseudoVFMUL_VFPR16_M8_E16, 643 }, { PseudoVFMUL_VFPR16_MF2_E16, 644 }, { PseudoVFMUL_VFPR16_MF4_E16, 645 }, { PseudoVFMUL_VFPR32_M1_E32, 646 }, { PseudoVFMUL_VFPR32_M2_E32, 647 }, { PseudoVFMUL_VFPR32_M4_E32, 648 }, { PseudoVFMUL_VFPR32_M8_E32, 649 }, { PseudoVFMUL_VFPR32_MF2_E32, 650 }, { PseudoVFMUL_VFPR64_M1_E64, 651 }, { PseudoVFMUL_VFPR64_M2_E64, 652 }, { PseudoVFMUL_VFPR64_M4_E64, 653 }, { PseudoVFMUL_VFPR64_M8_E64, 654 }, { PseudoVFMUL_VV_M1_E16, 655 }, { PseudoVFMUL_VV_M1_E32, 656 }, { PseudoVFMUL_VV_M1_E64, 657 }, { PseudoVFMUL_VV_M2_E16, 658 }, { PseudoVFMUL_VV_M2_E32, 659 }, { PseudoVFMUL_VV_M2_E64, 660 }, { PseudoVFMUL_VV_M4_E16, 661 }, { PseudoVFMUL_VV_M4_E32, 662 }, { PseudoVFMUL_VV_M4_E64, 663 }, { PseudoVFMUL_VV_M8_E16, 664 }, { PseudoVFMUL_VV_M8_E32, 665 }, { PseudoVFMUL_VV_M8_E64, 666 }, { PseudoVFMUL_VV_MF2_E16, 667 }, { PseudoVFMUL_VV_MF2_E32, 668 }, { PseudoVFMUL_VV_MF4_E16, 669 }, { PseudoVFNCVTBF16_F_F_W_M1_E16, 670 }, { PseudoVFNCVTBF16_F_F_W_M1_E32, 671 }, { PseudoVFNCVTBF16_F_F_W_M2_E16, 672 }, { PseudoVFNCVTBF16_F_F_W_M2_E32, 673 }, { PseudoVFNCVTBF16_F_F_W_M4_E16, 674 }, { PseudoVFNCVTBF16_F_F_W_M4_E32, 675 }, { PseudoVFNCVTBF16_F_F_W_MF2_E16, 676 }, { PseudoVFNCVTBF16_F_F_W_MF2_E32, 677 }, { PseudoVFNCVTBF16_F_F_W_MF4_E16, 678 }, { PseudoVFNCVT_F_F_W_M1_E16, 679 }, { PseudoVFNCVT_F_F_W_M1_E32, 680 }, { PseudoVFNCVT_F_F_W_M2_E16, 681 }, { PseudoVFNCVT_F_F_W_M2_E32, 682 }, { PseudoVFNCVT_F_F_W_M4_E16, 683 }, { PseudoVFNCVT_F_F_W_M4_E32, 684 }, { PseudoVFNCVT_F_F_W_MF2_E16, 685 }, { PseudoVFNCVT_F_F_W_MF2_E32, 686 }, { PseudoVFNCVT_F_F_W_MF4_E16, 687 }, { PseudoVFNCVT_F_XU_W_M1_E16, 688 }, { PseudoVFNCVT_F_XU_W_M1_E32, 689 }, { PseudoVFNCVT_F_XU_W_M2_E16, 690 }, { PseudoVFNCVT_F_XU_W_M2_E32, 691 }, { PseudoVFNCVT_F_XU_W_M4_E16, 692 }, { PseudoVFNCVT_F_XU_W_M4_E32, 693 }, { PseudoVFNCVT_F_XU_W_MF2_E16, 694 }, { PseudoVFNCVT_F_XU_W_MF2_E32, 695 }, { PseudoVFNCVT_F_XU_W_MF4_E16, 696 }, { PseudoVFNCVT_F_X_W_M1_E16, 697 }, { PseudoVFNCVT_F_X_W_M1_E32, 698 }, { PseudoVFNCVT_F_X_W_M2_E16, 699 }, { PseudoVFNCVT_F_X_W_M2_E32, 700 }, { PseudoVFNCVT_F_X_W_M4_E16, 701 }, { PseudoVFNCVT_F_X_W_M4_E32, 702 }, { PseudoVFNCVT_F_X_W_MF2_E16, 703 }, { PseudoVFNCVT_F_X_W_MF2_E32, 704 }, { PseudoVFNCVT_F_X_W_MF4_E16, 705 }, { PseudoVFNCVT_RM_F_XU_W_M1_E16, 706 }, { PseudoVFNCVT_RM_F_XU_W_M1_E32, 707 }, { PseudoVFNCVT_RM_F_XU_W_M2_E16, 708 }, { PseudoVFNCVT_RM_F_XU_W_M2_E32, 709 }, { PseudoVFNCVT_RM_F_XU_W_M4_E16, 710 }, { PseudoVFNCVT_RM_F_XU_W_M4_E32, 711 }, { PseudoVFNCVT_RM_F_XU_W_MF2_E16, 712 }, { PseudoVFNCVT_RM_F_XU_W_MF2_E32, 713 }, { PseudoVFNCVT_RM_F_XU_W_MF4_E16, 714 }, { PseudoVFNCVT_RM_F_X_W_M1_E16, 715 }, { PseudoVFNCVT_RM_F_X_W_M1_E32, 716 }, { PseudoVFNCVT_RM_F_X_W_M2_E16, 717 }, { PseudoVFNCVT_RM_F_X_W_M2_E32, 718 }, { PseudoVFNCVT_RM_F_X_W_M4_E16, 719 }, { PseudoVFNCVT_RM_F_X_W_M4_E32, 720 }, { PseudoVFNCVT_RM_F_X_W_MF2_E16, 721 }, { PseudoVFNCVT_RM_F_X_W_MF2_E32, 722 }, { PseudoVFNCVT_RM_F_X_W_MF4_E16, 723 }, { PseudoVFNCVT_RM_XU_F_W_M1, 724 }, { PseudoVFNCVT_RM_XU_F_W_M2, 725 }, { PseudoVFNCVT_RM_XU_F_W_M4, 726 }, { PseudoVFNCVT_RM_XU_F_W_MF2, 727 }, { PseudoVFNCVT_RM_XU_F_W_MF4, 728 }, { PseudoVFNCVT_RM_XU_F_W_MF8, 729 }, { PseudoVFNCVT_RM_X_F_W_M1, 730 }, { PseudoVFNCVT_RM_X_F_W_M2, 731 }, { PseudoVFNCVT_RM_X_F_W_M4, 732 }, { PseudoVFNCVT_RM_X_F_W_MF2, 733 }, { PseudoVFNCVT_RM_X_F_W_MF4, 734 }, { PseudoVFNCVT_RM_X_F_W_MF8, 735 }, { PseudoVFNCVT_ROD_F_F_W_M1_E16, 736 }, { PseudoVFNCVT_ROD_F_F_W_M1_E32, 737 }, { PseudoVFNCVT_ROD_F_F_W_M2_E16, 738 }, { PseudoVFNCVT_ROD_F_F_W_M2_E32, 739 }, { PseudoVFNCVT_ROD_F_F_W_M4_E16, 740 }, { PseudoVFNCVT_ROD_F_F_W_M4_E32, 741 }, { PseudoVFNCVT_ROD_F_F_W_MF2_E16, 742 }, { PseudoVFNCVT_ROD_F_F_W_MF2_E32, 743 }, { PseudoVFNCVT_ROD_F_F_W_MF4_E16, 744 }, { PseudoVFNCVT_RTZ_XU_F_W_M1, 745 }, { PseudoVFNCVT_RTZ_XU_F_W_M2, 746 }, { PseudoVFNCVT_RTZ_XU_F_W_M4, 747 }, { PseudoVFNCVT_RTZ_XU_F_W_MF2, 748 }, { PseudoVFNCVT_RTZ_XU_F_W_MF4, 749 }, { PseudoVFNCVT_RTZ_XU_F_W_MF8, 750 }, { PseudoVFNCVT_RTZ_X_F_W_M1, 751 }, { PseudoVFNCVT_RTZ_X_F_W_M2, 752 }, { PseudoVFNCVT_RTZ_X_F_W_M4, 753 }, { PseudoVFNCVT_RTZ_X_F_W_MF2, 754 }, { PseudoVFNCVT_RTZ_X_F_W_MF4, 755 }, { PseudoVFNCVT_RTZ_X_F_W_MF8, 756 }, { PseudoVFNCVT_XU_F_W_M1, 757 }, { PseudoVFNCVT_XU_F_W_M2, 758 }, { PseudoVFNCVT_XU_F_W_M4, 759 }, { PseudoVFNCVT_XU_F_W_MF2, 760 }, { PseudoVFNCVT_XU_F_W_MF4, 761 }, { PseudoVFNCVT_XU_F_W_MF8, 762 }, { PseudoVFNCVT_X_F_W_M1, 763 }, { PseudoVFNCVT_X_F_W_M2, 764 }, { PseudoVFNCVT_X_F_W_M4, 765 }, { PseudoVFNCVT_X_F_W_MF2, 766 }, { PseudoVFNCVT_X_F_W_MF4, 767 }, { PseudoVFNCVT_X_F_W_MF8, 768 }, { PseudoVFNMACC_VFPR16_M1_E16, 769 }, { PseudoVFNMACC_VFPR16_M2_E16, 770 }, { PseudoVFNMACC_VFPR16_M4_E16, 771 }, { PseudoVFNMACC_VFPR16_M8_E16, 772 }, { PseudoVFNMACC_VFPR16_MF2_E16, 773 }, { PseudoVFNMACC_VFPR16_MF4_E16, 774 }, { PseudoVFNMACC_VFPR32_M1_E32, 775 }, { PseudoVFNMACC_VFPR32_M2_E32, 776 }, { PseudoVFNMACC_VFPR32_M4_E32, 777 }, { PseudoVFNMACC_VFPR32_M8_E32, 778 }, { PseudoVFNMACC_VFPR32_MF2_E32, 779 }, { PseudoVFNMACC_VFPR64_M1_E64, 780 }, { PseudoVFNMACC_VFPR64_M2_E64, 781 }, { PseudoVFNMACC_VFPR64_M4_E64, 782 }, { PseudoVFNMACC_VFPR64_M8_E64, 783 }, { PseudoVFNMACC_VV_M1_E16, 784 }, { PseudoVFNMACC_VV_M1_E32, 785 }, { PseudoVFNMACC_VV_M1_E64, 786 }, { PseudoVFNMACC_VV_M2_E16, 787 }, { PseudoVFNMACC_VV_M2_E32, 788 }, { PseudoVFNMACC_VV_M2_E64, 789 }, { PseudoVFNMACC_VV_M4_E16, 790 }, { PseudoVFNMACC_VV_M4_E32, 791 }, { PseudoVFNMACC_VV_M4_E64, 792 }, { PseudoVFNMACC_VV_M8_E16, 793 }, { PseudoVFNMACC_VV_M8_E32, 794 }, { PseudoVFNMACC_VV_M8_E64, 795 }, { PseudoVFNMACC_VV_MF2_E16, 796 }, { PseudoVFNMACC_VV_MF2_E32, 797 }, { PseudoVFNMACC_VV_MF4_E16, 798 }, { PseudoVFNMADD_VFPR16_M1_E16, 799 }, { PseudoVFNMADD_VFPR16_M2_E16, 800 }, { PseudoVFNMADD_VFPR16_M4_E16, 801 }, { PseudoVFNMADD_VFPR16_M8_E16, 802 }, { PseudoVFNMADD_VFPR16_MF2_E16, 803 }, { PseudoVFNMADD_VFPR16_MF4_E16, 804 }, { PseudoVFNMADD_VFPR32_M1_E32, 805 }, { PseudoVFNMADD_VFPR32_M2_E32, 806 }, { PseudoVFNMADD_VFPR32_M4_E32, 807 }, { PseudoVFNMADD_VFPR32_M8_E32, 808 }, { PseudoVFNMADD_VFPR32_MF2_E32, 809 }, { PseudoVFNMADD_VFPR64_M1_E64, 810 }, { PseudoVFNMADD_VFPR64_M2_E64, 811 }, { PseudoVFNMADD_VFPR64_M4_E64, 812 }, { PseudoVFNMADD_VFPR64_M8_E64, 813 }, { PseudoVFNMADD_VV_M1_E16, 814 }, { PseudoVFNMADD_VV_M1_E32, 815 }, { PseudoVFNMADD_VV_M1_E64, 816 }, { PseudoVFNMADD_VV_M2_E16, 817 }, { PseudoVFNMADD_VV_M2_E32, 818 }, { PseudoVFNMADD_VV_M2_E64, 819 }, { PseudoVFNMADD_VV_M4_E16, 820 }, { PseudoVFNMADD_VV_M4_E32, 821 }, { PseudoVFNMADD_VV_M4_E64, 822 }, { PseudoVFNMADD_VV_M8_E16, 823 }, { PseudoVFNMADD_VV_M8_E32, 824 }, { PseudoVFNMADD_VV_M8_E64, 825 }, { PseudoVFNMADD_VV_MF2_E16, 826 }, { PseudoVFNMADD_VV_MF2_E32, 827 }, { PseudoVFNMADD_VV_MF4_E16, 828 }, { PseudoVFNMSAC_VFPR16_M1_E16, 829 }, { PseudoVFNMSAC_VFPR16_M2_E16, 830 }, { PseudoVFNMSAC_VFPR16_M4_E16, 831 }, { PseudoVFNMSAC_VFPR16_M8_E16, 832 }, { PseudoVFNMSAC_VFPR16_MF2_E16, 833 }, { PseudoVFNMSAC_VFPR16_MF4_E16, 834 }, { PseudoVFNMSAC_VFPR32_M1_E32, 835 }, { PseudoVFNMSAC_VFPR32_M2_E32, 836 }, { PseudoVFNMSAC_VFPR32_M4_E32, 837 }, { PseudoVFNMSAC_VFPR32_M8_E32, 838 }, { PseudoVFNMSAC_VFPR32_MF2_E32, 839 }, { PseudoVFNMSAC_VFPR64_M1_E64, 840 }, { PseudoVFNMSAC_VFPR64_M2_E64, 841 }, { PseudoVFNMSAC_VFPR64_M4_E64, 842 }, { PseudoVFNMSAC_VFPR64_M8_E64, 843 }, { PseudoVFNMSAC_VV_M1_E16, 844 }, { PseudoVFNMSAC_VV_M1_E32, 845 }, { PseudoVFNMSAC_VV_M1_E64, 846 }, { PseudoVFNMSAC_VV_M2_E16, 847 }, { PseudoVFNMSAC_VV_M2_E32, 848 }, { PseudoVFNMSAC_VV_M2_E64, 849 }, { PseudoVFNMSAC_VV_M4_E16, 850 }, { PseudoVFNMSAC_VV_M4_E32, 851 }, { PseudoVFNMSAC_VV_M4_E64, 852 }, { PseudoVFNMSAC_VV_M8_E16, 853 }, { PseudoVFNMSAC_VV_M8_E32, 854 }, { PseudoVFNMSAC_VV_M8_E64, 855 }, { PseudoVFNMSAC_VV_MF2_E16, 856 }, { PseudoVFNMSAC_VV_MF2_E32, 857 }, { PseudoVFNMSAC_VV_MF4_E16, 858 }, { PseudoVFNMSUB_VFPR16_M1_E16, 859 }, { PseudoVFNMSUB_VFPR16_M2_E16, 860 }, { PseudoVFNMSUB_VFPR16_M4_E16, 861 }, { PseudoVFNMSUB_VFPR16_M8_E16, 862 }, { PseudoVFNMSUB_VFPR16_MF2_E16, 863 }, { PseudoVFNMSUB_VFPR16_MF4_E16, 864 }, { PseudoVFNMSUB_VFPR32_M1_E32, 865 }, { PseudoVFNMSUB_VFPR32_M2_E32, 866 }, { PseudoVFNMSUB_VFPR32_M4_E32, 867 }, { PseudoVFNMSUB_VFPR32_M8_E32, 868 }, { PseudoVFNMSUB_VFPR32_MF2_E32, 869 }, { PseudoVFNMSUB_VFPR64_M1_E64, 870 }, { PseudoVFNMSUB_VFPR64_M2_E64, 871 }, { PseudoVFNMSUB_VFPR64_M4_E64, 872 }, { PseudoVFNMSUB_VFPR64_M8_E64, 873 }, { PseudoVFNMSUB_VV_M1_E16, 874 }, { PseudoVFNMSUB_VV_M1_E32, 875 }, { PseudoVFNMSUB_VV_M1_E64, 876 }, { PseudoVFNMSUB_VV_M2_E16, 877 }, { PseudoVFNMSUB_VV_M2_E32, 878 }, { PseudoVFNMSUB_VV_M2_E64, 879 }, { PseudoVFNMSUB_VV_M4_E16, 880 }, { PseudoVFNMSUB_VV_M4_E32, 881 }, { PseudoVFNMSUB_VV_M4_E64, 882 }, { PseudoVFNMSUB_VV_M8_E16, 883 }, { PseudoVFNMSUB_VV_M8_E32, 884 }, { PseudoVFNMSUB_VV_M8_E64, 885 }, { PseudoVFNMSUB_VV_MF2_E16, 886 }, { PseudoVFNMSUB_VV_MF2_E32, 887 }, { PseudoVFNMSUB_VV_MF4_E16, 888 }, { PseudoVFNRCLIP_XU_F_QF_M1, 889 }, { PseudoVFNRCLIP_XU_F_QF_M2, 890 }, { PseudoVFNRCLIP_XU_F_QF_MF2, 891 }, { PseudoVFNRCLIP_XU_F_QF_MF4, 892 }, { PseudoVFNRCLIP_XU_F_QF_MF8, 893 }, { PseudoVFNRCLIP_X_F_QF_M1, 894 }, { PseudoVFNRCLIP_X_F_QF_M2, 895 }, { PseudoVFNRCLIP_X_F_QF_MF2, 896 }, { PseudoVFNRCLIP_X_F_QF_MF4, 897 }, { PseudoVFNRCLIP_X_F_QF_MF8, 898 }, { PseudoVFRDIV_VFPR16_M1_E16, 899 }, { PseudoVFRDIV_VFPR16_M2_E16, 900 }, { PseudoVFRDIV_VFPR16_M4_E16, 901 }, { PseudoVFRDIV_VFPR16_M8_E16, 902 }, { PseudoVFRDIV_VFPR16_MF2_E16, 903 }, { PseudoVFRDIV_VFPR16_MF4_E16, 904 }, { PseudoVFRDIV_VFPR32_M1_E32, 905 }, { PseudoVFRDIV_VFPR32_M2_E32, 906 }, { PseudoVFRDIV_VFPR32_M4_E32, 907 }, { PseudoVFRDIV_VFPR32_M8_E32, 908 }, { PseudoVFRDIV_VFPR32_MF2_E32, 909 }, { PseudoVFRDIV_VFPR64_M1_E64, 910 }, { PseudoVFRDIV_VFPR64_M2_E64, 911 }, { PseudoVFRDIV_VFPR64_M4_E64, 912 }, { PseudoVFRDIV_VFPR64_M8_E64, 913 }, { PseudoVFREC7_V_M1_E16, 914 }, { PseudoVFREC7_V_M1_E32, 915 }, { PseudoVFREC7_V_M1_E64, 916 }, { PseudoVFREC7_V_M2_E16, 917 }, { PseudoVFREC7_V_M2_E32, 918 }, { PseudoVFREC7_V_M2_E64, 919 }, { PseudoVFREC7_V_M4_E16, 920 }, { PseudoVFREC7_V_M4_E32, 921 }, { PseudoVFREC7_V_M4_E64, 922 }, { PseudoVFREC7_V_M8_E16, 923 }, { PseudoVFREC7_V_M8_E32, 924 }, { PseudoVFREC7_V_M8_E64, 925 }, { PseudoVFREC7_V_MF2_E16, 926 }, { PseudoVFREC7_V_MF2_E32, 927 }, { PseudoVFREC7_V_MF4_E16, 928 }, { PseudoVFREDMAX_VS_M1_E16, 929 }, { PseudoVFREDMAX_VS_M1_E32, 930 }, { PseudoVFREDMAX_VS_M1_E64, 931 }, { PseudoVFREDMAX_VS_M2_E16, 932 }, { PseudoVFREDMAX_VS_M2_E32, 933 }, { PseudoVFREDMAX_VS_M2_E64, 934 }, { PseudoVFREDMAX_VS_M4_E16, 935 }, { PseudoVFREDMAX_VS_M4_E32, 936 }, { PseudoVFREDMAX_VS_M4_E64, 937 }, { PseudoVFREDMAX_VS_M8_E16, 938 }, { PseudoVFREDMAX_VS_M8_E32, 939 }, { PseudoVFREDMAX_VS_M8_E64, 940 }, { PseudoVFREDMAX_VS_MF2_E16, 941 }, { PseudoVFREDMAX_VS_MF2_E32, 942 }, { PseudoVFREDMAX_VS_MF4_E16, 943 }, { PseudoVFREDMIN_VS_M1_E16, 944 }, { PseudoVFREDMIN_VS_M1_E32, 945 }, { PseudoVFREDMIN_VS_M1_E64, 946 }, { PseudoVFREDMIN_VS_M2_E16, 947 }, { PseudoVFREDMIN_VS_M2_E32, 948 }, { PseudoVFREDMIN_VS_M2_E64, 949 }, { PseudoVFREDMIN_VS_M4_E16, 950 }, { PseudoVFREDMIN_VS_M4_E32, 951 }, { PseudoVFREDMIN_VS_M4_E64, 952 }, { PseudoVFREDMIN_VS_M8_E16, 953 }, { PseudoVFREDMIN_VS_M8_E32, 954 }, { PseudoVFREDMIN_VS_M8_E64, 955 }, { PseudoVFREDMIN_VS_MF2_E16, 956 }, { PseudoVFREDMIN_VS_MF2_E32, 957 }, { PseudoVFREDMIN_VS_MF4_E16, 958 }, { PseudoVFREDOSUM_VS_M1_E16, 959 }, { PseudoVFREDOSUM_VS_M1_E32, 960 }, { PseudoVFREDOSUM_VS_M1_E64, 961 }, { PseudoVFREDOSUM_VS_M2_E16, 962 }, { PseudoVFREDOSUM_VS_M2_E32, 963 }, { PseudoVFREDOSUM_VS_M2_E64, 964 }, { PseudoVFREDOSUM_VS_M4_E16, 965 }, { PseudoVFREDOSUM_VS_M4_E32, 966 }, { PseudoVFREDOSUM_VS_M4_E64, 967 }, { PseudoVFREDOSUM_VS_M8_E16, 968 }, { PseudoVFREDOSUM_VS_M8_E32, 969 }, { PseudoVFREDOSUM_VS_M8_E64, 970 }, { PseudoVFREDOSUM_VS_MF2_E16, 971 }, { PseudoVFREDOSUM_VS_MF2_E32, 972 }, { PseudoVFREDOSUM_VS_MF4_E16, 973 }, { PseudoVFREDUSUM_VS_M1_E16, 974 }, { PseudoVFREDUSUM_VS_M1_E32, 975 }, { PseudoVFREDUSUM_VS_M1_E64, 976 }, { PseudoVFREDUSUM_VS_M2_E16, 977 }, { PseudoVFREDUSUM_VS_M2_E32, 978 }, { PseudoVFREDUSUM_VS_M2_E64, 979 }, { PseudoVFREDUSUM_VS_M4_E16, 980 }, { PseudoVFREDUSUM_VS_M4_E32, 981 }, { PseudoVFREDUSUM_VS_M4_E64, 982 }, { PseudoVFREDUSUM_VS_M8_E16, 983 }, { PseudoVFREDUSUM_VS_M8_E32, 984 }, { PseudoVFREDUSUM_VS_M8_E64, 985 }, { PseudoVFREDUSUM_VS_MF2_E16, 986 }, { PseudoVFREDUSUM_VS_MF2_E32, 987 }, { PseudoVFREDUSUM_VS_MF4_E16, 988 }, { PseudoVFRSQRT7_V_M1_E16, 989 }, { PseudoVFRSQRT7_V_M1_E32, 990 }, { PseudoVFRSQRT7_V_M1_E64, 991 }, { PseudoVFRSQRT7_V_M2_E16, 992 }, { PseudoVFRSQRT7_V_M2_E32, 993 }, { PseudoVFRSQRT7_V_M2_E64, 994 }, { PseudoVFRSQRT7_V_M4_E16, 995 }, { PseudoVFRSQRT7_V_M4_E32, 996 }, { PseudoVFRSQRT7_V_M4_E64, 997 }, { PseudoVFRSQRT7_V_M8_E16, 998 }, { PseudoVFRSQRT7_V_M8_E32, 999 }, { PseudoVFRSQRT7_V_M8_E64, 1000 }, { PseudoVFRSQRT7_V_MF2_E16, 1001 }, { PseudoVFRSQRT7_V_MF2_E32, 1002 }, { PseudoVFRSQRT7_V_MF4_E16, 1003 }, { PseudoVFRSUB_VFPR16_M1_E16, 1004 }, { PseudoVFRSUB_VFPR16_M2_E16, 1005 }, { PseudoVFRSUB_VFPR16_M4_E16, 1006 }, { PseudoVFRSUB_VFPR16_M8_E16, 1007 }, { PseudoVFRSUB_VFPR16_MF2_E16, 1008 }, { PseudoVFRSUB_VFPR16_MF4_E16, 1009 }, { PseudoVFRSUB_VFPR32_M1_E32, 1010 }, { PseudoVFRSUB_VFPR32_M2_E32, 1011 }, { PseudoVFRSUB_VFPR32_M4_E32, 1012 }, { PseudoVFRSUB_VFPR32_M8_E32, 1013 }, { PseudoVFRSUB_VFPR32_MF2_E32, 1014 }, { PseudoVFRSUB_VFPR64_M1_E64, 1015 }, { PseudoVFRSUB_VFPR64_M2_E64, 1016 }, { PseudoVFRSUB_VFPR64_M4_E64, 1017 }, { PseudoVFRSUB_VFPR64_M8_E64, 1018 }, { PseudoVFSGNJN_VFPR16_M1_E16, 1019 }, { PseudoVFSGNJN_VFPR16_M2_E16, 1020 }, { PseudoVFSGNJN_VFPR16_M4_E16, 1021 }, { PseudoVFSGNJN_VFPR16_M8_E16, 1022 }, { PseudoVFSGNJN_VFPR16_MF2_E16, 1023 }, { PseudoVFSGNJN_VFPR16_MF4_E16, 1024 }, { PseudoVFSGNJN_VFPR32_M1_E32, 1025 }, { PseudoVFSGNJN_VFPR32_M2_E32, 1026 }, { PseudoVFSGNJN_VFPR32_M4_E32, 1027 }, { PseudoVFSGNJN_VFPR32_M8_E32, 1028 }, { PseudoVFSGNJN_VFPR32_MF2_E32, 1029 }, { PseudoVFSGNJN_VFPR64_M1_E64, 1030 }, { PseudoVFSGNJN_VFPR64_M2_E64, 1031 }, { PseudoVFSGNJN_VFPR64_M4_E64, 1032 }, { PseudoVFSGNJN_VFPR64_M8_E64, 1033 }, { PseudoVFSGNJN_VV_M1_E16, 1034 }, { PseudoVFSGNJN_VV_M1_E32, 1035 }, { PseudoVFSGNJN_VV_M1_E64, 1036 }, { PseudoVFSGNJN_VV_M2_E16, 1037 }, { PseudoVFSGNJN_VV_M2_E32, 1038 }, { PseudoVFSGNJN_VV_M2_E64, 1039 }, { PseudoVFSGNJN_VV_M4_E16, 1040 }, { PseudoVFSGNJN_VV_M4_E32, 1041 }, { PseudoVFSGNJN_VV_M4_E64, 1042 }, { PseudoVFSGNJN_VV_M8_E16, 1043 }, { PseudoVFSGNJN_VV_M8_E32, 1044 }, { PseudoVFSGNJN_VV_M8_E64, 1045 }, { PseudoVFSGNJN_VV_MF2_E16, 1046 }, { PseudoVFSGNJN_VV_MF2_E32, 1047 }, { PseudoVFSGNJN_VV_MF4_E16, 1048 }, { PseudoVFSGNJX_VFPR16_M1_E16, 1049 }, { PseudoVFSGNJX_VFPR16_M2_E16, 1050 }, { PseudoVFSGNJX_VFPR16_M4_E16, 1051 }, { PseudoVFSGNJX_VFPR16_M8_E16, 1052 }, { PseudoVFSGNJX_VFPR16_MF2_E16, 1053 }, { PseudoVFSGNJX_VFPR16_MF4_E16, 1054 }, { PseudoVFSGNJX_VFPR32_M1_E32, 1055 }, { PseudoVFSGNJX_VFPR32_M2_E32, 1056 }, { PseudoVFSGNJX_VFPR32_M4_E32, 1057 }, { PseudoVFSGNJX_VFPR32_M8_E32, 1058 }, { PseudoVFSGNJX_VFPR32_MF2_E32, 1059 }, { PseudoVFSGNJX_VFPR64_M1_E64, 1060 }, { PseudoVFSGNJX_VFPR64_M2_E64, 1061 }, { PseudoVFSGNJX_VFPR64_M4_E64, 1062 }, { PseudoVFSGNJX_VFPR64_M8_E64, 1063 }, { PseudoVFSGNJX_VV_M1_E16, 1064 }, { PseudoVFSGNJX_VV_M1_E32, 1065 }, { PseudoVFSGNJX_VV_M1_E64, 1066 }, { PseudoVFSGNJX_VV_M2_E16, 1067 }, { PseudoVFSGNJX_VV_M2_E32, 1068 }, { PseudoVFSGNJX_VV_M2_E64, 1069 }, { PseudoVFSGNJX_VV_M4_E16, 1070 }, { PseudoVFSGNJX_VV_M4_E32, 1071 }, { PseudoVFSGNJX_VV_M4_E64, 1072 }, { PseudoVFSGNJX_VV_M8_E16, 1073 }, { PseudoVFSGNJX_VV_M8_E32, 1074 }, { PseudoVFSGNJX_VV_M8_E64, 1075 }, { PseudoVFSGNJX_VV_MF2_E16, 1076 }, { PseudoVFSGNJX_VV_MF2_E32, 1077 }, { PseudoVFSGNJX_VV_MF4_E16, 1078 }, { PseudoVFSGNJ_VFPR16_M1_E16, 1079 }, { PseudoVFSGNJ_VFPR16_M2_E16, 1080 }, { PseudoVFSGNJ_VFPR16_M4_E16, 1081 }, { PseudoVFSGNJ_VFPR16_M8_E16, 1082 }, { PseudoVFSGNJ_VFPR16_MF2_E16, 1083 }, { PseudoVFSGNJ_VFPR16_MF4_E16, 1084 }, { PseudoVFSGNJ_VFPR32_M1_E32, 1085 }, { PseudoVFSGNJ_VFPR32_M2_E32, 1086 }, { PseudoVFSGNJ_VFPR32_M4_E32, 1087 }, { PseudoVFSGNJ_VFPR32_M8_E32, 1088 }, { PseudoVFSGNJ_VFPR32_MF2_E32, 1089 }, { PseudoVFSGNJ_VFPR64_M1_E64, 1090 }, { PseudoVFSGNJ_VFPR64_M2_E64, 1091 }, { PseudoVFSGNJ_VFPR64_M4_E64, 1092 }, { PseudoVFSGNJ_VFPR64_M8_E64, 1093 }, { PseudoVFSGNJ_VV_M1_E16, 1094 }, { PseudoVFSGNJ_VV_M1_E32, 1095 }, { PseudoVFSGNJ_VV_M1_E64, 1096 }, { PseudoVFSGNJ_VV_M2_E16, 1097 }, { PseudoVFSGNJ_VV_M2_E32, 1098 }, { PseudoVFSGNJ_VV_M2_E64, 1099 }, { PseudoVFSGNJ_VV_M4_E16, 1100 }, { PseudoVFSGNJ_VV_M4_E32, 1101 }, { PseudoVFSGNJ_VV_M4_E64, 1102 }, { PseudoVFSGNJ_VV_M8_E16, 1103 }, { PseudoVFSGNJ_VV_M8_E32, 1104 }, { PseudoVFSGNJ_VV_M8_E64, 1105 }, { PseudoVFSGNJ_VV_MF2_E16, 1106 }, { PseudoVFSGNJ_VV_MF2_E32, 1107 }, { PseudoVFSGNJ_VV_MF4_E16, 1108 }, { PseudoVFSLIDE1DOWN_VFPR16_M1, 1109 }, { PseudoVFSLIDE1DOWN_VFPR16_M2, 1110 }, { PseudoVFSLIDE1DOWN_VFPR16_M4, 1111 }, { PseudoVFSLIDE1DOWN_VFPR16_M8, 1112 }, { PseudoVFSLIDE1DOWN_VFPR16_MF2, 1113 }, { PseudoVFSLIDE1DOWN_VFPR16_MF4, 1114 }, { PseudoVFSLIDE1DOWN_VFPR32_M1, 1115 }, { PseudoVFSLIDE1DOWN_VFPR32_M2, 1116 }, { PseudoVFSLIDE1DOWN_VFPR32_M4, 1117 }, { PseudoVFSLIDE1DOWN_VFPR32_M8, 1118 }, { PseudoVFSLIDE1DOWN_VFPR32_MF2, 1119 }, { PseudoVFSLIDE1DOWN_VFPR64_M1, 1120 }, { PseudoVFSLIDE1DOWN_VFPR64_M2, 1121 }, { PseudoVFSLIDE1DOWN_VFPR64_M4, 1122 }, { PseudoVFSLIDE1DOWN_VFPR64_M8, 1123 }, { PseudoVFSLIDE1UP_VFPR16_M1, 1124 }, { PseudoVFSLIDE1UP_VFPR16_M2, 1125 }, { PseudoVFSLIDE1UP_VFPR16_M4, 1126 }, { PseudoVFSLIDE1UP_VFPR16_M8, 1127 }, { PseudoVFSLIDE1UP_VFPR16_MF2, 1128 }, { PseudoVFSLIDE1UP_VFPR16_MF4, 1129 }, { PseudoVFSLIDE1UP_VFPR32_M1, 1130 }, { PseudoVFSLIDE1UP_VFPR32_M2, 1131 }, { PseudoVFSLIDE1UP_VFPR32_M4, 1132 }, { PseudoVFSLIDE1UP_VFPR32_M8, 1133 }, { PseudoVFSLIDE1UP_VFPR32_MF2, 1134 }, { PseudoVFSLIDE1UP_VFPR64_M1, 1135 }, { PseudoVFSLIDE1UP_VFPR64_M2, 1136 }, { PseudoVFSLIDE1UP_VFPR64_M4, 1137 }, { PseudoVFSLIDE1UP_VFPR64_M8, 1138 }, { PseudoVFSQRT_V_M1_E16, 1139 }, { PseudoVFSQRT_V_M1_E32, 1140 }, { PseudoVFSQRT_V_M1_E64, 1141 }, { PseudoVFSQRT_V_M2_E16, 1142 }, { PseudoVFSQRT_V_M2_E32, 1143 }, { PseudoVFSQRT_V_M2_E64, 1144 }, { PseudoVFSQRT_V_M4_E16, 1145 }, { PseudoVFSQRT_V_M4_E32, 1146 }, { PseudoVFSQRT_V_M4_E64, 1147 }, { PseudoVFSQRT_V_M8_E16, 1148 }, { PseudoVFSQRT_V_M8_E32, 1149 }, { PseudoVFSQRT_V_M8_E64, 1150 }, { PseudoVFSQRT_V_MF2_E16, 1151 }, { PseudoVFSQRT_V_MF2_E32, 1152 }, { PseudoVFSQRT_V_MF4_E16, 1153 }, { PseudoVFSUB_VFPR16_M1_E16, 1154 }, { PseudoVFSUB_VFPR16_M2_E16, 1155 }, { PseudoVFSUB_VFPR16_M4_E16, 1156 }, { PseudoVFSUB_VFPR16_M8_E16, 1157 }, { PseudoVFSUB_VFPR16_MF2_E16, 1158 }, { PseudoVFSUB_VFPR16_MF4_E16, 1159 }, { PseudoVFSUB_VFPR32_M1_E32, 1160 }, { PseudoVFSUB_VFPR32_M2_E32, 1161 }, { PseudoVFSUB_VFPR32_M4_E32, 1162 }, { PseudoVFSUB_VFPR32_M8_E32, 1163 }, { PseudoVFSUB_VFPR32_MF2_E32, 1164 }, { PseudoVFSUB_VFPR64_M1_E64, 1165 }, { PseudoVFSUB_VFPR64_M2_E64, 1166 }, { PseudoVFSUB_VFPR64_M4_E64, 1167 }, { PseudoVFSUB_VFPR64_M8_E64, 1168 }, { PseudoVFSUB_VV_M1_E16, 1169 }, { PseudoVFSUB_VV_M1_E32, 1170 }, { PseudoVFSUB_VV_M1_E64, 1171 }, { PseudoVFSUB_VV_M2_E16, 1172 }, { PseudoVFSUB_VV_M2_E32, 1173 }, { PseudoVFSUB_VV_M2_E64, 1174 }, { PseudoVFSUB_VV_M4_E16, 1175 }, { PseudoVFSUB_VV_M4_E32, 1176 }, { PseudoVFSUB_VV_M4_E64, 1177 }, { PseudoVFSUB_VV_M8_E16, 1178 }, { PseudoVFSUB_VV_M8_E32, 1179 }, { PseudoVFSUB_VV_M8_E64, 1180 }, { PseudoVFSUB_VV_MF2_E16, 1181 }, { PseudoVFSUB_VV_MF2_E32, 1182 }, { PseudoVFSUB_VV_MF4_E16, 1183 }, { PseudoVFWADD_VFPR16_M1_E16, 1184 }, { PseudoVFWADD_VFPR16_M2_E16, 1185 }, { PseudoVFWADD_VFPR16_M4_E16, 1186 }, { PseudoVFWADD_VFPR16_MF2_E16, 1187 }, { PseudoVFWADD_VFPR16_MF4_E16, 1188 }, { PseudoVFWADD_VFPR32_M1_E32, 1189 }, { PseudoVFWADD_VFPR32_M2_E32, 1190 }, { PseudoVFWADD_VFPR32_M4_E32, 1191 }, { PseudoVFWADD_VFPR32_MF2_E32, 1192 }, { PseudoVFWADD_VV_M1_E16, 1193 }, { PseudoVFWADD_VV_M1_E32, 1194 }, { PseudoVFWADD_VV_M2_E16, 1195 }, { PseudoVFWADD_VV_M2_E32, 1196 }, { PseudoVFWADD_VV_M4_E16, 1197 }, { PseudoVFWADD_VV_M4_E32, 1198 }, { PseudoVFWADD_VV_MF2_E16, 1199 }, { PseudoVFWADD_VV_MF2_E32, 1200 }, { PseudoVFWADD_VV_MF4_E16, 1201 }, { PseudoVFWADD_WFPR16_M1_E16, 1202 }, { PseudoVFWADD_WFPR16_M2_E16, 1203 }, { PseudoVFWADD_WFPR16_M4_E16, 1204 }, { PseudoVFWADD_WFPR16_MF2_E16, 1205 }, { PseudoVFWADD_WFPR16_MF4_E16, 1206 }, { PseudoVFWADD_WFPR32_M1_E32, 1207 }, { PseudoVFWADD_WFPR32_M2_E32, 1208 }, { PseudoVFWADD_WFPR32_M4_E32, 1209 }, { PseudoVFWADD_WFPR32_MF2_E32, 1210 }, { PseudoVFWADD_WV_M1_E16, 1211 }, { PseudoVFWADD_WV_M1_E16_TIED, 1212 }, { PseudoVFWADD_WV_M1_E32, 1213 }, { PseudoVFWADD_WV_M1_E32_TIED, 1214 }, { PseudoVFWADD_WV_M2_E16, 1215 }, { PseudoVFWADD_WV_M2_E16_TIED, 1216 }, { PseudoVFWADD_WV_M2_E32, 1217 }, { PseudoVFWADD_WV_M2_E32_TIED, 1218 }, { PseudoVFWADD_WV_M4_E16, 1219 }, { PseudoVFWADD_WV_M4_E16_TIED, 1220 }, { PseudoVFWADD_WV_M4_E32, 1221 }, { PseudoVFWADD_WV_M4_E32_TIED, 1222 }, { PseudoVFWADD_WV_MF2_E16, 1223 }, { PseudoVFWADD_WV_MF2_E16_TIED, 1224 }, { PseudoVFWADD_WV_MF2_E32, 1225 }, { PseudoVFWADD_WV_MF2_E32_TIED, 1226 }, { PseudoVFWADD_WV_MF4_E16, 1227 }, { PseudoVFWADD_WV_MF4_E16_TIED, 1228 }, { PseudoVFWCVTBF16_F_F_V_M1_E16, 1229 }, { PseudoVFWCVTBF16_F_F_V_M1_E32, 1230 }, { PseudoVFWCVTBF16_F_F_V_M2_E16, 1231 }, { PseudoVFWCVTBF16_F_F_V_M2_E32, 1232 }, { PseudoVFWCVTBF16_F_F_V_M4_E16, 1233 }, { PseudoVFWCVTBF16_F_F_V_M4_E32, 1234 }, { PseudoVFWCVTBF16_F_F_V_MF2_E16, 1235 }, { PseudoVFWCVTBF16_F_F_V_MF2_E32, 1236 }, { PseudoVFWCVTBF16_F_F_V_MF4_E16, 1237 }, { PseudoVFWCVT_F_F_V_M1_E16, 1238 }, { PseudoVFWCVT_F_F_V_M1_E32, 1239 }, { PseudoVFWCVT_F_F_V_M2_E16, 1240 }, { PseudoVFWCVT_F_F_V_M2_E32, 1241 }, { PseudoVFWCVT_F_F_V_M4_E16, 1242 }, { PseudoVFWCVT_F_F_V_M4_E32, 1243 }, { PseudoVFWCVT_F_F_V_MF2_E16, 1244 }, { PseudoVFWCVT_F_F_V_MF2_E32, 1245 }, { PseudoVFWCVT_F_F_V_MF4_E16, 1246 }, { PseudoVFWCVT_F_XU_V_M1_E16, 1247 }, { PseudoVFWCVT_F_XU_V_M1_E32, 1248 }, { PseudoVFWCVT_F_XU_V_M1_E8, 1249 }, { PseudoVFWCVT_F_XU_V_M2_E16, 1250 }, { PseudoVFWCVT_F_XU_V_M2_E32, 1251 }, { PseudoVFWCVT_F_XU_V_M2_E8, 1252 }, { PseudoVFWCVT_F_XU_V_M4_E16, 1253 }, { PseudoVFWCVT_F_XU_V_M4_E32, 1254 }, { PseudoVFWCVT_F_XU_V_M4_E8, 1255 }, { PseudoVFWCVT_F_XU_V_MF2_E16, 1256 }, { PseudoVFWCVT_F_XU_V_MF2_E32, 1257 }, { PseudoVFWCVT_F_XU_V_MF2_E8, 1258 }, { PseudoVFWCVT_F_XU_V_MF4_E16, 1259 }, { PseudoVFWCVT_F_XU_V_MF4_E8, 1260 }, { PseudoVFWCVT_F_XU_V_MF8_E8, 1261 }, { PseudoVFWCVT_F_X_V_M1_E16, 1262 }, { PseudoVFWCVT_F_X_V_M1_E32, 1263 }, { PseudoVFWCVT_F_X_V_M1_E8, 1264 }, { PseudoVFWCVT_F_X_V_M2_E16, 1265 }, { PseudoVFWCVT_F_X_V_M2_E32, 1266 }, { PseudoVFWCVT_F_X_V_M2_E8, 1267 }, { PseudoVFWCVT_F_X_V_M4_E16, 1268 }, { PseudoVFWCVT_F_X_V_M4_E32, 1269 }, { PseudoVFWCVT_F_X_V_M4_E8, 1270 }, { PseudoVFWCVT_F_X_V_MF2_E16, 1271 }, { PseudoVFWCVT_F_X_V_MF2_E32, 1272 }, { PseudoVFWCVT_F_X_V_MF2_E8, 1273 }, { PseudoVFWCVT_F_X_V_MF4_E16, 1274 }, { PseudoVFWCVT_F_X_V_MF4_E8, 1275 }, { PseudoVFWCVT_F_X_V_MF8_E8, 1276 }, { PseudoVFWCVT_RM_XU_F_V_M1, 1277 }, { PseudoVFWCVT_RM_XU_F_V_M2, 1278 }, { PseudoVFWCVT_RM_XU_F_V_M4, 1279 }, { PseudoVFWCVT_RM_XU_F_V_MF2, 1280 }, { PseudoVFWCVT_RM_XU_F_V_MF4, 1281 }, { PseudoVFWCVT_RM_X_F_V_M1, 1282 }, { PseudoVFWCVT_RM_X_F_V_M2, 1283 }, { PseudoVFWCVT_RM_X_F_V_M4, 1284 }, { PseudoVFWCVT_RM_X_F_V_MF2, 1285 }, { PseudoVFWCVT_RM_X_F_V_MF4, 1286 }, { PseudoVFWCVT_RTZ_XU_F_V_M1, 1287 }, { PseudoVFWCVT_RTZ_XU_F_V_M2, 1288 }, { PseudoVFWCVT_RTZ_XU_F_V_M4, 1289 }, { PseudoVFWCVT_RTZ_XU_F_V_MF2, 1290 }, { PseudoVFWCVT_RTZ_XU_F_V_MF4, 1291 }, { PseudoVFWCVT_RTZ_X_F_V_M1, 1292 }, { PseudoVFWCVT_RTZ_X_F_V_M2, 1293 }, { PseudoVFWCVT_RTZ_X_F_V_M4, 1294 }, { PseudoVFWCVT_RTZ_X_F_V_MF2, 1295 }, { PseudoVFWCVT_RTZ_X_F_V_MF4, 1296 }, { PseudoVFWCVT_XU_F_V_M1, 1297 }, { PseudoVFWCVT_XU_F_V_M2, 1298 }, { PseudoVFWCVT_XU_F_V_M4, 1299 }, { PseudoVFWCVT_XU_F_V_MF2, 1300 }, { PseudoVFWCVT_XU_F_V_MF4, 1301 }, { PseudoVFWCVT_X_F_V_M1, 1302 }, { PseudoVFWCVT_X_F_V_M2, 1303 }, { PseudoVFWCVT_X_F_V_M4, 1304 }, { PseudoVFWCVT_X_F_V_MF2, 1305 }, { PseudoVFWCVT_X_F_V_MF4, 1306 }, { PseudoVFWMACCBF16_VFPR16_M1_E16, 1307 }, { PseudoVFWMACCBF16_VFPR16_M2_E16, 1308 }, { PseudoVFWMACCBF16_VFPR16_M4_E16, 1309 }, { PseudoVFWMACCBF16_VFPR16_MF2_E16, 1310 }, { PseudoVFWMACCBF16_VFPR16_MF4_E16, 1311 }, { PseudoVFWMACCBF16_VV_M1_E16, 1312 }, { PseudoVFWMACCBF16_VV_M1_E32, 1313 }, { PseudoVFWMACCBF16_VV_M2_E16, 1314 }, { PseudoVFWMACCBF16_VV_M2_E32, 1315 }, { PseudoVFWMACCBF16_VV_M4_E16, 1316 }, { PseudoVFWMACCBF16_VV_M4_E32, 1317 }, { PseudoVFWMACCBF16_VV_MF2_E16, 1318 }, { PseudoVFWMACCBF16_VV_MF2_E32, 1319 }, { PseudoVFWMACCBF16_VV_MF4_E16, 1320 }, { PseudoVFWMACC_VFPR16_M1_E16, 1321 }, { PseudoVFWMACC_VFPR16_M2_E16, 1322 }, { PseudoVFWMACC_VFPR16_M4_E16, 1323 }, { PseudoVFWMACC_VFPR16_MF2_E16, 1324 }, { PseudoVFWMACC_VFPR16_MF4_E16, 1325 }, { PseudoVFWMACC_VFPR32_M1_E32, 1326 }, { PseudoVFWMACC_VFPR32_M2_E32, 1327 }, { PseudoVFWMACC_VFPR32_M4_E32, 1328 }, { PseudoVFWMACC_VFPR32_MF2_E32, 1329 }, { PseudoVFWMACC_VV_M1_E16, 1330 }, { PseudoVFWMACC_VV_M1_E32, 1331 }, { PseudoVFWMACC_VV_M2_E16, 1332 }, { PseudoVFWMACC_VV_M2_E32, 1333 }, { PseudoVFWMACC_VV_M4_E16, 1334 }, { PseudoVFWMACC_VV_M4_E32, 1335 }, { PseudoVFWMACC_VV_MF2_E16, 1336 }, { PseudoVFWMACC_VV_MF2_E32, 1337 }, { PseudoVFWMACC_VV_MF4_E16, 1338 }, { PseudoVFWMSAC_VFPR16_M1_E16, 1339 }, { PseudoVFWMSAC_VFPR16_M2_E16, 1340 }, { PseudoVFWMSAC_VFPR16_M4_E16, 1341 }, { PseudoVFWMSAC_VFPR16_MF2_E16, 1342 }, { PseudoVFWMSAC_VFPR16_MF4_E16, 1343 }, { PseudoVFWMSAC_VFPR32_M1_E32, 1344 }, { PseudoVFWMSAC_VFPR32_M2_E32, 1345 }, { PseudoVFWMSAC_VFPR32_M4_E32, 1346 }, { PseudoVFWMSAC_VFPR32_MF2_E32, 1347 }, { PseudoVFWMSAC_VV_M1_E16, 1348 }, { PseudoVFWMSAC_VV_M1_E32, 1349 }, { PseudoVFWMSAC_VV_M2_E16, 1350 }, { PseudoVFWMSAC_VV_M2_E32, 1351 }, { PseudoVFWMSAC_VV_M4_E16, 1352 }, { PseudoVFWMSAC_VV_M4_E32, 1353 }, { PseudoVFWMSAC_VV_MF2_E16, 1354 }, { PseudoVFWMSAC_VV_MF2_E32, 1355 }, { PseudoVFWMSAC_VV_MF4_E16, 1356 }, { PseudoVFWMUL_VFPR16_M1_E16, 1357 }, { PseudoVFWMUL_VFPR16_M2_E16, 1358 }, { PseudoVFWMUL_VFPR16_M4_E16, 1359 }, { PseudoVFWMUL_VFPR16_MF2_E16, 1360 }, { PseudoVFWMUL_VFPR16_MF4_E16, 1361 }, { PseudoVFWMUL_VFPR32_M1_E32, 1362 }, { PseudoVFWMUL_VFPR32_M2_E32, 1363 }, { PseudoVFWMUL_VFPR32_M4_E32, 1364 }, { PseudoVFWMUL_VFPR32_MF2_E32, 1365 }, { PseudoVFWMUL_VV_M1_E16, 1366 }, { PseudoVFWMUL_VV_M1_E32, 1367 }, { PseudoVFWMUL_VV_M2_E16, 1368 }, { PseudoVFWMUL_VV_M2_E32, 1369 }, { PseudoVFWMUL_VV_M4_E16, 1370 }, { PseudoVFWMUL_VV_M4_E32, 1371 }, { PseudoVFWMUL_VV_MF2_E16, 1372 }, { PseudoVFWMUL_VV_MF2_E32, 1373 }, { PseudoVFWMUL_VV_MF4_E16, 1374 }, { PseudoVFWNMACC_VFPR16_M1_E16, 1375 }, { PseudoVFWNMACC_VFPR16_M2_E16, 1376 }, { PseudoVFWNMACC_VFPR16_M4_E16, 1377 }, { PseudoVFWNMACC_VFPR16_MF2_E16, 1378 }, { PseudoVFWNMACC_VFPR16_MF4_E16, 1379 }, { PseudoVFWNMACC_VFPR32_M1_E32, 1380 }, { PseudoVFWNMACC_VFPR32_M2_E32, 1381 }, { PseudoVFWNMACC_VFPR32_M4_E32, 1382 }, { PseudoVFWNMACC_VFPR32_MF2_E32, 1383 }, { PseudoVFWNMACC_VV_M1_E16, 1384 }, { PseudoVFWNMACC_VV_M1_E32, 1385 }, { PseudoVFWNMACC_VV_M2_E16, 1386 }, { PseudoVFWNMACC_VV_M2_E32, 1387 }, { PseudoVFWNMACC_VV_M4_E16, 1388 }, { PseudoVFWNMACC_VV_M4_E32, 1389 }, { PseudoVFWNMACC_VV_MF2_E16, 1390 }, { PseudoVFWNMACC_VV_MF2_E32, 1391 }, { PseudoVFWNMACC_VV_MF4_E16, 1392 }, { PseudoVFWNMSAC_VFPR16_M1_E16, 1393 }, { PseudoVFWNMSAC_VFPR16_M2_E16, 1394 }, { PseudoVFWNMSAC_VFPR16_M4_E16, 1395 }, { PseudoVFWNMSAC_VFPR16_MF2_E16, 1396 }, { PseudoVFWNMSAC_VFPR16_MF4_E16, 1397 }, { PseudoVFWNMSAC_VFPR32_M1_E32, 1398 }, { PseudoVFWNMSAC_VFPR32_M2_E32, 1399 }, { PseudoVFWNMSAC_VFPR32_M4_E32, 1400 }, { PseudoVFWNMSAC_VFPR32_MF2_E32, 1401 }, { PseudoVFWNMSAC_VV_M1_E16, 1402 }, { PseudoVFWNMSAC_VV_M1_E32, 1403 }, { PseudoVFWNMSAC_VV_M2_E16, 1404 }, { PseudoVFWNMSAC_VV_M2_E32, 1405 }, { PseudoVFWNMSAC_VV_M4_E16, 1406 }, { PseudoVFWNMSAC_VV_M4_E32, 1407 }, { PseudoVFWNMSAC_VV_MF2_E16, 1408 }, { PseudoVFWNMSAC_VV_MF2_E32, 1409 }, { PseudoVFWNMSAC_VV_MF4_E16, 1410 }, { PseudoVFWREDOSUM_VS_M1_E16, 1411 }, { PseudoVFWREDOSUM_VS_M1_E32, 1412 }, { PseudoVFWREDOSUM_VS_M2_E16, 1413 }, { PseudoVFWREDOSUM_VS_M2_E32, 1414 }, { PseudoVFWREDOSUM_VS_M4_E16, 1415 }, { PseudoVFWREDOSUM_VS_M4_E32, 1416 }, { PseudoVFWREDOSUM_VS_M8_E16, 1417 }, { PseudoVFWREDOSUM_VS_M8_E32, 1418 }, { PseudoVFWREDOSUM_VS_MF2_E16, 1419 }, { PseudoVFWREDOSUM_VS_MF2_E32, 1420 }, { PseudoVFWREDOSUM_VS_MF4_E16, 1421 }, { PseudoVFWREDUSUM_VS_M1_E16, 1422 }, { PseudoVFWREDUSUM_VS_M1_E32, 1423 }, { PseudoVFWREDUSUM_VS_M2_E16, 1424 }, { PseudoVFWREDUSUM_VS_M2_E32, 1425 }, { PseudoVFWREDUSUM_VS_M4_E16, 1426 }, { PseudoVFWREDUSUM_VS_M4_E32, 1427 }, { PseudoVFWREDUSUM_VS_M8_E16, 1428 }, { PseudoVFWREDUSUM_VS_M8_E32, 1429 }, { PseudoVFWREDUSUM_VS_MF2_E16, 1430 }, { PseudoVFWREDUSUM_VS_MF2_E32, 1431 }, { PseudoVFWREDUSUM_VS_MF4_E16, 1432 }, { PseudoVFWSUB_VFPR16_M1_E16, 1433 }, { PseudoVFWSUB_VFPR16_M2_E16, 1434 }, { PseudoVFWSUB_VFPR16_M4_E16, 1435 }, { PseudoVFWSUB_VFPR16_MF2_E16, 1436 }, { PseudoVFWSUB_VFPR16_MF4_E16, 1437 }, { PseudoVFWSUB_VFPR32_M1_E32, 1438 }, { PseudoVFWSUB_VFPR32_M2_E32, 1439 }, { PseudoVFWSUB_VFPR32_M4_E32, 1440 }, { PseudoVFWSUB_VFPR32_MF2_E32, 1441 }, { PseudoVFWSUB_VV_M1_E16, 1442 }, { PseudoVFWSUB_VV_M1_E32, 1443 }, { PseudoVFWSUB_VV_M2_E16, 1444 }, { PseudoVFWSUB_VV_M2_E32, 1445 }, { PseudoVFWSUB_VV_M4_E16, 1446 }, { PseudoVFWSUB_VV_M4_E32, 1447 }, { PseudoVFWSUB_VV_MF2_E16, 1448 }, { PseudoVFWSUB_VV_MF2_E32, 1449 }, { PseudoVFWSUB_VV_MF4_E16, 1450 }, { PseudoVFWSUB_WFPR16_M1_E16, 1451 }, { PseudoVFWSUB_WFPR16_M2_E16, 1452 }, { PseudoVFWSUB_WFPR16_M4_E16, 1453 }, { PseudoVFWSUB_WFPR16_MF2_E16, 1454 }, { PseudoVFWSUB_WFPR16_MF4_E16, 1455 }, { PseudoVFWSUB_WFPR32_M1_E32, 1456 }, { PseudoVFWSUB_WFPR32_M2_E32, 1457 }, { PseudoVFWSUB_WFPR32_M4_E32, 1458 }, { PseudoVFWSUB_WFPR32_MF2_E32, 1459 }, { PseudoVFWSUB_WV_M1_E16, 1460 }, { PseudoVFWSUB_WV_M1_E16_TIED, 1461 }, { PseudoVFWSUB_WV_M1_E32, 1462 }, { PseudoVFWSUB_WV_M1_E32_TIED, 1463 }, { PseudoVFWSUB_WV_M2_E16, 1464 }, { PseudoVFWSUB_WV_M2_E16_TIED, 1465 }, { PseudoVFWSUB_WV_M2_E32, 1466 }, { PseudoVFWSUB_WV_M2_E32_TIED, 1467 }, { PseudoVFWSUB_WV_M4_E16, 1468 }, { PseudoVFWSUB_WV_M4_E16_TIED, 1469 }, { PseudoVFWSUB_WV_M4_E32, 1470 }, { PseudoVFWSUB_WV_M4_E32_TIED, 1471 }, { PseudoVFWSUB_WV_MF2_E16, 1472 }, { PseudoVFWSUB_WV_MF2_E16_TIED, 1473 }, { PseudoVFWSUB_WV_MF2_E32, 1474 }, { PseudoVFWSUB_WV_MF2_E32_TIED, 1475 }, { PseudoVFWSUB_WV_MF4_E16, 1476 }, { PseudoVFWSUB_WV_MF4_E16_TIED, 1477 }, { PseudoVID_V_M1, 1478 }, { PseudoVID_V_M2, 1479 }, { PseudoVID_V_M4, 1480 }, { PseudoVID_V_M8, 1481 }, { PseudoVID_V_MF2, 1482 }, { PseudoVID_V_MF4, 1483 }, { PseudoVID_V_MF8, 1484 }, { PseudoVIOTA_M_M1, 1485 }, { PseudoVIOTA_M_M2, 1486 }, { PseudoVIOTA_M_M4, 1487 }, { PseudoVIOTA_M_M8, 1488 }, { PseudoVIOTA_M_MF2, 1489 }, { PseudoVIOTA_M_MF4, 1490 }, { PseudoVIOTA_M_MF8, 1491 }, { PseudoVLE16FF_V_M1, 1492 }, { PseudoVLE16FF_V_M2, 1493 }, { PseudoVLE16FF_V_M4, 1494 }, { PseudoVLE16FF_V_M8, 1495 }, { PseudoVLE16FF_V_MF2, 1496 }, { PseudoVLE16FF_V_MF4, 1497 }, { PseudoVLE16_V_M1, 1498 }, { PseudoVLE16_V_M2, 1499 }, { PseudoVLE16_V_M4, 1500 }, { PseudoVLE16_V_M8, 1501 }, { PseudoVLE16_V_MF2, 1502 }, { PseudoVLE16_V_MF4, 1503 }, { PseudoVLE32FF_V_M1, 1504 }, { PseudoVLE32FF_V_M2, 1505 }, { PseudoVLE32FF_V_M4, 1506 }, { PseudoVLE32FF_V_M8, 1507 }, { PseudoVLE32FF_V_MF2, 1508 }, { PseudoVLE32_V_M1, 1509 }, { PseudoVLE32_V_M2, 1510 }, { PseudoVLE32_V_M4, 1511 }, { PseudoVLE32_V_M8, 1512 }, { PseudoVLE32_V_MF2, 1513 }, { PseudoVLE64FF_V_M1, 1514 }, { PseudoVLE64FF_V_M2, 1515 }, { PseudoVLE64FF_V_M4, 1516 }, { PseudoVLE64FF_V_M8, 1517 }, { PseudoVLE64_V_M1, 1518 }, { PseudoVLE64_V_M2, 1519 }, { PseudoVLE64_V_M4, 1520 }, { PseudoVLE64_V_M8, 1521 }, { PseudoVLE8FF_V_M1, 1522 }, { PseudoVLE8FF_V_M2, 1523 }, { PseudoVLE8FF_V_M4, 1524 }, { PseudoVLE8FF_V_M8, 1525 }, { PseudoVLE8FF_V_MF2, 1526 }, { PseudoVLE8FF_V_MF4, 1527 }, { PseudoVLE8FF_V_MF8, 1528 }, { PseudoVLE8_V_M1, 1529 }, { PseudoVLE8_V_M2, 1530 }, { PseudoVLE8_V_M4, 1531 }, { PseudoVLE8_V_M8, 1532 }, { PseudoVLE8_V_MF2, 1533 }, { PseudoVLE8_V_MF4, 1534 }, { PseudoVLE8_V_MF8, 1535 }, { PseudoVLOXEI16_V_M1_M1, 1536 }, { PseudoVLOXEI16_V_M1_M2, 1537 }, { PseudoVLOXEI16_V_M1_M4, 1538 }, { PseudoVLOXEI16_V_M1_MF2, 1539 }, { PseudoVLOXEI16_V_M2_M1, 1540 }, { PseudoVLOXEI16_V_M2_M2, 1541 }, { PseudoVLOXEI16_V_M2_M4, 1542 }, { PseudoVLOXEI16_V_M2_M8, 1543 }, { PseudoVLOXEI16_V_M4_M2, 1544 }, { PseudoVLOXEI16_V_M4_M4, 1545 }, { PseudoVLOXEI16_V_M4_M8, 1546 }, { PseudoVLOXEI16_V_M8_M4, 1547 }, { PseudoVLOXEI16_V_M8_M8, 1548 }, { PseudoVLOXEI16_V_MF2_M1, 1549 }, { PseudoVLOXEI16_V_MF2_M2, 1550 }, { PseudoVLOXEI16_V_MF2_MF2, 1551 }, { PseudoVLOXEI16_V_MF2_MF4, 1552 }, { PseudoVLOXEI16_V_MF4_M1, 1553 }, { PseudoVLOXEI16_V_MF4_MF2, 1554 }, { PseudoVLOXEI16_V_MF4_MF4, 1555 }, { PseudoVLOXEI16_V_MF4_MF8, 1556 }, { PseudoVLOXEI32_V_M1_M1, 1557 }, { PseudoVLOXEI32_V_M1_M2, 1558 }, { PseudoVLOXEI32_V_M1_MF2, 1559 }, { PseudoVLOXEI32_V_M1_MF4, 1560 }, { PseudoVLOXEI32_V_M2_M1, 1561 }, { PseudoVLOXEI32_V_M2_M2, 1562 }, { PseudoVLOXEI32_V_M2_M4, 1563 }, { PseudoVLOXEI32_V_M2_MF2, 1564 }, { PseudoVLOXEI32_V_M4_M1, 1565 }, { PseudoVLOXEI32_V_M4_M2, 1566 }, { PseudoVLOXEI32_V_M4_M4, 1567 }, { PseudoVLOXEI32_V_M4_M8, 1568 }, { PseudoVLOXEI32_V_M8_M2, 1569 }, { PseudoVLOXEI32_V_M8_M4, 1570 }, { PseudoVLOXEI32_V_M8_M8, 1571 }, { PseudoVLOXEI32_V_MF2_M1, 1572 }, { PseudoVLOXEI32_V_MF2_MF2, 1573 }, { PseudoVLOXEI32_V_MF2_MF4, 1574 }, { PseudoVLOXEI32_V_MF2_MF8, 1575 }, { PseudoVLOXEI64_V_M1_M1, 1576 }, { PseudoVLOXEI64_V_M1_MF2, 1577 }, { PseudoVLOXEI64_V_M1_MF4, 1578 }, { PseudoVLOXEI64_V_M1_MF8, 1579 }, { PseudoVLOXEI64_V_M2_M1, 1580 }, { PseudoVLOXEI64_V_M2_M2, 1581 }, { PseudoVLOXEI64_V_M2_MF2, 1582 }, { PseudoVLOXEI64_V_M2_MF4, 1583 }, { PseudoVLOXEI64_V_M4_M1, 1584 }, { PseudoVLOXEI64_V_M4_M2, 1585 }, { PseudoVLOXEI64_V_M4_M4, 1586 }, { PseudoVLOXEI64_V_M4_MF2, 1587 }, { PseudoVLOXEI64_V_M8_M1, 1588 }, { PseudoVLOXEI64_V_M8_M2, 1589 }, { PseudoVLOXEI64_V_M8_M4, 1590 }, { PseudoVLOXEI64_V_M8_M8, 1591 }, { PseudoVLOXEI8_V_M1_M1, 1592 }, { PseudoVLOXEI8_V_M1_M2, 1593 }, { PseudoVLOXEI8_V_M1_M4, 1594 }, { PseudoVLOXEI8_V_M1_M8, 1595 }, { PseudoVLOXEI8_V_M2_M2, 1596 }, { PseudoVLOXEI8_V_M2_M4, 1597 }, { PseudoVLOXEI8_V_M2_M8, 1598 }, { PseudoVLOXEI8_V_M4_M4, 1599 }, { PseudoVLOXEI8_V_M4_M8, 1600 }, { PseudoVLOXEI8_V_M8_M8, 1601 }, { PseudoVLOXEI8_V_MF2_M1, 1602 }, { PseudoVLOXEI8_V_MF2_M2, 1603 }, { PseudoVLOXEI8_V_MF2_M4, 1604 }, { PseudoVLOXEI8_V_MF2_MF2, 1605 }, { PseudoVLOXEI8_V_MF4_M1, 1606 }, { PseudoVLOXEI8_V_MF4_M2, 1607 }, { PseudoVLOXEI8_V_MF4_MF2, 1608 }, { PseudoVLOXEI8_V_MF4_MF4, 1609 }, { PseudoVLOXEI8_V_MF8_M1, 1610 }, { PseudoVLOXEI8_V_MF8_MF2, 1611 }, { PseudoVLOXEI8_V_MF8_MF4, 1612 }, { PseudoVLOXEI8_V_MF8_MF8, 1613 }, { PseudoVLSE16_V_M1, 1614 }, { PseudoVLSE16_V_M2, 1615 }, { PseudoVLSE16_V_M4, 1616 }, { PseudoVLSE16_V_M8, 1617 }, { PseudoVLSE16_V_MF2, 1618 }, { PseudoVLSE16_V_MF4, 1619 }, { PseudoVLSE32_V_M1, 1620 }, { PseudoVLSE32_V_M2, 1621 }, { PseudoVLSE32_V_M4, 1622 }, { PseudoVLSE32_V_M8, 1623 }, { PseudoVLSE32_V_MF2, 1624 }, { PseudoVLSE64_V_M1, 1625 }, { PseudoVLSE64_V_M2, 1626 }, { PseudoVLSE64_V_M4, 1627 }, { PseudoVLSE64_V_M8, 1628 }, { PseudoVLSE8_V_M1, 1629 }, { PseudoVLSE8_V_M2, 1630 }, { PseudoVLSE8_V_M4, 1631 }, { PseudoVLSE8_V_M8, 1632 }, { PseudoVLSE8_V_MF2, 1633 }, { PseudoVLSE8_V_MF4, 1634 }, { PseudoVLSE8_V_MF8, 1635 }, { PseudoVLUXEI16_V_M1_M1, 1636 }, { PseudoVLUXEI16_V_M1_M2, 1637 }, { PseudoVLUXEI16_V_M1_M4, 1638 }, { PseudoVLUXEI16_V_M1_MF2, 1639 }, { PseudoVLUXEI16_V_M2_M1, 1640 }, { PseudoVLUXEI16_V_M2_M2, 1641 }, { PseudoVLUXEI16_V_M2_M4, 1642 }, { PseudoVLUXEI16_V_M2_M8, 1643 }, { PseudoVLUXEI16_V_M4_M2, 1644 }, { PseudoVLUXEI16_V_M4_M4, 1645 }, { PseudoVLUXEI16_V_M4_M8, 1646 }, { PseudoVLUXEI16_V_M8_M4, 1647 }, { PseudoVLUXEI16_V_M8_M8, 1648 }, { PseudoVLUXEI16_V_MF2_M1, 1649 }, { PseudoVLUXEI16_V_MF2_M2, 1650 }, { PseudoVLUXEI16_V_MF2_MF2, 1651 }, { PseudoVLUXEI16_V_MF2_MF4, 1652 }, { PseudoVLUXEI16_V_MF4_M1, 1653 }, { PseudoVLUXEI16_V_MF4_MF2, 1654 }, { PseudoVLUXEI16_V_MF4_MF4, 1655 }, { PseudoVLUXEI16_V_MF4_MF8, 1656 }, { PseudoVLUXEI32_V_M1_M1, 1657 }, { PseudoVLUXEI32_V_M1_M2, 1658 }, { PseudoVLUXEI32_V_M1_MF2, 1659 }, { PseudoVLUXEI32_V_M1_MF4, 1660 }, { PseudoVLUXEI32_V_M2_M1, 1661 }, { PseudoVLUXEI32_V_M2_M2, 1662 }, { PseudoVLUXEI32_V_M2_M4, 1663 }, { PseudoVLUXEI32_V_M2_MF2, 1664 }, { PseudoVLUXEI32_V_M4_M1, 1665 }, { PseudoVLUXEI32_V_M4_M2, 1666 }, { PseudoVLUXEI32_V_M4_M4, 1667 }, { PseudoVLUXEI32_V_M4_M8, 1668 }, { PseudoVLUXEI32_V_M8_M2, 1669 }, { PseudoVLUXEI32_V_M8_M4, 1670 }, { PseudoVLUXEI32_V_M8_M8, 1671 }, { PseudoVLUXEI32_V_MF2_M1, 1672 }, { PseudoVLUXEI32_V_MF2_MF2, 1673 }, { PseudoVLUXEI32_V_MF2_MF4, 1674 }, { PseudoVLUXEI32_V_MF2_MF8, 1675 }, { PseudoVLUXEI64_V_M1_M1, 1676 }, { PseudoVLUXEI64_V_M1_MF2, 1677 }, { PseudoVLUXEI64_V_M1_MF4, 1678 }, { PseudoVLUXEI64_V_M1_MF8, 1679 }, { PseudoVLUXEI64_V_M2_M1, 1680 }, { PseudoVLUXEI64_V_M2_M2, 1681 }, { PseudoVLUXEI64_V_M2_MF2, 1682 }, { PseudoVLUXEI64_V_M2_MF4, 1683 }, { PseudoVLUXEI64_V_M4_M1, 1684 }, { PseudoVLUXEI64_V_M4_M2, 1685 }, { PseudoVLUXEI64_V_M4_M4, 1686 }, { PseudoVLUXEI64_V_M4_MF2, 1687 }, { PseudoVLUXEI64_V_M8_M1, 1688 }, { PseudoVLUXEI64_V_M8_M2, 1689 }, { PseudoVLUXEI64_V_M8_M4, 1690 }, { PseudoVLUXEI64_V_M8_M8, 1691 }, { PseudoVLUXEI8_V_M1_M1, 1692 }, { PseudoVLUXEI8_V_M1_M2, 1693 }, { PseudoVLUXEI8_V_M1_M4, 1694 }, { PseudoVLUXEI8_V_M1_M8, 1695 }, { PseudoVLUXEI8_V_M2_M2, 1696 }, { PseudoVLUXEI8_V_M2_M4, 1697 }, { PseudoVLUXEI8_V_M2_M8, 1698 }, { PseudoVLUXEI8_V_M4_M4, 1699 }, { PseudoVLUXEI8_V_M4_M8, 1700 }, { PseudoVLUXEI8_V_M8_M8, 1701 }, { PseudoVLUXEI8_V_MF2_M1, 1702 }, { PseudoVLUXEI8_V_MF2_M2, 1703 }, { PseudoVLUXEI8_V_MF2_M4, 1704 }, { PseudoVLUXEI8_V_MF2_MF2, 1705 }, { PseudoVLUXEI8_V_MF4_M1, 1706 }, { PseudoVLUXEI8_V_MF4_M2, 1707 }, { PseudoVLUXEI8_V_MF4_MF2, 1708 }, { PseudoVLUXEI8_V_MF4_MF4, 1709 }, { PseudoVLUXEI8_V_MF8_M1, 1710 }, { PseudoVLUXEI8_V_MF8_MF2, 1711 }, { PseudoVLUXEI8_V_MF8_MF4, 1712 }, { PseudoVLUXEI8_V_MF8_MF8, 1713 }, { PseudoVMACC_VV_M1, 1714 }, { PseudoVMACC_VV_M2, 1715 }, { PseudoVMACC_VV_M4, 1716 }, { PseudoVMACC_VV_M8, 1717 }, { PseudoVMACC_VV_MF2, 1718 }, { PseudoVMACC_VV_MF4, 1719 }, { PseudoVMACC_VV_MF8, 1720 }, { PseudoVMACC_VX_M1, 1721 }, { PseudoVMACC_VX_M2, 1722 }, { PseudoVMACC_VX_M4, 1723 }, { PseudoVMACC_VX_M8, 1724 }, { PseudoVMACC_VX_MF2, 1725 }, { PseudoVMACC_VX_MF4, 1726 }, { PseudoVMACC_VX_MF8, 1727 }, { PseudoVMADD_VV_M1, 1728 }, { PseudoVMADD_VV_M2, 1729 }, { PseudoVMADD_VV_M4, 1730 }, { PseudoVMADD_VV_M8, 1731 }, { PseudoVMADD_VV_MF2, 1732 }, { PseudoVMADD_VV_MF4, 1733 }, { PseudoVMADD_VV_MF8, 1734 }, { PseudoVMADD_VX_M1, 1735 }, { PseudoVMADD_VX_M2, 1736 }, { PseudoVMADD_VX_M4, 1737 }, { PseudoVMADD_VX_M8, 1738 }, { PseudoVMADD_VX_MF2, 1739 }, { PseudoVMADD_VX_MF4, 1740 }, { PseudoVMADD_VX_MF8, 1741 }, { PseudoVMAXU_VV_M1, 1742 }, { PseudoVMAXU_VV_M2, 1743 }, { PseudoVMAXU_VV_M4, 1744 }, { PseudoVMAXU_VV_M8, 1745 }, { PseudoVMAXU_VV_MF2, 1746 }, { PseudoVMAXU_VV_MF4, 1747 }, { PseudoVMAXU_VV_MF8, 1748 }, { PseudoVMAXU_VX_M1, 1749 }, { PseudoVMAXU_VX_M2, 1750 }, { PseudoVMAXU_VX_M4, 1751 }, { PseudoVMAXU_VX_M8, 1752 }, { PseudoVMAXU_VX_MF2, 1753 }, { PseudoVMAXU_VX_MF4, 1754 }, { PseudoVMAXU_VX_MF8, 1755 }, { PseudoVMAX_VV_M1, 1756 }, { PseudoVMAX_VV_M2, 1757 }, { PseudoVMAX_VV_M4, 1758 }, { PseudoVMAX_VV_M8, 1759 }, { PseudoVMAX_VV_MF2, 1760 }, { PseudoVMAX_VV_MF4, 1761 }, { PseudoVMAX_VV_MF8, 1762 }, { PseudoVMAX_VX_M1, 1763 }, { PseudoVMAX_VX_M2, 1764 }, { PseudoVMAX_VX_M4, 1765 }, { PseudoVMAX_VX_M8, 1766 }, { PseudoVMAX_VX_MF2, 1767 }, { PseudoVMAX_VX_MF4, 1768 }, { PseudoVMAX_VX_MF8, 1769 }, { PseudoVMFEQ_VFPR16_M1, 1770 }, { PseudoVMFEQ_VFPR16_M2, 1771 }, { PseudoVMFEQ_VFPR16_M4, 1772 }, { PseudoVMFEQ_VFPR16_M8, 1773 }, { PseudoVMFEQ_VFPR16_MF2, 1774 }, { PseudoVMFEQ_VFPR16_MF4, 1775 }, { PseudoVMFEQ_VFPR32_M1, 1776 }, { PseudoVMFEQ_VFPR32_M2, 1777 }, { PseudoVMFEQ_VFPR32_M4, 1778 }, { PseudoVMFEQ_VFPR32_M8, 1779 }, { PseudoVMFEQ_VFPR32_MF2, 1780 }, { PseudoVMFEQ_VFPR64_M1, 1781 }, { PseudoVMFEQ_VFPR64_M2, 1782 }, { PseudoVMFEQ_VFPR64_M4, 1783 }, { PseudoVMFEQ_VFPR64_M8, 1784 }, { PseudoVMFEQ_VV_M1, 1785 }, { PseudoVMFEQ_VV_M2, 1786 }, { PseudoVMFEQ_VV_M4, 1787 }, { PseudoVMFEQ_VV_M8, 1788 }, { PseudoVMFEQ_VV_MF2, 1789 }, { PseudoVMFEQ_VV_MF4, 1790 }, { PseudoVMFGE_VFPR16_M1, 1791 }, { PseudoVMFGE_VFPR16_M2, 1792 }, { PseudoVMFGE_VFPR16_M4, 1793 }, { PseudoVMFGE_VFPR16_M8, 1794 }, { PseudoVMFGE_VFPR16_MF2, 1795 }, { PseudoVMFGE_VFPR16_MF4, 1796 }, { PseudoVMFGE_VFPR32_M1, 1797 }, { PseudoVMFGE_VFPR32_M2, 1798 }, { PseudoVMFGE_VFPR32_M4, 1799 }, { PseudoVMFGE_VFPR32_M8, 1800 }, { PseudoVMFGE_VFPR32_MF2, 1801 }, { PseudoVMFGE_VFPR64_M1, 1802 }, { PseudoVMFGE_VFPR64_M2, 1803 }, { PseudoVMFGE_VFPR64_M4, 1804 }, { PseudoVMFGE_VFPR64_M8, 1805 }, { PseudoVMFGT_VFPR16_M1, 1806 }, { PseudoVMFGT_VFPR16_M2, 1807 }, { PseudoVMFGT_VFPR16_M4, 1808 }, { PseudoVMFGT_VFPR16_M8, 1809 }, { PseudoVMFGT_VFPR16_MF2, 1810 }, { PseudoVMFGT_VFPR16_MF4, 1811 }, { PseudoVMFGT_VFPR32_M1, 1812 }, { PseudoVMFGT_VFPR32_M2, 1813 }, { PseudoVMFGT_VFPR32_M4, 1814 }, { PseudoVMFGT_VFPR32_M8, 1815 }, { PseudoVMFGT_VFPR32_MF2, 1816 }, { PseudoVMFGT_VFPR64_M1, 1817 }, { PseudoVMFGT_VFPR64_M2, 1818 }, { PseudoVMFGT_VFPR64_M4, 1819 }, { PseudoVMFGT_VFPR64_M8, 1820 }, { PseudoVMFLE_VFPR16_M1, 1821 }, { PseudoVMFLE_VFPR16_M2, 1822 }, { PseudoVMFLE_VFPR16_M4, 1823 }, { PseudoVMFLE_VFPR16_M8, 1824 }, { PseudoVMFLE_VFPR16_MF2, 1825 }, { PseudoVMFLE_VFPR16_MF4, 1826 }, { PseudoVMFLE_VFPR32_M1, 1827 }, { PseudoVMFLE_VFPR32_M2, 1828 }, { PseudoVMFLE_VFPR32_M4, 1829 }, { PseudoVMFLE_VFPR32_M8, 1830 }, { PseudoVMFLE_VFPR32_MF2, 1831 }, { PseudoVMFLE_VFPR64_M1, 1832 }, { PseudoVMFLE_VFPR64_M2, 1833 }, { PseudoVMFLE_VFPR64_M4, 1834 }, { PseudoVMFLE_VFPR64_M8, 1835 }, { PseudoVMFLE_VV_M1, 1836 }, { PseudoVMFLE_VV_M2, 1837 }, { PseudoVMFLE_VV_M4, 1838 }, { PseudoVMFLE_VV_M8, 1839 }, { PseudoVMFLE_VV_MF2, 1840 }, { PseudoVMFLE_VV_MF4, 1841 }, { PseudoVMFLT_VFPR16_M1, 1842 }, { PseudoVMFLT_VFPR16_M2, 1843 }, { PseudoVMFLT_VFPR16_M4, 1844 }, { PseudoVMFLT_VFPR16_M8, 1845 }, { PseudoVMFLT_VFPR16_MF2, 1846 }, { PseudoVMFLT_VFPR16_MF4, 1847 }, { PseudoVMFLT_VFPR32_M1, 1848 }, { PseudoVMFLT_VFPR32_M2, 1849 }, { PseudoVMFLT_VFPR32_M4, 1850 }, { PseudoVMFLT_VFPR32_M8, 1851 }, { PseudoVMFLT_VFPR32_MF2, 1852 }, { PseudoVMFLT_VFPR64_M1, 1853 }, { PseudoVMFLT_VFPR64_M2, 1854 }, { PseudoVMFLT_VFPR64_M4, 1855 }, { PseudoVMFLT_VFPR64_M8, 1856 }, { PseudoVMFLT_VV_M1, 1857 }, { PseudoVMFLT_VV_M2, 1858 }, { PseudoVMFLT_VV_M4, 1859 }, { PseudoVMFLT_VV_M8, 1860 }, { PseudoVMFLT_VV_MF2, 1861 }, { PseudoVMFLT_VV_MF4, 1862 }, { PseudoVMFNE_VFPR16_M1, 1863 }, { PseudoVMFNE_VFPR16_M2, 1864 }, { PseudoVMFNE_VFPR16_M4, 1865 }, { PseudoVMFNE_VFPR16_M8, 1866 }, { PseudoVMFNE_VFPR16_MF2, 1867 }, { PseudoVMFNE_VFPR16_MF4, 1868 }, { PseudoVMFNE_VFPR32_M1, 1869 }, { PseudoVMFNE_VFPR32_M2, 1870 }, { PseudoVMFNE_VFPR32_M4, 1871 }, { PseudoVMFNE_VFPR32_M8, 1872 }, { PseudoVMFNE_VFPR32_MF2, 1873 }, { PseudoVMFNE_VFPR64_M1, 1874 }, { PseudoVMFNE_VFPR64_M2, 1875 }, { PseudoVMFNE_VFPR64_M4, 1876 }, { PseudoVMFNE_VFPR64_M8, 1877 }, { PseudoVMFNE_VV_M1, 1878 }, { PseudoVMFNE_VV_M2, 1879 }, { PseudoVMFNE_VV_M4, 1880 }, { PseudoVMFNE_VV_M8, 1881 }, { PseudoVMFNE_VV_MF2, 1882 }, { PseudoVMFNE_VV_MF4, 1883 }, { PseudoVMINU_VV_M1, 1884 }, { PseudoVMINU_VV_M2, 1885 }, { PseudoVMINU_VV_M4, 1886 }, { PseudoVMINU_VV_M8, 1887 }, { PseudoVMINU_VV_MF2, 1888 }, { PseudoVMINU_VV_MF4, 1889 }, { PseudoVMINU_VV_MF8, 1890 }, { PseudoVMINU_VX_M1, 1891 }, { PseudoVMINU_VX_M2, 1892 }, { PseudoVMINU_VX_M4, 1893 }, { PseudoVMINU_VX_M8, 1894 }, { PseudoVMINU_VX_MF2, 1895 }, { PseudoVMINU_VX_MF4, 1896 }, { PseudoVMINU_VX_MF8, 1897 }, { PseudoVMIN_VV_M1, 1898 }, { PseudoVMIN_VV_M2, 1899 }, { PseudoVMIN_VV_M4, 1900 }, { PseudoVMIN_VV_M8, 1901 }, { PseudoVMIN_VV_MF2, 1902 }, { PseudoVMIN_VV_MF4, 1903 }, { PseudoVMIN_VV_MF8, 1904 }, { PseudoVMIN_VX_M1, 1905 }, { PseudoVMIN_VX_M2, 1906 }, { PseudoVMIN_VX_M4, 1907 }, { PseudoVMIN_VX_M8, 1908 }, { PseudoVMIN_VX_MF2, 1909 }, { PseudoVMIN_VX_MF4, 1910 }, { PseudoVMIN_VX_MF8, 1911 }, { PseudoVMSEQ_VI_M1, 1912 }, { PseudoVMSEQ_VI_M2, 1913 }, { PseudoVMSEQ_VI_M4, 1914 }, { PseudoVMSEQ_VI_M8, 1915 }, { PseudoVMSEQ_VI_MF2, 1916 }, { PseudoVMSEQ_VI_MF4, 1917 }, { PseudoVMSEQ_VI_MF8, 1918 }, { PseudoVMSEQ_VV_M1, 1919 }, { PseudoVMSEQ_VV_M2, 1920 }, { PseudoVMSEQ_VV_M4, 1921 }, { PseudoVMSEQ_VV_M8, 1922 }, { PseudoVMSEQ_VV_MF2, 1923 }, { PseudoVMSEQ_VV_MF4, 1924 }, { PseudoVMSEQ_VV_MF8, 1925 }, { PseudoVMSEQ_VX_M1, 1926 }, { PseudoVMSEQ_VX_M2, 1927 }, { PseudoVMSEQ_VX_M4, 1928 }, { PseudoVMSEQ_VX_M8, 1929 }, { PseudoVMSEQ_VX_MF2, 1930 }, { PseudoVMSEQ_VX_MF4, 1931 }, { PseudoVMSEQ_VX_MF8, 1932 }, { PseudoVMSGTU_VI_M1, 1933 }, { PseudoVMSGTU_VI_M2, 1934 }, { PseudoVMSGTU_VI_M4, 1935 }, { PseudoVMSGTU_VI_M8, 1936 }, { PseudoVMSGTU_VI_MF2, 1937 }, { PseudoVMSGTU_VI_MF4, 1938 }, { PseudoVMSGTU_VI_MF8, 1939 }, { PseudoVMSGTU_VX_M1, 1940 }, { PseudoVMSGTU_VX_M2, 1941 }, { PseudoVMSGTU_VX_M4, 1942 }, { PseudoVMSGTU_VX_M8, 1943 }, { PseudoVMSGTU_VX_MF2, 1944 }, { PseudoVMSGTU_VX_MF4, 1945 }, { PseudoVMSGTU_VX_MF8, 1946 }, { PseudoVMSGT_VI_M1, 1947 }, { PseudoVMSGT_VI_M2, 1948 }, { PseudoVMSGT_VI_M4, 1949 }, { PseudoVMSGT_VI_M8, 1950 }, { PseudoVMSGT_VI_MF2, 1951 }, { PseudoVMSGT_VI_MF4, 1952 }, { PseudoVMSGT_VI_MF8, 1953 }, { PseudoVMSGT_VX_M1, 1954 }, { PseudoVMSGT_VX_M2, 1955 }, { PseudoVMSGT_VX_M4, 1956 }, { PseudoVMSGT_VX_M8, 1957 }, { PseudoVMSGT_VX_MF2, 1958 }, { PseudoVMSGT_VX_MF4, 1959 }, { PseudoVMSGT_VX_MF8, 1960 }, { PseudoVMSLEU_VI_M1, 1961 }, { PseudoVMSLEU_VI_M2, 1962 }, { PseudoVMSLEU_VI_M4, 1963 }, { PseudoVMSLEU_VI_M8, 1964 }, { PseudoVMSLEU_VI_MF2, 1965 }, { PseudoVMSLEU_VI_MF4, 1966 }, { PseudoVMSLEU_VI_MF8, 1967 }, { PseudoVMSLEU_VV_M1, 1968 }, { PseudoVMSLEU_VV_M2, 1969 }, { PseudoVMSLEU_VV_M4, 1970 }, { PseudoVMSLEU_VV_M8, 1971 }, { PseudoVMSLEU_VV_MF2, 1972 }, { PseudoVMSLEU_VV_MF4, 1973 }, { PseudoVMSLEU_VV_MF8, 1974 }, { PseudoVMSLEU_VX_M1, 1975 }, { PseudoVMSLEU_VX_M2, 1976 }, { PseudoVMSLEU_VX_M4, 1977 }, { PseudoVMSLEU_VX_M8, 1978 }, { PseudoVMSLEU_VX_MF2, 1979 }, { PseudoVMSLEU_VX_MF4, 1980 }, { PseudoVMSLEU_VX_MF8, 1981 }, { PseudoVMSLE_VI_M1, 1982 }, { PseudoVMSLE_VI_M2, 1983 }, { PseudoVMSLE_VI_M4, 1984 }, { PseudoVMSLE_VI_M8, 1985 }, { PseudoVMSLE_VI_MF2, 1986 }, { PseudoVMSLE_VI_MF4, 1987 }, { PseudoVMSLE_VI_MF8, 1988 }, { PseudoVMSLE_VV_M1, 1989 }, { PseudoVMSLE_VV_M2, 1990 }, { PseudoVMSLE_VV_M4, 1991 }, { PseudoVMSLE_VV_M8, 1992 }, { PseudoVMSLE_VV_MF2, 1993 }, { PseudoVMSLE_VV_MF4, 1994 }, { PseudoVMSLE_VV_MF8, 1995 }, { PseudoVMSLE_VX_M1, 1996 }, { PseudoVMSLE_VX_M2, 1997 }, { PseudoVMSLE_VX_M4, 1998 }, { PseudoVMSLE_VX_M8, 1999 }, { PseudoVMSLE_VX_MF2, 2000 }, { PseudoVMSLE_VX_MF4, 2001 }, { PseudoVMSLE_VX_MF8, 2002 }, { PseudoVMSLTU_VV_M1, 2003 }, { PseudoVMSLTU_VV_M2, 2004 }, { PseudoVMSLTU_VV_M4, 2005 }, { PseudoVMSLTU_VV_M8, 2006 }, { PseudoVMSLTU_VV_MF2, 2007 }, { PseudoVMSLTU_VV_MF4, 2008 }, { PseudoVMSLTU_VV_MF8, 2009 }, { PseudoVMSLTU_VX_M1, 2010 }, { PseudoVMSLTU_VX_M2, 2011 }, { PseudoVMSLTU_VX_M4, 2012 }, { PseudoVMSLTU_VX_M8, 2013 }, { PseudoVMSLTU_VX_MF2, 2014 }, { PseudoVMSLTU_VX_MF4, 2015 }, { PseudoVMSLTU_VX_MF8, 2016 }, { PseudoVMSLT_VV_M1, 2017 }, { PseudoVMSLT_VV_M2, 2018 }, { PseudoVMSLT_VV_M4, 2019 }, { PseudoVMSLT_VV_M8, 2020 }, { PseudoVMSLT_VV_MF2, 2021 }, { PseudoVMSLT_VV_MF4, 2022 }, { PseudoVMSLT_VV_MF8, 2023 }, { PseudoVMSLT_VX_M1, 2024 }, { PseudoVMSLT_VX_M2, 2025 }, { PseudoVMSLT_VX_M4, 2026 }, { PseudoVMSLT_VX_M8, 2027 }, { PseudoVMSLT_VX_MF2, 2028 }, { PseudoVMSLT_VX_MF4, 2029 }, { PseudoVMSLT_VX_MF8, 2030 }, { PseudoVMSNE_VI_M1, 2031 }, { PseudoVMSNE_VI_M2, 2032 }, { PseudoVMSNE_VI_M4, 2033 }, { PseudoVMSNE_VI_M8, 2034 }, { PseudoVMSNE_VI_MF2, 2035 }, { PseudoVMSNE_VI_MF4, 2036 }, { PseudoVMSNE_VI_MF8, 2037 }, { PseudoVMSNE_VV_M1, 2038 }, { PseudoVMSNE_VV_M2, 2039 }, { PseudoVMSNE_VV_M4, 2040 }, { PseudoVMSNE_VV_M8, 2041 }, { PseudoVMSNE_VV_MF2, 2042 }, { PseudoVMSNE_VV_MF4, 2043 }, { PseudoVMSNE_VV_MF8, 2044 }, { PseudoVMSNE_VX_M1, 2045 }, { PseudoVMSNE_VX_M2, 2046 }, { PseudoVMSNE_VX_M4, 2047 }, { PseudoVMSNE_VX_M8, 2048 }, { PseudoVMSNE_VX_MF2, 2049 }, { PseudoVMSNE_VX_MF4, 2050 }, { PseudoVMSNE_VX_MF8, 2051 }, { PseudoVMULHSU_VV_M1, 2052 }, { PseudoVMULHSU_VV_M2, 2053 }, { PseudoVMULHSU_VV_M4, 2054 }, { PseudoVMULHSU_VV_M8, 2055 }, { PseudoVMULHSU_VV_MF2, 2056 }, { PseudoVMULHSU_VV_MF4, 2057 }, { PseudoVMULHSU_VV_MF8, 2058 }, { PseudoVMULHSU_VX_M1, 2059 }, { PseudoVMULHSU_VX_M2, 2060 }, { PseudoVMULHSU_VX_M4, 2061 }, { PseudoVMULHSU_VX_M8, 2062 }, { PseudoVMULHSU_VX_MF2, 2063 }, { PseudoVMULHSU_VX_MF4, 2064 }, { PseudoVMULHSU_VX_MF8, 2065 }, { PseudoVMULHU_VV_M1, 2066 }, { PseudoVMULHU_VV_M2, 2067 }, { PseudoVMULHU_VV_M4, 2068 }, { PseudoVMULHU_VV_M8, 2069 }, { PseudoVMULHU_VV_MF2, 2070 }, { PseudoVMULHU_VV_MF4, 2071 }, { PseudoVMULHU_VV_MF8, 2072 }, { PseudoVMULHU_VX_M1, 2073 }, { PseudoVMULHU_VX_M2, 2074 }, { PseudoVMULHU_VX_M4, 2075 }, { PseudoVMULHU_VX_M8, 2076 }, { PseudoVMULHU_VX_MF2, 2077 }, { PseudoVMULHU_VX_MF4, 2078 }, { PseudoVMULHU_VX_MF8, 2079 }, { PseudoVMULH_VV_M1, 2080 }, { PseudoVMULH_VV_M2, 2081 }, { PseudoVMULH_VV_M4, 2082 }, { PseudoVMULH_VV_M8, 2083 }, { PseudoVMULH_VV_MF2, 2084 }, { PseudoVMULH_VV_MF4, 2085 }, { PseudoVMULH_VV_MF8, 2086 }, { PseudoVMULH_VX_M1, 2087 }, { PseudoVMULH_VX_M2, 2088 }, { PseudoVMULH_VX_M4, 2089 }, { PseudoVMULH_VX_M8, 2090 }, { PseudoVMULH_VX_MF2, 2091 }, { PseudoVMULH_VX_MF4, 2092 }, { PseudoVMULH_VX_MF8, 2093 }, { PseudoVMUL_VV_M1, 2094 }, { PseudoVMUL_VV_M2, 2095 }, { PseudoVMUL_VV_M4, 2096 }, { PseudoVMUL_VV_M8, 2097 }, { PseudoVMUL_VV_MF2, 2098 }, { PseudoVMUL_VV_MF4, 2099 }, { PseudoVMUL_VV_MF8, 2100 }, { PseudoVMUL_VX_M1, 2101 }, { PseudoVMUL_VX_M2, 2102 }, { PseudoVMUL_VX_M4, 2103 }, { PseudoVMUL_VX_M8, 2104 }, { PseudoVMUL_VX_MF2, 2105 }, { PseudoVMUL_VX_MF4, 2106 }, { PseudoVMUL_VX_MF8, 2107 }, { PseudoVNCLIPU_WI_M1, 2108 }, { PseudoVNCLIPU_WI_M2, 2109 }, { PseudoVNCLIPU_WI_M4, 2110 }, { PseudoVNCLIPU_WI_MF2, 2111 }, { PseudoVNCLIPU_WI_MF4, 2112 }, { PseudoVNCLIPU_WI_MF8, 2113 }, { PseudoVNCLIPU_WV_M1, 2114 }, { PseudoVNCLIPU_WV_M2, 2115 }, { PseudoVNCLIPU_WV_M4, 2116 }, { PseudoVNCLIPU_WV_MF2, 2117 }, { PseudoVNCLIPU_WV_MF4, 2118 }, { PseudoVNCLIPU_WV_MF8, 2119 }, { PseudoVNCLIPU_WX_M1, 2120 }, { PseudoVNCLIPU_WX_M2, 2121 }, { PseudoVNCLIPU_WX_M4, 2122 }, { PseudoVNCLIPU_WX_MF2, 2123 }, { PseudoVNCLIPU_WX_MF4, 2124 }, { PseudoVNCLIPU_WX_MF8, 2125 }, { PseudoVNCLIP_WI_M1, 2126 }, { PseudoVNCLIP_WI_M2, 2127 }, { PseudoVNCLIP_WI_M4, 2128 }, { PseudoVNCLIP_WI_MF2, 2129 }, { PseudoVNCLIP_WI_MF4, 2130 }, { PseudoVNCLIP_WI_MF8, 2131 }, { PseudoVNCLIP_WV_M1, 2132 }, { PseudoVNCLIP_WV_M2, 2133 }, { PseudoVNCLIP_WV_M4, 2134 }, { PseudoVNCLIP_WV_MF2, 2135 }, { PseudoVNCLIP_WV_MF4, 2136 }, { PseudoVNCLIP_WV_MF8, 2137 }, { PseudoVNCLIP_WX_M1, 2138 }, { PseudoVNCLIP_WX_M2, 2139 }, { PseudoVNCLIP_WX_M4, 2140 }, { PseudoVNCLIP_WX_MF2, 2141 }, { PseudoVNCLIP_WX_MF4, 2142 }, { PseudoVNCLIP_WX_MF8, 2143 }, { PseudoVNMSAC_VV_M1, 2144 }, { PseudoVNMSAC_VV_M2, 2145 }, { PseudoVNMSAC_VV_M4, 2146 }, { PseudoVNMSAC_VV_M8, 2147 }, { PseudoVNMSAC_VV_MF2, 2148 }, { PseudoVNMSAC_VV_MF4, 2149 }, { PseudoVNMSAC_VV_MF8, 2150 }, { PseudoVNMSAC_VX_M1, 2151 }, { PseudoVNMSAC_VX_M2, 2152 }, { PseudoVNMSAC_VX_M4, 2153 }, { PseudoVNMSAC_VX_M8, 2154 }, { PseudoVNMSAC_VX_MF2, 2155 }, { PseudoVNMSAC_VX_MF4, 2156 }, { PseudoVNMSAC_VX_MF8, 2157 }, { PseudoVNMSUB_VV_M1, 2158 }, { PseudoVNMSUB_VV_M2, 2159 }, { PseudoVNMSUB_VV_M4, 2160 }, { PseudoVNMSUB_VV_M8, 2161 }, { PseudoVNMSUB_VV_MF2, 2162 }, { PseudoVNMSUB_VV_MF4, 2163 }, { PseudoVNMSUB_VV_MF8, 2164 }, { PseudoVNMSUB_VX_M1, 2165 }, { PseudoVNMSUB_VX_M2, 2166 }, { PseudoVNMSUB_VX_M4, 2167 }, { PseudoVNMSUB_VX_M8, 2168 }, { PseudoVNMSUB_VX_MF2, 2169 }, { PseudoVNMSUB_VX_MF4, 2170 }, { PseudoVNMSUB_VX_MF8, 2171 }, { PseudoVNSRA_WI_M1, 2172 }, { PseudoVNSRA_WI_M2, 2173 }, { PseudoVNSRA_WI_M4, 2174 }, { PseudoVNSRA_WI_MF2, 2175 }, { PseudoVNSRA_WI_MF4, 2176 }, { PseudoVNSRA_WI_MF8, 2177 }, { PseudoVNSRA_WV_M1, 2178 }, { PseudoVNSRA_WV_M2, 2179 }, { PseudoVNSRA_WV_M4, 2180 }, { PseudoVNSRA_WV_MF2, 2181 }, { PseudoVNSRA_WV_MF4, 2182 }, { PseudoVNSRA_WV_MF8, 2183 }, { PseudoVNSRA_WX_M1, 2184 }, { PseudoVNSRA_WX_M2, 2185 }, { PseudoVNSRA_WX_M4, 2186 }, { PseudoVNSRA_WX_MF2, 2187 }, { PseudoVNSRA_WX_MF4, 2188 }, { PseudoVNSRA_WX_MF8, 2189 }, { PseudoVNSRL_WI_M1, 2190 }, { PseudoVNSRL_WI_M2, 2191 }, { PseudoVNSRL_WI_M4, 2192 }, { PseudoVNSRL_WI_MF2, 2193 }, { PseudoVNSRL_WI_MF4, 2194 }, { PseudoVNSRL_WI_MF8, 2195 }, { PseudoVNSRL_WV_M1, 2196 }, { PseudoVNSRL_WV_M2, 2197 }, { PseudoVNSRL_WV_M4, 2198 }, { PseudoVNSRL_WV_MF2, 2199 }, { PseudoVNSRL_WV_MF4, 2200 }, { PseudoVNSRL_WV_MF8, 2201 }, { PseudoVNSRL_WX_M1, 2202 }, { PseudoVNSRL_WX_M2, 2203 }, { PseudoVNSRL_WX_M4, 2204 }, { PseudoVNSRL_WX_MF2, 2205 }, { PseudoVNSRL_WX_MF4, 2206 }, { PseudoVNSRL_WX_MF8, 2207 }, { PseudoVOR_VI_M1, 2208 }, { PseudoVOR_VI_M2, 2209 }, { PseudoVOR_VI_M4, 2210 }, { PseudoVOR_VI_M8, 2211 }, { PseudoVOR_VI_MF2, 2212 }, { PseudoVOR_VI_MF4, 2213 }, { PseudoVOR_VI_MF8, 2214 }, { PseudoVOR_VV_M1, 2215 }, { PseudoVOR_VV_M2, 2216 }, { PseudoVOR_VV_M4, 2217 }, { PseudoVOR_VV_M8, 2218 }, { PseudoVOR_VV_MF2, 2219 }, { PseudoVOR_VV_MF4, 2220 }, { PseudoVOR_VV_MF8, 2221 }, { PseudoVOR_VX_M1, 2222 }, { PseudoVOR_VX_M2, 2223 }, { PseudoVOR_VX_M4, 2224 }, { PseudoVOR_VX_M8, 2225 }, { PseudoVOR_VX_MF2, 2226 }, { PseudoVOR_VX_MF4, 2227 }, { PseudoVOR_VX_MF8, 2228 }, { PseudoVREDAND_VS_M1_E16, 2229 }, { PseudoVREDAND_VS_M1_E32, 2230 }, { PseudoVREDAND_VS_M1_E64, 2231 }, { PseudoVREDAND_VS_M1_E8, 2232 }, { PseudoVREDAND_VS_M2_E16, 2233 }, { PseudoVREDAND_VS_M2_E32, 2234 }, { PseudoVREDAND_VS_M2_E64, 2235 }, { PseudoVREDAND_VS_M2_E8, 2236 }, { PseudoVREDAND_VS_M4_E16, 2237 }, { PseudoVREDAND_VS_M4_E32, 2238 }, { PseudoVREDAND_VS_M4_E64, 2239 }, { PseudoVREDAND_VS_M4_E8, 2240 }, { PseudoVREDAND_VS_M8_E16, 2241 }, { PseudoVREDAND_VS_M8_E32, 2242 }, { PseudoVREDAND_VS_M8_E64, 2243 }, { PseudoVREDAND_VS_M8_E8, 2244 }, { PseudoVREDAND_VS_MF2_E16, 2245 }, { PseudoVREDAND_VS_MF2_E32, 2246 }, { PseudoVREDAND_VS_MF2_E8, 2247 }, { PseudoVREDAND_VS_MF4_E16, 2248 }, { PseudoVREDAND_VS_MF4_E8, 2249 }, { PseudoVREDAND_VS_MF8_E8, 2250 }, { PseudoVREDMAXU_VS_M1_E16, 2251 }, { PseudoVREDMAXU_VS_M1_E32, 2252 }, { PseudoVREDMAXU_VS_M1_E64, 2253 }, { PseudoVREDMAXU_VS_M1_E8, 2254 }, { PseudoVREDMAXU_VS_M2_E16, 2255 }, { PseudoVREDMAXU_VS_M2_E32, 2256 }, { PseudoVREDMAXU_VS_M2_E64, 2257 }, { PseudoVREDMAXU_VS_M2_E8, 2258 }, { PseudoVREDMAXU_VS_M4_E16, 2259 }, { PseudoVREDMAXU_VS_M4_E32, 2260 }, { PseudoVREDMAXU_VS_M4_E64, 2261 }, { PseudoVREDMAXU_VS_M4_E8, 2262 }, { PseudoVREDMAXU_VS_M8_E16, 2263 }, { PseudoVREDMAXU_VS_M8_E32, 2264 }, { PseudoVREDMAXU_VS_M8_E64, 2265 }, { PseudoVREDMAXU_VS_M8_E8, 2266 }, { PseudoVREDMAXU_VS_MF2_E16, 2267 }, { PseudoVREDMAXU_VS_MF2_E32, 2268 }, { PseudoVREDMAXU_VS_MF2_E8, 2269 }, { PseudoVREDMAXU_VS_MF4_E16, 2270 }, { PseudoVREDMAXU_VS_MF4_E8, 2271 }, { PseudoVREDMAXU_VS_MF8_E8, 2272 }, { PseudoVREDMAX_VS_M1_E16, 2273 }, { PseudoVREDMAX_VS_M1_E32, 2274 }, { PseudoVREDMAX_VS_M1_E64, 2275 }, { PseudoVREDMAX_VS_M1_E8, 2276 }, { PseudoVREDMAX_VS_M2_E16, 2277 }, { PseudoVREDMAX_VS_M2_E32, 2278 }, { PseudoVREDMAX_VS_M2_E64, 2279 }, { PseudoVREDMAX_VS_M2_E8, 2280 }, { PseudoVREDMAX_VS_M4_E16, 2281 }, { PseudoVREDMAX_VS_M4_E32, 2282 }, { PseudoVREDMAX_VS_M4_E64, 2283 }, { PseudoVREDMAX_VS_M4_E8, 2284 }, { PseudoVREDMAX_VS_M8_E16, 2285 }, { PseudoVREDMAX_VS_M8_E32, 2286 }, { PseudoVREDMAX_VS_M8_E64, 2287 }, { PseudoVREDMAX_VS_M8_E8, 2288 }, { PseudoVREDMAX_VS_MF2_E16, 2289 }, { PseudoVREDMAX_VS_MF2_E32, 2290 }, { PseudoVREDMAX_VS_MF2_E8, 2291 }, { PseudoVREDMAX_VS_MF4_E16, 2292 }, { PseudoVREDMAX_VS_MF4_E8, 2293 }, { PseudoVREDMAX_VS_MF8_E8, 2294 }, { PseudoVREDMINU_VS_M1_E16, 2295 }, { PseudoVREDMINU_VS_M1_E32, 2296 }, { PseudoVREDMINU_VS_M1_E64, 2297 }, { PseudoVREDMINU_VS_M1_E8, 2298 }, { PseudoVREDMINU_VS_M2_E16, 2299 }, { PseudoVREDMINU_VS_M2_E32, 2300 }, { PseudoVREDMINU_VS_M2_E64, 2301 }, { PseudoVREDMINU_VS_M2_E8, 2302 }, { PseudoVREDMINU_VS_M4_E16, 2303 }, { PseudoVREDMINU_VS_M4_E32, 2304 }, { PseudoVREDMINU_VS_M4_E64, 2305 }, { PseudoVREDMINU_VS_M4_E8, 2306 }, { PseudoVREDMINU_VS_M8_E16, 2307 }, { PseudoVREDMINU_VS_M8_E32, 2308 }, { PseudoVREDMINU_VS_M8_E64, 2309 }, { PseudoVREDMINU_VS_M8_E8, 2310 }, { PseudoVREDMINU_VS_MF2_E16, 2311 }, { PseudoVREDMINU_VS_MF2_E32, 2312 }, { PseudoVREDMINU_VS_MF2_E8, 2313 }, { PseudoVREDMINU_VS_MF4_E16, 2314 }, { PseudoVREDMINU_VS_MF4_E8, 2315 }, { PseudoVREDMINU_VS_MF8_E8, 2316 }, { PseudoVREDMIN_VS_M1_E16, 2317 }, { PseudoVREDMIN_VS_M1_E32, 2318 }, { PseudoVREDMIN_VS_M1_E64, 2319 }, { PseudoVREDMIN_VS_M1_E8, 2320 }, { PseudoVREDMIN_VS_M2_E16, 2321 }, { PseudoVREDMIN_VS_M2_E32, 2322 }, { PseudoVREDMIN_VS_M2_E64, 2323 }, { PseudoVREDMIN_VS_M2_E8, 2324 }, { PseudoVREDMIN_VS_M4_E16, 2325 }, { PseudoVREDMIN_VS_M4_E32, 2326 }, { PseudoVREDMIN_VS_M4_E64, 2327 }, { PseudoVREDMIN_VS_M4_E8, 2328 }, { PseudoVREDMIN_VS_M8_E16, 2329 }, { PseudoVREDMIN_VS_M8_E32, 2330 }, { PseudoVREDMIN_VS_M8_E64, 2331 }, { PseudoVREDMIN_VS_M8_E8, 2332 }, { PseudoVREDMIN_VS_MF2_E16, 2333 }, { PseudoVREDMIN_VS_MF2_E32, 2334 }, { PseudoVREDMIN_VS_MF2_E8, 2335 }, { PseudoVREDMIN_VS_MF4_E16, 2336 }, { PseudoVREDMIN_VS_MF4_E8, 2337 }, { PseudoVREDMIN_VS_MF8_E8, 2338 }, { PseudoVREDOR_VS_M1_E16, 2339 }, { PseudoVREDOR_VS_M1_E32, 2340 }, { PseudoVREDOR_VS_M1_E64, 2341 }, { PseudoVREDOR_VS_M1_E8, 2342 }, { PseudoVREDOR_VS_M2_E16, 2343 }, { PseudoVREDOR_VS_M2_E32, 2344 }, { PseudoVREDOR_VS_M2_E64, 2345 }, { PseudoVREDOR_VS_M2_E8, 2346 }, { PseudoVREDOR_VS_M4_E16, 2347 }, { PseudoVREDOR_VS_M4_E32, 2348 }, { PseudoVREDOR_VS_M4_E64, 2349 }, { PseudoVREDOR_VS_M4_E8, 2350 }, { PseudoVREDOR_VS_M8_E16, 2351 }, { PseudoVREDOR_VS_M8_E32, 2352 }, { PseudoVREDOR_VS_M8_E64, 2353 }, { PseudoVREDOR_VS_M8_E8, 2354 }, { PseudoVREDOR_VS_MF2_E16, 2355 }, { PseudoVREDOR_VS_MF2_E32, 2356 }, { PseudoVREDOR_VS_MF2_E8, 2357 }, { PseudoVREDOR_VS_MF4_E16, 2358 }, { PseudoVREDOR_VS_MF4_E8, 2359 }, { PseudoVREDOR_VS_MF8_E8, 2360 }, { PseudoVREDSUM_VS_M1_E16, 2361 }, { PseudoVREDSUM_VS_M1_E32, 2362 }, { PseudoVREDSUM_VS_M1_E64, 2363 }, { PseudoVREDSUM_VS_M1_E8, 2364 }, { PseudoVREDSUM_VS_M2_E16, 2365 }, { PseudoVREDSUM_VS_M2_E32, 2366 }, { PseudoVREDSUM_VS_M2_E64, 2367 }, { PseudoVREDSUM_VS_M2_E8, 2368 }, { PseudoVREDSUM_VS_M4_E16, 2369 }, { PseudoVREDSUM_VS_M4_E32, 2370 }, { PseudoVREDSUM_VS_M4_E64, 2371 }, { PseudoVREDSUM_VS_M4_E8, 2372 }, { PseudoVREDSUM_VS_M8_E16, 2373 }, { PseudoVREDSUM_VS_M8_E32, 2374 }, { PseudoVREDSUM_VS_M8_E64, 2375 }, { PseudoVREDSUM_VS_M8_E8, 2376 }, { PseudoVREDSUM_VS_MF2_E16, 2377 }, { PseudoVREDSUM_VS_MF2_E32, 2378 }, { PseudoVREDSUM_VS_MF2_E8, 2379 }, { PseudoVREDSUM_VS_MF4_E16, 2380 }, { PseudoVREDSUM_VS_MF4_E8, 2381 }, { PseudoVREDSUM_VS_MF8_E8, 2382 }, { PseudoVREDXOR_VS_M1_E16, 2383 }, { PseudoVREDXOR_VS_M1_E32, 2384 }, { PseudoVREDXOR_VS_M1_E64, 2385 }, { PseudoVREDXOR_VS_M1_E8, 2386 }, { PseudoVREDXOR_VS_M2_E16, 2387 }, { PseudoVREDXOR_VS_M2_E32, 2388 }, { PseudoVREDXOR_VS_M2_E64, 2389 }, { PseudoVREDXOR_VS_M2_E8, 2390 }, { PseudoVREDXOR_VS_M4_E16, 2391 }, { PseudoVREDXOR_VS_M4_E32, 2392 }, { PseudoVREDXOR_VS_M4_E64, 2393 }, { PseudoVREDXOR_VS_M4_E8, 2394 }, { PseudoVREDXOR_VS_M8_E16, 2395 }, { PseudoVREDXOR_VS_M8_E32, 2396 }, { PseudoVREDXOR_VS_M8_E64, 2397 }, { PseudoVREDXOR_VS_M8_E8, 2398 }, { PseudoVREDXOR_VS_MF2_E16, 2399 }, { PseudoVREDXOR_VS_MF2_E32, 2400 }, { PseudoVREDXOR_VS_MF2_E8, 2401 }, { PseudoVREDXOR_VS_MF4_E16, 2402 }, { PseudoVREDXOR_VS_MF4_E8, 2403 }, { PseudoVREDXOR_VS_MF8_E8, 2404 }, { PseudoVREMU_VV_M1_E16, 2405 }, { PseudoVREMU_VV_M1_E32, 2406 }, { PseudoVREMU_VV_M1_E64, 2407 }, { PseudoVREMU_VV_M1_E8, 2408 }, { PseudoVREMU_VV_M2_E16, 2409 }, { PseudoVREMU_VV_M2_E32, 2410 }, { PseudoVREMU_VV_M2_E64, 2411 }, { PseudoVREMU_VV_M2_E8, 2412 }, { PseudoVREMU_VV_M4_E16, 2413 }, { PseudoVREMU_VV_M4_E32, 2414 }, { PseudoVREMU_VV_M4_E64, 2415 }, { PseudoVREMU_VV_M4_E8, 2416 }, { PseudoVREMU_VV_M8_E16, 2417 }, { PseudoVREMU_VV_M8_E32, 2418 }, { PseudoVREMU_VV_M8_E64, 2419 }, { PseudoVREMU_VV_M8_E8, 2420 }, { PseudoVREMU_VV_MF2_E16, 2421 }, { PseudoVREMU_VV_MF2_E32, 2422 }, { PseudoVREMU_VV_MF2_E8, 2423 }, { PseudoVREMU_VV_MF4_E16, 2424 }, { PseudoVREMU_VV_MF4_E8, 2425 }, { PseudoVREMU_VV_MF8_E8, 2426 }, { PseudoVREMU_VX_M1_E16, 2427 }, { PseudoVREMU_VX_M1_E32, 2428 }, { PseudoVREMU_VX_M1_E64, 2429 }, { PseudoVREMU_VX_M1_E8, 2430 }, { PseudoVREMU_VX_M2_E16, 2431 }, { PseudoVREMU_VX_M2_E32, 2432 }, { PseudoVREMU_VX_M2_E64, 2433 }, { PseudoVREMU_VX_M2_E8, 2434 }, { PseudoVREMU_VX_M4_E16, 2435 }, { PseudoVREMU_VX_M4_E32, 2436 }, { PseudoVREMU_VX_M4_E64, 2437 }, { PseudoVREMU_VX_M4_E8, 2438 }, { PseudoVREMU_VX_M8_E16, 2439 }, { PseudoVREMU_VX_M8_E32, 2440 }, { PseudoVREMU_VX_M8_E64, 2441 }, { PseudoVREMU_VX_M8_E8, 2442 }, { PseudoVREMU_VX_MF2_E16, 2443 }, { PseudoVREMU_VX_MF2_E32, 2444 }, { PseudoVREMU_VX_MF2_E8, 2445 }, { PseudoVREMU_VX_MF4_E16, 2446 }, { PseudoVREMU_VX_MF4_E8, 2447 }, { PseudoVREMU_VX_MF8_E8, 2448 }, { PseudoVREM_VV_M1_E16, 2449 }, { PseudoVREM_VV_M1_E32, 2450 }, { PseudoVREM_VV_M1_E64, 2451 }, { PseudoVREM_VV_M1_E8, 2452 }, { PseudoVREM_VV_M2_E16, 2453 }, { PseudoVREM_VV_M2_E32, 2454 }, { PseudoVREM_VV_M2_E64, 2455 }, { PseudoVREM_VV_M2_E8, 2456 }, { PseudoVREM_VV_M4_E16, 2457 }, { PseudoVREM_VV_M4_E32, 2458 }, { PseudoVREM_VV_M4_E64, 2459 }, { PseudoVREM_VV_M4_E8, 2460 }, { PseudoVREM_VV_M8_E16, 2461 }, { PseudoVREM_VV_M8_E32, 2462 }, { PseudoVREM_VV_M8_E64, 2463 }, { PseudoVREM_VV_M8_E8, 2464 }, { PseudoVREM_VV_MF2_E16, 2465 }, { PseudoVREM_VV_MF2_E32, 2466 }, { PseudoVREM_VV_MF2_E8, 2467 }, { PseudoVREM_VV_MF4_E16, 2468 }, { PseudoVREM_VV_MF4_E8, 2469 }, { PseudoVREM_VV_MF8_E8, 2470 }, { PseudoVREM_VX_M1_E16, 2471 }, { PseudoVREM_VX_M1_E32, 2472 }, { PseudoVREM_VX_M1_E64, 2473 }, { PseudoVREM_VX_M1_E8, 2474 }, { PseudoVREM_VX_M2_E16, 2475 }, { PseudoVREM_VX_M2_E32, 2476 }, { PseudoVREM_VX_M2_E64, 2477 }, { PseudoVREM_VX_M2_E8, 2478 }, { PseudoVREM_VX_M4_E16, 2479 }, { PseudoVREM_VX_M4_E32, 2480 }, { PseudoVREM_VX_M4_E64, 2481 }, { PseudoVREM_VX_M4_E8, 2482 }, { PseudoVREM_VX_M8_E16, 2483 }, { PseudoVREM_VX_M8_E32, 2484 }, { PseudoVREM_VX_M8_E64, 2485 }, { PseudoVREM_VX_M8_E8, 2486 }, { PseudoVREM_VX_MF2_E16, 2487 }, { PseudoVREM_VX_MF2_E32, 2488 }, { PseudoVREM_VX_MF2_E8, 2489 }, { PseudoVREM_VX_MF4_E16, 2490 }, { PseudoVREM_VX_MF4_E8, 2491 }, { PseudoVREM_VX_MF8_E8, 2492 }, { PseudoVREV8_V_M1, 2493 }, { PseudoVREV8_V_M2, 2494 }, { PseudoVREV8_V_M4, 2495 }, { PseudoVREV8_V_M8, 2496 }, { PseudoVREV8_V_MF2, 2497 }, { PseudoVREV8_V_MF4, 2498 }, { PseudoVREV8_V_MF8, 2499 }, { PseudoVRGATHEREI16_VV_M1_E16_M1, 2500 }, { PseudoVRGATHEREI16_VV_M1_E16_M2, 2501 }, { PseudoVRGATHEREI16_VV_M1_E16_MF2, 2502 }, { PseudoVRGATHEREI16_VV_M1_E16_MF4, 2503 }, { PseudoVRGATHEREI16_VV_M1_E32_M1, 2504 }, { PseudoVRGATHEREI16_VV_M1_E32_M2, 2505 }, { PseudoVRGATHEREI16_VV_M1_E32_MF2, 2506 }, { PseudoVRGATHEREI16_VV_M1_E32_MF4, 2507 }, { PseudoVRGATHEREI16_VV_M1_E64_M1, 2508 }, { PseudoVRGATHEREI16_VV_M1_E64_M2, 2509 }, { PseudoVRGATHEREI16_VV_M1_E64_MF2, 2510 }, { PseudoVRGATHEREI16_VV_M1_E64_MF4, 2511 }, { PseudoVRGATHEREI16_VV_M1_E8_M1, 2512 }, { PseudoVRGATHEREI16_VV_M1_E8_M2, 2513 }, { PseudoVRGATHEREI16_VV_M1_E8_MF2, 2514 }, { PseudoVRGATHEREI16_VV_M1_E8_MF4, 2515 }, { PseudoVRGATHEREI16_VV_M2_E16_M1, 2516 }, { PseudoVRGATHEREI16_VV_M2_E16_M2, 2517 }, { PseudoVRGATHEREI16_VV_M2_E16_M4, 2518 }, { PseudoVRGATHEREI16_VV_M2_E16_MF2, 2519 }, { PseudoVRGATHEREI16_VV_M2_E32_M1, 2520 }, { PseudoVRGATHEREI16_VV_M2_E32_M2, 2521 }, { PseudoVRGATHEREI16_VV_M2_E32_M4, 2522 }, { PseudoVRGATHEREI16_VV_M2_E32_MF2, 2523 }, { PseudoVRGATHEREI16_VV_M2_E64_M1, 2524 }, { PseudoVRGATHEREI16_VV_M2_E64_M2, 2525 }, { PseudoVRGATHEREI16_VV_M2_E64_M4, 2526 }, { PseudoVRGATHEREI16_VV_M2_E64_MF2, 2527 }, { PseudoVRGATHEREI16_VV_M2_E8_M1, 2528 }, { PseudoVRGATHEREI16_VV_M2_E8_M2, 2529 }, { PseudoVRGATHEREI16_VV_M2_E8_M4, 2530 }, { PseudoVRGATHEREI16_VV_M2_E8_MF2, 2531 }, { PseudoVRGATHEREI16_VV_M4_E16_M1, 2532 }, { PseudoVRGATHEREI16_VV_M4_E16_M2, 2533 }, { PseudoVRGATHEREI16_VV_M4_E16_M4, 2534 }, { PseudoVRGATHEREI16_VV_M4_E16_M8, 2535 }, { PseudoVRGATHEREI16_VV_M4_E32_M1, 2536 }, { PseudoVRGATHEREI16_VV_M4_E32_M2, 2537 }, { PseudoVRGATHEREI16_VV_M4_E32_M4, 2538 }, { PseudoVRGATHEREI16_VV_M4_E32_M8, 2539 }, { PseudoVRGATHEREI16_VV_M4_E64_M1, 2540 }, { PseudoVRGATHEREI16_VV_M4_E64_M2, 2541 }, { PseudoVRGATHEREI16_VV_M4_E64_M4, 2542 }, { PseudoVRGATHEREI16_VV_M4_E64_M8, 2543 }, { PseudoVRGATHEREI16_VV_M4_E8_M1, 2544 }, { PseudoVRGATHEREI16_VV_M4_E8_M2, 2545 }, { PseudoVRGATHEREI16_VV_M4_E8_M4, 2546 }, { PseudoVRGATHEREI16_VV_M4_E8_M8, 2547 }, { PseudoVRGATHEREI16_VV_M8_E16_M2, 2548 }, { PseudoVRGATHEREI16_VV_M8_E16_M4, 2549 }, { PseudoVRGATHEREI16_VV_M8_E16_M8, 2550 }, { PseudoVRGATHEREI16_VV_M8_E32_M2, 2551 }, { PseudoVRGATHEREI16_VV_M8_E32_M4, 2552 }, { PseudoVRGATHEREI16_VV_M8_E32_M8, 2553 }, { PseudoVRGATHEREI16_VV_M8_E64_M2, 2554 }, { PseudoVRGATHEREI16_VV_M8_E64_M4, 2555 }, { PseudoVRGATHEREI16_VV_M8_E64_M8, 2556 }, { PseudoVRGATHEREI16_VV_M8_E8_M2, 2557 }, { PseudoVRGATHEREI16_VV_M8_E8_M4, 2558 }, { PseudoVRGATHEREI16_VV_M8_E8_M8, 2559 }, { PseudoVRGATHEREI16_VV_MF2_E16_M1, 2560 }, { PseudoVRGATHEREI16_VV_MF2_E16_MF2, 2561 }, { PseudoVRGATHEREI16_VV_MF2_E16_MF4, 2562 }, { PseudoVRGATHEREI16_VV_MF2_E16_MF8, 2563 }, { PseudoVRGATHEREI16_VV_MF2_E32_M1, 2564 }, { PseudoVRGATHEREI16_VV_MF2_E32_MF2, 2565 }, { PseudoVRGATHEREI16_VV_MF2_E32_MF4, 2566 }, { PseudoVRGATHEREI16_VV_MF2_E32_MF8, 2567 }, { PseudoVRGATHEREI16_VV_MF2_E8_M1, 2568 }, { PseudoVRGATHEREI16_VV_MF2_E8_MF2, 2569 }, { PseudoVRGATHEREI16_VV_MF2_E8_MF4, 2570 }, { PseudoVRGATHEREI16_VV_MF2_E8_MF8, 2571 }, { PseudoVRGATHEREI16_VV_MF4_E16_MF2, 2572 }, { PseudoVRGATHEREI16_VV_MF4_E16_MF4, 2573 }, { PseudoVRGATHEREI16_VV_MF4_E16_MF8, 2574 }, { PseudoVRGATHEREI16_VV_MF4_E8_MF2, 2575 }, { PseudoVRGATHEREI16_VV_MF4_E8_MF4, 2576 }, { PseudoVRGATHEREI16_VV_MF4_E8_MF8, 2577 }, { PseudoVRGATHEREI16_VV_MF8_E8_MF4, 2578 }, { PseudoVRGATHEREI16_VV_MF8_E8_MF8, 2579 }, { PseudoVRGATHER_VI_M1, 2580 }, { PseudoVRGATHER_VI_M2, 2581 }, { PseudoVRGATHER_VI_M4, 2582 }, { PseudoVRGATHER_VI_M8, 2583 }, { PseudoVRGATHER_VI_MF2, 2584 }, { PseudoVRGATHER_VI_MF4, 2585 }, { PseudoVRGATHER_VI_MF8, 2586 }, { PseudoVRGATHER_VV_M1_E16, 2587 }, { PseudoVRGATHER_VV_M1_E32, 2588 }, { PseudoVRGATHER_VV_M1_E64, 2589 }, { PseudoVRGATHER_VV_M1_E8, 2590 }, { PseudoVRGATHER_VV_M2_E16, 2591 }, { PseudoVRGATHER_VV_M2_E32, 2592 }, { PseudoVRGATHER_VV_M2_E64, 2593 }, { PseudoVRGATHER_VV_M2_E8, 2594 }, { PseudoVRGATHER_VV_M4_E16, 2595 }, { PseudoVRGATHER_VV_M4_E32, 2596 }, { PseudoVRGATHER_VV_M4_E64, 2597 }, { PseudoVRGATHER_VV_M4_E8, 2598 }, { PseudoVRGATHER_VV_M8_E16, 2599 }, { PseudoVRGATHER_VV_M8_E32, 2600 }, { PseudoVRGATHER_VV_M8_E64, 2601 }, { PseudoVRGATHER_VV_M8_E8, 2602 }, { PseudoVRGATHER_VV_MF2_E16, 2603 }, { PseudoVRGATHER_VV_MF2_E32, 2604 }, { PseudoVRGATHER_VV_MF2_E8, 2605 }, { PseudoVRGATHER_VV_MF4_E16, 2606 }, { PseudoVRGATHER_VV_MF4_E8, 2607 }, { PseudoVRGATHER_VV_MF8_E8, 2608 }, { PseudoVRGATHER_VX_M1, 2609 }, { PseudoVRGATHER_VX_M2, 2610 }, { PseudoVRGATHER_VX_M4, 2611 }, { PseudoVRGATHER_VX_M8, 2612 }, { PseudoVRGATHER_VX_MF2, 2613 }, { PseudoVRGATHER_VX_MF4, 2614 }, { PseudoVRGATHER_VX_MF8, 2615 }, { PseudoVROL_VV_M1, 2616 }, { PseudoVROL_VV_M2, 2617 }, { PseudoVROL_VV_M4, 2618 }, { PseudoVROL_VV_M8, 2619 }, { PseudoVROL_VV_MF2, 2620 }, { PseudoVROL_VV_MF4, 2621 }, { PseudoVROL_VV_MF8, 2622 }, { PseudoVROL_VX_M1, 2623 }, { PseudoVROL_VX_M2, 2624 }, { PseudoVROL_VX_M4, 2625 }, { PseudoVROL_VX_M8, 2626 }, { PseudoVROL_VX_MF2, 2627 }, { PseudoVROL_VX_MF4, 2628 }, { PseudoVROL_VX_MF8, 2629 }, { PseudoVROR_VI_M1, 2630 }, { PseudoVROR_VI_M2, 2631 }, { PseudoVROR_VI_M4, 2632 }, { PseudoVROR_VI_M8, 2633 }, { PseudoVROR_VI_MF2, 2634 }, { PseudoVROR_VI_MF4, 2635 }, { PseudoVROR_VI_MF8, 2636 }, { PseudoVROR_VV_M1, 2637 }, { PseudoVROR_VV_M2, 2638 }, { PseudoVROR_VV_M4, 2639 }, { PseudoVROR_VV_M8, 2640 }, { PseudoVROR_VV_MF2, 2641 }, { PseudoVROR_VV_MF4, 2642 }, { PseudoVROR_VV_MF8, 2643 }, { PseudoVROR_VX_M1, 2644 }, { PseudoVROR_VX_M2, 2645 }, { PseudoVROR_VX_M4, 2646 }, { PseudoVROR_VX_M8, 2647 }, { PseudoVROR_VX_MF2, 2648 }, { PseudoVROR_VX_MF4, 2649 }, { PseudoVROR_VX_MF8, 2650 }, { PseudoVRSUB_VI_M1, 2651 }, { PseudoVRSUB_VI_M2, 2652 }, { PseudoVRSUB_VI_M4, 2653 }, { PseudoVRSUB_VI_M8, 2654 }, { PseudoVRSUB_VI_MF2, 2655 }, { PseudoVRSUB_VI_MF4, 2656 }, { PseudoVRSUB_VI_MF8, 2657 }, { PseudoVRSUB_VX_M1, 2658 }, { PseudoVRSUB_VX_M2, 2659 }, { PseudoVRSUB_VX_M4, 2660 }, { PseudoVRSUB_VX_M8, 2661 }, { PseudoVRSUB_VX_MF2, 2662 }, { PseudoVRSUB_VX_MF4, 2663 }, { PseudoVRSUB_VX_MF8, 2664 }, { PseudoVSADDU_VI_M1, 2665 }, { PseudoVSADDU_VI_M2, 2666 }, { PseudoVSADDU_VI_M4, 2667 }, { PseudoVSADDU_VI_M8, 2668 }, { PseudoVSADDU_VI_MF2, 2669 }, { PseudoVSADDU_VI_MF4, 2670 }, { PseudoVSADDU_VI_MF8, 2671 }, { PseudoVSADDU_VV_M1, 2672 }, { PseudoVSADDU_VV_M2, 2673 }, { PseudoVSADDU_VV_M4, 2674 }, { PseudoVSADDU_VV_M8, 2675 }, { PseudoVSADDU_VV_MF2, 2676 }, { PseudoVSADDU_VV_MF4, 2677 }, { PseudoVSADDU_VV_MF8, 2678 }, { PseudoVSADDU_VX_M1, 2679 }, { PseudoVSADDU_VX_M2, 2680 }, { PseudoVSADDU_VX_M4, 2681 }, { PseudoVSADDU_VX_M8, 2682 }, { PseudoVSADDU_VX_MF2, 2683 }, { PseudoVSADDU_VX_MF4, 2684 }, { PseudoVSADDU_VX_MF8, 2685 }, { PseudoVSADD_VI_M1, 2686 }, { PseudoVSADD_VI_M2, 2687 }, { PseudoVSADD_VI_M4, 2688 }, { PseudoVSADD_VI_M8, 2689 }, { PseudoVSADD_VI_MF2, 2690 }, { PseudoVSADD_VI_MF4, 2691 }, { PseudoVSADD_VI_MF8, 2692 }, { PseudoVSADD_VV_M1, 2693 }, { PseudoVSADD_VV_M2, 2694 }, { PseudoVSADD_VV_M4, 2695 }, { PseudoVSADD_VV_M8, 2696 }, { PseudoVSADD_VV_MF2, 2697 }, { PseudoVSADD_VV_MF4, 2698 }, { PseudoVSADD_VV_MF8, 2699 }, { PseudoVSADD_VX_M1, 2700 }, { PseudoVSADD_VX_M2, 2701 }, { PseudoVSADD_VX_M4, 2702 }, { PseudoVSADD_VX_M8, 2703 }, { PseudoVSADD_VX_MF2, 2704 }, { PseudoVSADD_VX_MF4, 2705 }, { PseudoVSADD_VX_MF8, 2706 }, { PseudoVSEXT_VF2_M1, 2707 }, { PseudoVSEXT_VF2_M2, 2708 }, { PseudoVSEXT_VF2_M4, 2709 }, { PseudoVSEXT_VF2_M8, 2710 }, { PseudoVSEXT_VF2_MF2, 2711 }, { PseudoVSEXT_VF2_MF4, 2712 }, { PseudoVSEXT_VF4_M1, 2713 }, { PseudoVSEXT_VF4_M2, 2714 }, { PseudoVSEXT_VF4_M4, 2715 }, { PseudoVSEXT_VF4_M8, 2716 }, { PseudoVSEXT_VF4_MF2, 2717 }, { PseudoVSEXT_VF8_M1, 2718 }, { PseudoVSEXT_VF8_M2, 2719 }, { PseudoVSEXT_VF8_M4, 2720 }, { PseudoVSEXT_VF8_M8, 2721 }, { PseudoVSLIDE1DOWN_VX_M1, 2722 }, { PseudoVSLIDE1DOWN_VX_M2, 2723 }, { PseudoVSLIDE1DOWN_VX_M4, 2724 }, { PseudoVSLIDE1DOWN_VX_M8, 2725 }, { PseudoVSLIDE1DOWN_VX_MF2, 2726 }, { PseudoVSLIDE1DOWN_VX_MF4, 2727 }, { PseudoVSLIDE1DOWN_VX_MF8, 2728 }, { PseudoVSLIDE1UP_VX_M1, 2729 }, { PseudoVSLIDE1UP_VX_M2, 2730 }, { PseudoVSLIDE1UP_VX_M4, 2731 }, { PseudoVSLIDE1UP_VX_M8, 2732 }, { PseudoVSLIDE1UP_VX_MF2, 2733 }, { PseudoVSLIDE1UP_VX_MF4, 2734 }, { PseudoVSLIDE1UP_VX_MF8, 2735 }, { PseudoVSLIDEDOWN_VI_M1, 2736 }, { PseudoVSLIDEDOWN_VI_M2, 2737 }, { PseudoVSLIDEDOWN_VI_M4, 2738 }, { PseudoVSLIDEDOWN_VI_M8, 2739 }, { PseudoVSLIDEDOWN_VI_MF2, 2740 }, { PseudoVSLIDEDOWN_VI_MF4, 2741 }, { PseudoVSLIDEDOWN_VI_MF8, 2742 }, { PseudoVSLIDEDOWN_VX_M1, 2743 }, { PseudoVSLIDEDOWN_VX_M2, 2744 }, { PseudoVSLIDEDOWN_VX_M4, 2745 }, { PseudoVSLIDEDOWN_VX_M8, 2746 }, { PseudoVSLIDEDOWN_VX_MF2, 2747 }, { PseudoVSLIDEDOWN_VX_MF4, 2748 }, { PseudoVSLIDEDOWN_VX_MF8, 2749 }, { PseudoVSLIDEUP_VI_M1, 2750 }, { PseudoVSLIDEUP_VI_M2, 2751 }, { PseudoVSLIDEUP_VI_M4, 2752 }, { PseudoVSLIDEUP_VI_M8, 2753 }, { PseudoVSLIDEUP_VI_MF2, 2754 }, { PseudoVSLIDEUP_VI_MF4, 2755 }, { PseudoVSLIDEUP_VI_MF8, 2756 }, { PseudoVSLIDEUP_VX_M1, 2757 }, { PseudoVSLIDEUP_VX_M2, 2758 }, { PseudoVSLIDEUP_VX_M4, 2759 }, { PseudoVSLIDEUP_VX_M8, 2760 }, { PseudoVSLIDEUP_VX_MF2, 2761 }, { PseudoVSLIDEUP_VX_MF4, 2762 }, { PseudoVSLIDEUP_VX_MF8, 2763 }, { PseudoVSLL_VI_M1, 2764 }, { PseudoVSLL_VI_M2, 2765 }, { PseudoVSLL_VI_M4, 2766 }, { PseudoVSLL_VI_M8, 2767 }, { PseudoVSLL_VI_MF2, 2768 }, { PseudoVSLL_VI_MF4, 2769 }, { PseudoVSLL_VI_MF8, 2770 }, { PseudoVSLL_VV_M1, 2771 }, { PseudoVSLL_VV_M2, 2772 }, { PseudoVSLL_VV_M4, 2773 }, { PseudoVSLL_VV_M8, 2774 }, { PseudoVSLL_VV_MF2, 2775 }, { PseudoVSLL_VV_MF4, 2776 }, { PseudoVSLL_VV_MF8, 2777 }, { PseudoVSLL_VX_M1, 2778 }, { PseudoVSLL_VX_M2, 2779 }, { PseudoVSLL_VX_M4, 2780 }, { PseudoVSLL_VX_M8, 2781 }, { PseudoVSLL_VX_MF2, 2782 }, { PseudoVSLL_VX_MF4, 2783 }, { PseudoVSLL_VX_MF8, 2784 }, { PseudoVSMUL_VV_M1, 2785 }, { PseudoVSMUL_VV_M2, 2786 }, { PseudoVSMUL_VV_M4, 2787 }, { PseudoVSMUL_VV_M8, 2788 }, { PseudoVSMUL_VV_MF2, 2789 }, { PseudoVSMUL_VV_MF4, 2790 }, { PseudoVSMUL_VV_MF8, 2791 }, { PseudoVSMUL_VX_M1, 2792 }, { PseudoVSMUL_VX_M2, 2793 }, { PseudoVSMUL_VX_M4, 2794 }, { PseudoVSMUL_VX_M8, 2795 }, { PseudoVSMUL_VX_MF2, 2796 }, { PseudoVSMUL_VX_MF4, 2797 }, { PseudoVSMUL_VX_MF8, 2798 }, { PseudoVSRA_VI_M1, 2799 }, { PseudoVSRA_VI_M2, 2800 }, { PseudoVSRA_VI_M4, 2801 }, { PseudoVSRA_VI_M8, 2802 }, { PseudoVSRA_VI_MF2, 2803 }, { PseudoVSRA_VI_MF4, 2804 }, { PseudoVSRA_VI_MF8, 2805 }, { PseudoVSRA_VV_M1, 2806 }, { PseudoVSRA_VV_M2, 2807 }, { PseudoVSRA_VV_M4, 2808 }, { PseudoVSRA_VV_M8, 2809 }, { PseudoVSRA_VV_MF2, 2810 }, { PseudoVSRA_VV_MF4, 2811 }, { PseudoVSRA_VV_MF8, 2812 }, { PseudoVSRA_VX_M1, 2813 }, { PseudoVSRA_VX_M2, 2814 }, { PseudoVSRA_VX_M4, 2815 }, { PseudoVSRA_VX_M8, 2816 }, { PseudoVSRA_VX_MF2, 2817 }, { PseudoVSRA_VX_MF4, 2818 }, { PseudoVSRA_VX_MF8, 2819 }, { PseudoVSRL_VI_M1, 2820 }, { PseudoVSRL_VI_M2, 2821 }, { PseudoVSRL_VI_M4, 2822 }, { PseudoVSRL_VI_M8, 2823 }, { PseudoVSRL_VI_MF2, 2824 }, { PseudoVSRL_VI_MF4, 2825 }, { PseudoVSRL_VI_MF8, 2826 }, { PseudoVSRL_VV_M1, 2827 }, { PseudoVSRL_VV_M2, 2828 }, { PseudoVSRL_VV_M4, 2829 }, { PseudoVSRL_VV_M8, 2830 }, { PseudoVSRL_VV_MF2, 2831 }, { PseudoVSRL_VV_MF4, 2832 }, { PseudoVSRL_VV_MF8, 2833 }, { PseudoVSRL_VX_M1, 2834 }, { PseudoVSRL_VX_M2, 2835 }, { PseudoVSRL_VX_M4, 2836 }, { PseudoVSRL_VX_M8, 2837 }, { PseudoVSRL_VX_MF2, 2838 }, { PseudoVSRL_VX_MF4, 2839 }, { PseudoVSRL_VX_MF8, 2840 }, { PseudoVSSRA_VI_M1, 2841 }, { PseudoVSSRA_VI_M2, 2842 }, { PseudoVSSRA_VI_M4, 2843 }, { PseudoVSSRA_VI_M8, 2844 }, { PseudoVSSRA_VI_MF2, 2845 }, { PseudoVSSRA_VI_MF4, 2846 }, { PseudoVSSRA_VI_MF8, 2847 }, { PseudoVSSRA_VV_M1, 2848 }, { PseudoVSSRA_VV_M2, 2849 }, { PseudoVSSRA_VV_M4, 2850 }, { PseudoVSSRA_VV_M8, 2851 }, { PseudoVSSRA_VV_MF2, 2852 }, { PseudoVSSRA_VV_MF4, 2853 }, { PseudoVSSRA_VV_MF8, 2854 }, { PseudoVSSRA_VX_M1, 2855 }, { PseudoVSSRA_VX_M2, 2856 }, { PseudoVSSRA_VX_M4, 2857 }, { PseudoVSSRA_VX_M8, 2858 }, { PseudoVSSRA_VX_MF2, 2859 }, { PseudoVSSRA_VX_MF4, 2860 }, { PseudoVSSRA_VX_MF8, 2861 }, { PseudoVSSRL_VI_M1, 2862 }, { PseudoVSSRL_VI_M2, 2863 }, { PseudoVSSRL_VI_M4, 2864 }, { PseudoVSSRL_VI_M8, 2865 }, { PseudoVSSRL_VI_MF2, 2866 }, { PseudoVSSRL_VI_MF4, 2867 }, { PseudoVSSRL_VI_MF8, 2868 }, { PseudoVSSRL_VV_M1, 2869 }, { PseudoVSSRL_VV_M2, 2870 }, { PseudoVSSRL_VV_M4, 2871 }, { PseudoVSSRL_VV_M8, 2872 }, { PseudoVSSRL_VV_MF2, 2873 }, { PseudoVSSRL_VV_MF4, 2874 }, { PseudoVSSRL_VV_MF8, 2875 }, { PseudoVSSRL_VX_M1, 2876 }, { PseudoVSSRL_VX_M2, 2877 }, { PseudoVSSRL_VX_M4, 2878 }, { PseudoVSSRL_VX_M8, 2879 }, { PseudoVSSRL_VX_MF2, 2880 }, { PseudoVSSRL_VX_MF4, 2881 }, { PseudoVSSRL_VX_MF8, 2882 }, { PseudoVSSUBU_VV_M1, 2883 }, { PseudoVSSUBU_VV_M2, 2884 }, { PseudoVSSUBU_VV_M4, 2885 }, { PseudoVSSUBU_VV_M8, 2886 }, { PseudoVSSUBU_VV_MF2, 2887 }, { PseudoVSSUBU_VV_MF4, 2888 }, { PseudoVSSUBU_VV_MF8, 2889 }, { PseudoVSSUBU_VX_M1, 2890 }, { PseudoVSSUBU_VX_M2, 2891 }, { PseudoVSSUBU_VX_M4, 2892 }, { PseudoVSSUBU_VX_M8, 2893 }, { PseudoVSSUBU_VX_MF2, 2894 }, { PseudoVSSUBU_VX_MF4, 2895 }, { PseudoVSSUBU_VX_MF8, 2896 }, { PseudoVSSUB_VV_M1, 2897 }, { PseudoVSSUB_VV_M2, 2898 }, { PseudoVSSUB_VV_M4, 2899 }, { PseudoVSSUB_VV_M8, 2900 }, { PseudoVSSUB_VV_MF2, 2901 }, { PseudoVSSUB_VV_MF4, 2902 }, { PseudoVSSUB_VV_MF8, 2903 }, { PseudoVSSUB_VX_M1, 2904 }, { PseudoVSSUB_VX_M2, 2905 }, { PseudoVSSUB_VX_M4, 2906 }, { PseudoVSSUB_VX_M8, 2907 }, { PseudoVSSUB_VX_MF2, 2908 }, { PseudoVSSUB_VX_MF4, 2909 }, { PseudoVSSUB_VX_MF8, 2910 }, { PseudoVSUB_VV_M1, 2911 }, { PseudoVSUB_VV_M2, 2912 }, { PseudoVSUB_VV_M4, 2913 }, { PseudoVSUB_VV_M8, 2914 }, { PseudoVSUB_VV_MF2, 2915 }, { PseudoVSUB_VV_MF4, 2916 }, { PseudoVSUB_VV_MF8, 2917 }, { PseudoVSUB_VX_M1, 2918 }, { PseudoVSUB_VX_M2, 2919 }, { PseudoVSUB_VX_M4, 2920 }, { PseudoVSUB_VX_M8, 2921 }, { PseudoVSUB_VX_MF2, 2922 }, { PseudoVSUB_VX_MF4, 2923 }, { PseudoVSUB_VX_MF8, 2924 }, { PseudoVWADDU_VV_M1, 2925 }, { PseudoVWADDU_VV_M2, 2926 }, { PseudoVWADDU_VV_M4, 2927 }, { PseudoVWADDU_VV_MF2, 2928 }, { PseudoVWADDU_VV_MF4, 2929 }, { PseudoVWADDU_VV_MF8, 2930 }, { PseudoVWADDU_VX_M1, 2931 }, { PseudoVWADDU_VX_M2, 2932 }, { PseudoVWADDU_VX_M4, 2933 }, { PseudoVWADDU_VX_MF2, 2934 }, { PseudoVWADDU_VX_MF4, 2935 }, { PseudoVWADDU_VX_MF8, 2936 }, { PseudoVWADDU_WV_M1, 2937 }, { PseudoVWADDU_WV_M1_TIED, 2938 }, { PseudoVWADDU_WV_M2, 2939 }, { PseudoVWADDU_WV_M2_TIED, 2940 }, { PseudoVWADDU_WV_M4, 2941 }, { PseudoVWADDU_WV_M4_TIED, 2942 }, { PseudoVWADDU_WV_MF2, 2943 }, { PseudoVWADDU_WV_MF2_TIED, 2944 }, { PseudoVWADDU_WV_MF4, 2945 }, { PseudoVWADDU_WV_MF4_TIED, 2946 }, { PseudoVWADDU_WV_MF8, 2947 }, { PseudoVWADDU_WV_MF8_TIED, 2948 }, { PseudoVWADDU_WX_M1, 2949 }, { PseudoVWADDU_WX_M2, 2950 }, { PseudoVWADDU_WX_M4, 2951 }, { PseudoVWADDU_WX_MF2, 2952 }, { PseudoVWADDU_WX_MF4, 2953 }, { PseudoVWADDU_WX_MF8, 2954 }, { PseudoVWADD_VV_M1, 2955 }, { PseudoVWADD_VV_M2, 2956 }, { PseudoVWADD_VV_M4, 2957 }, { PseudoVWADD_VV_MF2, 2958 }, { PseudoVWADD_VV_MF4, 2959 }, { PseudoVWADD_VV_MF8, 2960 }, { PseudoVWADD_VX_M1, 2961 }, { PseudoVWADD_VX_M2, 2962 }, { PseudoVWADD_VX_M4, 2963 }, { PseudoVWADD_VX_MF2, 2964 }, { PseudoVWADD_VX_MF4, 2965 }, { PseudoVWADD_VX_MF8, 2966 }, { PseudoVWADD_WV_M1, 2967 }, { PseudoVWADD_WV_M1_TIED, 2968 }, { PseudoVWADD_WV_M2, 2969 }, { PseudoVWADD_WV_M2_TIED, 2970 }, { PseudoVWADD_WV_M4, 2971 }, { PseudoVWADD_WV_M4_TIED, 2972 }, { PseudoVWADD_WV_MF2, 2973 }, { PseudoVWADD_WV_MF2_TIED, 2974 }, { PseudoVWADD_WV_MF4, 2975 }, { PseudoVWADD_WV_MF4_TIED, 2976 }, { PseudoVWADD_WV_MF8, 2977 }, { PseudoVWADD_WV_MF8_TIED, 2978 }, { PseudoVWADD_WX_M1, 2979 }, { PseudoVWADD_WX_M2, 2980 }, { PseudoVWADD_WX_M4, 2981 }, { PseudoVWADD_WX_MF2, 2982 }, { PseudoVWADD_WX_MF4, 2983 }, { PseudoVWADD_WX_MF8, 2984 }, { PseudoVWMACCSU_VV_M1, 2985 }, { PseudoVWMACCSU_VV_M2, 2986 }, { PseudoVWMACCSU_VV_M4, 2987 }, { PseudoVWMACCSU_VV_MF2, 2988 }, { PseudoVWMACCSU_VV_MF4, 2989 }, { PseudoVWMACCSU_VV_MF8, 2990 }, { PseudoVWMACCSU_VX_M1, 2991 }, { PseudoVWMACCSU_VX_M2, 2992 }, { PseudoVWMACCSU_VX_M4, 2993 }, { PseudoVWMACCSU_VX_MF2, 2994 }, { PseudoVWMACCSU_VX_MF4, 2995 }, { PseudoVWMACCSU_VX_MF8, 2996 }, { PseudoVWMACCUS_VX_M1, 2997 }, { PseudoVWMACCUS_VX_M2, 2998 }, { PseudoVWMACCUS_VX_M4, 2999 }, { PseudoVWMACCUS_VX_MF2, 3000 }, { PseudoVWMACCUS_VX_MF4, 3001 }, { PseudoVWMACCUS_VX_MF8, 3002 }, { PseudoVWMACCU_VV_M1, 3003 }, { PseudoVWMACCU_VV_M2, 3004 }, { PseudoVWMACCU_VV_M4, 3005 }, { PseudoVWMACCU_VV_MF2, 3006 }, { PseudoVWMACCU_VV_MF4, 3007 }, { PseudoVWMACCU_VV_MF8, 3008 }, { PseudoVWMACCU_VX_M1, 3009 }, { PseudoVWMACCU_VX_M2, 3010 }, { PseudoVWMACCU_VX_M4, 3011 }, { PseudoVWMACCU_VX_MF2, 3012 }, { PseudoVWMACCU_VX_MF4, 3013 }, { PseudoVWMACCU_VX_MF8, 3014 }, { PseudoVWMACC_VV_M1, 3015 }, { PseudoVWMACC_VV_M2, 3016 }, { PseudoVWMACC_VV_M4, 3017 }, { PseudoVWMACC_VV_MF2, 3018 }, { PseudoVWMACC_VV_MF4, 3019 }, { PseudoVWMACC_VV_MF8, 3020 }, { PseudoVWMACC_VX_M1, 3021 }, { PseudoVWMACC_VX_M2, 3022 }, { PseudoVWMACC_VX_M4, 3023 }, { PseudoVWMACC_VX_MF2, 3024 }, { PseudoVWMACC_VX_MF4, 3025 }, { PseudoVWMACC_VX_MF8, 3026 }, { PseudoVWMULSU_VV_M1, 3027 }, { PseudoVWMULSU_VV_M2, 3028 }, { PseudoVWMULSU_VV_M4, 3029 }, { PseudoVWMULSU_VV_MF2, 3030 }, { PseudoVWMULSU_VV_MF4, 3031 }, { PseudoVWMULSU_VV_MF8, 3032 }, { PseudoVWMULSU_VX_M1, 3033 }, { PseudoVWMULSU_VX_M2, 3034 }, { PseudoVWMULSU_VX_M4, 3035 }, { PseudoVWMULSU_VX_MF2, 3036 }, { PseudoVWMULSU_VX_MF4, 3037 }, { PseudoVWMULSU_VX_MF8, 3038 }, { PseudoVWMULU_VV_M1, 3039 }, { PseudoVWMULU_VV_M2, 3040 }, { PseudoVWMULU_VV_M4, 3041 }, { PseudoVWMULU_VV_MF2, 3042 }, { PseudoVWMULU_VV_MF4, 3043 }, { PseudoVWMULU_VV_MF8, 3044 }, { PseudoVWMULU_VX_M1, 3045 }, { PseudoVWMULU_VX_M2, 3046 }, { PseudoVWMULU_VX_M4, 3047 }, { PseudoVWMULU_VX_MF2, 3048 }, { PseudoVWMULU_VX_MF4, 3049 }, { PseudoVWMULU_VX_MF8, 3050 }, { PseudoVWMUL_VV_M1, 3051 }, { PseudoVWMUL_VV_M2, 3052 }, { PseudoVWMUL_VV_M4, 3053 }, { PseudoVWMUL_VV_MF2, 3054 }, { PseudoVWMUL_VV_MF4, 3055 }, { PseudoVWMUL_VV_MF8, 3056 }, { PseudoVWMUL_VX_M1, 3057 }, { PseudoVWMUL_VX_M2, 3058 }, { PseudoVWMUL_VX_M4, 3059 }, { PseudoVWMUL_VX_MF2, 3060 }, { PseudoVWMUL_VX_MF4, 3061 }, { PseudoVWMUL_VX_MF8, 3062 }, { PseudoVWREDSUMU_VS_M1_E16, 3063 }, { PseudoVWREDSUMU_VS_M1_E32, 3064 }, { PseudoVWREDSUMU_VS_M1_E8, 3065 }, { PseudoVWREDSUMU_VS_M2_E16, 3066 }, { PseudoVWREDSUMU_VS_M2_E32, 3067 }, { PseudoVWREDSUMU_VS_M2_E8, 3068 }, { PseudoVWREDSUMU_VS_M4_E16, 3069 }, { PseudoVWREDSUMU_VS_M4_E32, 3070 }, { PseudoVWREDSUMU_VS_M4_E8, 3071 }, { PseudoVWREDSUMU_VS_M8_E16, 3072 }, { PseudoVWREDSUMU_VS_M8_E32, 3073 }, { PseudoVWREDSUMU_VS_M8_E8, 3074 }, { PseudoVWREDSUMU_VS_MF2_E16, 3075 }, { PseudoVWREDSUMU_VS_MF2_E32, 3076 }, { PseudoVWREDSUMU_VS_MF2_E8, 3077 }, { PseudoVWREDSUMU_VS_MF4_E16, 3078 }, { PseudoVWREDSUMU_VS_MF4_E8, 3079 }, { PseudoVWREDSUMU_VS_MF8_E8, 3080 }, { PseudoVWREDSUM_VS_M1_E16, 3081 }, { PseudoVWREDSUM_VS_M1_E32, 3082 }, { PseudoVWREDSUM_VS_M1_E8, 3083 }, { PseudoVWREDSUM_VS_M2_E16, 3084 }, { PseudoVWREDSUM_VS_M2_E32, 3085 }, { PseudoVWREDSUM_VS_M2_E8, 3086 }, { PseudoVWREDSUM_VS_M4_E16, 3087 }, { PseudoVWREDSUM_VS_M4_E32, 3088 }, { PseudoVWREDSUM_VS_M4_E8, 3089 }, { PseudoVWREDSUM_VS_M8_E16, 3090 }, { PseudoVWREDSUM_VS_M8_E32, 3091 }, { PseudoVWREDSUM_VS_M8_E8, 3092 }, { PseudoVWREDSUM_VS_MF2_E16, 3093 }, { PseudoVWREDSUM_VS_MF2_E32, 3094 }, { PseudoVWREDSUM_VS_MF2_E8, 3095 }, { PseudoVWREDSUM_VS_MF4_E16, 3096 }, { PseudoVWREDSUM_VS_MF4_E8, 3097 }, { PseudoVWREDSUM_VS_MF8_E8, 3098 }, { PseudoVWSLL_VI_M1, 3099 }, { PseudoVWSLL_VI_M2, 3100 }, { PseudoVWSLL_VI_M4, 3101 }, { PseudoVWSLL_VI_MF2, 3102 }, { PseudoVWSLL_VI_MF4, 3103 }, { PseudoVWSLL_VI_MF8, 3104 }, { PseudoVWSLL_VV_M1, 3105 }, { PseudoVWSLL_VV_M2, 3106 }, { PseudoVWSLL_VV_M4, 3107 }, { PseudoVWSLL_VV_MF2, 3108 }, { PseudoVWSLL_VV_MF4, 3109 }, { PseudoVWSLL_VV_MF8, 3110 }, { PseudoVWSLL_VX_M1, 3111 }, { PseudoVWSLL_VX_M2, 3112 }, { PseudoVWSLL_VX_M4, 3113 }, { PseudoVWSLL_VX_MF2, 3114 }, { PseudoVWSLL_VX_MF4, 3115 }, { PseudoVWSLL_VX_MF8, 3116 }, { PseudoVWSUBU_VV_M1, 3117 }, { PseudoVWSUBU_VV_M2, 3118 }, { PseudoVWSUBU_VV_M4, 3119 }, { PseudoVWSUBU_VV_MF2, 3120 }, { PseudoVWSUBU_VV_MF4, 3121 }, { PseudoVWSUBU_VV_MF8, 3122 }, { PseudoVWSUBU_VX_M1, 3123 }, { PseudoVWSUBU_VX_M2, 3124 }, { PseudoVWSUBU_VX_M4, 3125 }, { PseudoVWSUBU_VX_MF2, 3126 }, { PseudoVWSUBU_VX_MF4, 3127 }, { PseudoVWSUBU_VX_MF8, 3128 }, { PseudoVWSUBU_WV_M1, 3129 }, { PseudoVWSUBU_WV_M1_TIED, 3130 }, { PseudoVWSUBU_WV_M2, 3131 }, { PseudoVWSUBU_WV_M2_TIED, 3132 }, { PseudoVWSUBU_WV_M4, 3133 }, { PseudoVWSUBU_WV_M4_TIED, 3134 }, { PseudoVWSUBU_WV_MF2, 3135 }, { PseudoVWSUBU_WV_MF2_TIED, 3136 }, { PseudoVWSUBU_WV_MF4, 3137 }, { PseudoVWSUBU_WV_MF4_TIED, 3138 }, { PseudoVWSUBU_WV_MF8, 3139 }, { PseudoVWSUBU_WV_MF8_TIED, 3140 }, { PseudoVWSUBU_WX_M1, 3141 }, { PseudoVWSUBU_WX_M2, 3142 }, { PseudoVWSUBU_WX_M4, 3143 }, { PseudoVWSUBU_WX_MF2, 3144 }, { PseudoVWSUBU_WX_MF4, 3145 }, { PseudoVWSUBU_WX_MF8, 3146 }, { PseudoVWSUB_VV_M1, 3147 }, { PseudoVWSUB_VV_M2, 3148 }, { PseudoVWSUB_VV_M4, 3149 }, { PseudoVWSUB_VV_MF2, 3150 }, { PseudoVWSUB_VV_MF4, 3151 }, { PseudoVWSUB_VV_MF8, 3152 }, { PseudoVWSUB_VX_M1, 3153 }, { PseudoVWSUB_VX_M2, 3154 }, { PseudoVWSUB_VX_M4, 3155 }, { PseudoVWSUB_VX_MF2, 3156 }, { PseudoVWSUB_VX_MF4, 3157 }, { PseudoVWSUB_VX_MF8, 3158 }, { PseudoVWSUB_WV_M1, 3159 }, { PseudoVWSUB_WV_M1_TIED, 3160 }, { PseudoVWSUB_WV_M2, 3161 }, { PseudoVWSUB_WV_M2_TIED, 3162 }, { PseudoVWSUB_WV_M4, 3163 }, { PseudoVWSUB_WV_M4_TIED, 3164 }, { PseudoVWSUB_WV_MF2, 3165 }, { PseudoVWSUB_WV_MF2_TIED, 3166 }, { PseudoVWSUB_WV_MF4, 3167 }, { PseudoVWSUB_WV_MF4_TIED, 3168 }, { PseudoVWSUB_WV_MF8, 3169 }, { PseudoVWSUB_WV_MF8_TIED, 3170 }, { PseudoVWSUB_WX_M1, 3171 }, { PseudoVWSUB_WX_M2, 3172 }, { PseudoVWSUB_WX_M4, 3173 }, { PseudoVWSUB_WX_MF2, 3174 }, { PseudoVWSUB_WX_MF4, 3175 }, { PseudoVWSUB_WX_MF8, 3176 }, { PseudoVXOR_VI_M1, 3177 }, { PseudoVXOR_VI_M2, 3178 }, { PseudoVXOR_VI_M4, 3179 }, { PseudoVXOR_VI_M8, 3180 }, { PseudoVXOR_VI_MF2, 3181 }, { PseudoVXOR_VI_MF4, 3182 }, { PseudoVXOR_VI_MF8, 3183 }, { PseudoVXOR_VV_M1, 3184 }, { PseudoVXOR_VV_M2, 3185 }, { PseudoVXOR_VV_M4, 3186 }, { PseudoVXOR_VV_M8, 3187 }, { PseudoVXOR_VV_MF2, 3188 }, { PseudoVXOR_VV_MF4, 3189 }, { PseudoVXOR_VV_MF8, 3190 }, { PseudoVXOR_VX_M1, 3191 }, { PseudoVXOR_VX_M2, 3192 }, { PseudoVXOR_VX_M4, 3193 }, { PseudoVXOR_VX_M8, 3194 }, { PseudoVXOR_VX_MF2, 3195 }, { PseudoVXOR_VX_MF4, 3196 }, { PseudoVXOR_VX_MF8, 3197 }, { PseudoVZEXT_VF2_M1, 3198 }, { PseudoVZEXT_VF2_M2, 3199 }, { PseudoVZEXT_VF2_M4, 3200 }, { PseudoVZEXT_VF2_M8, 3201 }, { PseudoVZEXT_VF2_MF2, 3202 }, { PseudoVZEXT_VF2_MF4, 3203 }, { PseudoVZEXT_VF4_M1, 3204 }, { PseudoVZEXT_VF4_M2, 3205 }, { PseudoVZEXT_VF4_M4, 3206 }, { PseudoVZEXT_VF4_M8, 3207 }, { PseudoVZEXT_VF4_MF2, 3208 }, { PseudoVZEXT_VF8_M1, 3209 }, { PseudoVZEXT_VF8_M2, 3210 }, { PseudoVZEXT_VF8_M4, 3211 }, { PseudoVZEXT_VF8_M8, 3212 }, }; struct KeyType { unsigned UnmaskedPseudo; }; KeyType Key = {UnmaskedPseudo}; struct Comp { bool operator()(const IndexType &LHS, const KeyType &RHS) const { if (LHS.UnmaskedPseudo < RHS.UnmaskedPseudo) return true; if (LHS.UnmaskedPseudo > RHS.UnmaskedPseudo) return false; return false; } }; auto Table = ArrayRef(Index); auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); if (Idx == Table.end() || Key.UnmaskedPseudo != Idx->UnmaskedPseudo) return nullptr; return &RISCVMaskedPseudosTable[Idx->_index]; } #endif #ifdef GET_RISCVOpcodesList_DECL const RISCVOpcode *lookupRISCVOpcodeByValue(uint8_t Value); const RISCVOpcode *lookupRISCVOpcodeByName(StringRef Name); #endif #ifdef GET_RISCVOpcodesList_IMPL constexpr RISCVOpcode RISCVOpcodesList[] = { { "LOAD", 0x3 }, // 0 { "LOAD_FP", 0x7 }, // 1 { "CUSTOM_0", 0xB }, // 2 { "MISC_MEM", 0xF }, // 3 { "OP_IMM", 0x13 }, // 4 { "AUIPC", 0x17 }, // 5 { "OP_IMM_32", 0x1B }, // 6 { "STORE", 0x23 }, // 7 { "STORE_FP", 0x27 }, // 8 { "CUSTOM_1", 0x2B }, // 9 { "AMO", 0x2F }, // 10 { "OP", 0x33 }, // 11 { "LUI", 0x37 }, // 12 { "OP_32", 0x3B }, // 13 { "MADD", 0x43 }, // 14 { "MSUB", 0x47 }, // 15 { "NMSUB", 0x4B }, // 16 { "NMADD", 0x4F }, // 17 { "OP_FP", 0x53 }, // 18 { "OP_V", 0x57 }, // 19 { "CUSTOM_2", 0x5B }, // 20 { "BRANCH", 0x63 }, // 21 { "JALR", 0x67 }, // 22 { "JAL", 0x6F }, // 23 { "SYSTEM", 0x73 }, // 24 { "OP_VE", 0x77 }, // 25 { "CUSTOM_3", 0x7B }, // 26 }; const RISCVOpcode *lookupRISCVOpcodeByValue(uint8_t Value) { struct KeyType { uint8_t Value; }; KeyType Key = {Value}; struct Comp { bool operator()(const RISCVOpcode &LHS, const KeyType &RHS) const { if (LHS.Value < RHS.Value) return true; if (LHS.Value > RHS.Value) return false; return false; } }; auto Table = ArrayRef(RISCVOpcodesList); auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); if (Idx == Table.end() || Key.Value != Idx->Value) return nullptr; return &*Idx; } const RISCVOpcode *lookupRISCVOpcodeByName(StringRef Name) { struct IndexType { const char * Name; unsigned _index; }; static const struct IndexType Index[] = { { "AMO", 10 }, { "AUIPC", 5 }, { "BRANCH", 21 }, { "CUSTOM_0", 2 }, { "CUSTOM_1", 9 }, { "CUSTOM_2", 20 }, { "CUSTOM_3", 26 }, { "JAL", 23 }, { "JALR", 22 }, { "LOAD", 0 }, { "LOAD_FP", 1 }, { "LUI", 12 }, { "MADD", 14 }, { "MISC_MEM", 3 }, { "MSUB", 15 }, { "NMADD", 17 }, { "NMSUB", 16 }, { "OP", 11 }, { "OP_32", 13 }, { "OP_FP", 18 }, { "OP_IMM", 4 }, { "OP_IMM_32", 6 }, { "OP_V", 19 }, { "OP_VE", 25 }, { "STORE", 7 }, { "STORE_FP", 8 }, { "SYSTEM", 24 }, }; struct KeyType { std::string Name; }; KeyType Key = {Name.upper()}; struct Comp { bool operator()(const IndexType &LHS, const KeyType &RHS) const { int CmpName = StringRef(LHS.Name).compare(RHS.Name); if (CmpName < 0) return true; if (CmpName > 0) return false; return false; } }; auto Table = ArrayRef(Index); auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); if (Idx == Table.end() || Key.Name != Idx->Name) return nullptr; return &RISCVOpcodesList[Idx->_index]; } #endif #ifdef GET_RISCVTuneInfoTable_DECL const RISCVTuneInfo *getRISCVTuneInfo(StringRef Name); #endif #ifdef GET_RISCVTuneInfoTable_IMPL constexpr RISCVTuneInfo RISCVTuneInfoTable[] = { { "generic", 0x1, 0x1, 0x0, 0x0, 0x1, 0xFFFFFFFF, 0x5, 0x6 }, // 0 { "generic-rv32", 0x1, 0x1, 0x0, 0x0, 0x1, 0xFFFFFFFF, 0x5, 0x6 }, // 1 { "generic-rv64", 0x1, 0x1, 0x0, 0x0, 0x1, 0xFFFFFFFF, 0x5, 0x6 }, // 2 }; const RISCVTuneInfo *getRISCVTuneInfo(StringRef Name) { struct IndexType { const char * Name; unsigned _index; }; static const struct IndexType Index[] = { { "GENERIC", 0 }, { "GENERIC-RV32", 1 }, { "GENERIC-RV64", 2 }, }; struct KeyType { std::string Name; }; KeyType Key = {Name.upper()}; struct Comp { bool operator()(const IndexType &LHS, const KeyType &RHS) const { int CmpName = StringRef(LHS.Name).compare(RHS.Name); if (CmpName < 0) return true; if (CmpName > 0) return false; return false; } }; auto Table = ArrayRef(Index); auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); if (Idx == Table.end() || Key.Name != Idx->Name) return nullptr; return &RISCVTuneInfoTable[Idx->_index]; } #endif #ifdef GET_RISCVVIntrinsicsTable_DECL const RISCVVIntrinsicInfo *getRISCVVIntrinsicInfo(unsigned IntrinsicID); #endif #ifdef GET_RISCVVIntrinsicsTable_IMPL constexpr RISCVVIntrinsicInfo RISCVVIntrinsicsTable[] = { { Intrinsic::riscv_sf_vc_fv_se, 0x3, 0x4 }, // 0 { Intrinsic::riscv_sf_vc_fvv_se, 0x3, 0x4 }, // 1 { Intrinsic::riscv_sf_vc_fvw_se, 0x3, 0x4 }, // 2 { Intrinsic::riscv_sf_vc_i_se, 0xF, 0x6 }, // 3 { Intrinsic::riscv_sf_vc_iv_se, 0xF, 0x4 }, // 4 { Intrinsic::riscv_sf_vc_ivv_se, 0xF, 0x4 }, // 5 { Intrinsic::riscv_sf_vc_ivw_se, 0xF, 0x4 }, // 6 { Intrinsic::riscv_sf_vc_v_fv, 0x2, 0x3 }, // 7 { Intrinsic::riscv_sf_vc_v_fv_se, 0x2, 0x3 }, // 8 { Intrinsic::riscv_sf_vc_v_fvv, 0x3, 0x4 }, // 9 { Intrinsic::riscv_sf_vc_v_fvv_se, 0x3, 0x4 }, // 10 { Intrinsic::riscv_sf_vc_v_fvw, 0x3, 0x4 }, // 11 { Intrinsic::riscv_sf_vc_v_fvw_se, 0x3, 0x4 }, // 12 { Intrinsic::riscv_sf_vc_v_i, 0xF, 0x3 }, // 13 { Intrinsic::riscv_sf_vc_v_i_se, 0xF, 0x3 }, // 14 { Intrinsic::riscv_sf_vc_v_iv, 0xF, 0x3 }, // 15 { Intrinsic::riscv_sf_vc_v_iv_se, 0xF, 0x3 }, // 16 { Intrinsic::riscv_sf_vc_v_ivv, 0xF, 0x4 }, // 17 { Intrinsic::riscv_sf_vc_v_ivv_se, 0xF, 0x4 }, // 18 { Intrinsic::riscv_sf_vc_v_ivw, 0xF, 0x4 }, // 19 { Intrinsic::riscv_sf_vc_v_ivw_se, 0xF, 0x4 }, // 20 { Intrinsic::riscv_sf_vc_v_vv, 0x2, 0x3 }, // 21 { Intrinsic::riscv_sf_vc_v_vv_se, 0x2, 0x3 }, // 22 { Intrinsic::riscv_sf_vc_v_vvv, 0x3, 0x4 }, // 23 { Intrinsic::riscv_sf_vc_v_vvv_se, 0x3, 0x4 }, // 24 { Intrinsic::riscv_sf_vc_v_vvw, 0x3, 0x4 }, // 25 { Intrinsic::riscv_sf_vc_v_vvw_se, 0x3, 0x4 }, // 26 { Intrinsic::riscv_sf_vc_v_x, 0x2, 0x3 }, // 27 { Intrinsic::riscv_sf_vc_v_x_se, 0x2, 0x3 }, // 28 { Intrinsic::riscv_sf_vc_v_xv, 0x2, 0x3 }, // 29 { Intrinsic::riscv_sf_vc_v_xv_se, 0x2, 0x3 }, // 30 { Intrinsic::riscv_sf_vc_v_xvv, 0x3, 0x4 }, // 31 { Intrinsic::riscv_sf_vc_v_xvv_se, 0x3, 0x4 }, // 32 { Intrinsic::riscv_sf_vc_v_xvw, 0x3, 0x4 }, // 33 { Intrinsic::riscv_sf_vc_v_xvw_se, 0x3, 0x4 }, // 34 { Intrinsic::riscv_sf_vc_vv_se, 0x3, 0x4 }, // 35 { Intrinsic::riscv_sf_vc_vvv_se, 0x3, 0x4 }, // 36 { Intrinsic::riscv_sf_vc_vvw_se, 0x3, 0x4 }, // 37 { Intrinsic::riscv_sf_vc_x_se, 0x3, 0x6 }, // 38 { Intrinsic::riscv_sf_vc_xv_se, 0x3, 0x4 }, // 39 { Intrinsic::riscv_sf_vc_xvv_se, 0x3, 0x4 }, // 40 { Intrinsic::riscv_sf_vc_xvw_se, 0x3, 0x4 }, // 41 { Intrinsic::riscv_sf_vfnrclip_x_f_qf, 0xF, 0x4 }, // 42 { Intrinsic::riscv_sf_vfnrclip_x_f_qf_mask, 0xF, 0x5 }, // 43 { Intrinsic::riscv_sf_vfnrclip_xu_f_qf, 0xF, 0x4 }, // 44 { Intrinsic::riscv_sf_vfnrclip_xu_f_qf_mask, 0xF, 0x5 }, // 45 { Intrinsic::riscv_sf_vfwmacc_4x4x4, 0xF, 0x3 }, // 46 { Intrinsic::riscv_sf_vqmacc_2x8x2, 0xF, 0x3 }, // 47 { Intrinsic::riscv_sf_vqmacc_4x8x4, 0xF, 0x3 }, // 48 { Intrinsic::riscv_sf_vqmaccsu_2x8x2, 0xF, 0x3 }, // 49 { Intrinsic::riscv_sf_vqmaccsu_4x8x4, 0xF, 0x3 }, // 50 { Intrinsic::riscv_sf_vqmaccu_2x8x2, 0xF, 0x3 }, // 51 { Intrinsic::riscv_sf_vqmaccu_4x8x4, 0xF, 0x3 }, // 52 { Intrinsic::riscv_sf_vqmaccus_2x8x2, 0xF, 0x3 }, // 53 { Intrinsic::riscv_sf_vqmaccus_4x8x4, 0xF, 0x3 }, // 54 { Intrinsic::riscv_th_vmaqa, 0x1, 0x3 }, // 55 { Intrinsic::riscv_th_vmaqa_mask, 0x1, 0x4 }, // 56 { Intrinsic::riscv_th_vmaqasu, 0x1, 0x3 }, // 57 { Intrinsic::riscv_th_vmaqasu_mask, 0x1, 0x4 }, // 58 { Intrinsic::riscv_th_vmaqau, 0x1, 0x3 }, // 59 { Intrinsic::riscv_th_vmaqau_mask, 0x1, 0x4 }, // 60 { Intrinsic::riscv_th_vmaqaus, 0x1, 0x3 }, // 61 { Intrinsic::riscv_th_vmaqaus_mask, 0x1, 0x4 }, // 62 { Intrinsic::riscv_vaadd, 0x2, 0x4 }, // 63 { Intrinsic::riscv_vaadd_mask, 0x2, 0x5 }, // 64 { Intrinsic::riscv_vaaddu, 0x2, 0x4 }, // 65 { Intrinsic::riscv_vaaddu_mask, 0x2, 0x5 }, // 66 { Intrinsic::riscv_vadc, 0x2, 0x4 }, // 67 { Intrinsic::riscv_vadd, 0x2, 0x3 }, // 68 { Intrinsic::riscv_vadd_mask, 0x2, 0x4 }, // 69 { Intrinsic::riscv_vaesdf_vs, 0xF, 0x2 }, // 70 { Intrinsic::riscv_vaesdf_vv, 0xF, 0x2 }, // 71 { Intrinsic::riscv_vaesdm_vs, 0xF, 0x2 }, // 72 { Intrinsic::riscv_vaesdm_vv, 0xF, 0x2 }, // 73 { Intrinsic::riscv_vaesef_vs, 0xF, 0x2 }, // 74 { Intrinsic::riscv_vaesef_vv, 0xF, 0x2 }, // 75 { Intrinsic::riscv_vaesem_vs, 0xF, 0x2 }, // 76 { Intrinsic::riscv_vaesem_vv, 0xF, 0x2 }, // 77 { Intrinsic::riscv_vaeskf1, 0x2, 0x3 }, // 78 { Intrinsic::riscv_vaeskf2, 0x2, 0x3 }, // 79 { Intrinsic::riscv_vaesz_vs, 0xF, 0x2 }, // 80 { Intrinsic::riscv_vand, 0x2, 0x3 }, // 81 { Intrinsic::riscv_vand_mask, 0x2, 0x4 }, // 82 { Intrinsic::riscv_vandn, 0x2, 0x3 }, // 83 { Intrinsic::riscv_vandn_mask, 0x2, 0x4 }, // 84 { Intrinsic::riscv_vasub, 0x2, 0x4 }, // 85 { Intrinsic::riscv_vasub_mask, 0x2, 0x5 }, // 86 { Intrinsic::riscv_vasubu, 0x2, 0x4 }, // 87 { Intrinsic::riscv_vasubu_mask, 0x2, 0x5 }, // 88 { Intrinsic::riscv_vbrev, 0xF, 0x2 }, // 89 { Intrinsic::riscv_vbrev_mask, 0xF, 0x3 }, // 90 { Intrinsic::riscv_vbrev8, 0xF, 0x2 }, // 91 { Intrinsic::riscv_vbrev8_mask, 0xF, 0x3 }, // 92 { Intrinsic::riscv_vclmul, 0x2, 0x3 }, // 93 { Intrinsic::riscv_vclmul_mask, 0x2, 0x4 }, // 94 { Intrinsic::riscv_vclmulh, 0x2, 0x3 }, // 95 { Intrinsic::riscv_vclmulh_mask, 0x2, 0x4 }, // 96 { Intrinsic::riscv_vclz, 0xF, 0x2 }, // 97 { Intrinsic::riscv_vclz_mask, 0xF, 0x3 }, // 98 { Intrinsic::riscv_vcompress, 0xF, 0x3 }, // 99 { Intrinsic::riscv_vcpop, 0xF, 0x1 }, // 100 { Intrinsic::riscv_vcpop_mask, 0xF, 0x2 }, // 101 { Intrinsic::riscv_vcpopv, 0xF, 0x2 }, // 102 { Intrinsic::riscv_vcpopv_mask, 0xF, 0x3 }, // 103 { Intrinsic::riscv_vctz, 0xF, 0x2 }, // 104 { Intrinsic::riscv_vctz_mask, 0xF, 0x3 }, // 105 { Intrinsic::riscv_vdiv, 0x2, 0x3 }, // 106 { Intrinsic::riscv_vdiv_mask, 0x2, 0x4 }, // 107 { Intrinsic::riscv_vdivu, 0x2, 0x3 }, // 108 { Intrinsic::riscv_vdivu_mask, 0x2, 0x4 }, // 109 { Intrinsic::riscv_vfadd, 0x2, 0x4 }, // 110 { Intrinsic::riscv_vfadd_mask, 0x2, 0x5 }, // 111 { Intrinsic::riscv_vfclass, 0xF, 0x1 }, // 112 { Intrinsic::riscv_vfclass_mask, 0xF, 0x3 }, // 113 { Intrinsic::riscv_vfcvt_f_x_v, 0xF, 0x3 }, // 114 { Intrinsic::riscv_vfcvt_f_x_v_mask, 0xF, 0x4 }, // 115 { Intrinsic::riscv_vfcvt_f_xu_v, 0xF, 0x3 }, // 116 { Intrinsic::riscv_vfcvt_f_xu_v_mask, 0xF, 0x4 }, // 117 { Intrinsic::riscv_vfcvt_rtz_x_f_v, 0xF, 0x2 }, // 118 { Intrinsic::riscv_vfcvt_rtz_x_f_v_mask, 0xF, 0x3 }, // 119 { Intrinsic::riscv_vfcvt_rtz_xu_f_v, 0xF, 0x2 }, // 120 { Intrinsic::riscv_vfcvt_rtz_xu_f_v_mask, 0xF, 0x3 }, // 121 { Intrinsic::riscv_vfcvt_x_f_v, 0xF, 0x3 }, // 122 { Intrinsic::riscv_vfcvt_x_f_v_mask, 0xF, 0x4 }, // 123 { Intrinsic::riscv_vfcvt_xu_f_v, 0xF, 0x3 }, // 124 { Intrinsic::riscv_vfcvt_xu_f_v_mask, 0xF, 0x4 }, // 125 { Intrinsic::riscv_vfdiv, 0x2, 0x4 }, // 126 { Intrinsic::riscv_vfdiv_mask, 0x2, 0x5 }, // 127 { Intrinsic::riscv_vfirst, 0xF, 0x1 }, // 128 { Intrinsic::riscv_vfirst_mask, 0xF, 0x2 }, // 129 { Intrinsic::riscv_vfmacc, 0x1, 0x4 }, // 130 { Intrinsic::riscv_vfmacc_mask, 0x1, 0x5 }, // 131 { Intrinsic::riscv_vfmadd, 0x1, 0x4 }, // 132 { Intrinsic::riscv_vfmadd_mask, 0x1, 0x5 }, // 133 { Intrinsic::riscv_vfmax, 0x2, 0x3 }, // 134 { Intrinsic::riscv_vfmax_mask, 0x2, 0x4 }, // 135 { Intrinsic::riscv_vfmerge, 0x2, 0x4 }, // 136 { Intrinsic::riscv_vfmin, 0x2, 0x3 }, // 137 { Intrinsic::riscv_vfmin_mask, 0x2, 0x4 }, // 138 { Intrinsic::riscv_vfmsac, 0x1, 0x4 }, // 139 { Intrinsic::riscv_vfmsac_mask, 0x1, 0x5 }, // 140 { Intrinsic::riscv_vfmsub, 0x1, 0x4 }, // 141 { Intrinsic::riscv_vfmsub_mask, 0x1, 0x5 }, // 142 { Intrinsic::riscv_vfmul, 0x2, 0x4 }, // 143 { Intrinsic::riscv_vfmul_mask, 0x2, 0x5 }, // 144 { Intrinsic::riscv_vfmv_f_s, 0xF, 0x1F }, // 145 { Intrinsic::riscv_vfmv_s_f, 0xF, 0x2 }, // 146 { Intrinsic::riscv_vfmv_v_f, 0xF, 0x2 }, // 147 { Intrinsic::riscv_vfncvt_f_f_w, 0xF, 0x3 }, // 148 { Intrinsic::riscv_vfncvt_f_f_w_mask, 0xF, 0x4 }, // 149 { Intrinsic::riscv_vfncvt_f_x_w, 0xF, 0x3 }, // 150 { Intrinsic::riscv_vfncvt_f_x_w_mask, 0xF, 0x4 }, // 151 { Intrinsic::riscv_vfncvt_f_xu_w, 0xF, 0x3 }, // 152 { Intrinsic::riscv_vfncvt_f_xu_w_mask, 0xF, 0x4 }, // 153 { Intrinsic::riscv_vfncvt_rod_f_f_w, 0xF, 0x2 }, // 154 { Intrinsic::riscv_vfncvt_rod_f_f_w_mask, 0xF, 0x3 }, // 155 { Intrinsic::riscv_vfncvt_rtz_x_f_w, 0xF, 0x2 }, // 156 { Intrinsic::riscv_vfncvt_rtz_x_f_w_mask, 0xF, 0x3 }, // 157 { Intrinsic::riscv_vfncvt_rtz_xu_f_w, 0xF, 0x2 }, // 158 { Intrinsic::riscv_vfncvt_rtz_xu_f_w_mask, 0xF, 0x3 }, // 159 { Intrinsic::riscv_vfncvt_x_f_w, 0xF, 0x3 }, // 160 { Intrinsic::riscv_vfncvt_x_f_w_mask, 0xF, 0x4 }, // 161 { Intrinsic::riscv_vfncvt_xu_f_w, 0xF, 0x3 }, // 162 { Intrinsic::riscv_vfncvt_xu_f_w_mask, 0xF, 0x4 }, // 163 { Intrinsic::riscv_vfncvtbf16_f_f_w, 0xF, 0x3 }, // 164 { Intrinsic::riscv_vfncvtbf16_f_f_w_mask, 0xF, 0x4 }, // 165 { Intrinsic::riscv_vfnmacc, 0x1, 0x4 }, // 166 { Intrinsic::riscv_vfnmacc_mask, 0x1, 0x5 }, // 167 { Intrinsic::riscv_vfnmadd, 0x1, 0x4 }, // 168 { Intrinsic::riscv_vfnmadd_mask, 0x1, 0x5 }, // 169 { Intrinsic::riscv_vfnmsac, 0x1, 0x4 }, // 170 { Intrinsic::riscv_vfnmsac_mask, 0x1, 0x5 }, // 171 { Intrinsic::riscv_vfnmsub, 0x1, 0x4 }, // 172 { Intrinsic::riscv_vfnmsub_mask, 0x1, 0x5 }, // 173 { Intrinsic::riscv_vfrdiv, 0x2, 0x4 }, // 174 { Intrinsic::riscv_vfrdiv_mask, 0x2, 0x5 }, // 175 { Intrinsic::riscv_vfrec7, 0xF, 0x3 }, // 176 { Intrinsic::riscv_vfrec7_mask, 0xF, 0x4 }, // 177 { Intrinsic::riscv_vfredmax, 0xF, 0x3 }, // 178 { Intrinsic::riscv_vfredmax_mask, 0xF, 0x4 }, // 179 { Intrinsic::riscv_vfredmin, 0xF, 0x3 }, // 180 { Intrinsic::riscv_vfredmin_mask, 0xF, 0x4 }, // 181 { Intrinsic::riscv_vfredosum, 0xF, 0x4 }, // 182 { Intrinsic::riscv_vfredosum_mask, 0xF, 0x5 }, // 183 { Intrinsic::riscv_vfredusum, 0xF, 0x4 }, // 184 { Intrinsic::riscv_vfredusum_mask, 0xF, 0x5 }, // 185 { Intrinsic::riscv_vfrsqrt7, 0xF, 0x2 }, // 186 { Intrinsic::riscv_vfrsqrt7_mask, 0xF, 0x3 }, // 187 { Intrinsic::riscv_vfrsub, 0x2, 0x4 }, // 188 { Intrinsic::riscv_vfrsub_mask, 0x2, 0x5 }, // 189 { Intrinsic::riscv_vfsgnj, 0x2, 0x3 }, // 190 { Intrinsic::riscv_vfsgnj_mask, 0x2, 0x4 }, // 191 { Intrinsic::riscv_vfsgnjn, 0x2, 0x3 }, // 192 { Intrinsic::riscv_vfsgnjn_mask, 0x2, 0x4 }, // 193 { Intrinsic::riscv_vfsgnjx, 0x2, 0x3 }, // 194 { Intrinsic::riscv_vfsgnjx_mask, 0x2, 0x4 }, // 195 { Intrinsic::riscv_vfslide1down, 0x2, 0x3 }, // 196 { Intrinsic::riscv_vfslide1down_mask, 0x2, 0x4 }, // 197 { Intrinsic::riscv_vfslide1up, 0x2, 0x3 }, // 198 { Intrinsic::riscv_vfslide1up_mask, 0x2, 0x4 }, // 199 { Intrinsic::riscv_vfsqrt, 0xF, 0x3 }, // 200 { Intrinsic::riscv_vfsqrt_mask, 0xF, 0x4 }, // 201 { Intrinsic::riscv_vfsub, 0x2, 0x4 }, // 202 { Intrinsic::riscv_vfsub_mask, 0x2, 0x5 }, // 203 { Intrinsic::riscv_vfwadd, 0x2, 0x4 }, // 204 { Intrinsic::riscv_vfwadd_mask, 0x2, 0x5 }, // 205 { Intrinsic::riscv_vfwadd_w, 0x2, 0x4 }, // 206 { Intrinsic::riscv_vfwadd_w_mask, 0x2, 0x5 }, // 207 { Intrinsic::riscv_vfwcvt_f_f_v, 0xF, 0x2 }, // 208 { Intrinsic::riscv_vfwcvt_f_f_v_mask, 0xF, 0x3 }, // 209 { Intrinsic::riscv_vfwcvt_f_x_v, 0xF, 0x2 }, // 210 { Intrinsic::riscv_vfwcvt_f_x_v_mask, 0xF, 0x3 }, // 211 { Intrinsic::riscv_vfwcvt_f_xu_v, 0xF, 0x2 }, // 212 { Intrinsic::riscv_vfwcvt_f_xu_v_mask, 0xF, 0x3 }, // 213 { Intrinsic::riscv_vfwcvt_rtz_x_f_v, 0xF, 0x2 }, // 214 { Intrinsic::riscv_vfwcvt_rtz_x_f_v_mask, 0xF, 0x3 }, // 215 { Intrinsic::riscv_vfwcvt_rtz_xu_f_v, 0xF, 0x2 }, // 216 { Intrinsic::riscv_vfwcvt_rtz_xu_f_v_mask, 0xF, 0x3 }, // 217 { Intrinsic::riscv_vfwcvt_x_f_v, 0xF, 0x3 }, // 218 { Intrinsic::riscv_vfwcvt_x_f_v_mask, 0xF, 0x4 }, // 219 { Intrinsic::riscv_vfwcvt_xu_f_v, 0xF, 0x3 }, // 220 { Intrinsic::riscv_vfwcvt_xu_f_v_mask, 0xF, 0x4 }, // 221 { Intrinsic::riscv_vfwcvtbf16_f_f_v, 0xF, 0x2 }, // 222 { Intrinsic::riscv_vfwcvtbf16_f_f_v_mask, 0xF, 0x3 }, // 223 { Intrinsic::riscv_vfwmacc, 0x1, 0x4 }, // 224 { Intrinsic::riscv_vfwmacc_mask, 0x1, 0x5 }, // 225 { Intrinsic::riscv_vfwmaccbf16, 0x1, 0x4 }, // 226 { Intrinsic::riscv_vfwmaccbf16_mask, 0x1, 0x5 }, // 227 { Intrinsic::riscv_vfwmsac, 0x1, 0x4 }, // 228 { Intrinsic::riscv_vfwmsac_mask, 0x1, 0x5 }, // 229 { Intrinsic::riscv_vfwmul, 0x2, 0x4 }, // 230 { Intrinsic::riscv_vfwmul_mask, 0x2, 0x5 }, // 231 { Intrinsic::riscv_vfwnmacc, 0x1, 0x4 }, // 232 { Intrinsic::riscv_vfwnmacc_mask, 0x1, 0x5 }, // 233 { Intrinsic::riscv_vfwnmsac, 0x1, 0x4 }, // 234 { Intrinsic::riscv_vfwnmsac_mask, 0x1, 0x5 }, // 235 { Intrinsic::riscv_vfwredosum, 0xF, 0x4 }, // 236 { Intrinsic::riscv_vfwredosum_mask, 0xF, 0x5 }, // 237 { Intrinsic::riscv_vfwredusum, 0xF, 0x4 }, // 238 { Intrinsic::riscv_vfwredusum_mask, 0xF, 0x5 }, // 239 { Intrinsic::riscv_vfwsub, 0x2, 0x4 }, // 240 { Intrinsic::riscv_vfwsub_mask, 0x2, 0x5 }, // 241 { Intrinsic::riscv_vfwsub_w, 0x2, 0x4 }, // 242 { Intrinsic::riscv_vfwsub_w_mask, 0x2, 0x5 }, // 243 { Intrinsic::riscv_vghsh, 0x2, 0x3 }, // 244 { Intrinsic::riscv_vgmul_vv, 0xF, 0x2 }, // 245 { Intrinsic::riscv_vid, 0xF, 0x1 }, // 246 { Intrinsic::riscv_vid_mask, 0xF, 0x2 }, // 247 { Intrinsic::riscv_viota, 0xF, 0x2 }, // 248 { Intrinsic::riscv_viota_mask, 0xF, 0x3 }, // 249 { Intrinsic::riscv_vle, 0xF, 0x2 }, // 250 { Intrinsic::riscv_vle_mask, 0xF, 0x3 }, // 251 { Intrinsic::riscv_vleff, 0xF, 0x2 }, // 252 { Intrinsic::riscv_vleff_mask, 0xF, 0x3 }, // 253 { Intrinsic::riscv_vlm, 0xF, 0x1 }, // 254 { Intrinsic::riscv_vloxei, 0xF, 0x3 }, // 255 { Intrinsic::riscv_vloxei_mask, 0xF, 0x4 }, // 256 { Intrinsic::riscv_vloxseg2, 0xF, 0x3 }, // 257 { Intrinsic::riscv_vloxseg2_mask, 0xF, 0x4 }, // 258 { Intrinsic::riscv_vloxseg3, 0xF, 0x3 }, // 259 { Intrinsic::riscv_vloxseg3_mask, 0xF, 0x4 }, // 260 { Intrinsic::riscv_vloxseg4, 0xF, 0x3 }, // 261 { Intrinsic::riscv_vloxseg4_mask, 0xF, 0x4 }, // 262 { Intrinsic::riscv_vloxseg5, 0xF, 0x3 }, // 263 { Intrinsic::riscv_vloxseg5_mask, 0xF, 0x4 }, // 264 { Intrinsic::riscv_vloxseg6, 0xF, 0x3 }, // 265 { Intrinsic::riscv_vloxseg6_mask, 0xF, 0x4 }, // 266 { Intrinsic::riscv_vloxseg7, 0xF, 0x3 }, // 267 { Intrinsic::riscv_vloxseg7_mask, 0xF, 0x4 }, // 268 { Intrinsic::riscv_vloxseg8, 0xF, 0x3 }, // 269 { Intrinsic::riscv_vloxseg8_mask, 0xF, 0x4 }, // 270 { Intrinsic::riscv_vlse, 0xF, 0x3 }, // 271 { Intrinsic::riscv_vlse_mask, 0xF, 0x4 }, // 272 { Intrinsic::riscv_vlseg2, 0xF, 0x2 }, // 273 { Intrinsic::riscv_vlseg2_mask, 0xF, 0x3 }, // 274 { Intrinsic::riscv_vlseg2ff, 0xF, 0x2 }, // 275 { Intrinsic::riscv_vlseg2ff_mask, 0xF, 0x3 }, // 276 { Intrinsic::riscv_vlseg3, 0xF, 0x2 }, // 277 { Intrinsic::riscv_vlseg3_mask, 0xF, 0x3 }, // 278 { Intrinsic::riscv_vlseg3ff, 0xF, 0x2 }, // 279 { Intrinsic::riscv_vlseg3ff_mask, 0xF, 0x3 }, // 280 { Intrinsic::riscv_vlseg4, 0xF, 0x2 }, // 281 { Intrinsic::riscv_vlseg4_mask, 0xF, 0x3 }, // 282 { Intrinsic::riscv_vlseg4ff, 0xF, 0x2 }, // 283 { Intrinsic::riscv_vlseg4ff_mask, 0xF, 0x3 }, // 284 { Intrinsic::riscv_vlseg5, 0xF, 0x2 }, // 285 { Intrinsic::riscv_vlseg5_mask, 0xF, 0x3 }, // 286 { Intrinsic::riscv_vlseg5ff, 0xF, 0x2 }, // 287 { Intrinsic::riscv_vlseg5ff_mask, 0xF, 0x3 }, // 288 { Intrinsic::riscv_vlseg6, 0xF, 0x2 }, // 289 { Intrinsic::riscv_vlseg6_mask, 0xF, 0x3 }, // 290 { Intrinsic::riscv_vlseg6ff, 0xF, 0x2 }, // 291 { Intrinsic::riscv_vlseg6ff_mask, 0xF, 0x3 }, // 292 { Intrinsic::riscv_vlseg7, 0xF, 0x2 }, // 293 { Intrinsic::riscv_vlseg7_mask, 0xF, 0x3 }, // 294 { Intrinsic::riscv_vlseg7ff, 0xF, 0x2 }, // 295 { Intrinsic::riscv_vlseg7ff_mask, 0xF, 0x3 }, // 296 { Intrinsic::riscv_vlseg8, 0xF, 0x2 }, // 297 { Intrinsic::riscv_vlseg8_mask, 0xF, 0x3 }, // 298 { Intrinsic::riscv_vlseg8ff, 0xF, 0x2 }, // 299 { Intrinsic::riscv_vlseg8ff_mask, 0xF, 0x3 }, // 300 { Intrinsic::riscv_vlsseg2, 0xF, 0x3 }, // 301 { Intrinsic::riscv_vlsseg2_mask, 0xF, 0x4 }, // 302 { Intrinsic::riscv_vlsseg3, 0xF, 0x3 }, // 303 { Intrinsic::riscv_vlsseg3_mask, 0xF, 0x4 }, // 304 { Intrinsic::riscv_vlsseg4, 0xF, 0x3 }, // 305 { Intrinsic::riscv_vlsseg4_mask, 0xF, 0x4 }, // 306 { Intrinsic::riscv_vlsseg5, 0xF, 0x3 }, // 307 { Intrinsic::riscv_vlsseg5_mask, 0xF, 0x4 }, // 308 { Intrinsic::riscv_vlsseg6, 0xF, 0x3 }, // 309 { Intrinsic::riscv_vlsseg6_mask, 0xF, 0x4 }, // 310 { Intrinsic::riscv_vlsseg7, 0xF, 0x3 }, // 311 { Intrinsic::riscv_vlsseg7_mask, 0xF, 0x4 }, // 312 { Intrinsic::riscv_vlsseg8, 0xF, 0x3 }, // 313 { Intrinsic::riscv_vlsseg8_mask, 0xF, 0x4 }, // 314 { Intrinsic::riscv_vluxei, 0xF, 0x3 }, // 315 { Intrinsic::riscv_vluxei_mask, 0xF, 0x4 }, // 316 { Intrinsic::riscv_vluxseg2, 0xF, 0x3 }, // 317 { Intrinsic::riscv_vluxseg2_mask, 0xF, 0x4 }, // 318 { Intrinsic::riscv_vluxseg3, 0xF, 0x3 }, // 319 { Intrinsic::riscv_vluxseg3_mask, 0xF, 0x4 }, // 320 { Intrinsic::riscv_vluxseg4, 0xF, 0x3 }, // 321 { Intrinsic::riscv_vluxseg4_mask, 0xF, 0x4 }, // 322 { Intrinsic::riscv_vluxseg5, 0xF, 0x3 }, // 323 { Intrinsic::riscv_vluxseg5_mask, 0xF, 0x4 }, // 324 { Intrinsic::riscv_vluxseg6, 0xF, 0x3 }, // 325 { Intrinsic::riscv_vluxseg6_mask, 0xF, 0x4 }, // 326 { Intrinsic::riscv_vluxseg7, 0xF, 0x3 }, // 327 { Intrinsic::riscv_vluxseg7_mask, 0xF, 0x4 }, // 328 { Intrinsic::riscv_vluxseg8, 0xF, 0x3 }, // 329 { Intrinsic::riscv_vluxseg8_mask, 0xF, 0x4 }, // 330 { Intrinsic::riscv_vmacc, 0x1, 0x3 }, // 331 { Intrinsic::riscv_vmacc_mask, 0x1, 0x4 }, // 332 { Intrinsic::riscv_vmadc, 0x1, 0x2 }, // 333 { Intrinsic::riscv_vmadc_carry_in, 0x1, 0x3 }, // 334 { Intrinsic::riscv_vmadd, 0x1, 0x3 }, // 335 { Intrinsic::riscv_vmadd_mask, 0x1, 0x4 }, // 336 { Intrinsic::riscv_vmand, 0xF, 0x2 }, // 337 { Intrinsic::riscv_vmandn, 0xF, 0x2 }, // 338 { Intrinsic::riscv_vmax, 0x2, 0x3 }, // 339 { Intrinsic::riscv_vmax_mask, 0x2, 0x4 }, // 340 { Intrinsic::riscv_vmaxu, 0x2, 0x3 }, // 341 { Intrinsic::riscv_vmaxu_mask, 0x2, 0x4 }, // 342 { Intrinsic::riscv_vmclr, 0xF, 0x1 }, // 343 { Intrinsic::riscv_vmerge, 0x2, 0x4 }, // 344 { Intrinsic::riscv_vmfeq, 0x1, 0x2 }, // 345 { Intrinsic::riscv_vmfeq_mask, 0x2, 0x4 }, // 346 { Intrinsic::riscv_vmfge, 0x1, 0x2 }, // 347 { Intrinsic::riscv_vmfge_mask, 0x2, 0x4 }, // 348 { Intrinsic::riscv_vmfgt, 0x1, 0x2 }, // 349 { Intrinsic::riscv_vmfgt_mask, 0x2, 0x4 }, // 350 { Intrinsic::riscv_vmfle, 0x1, 0x2 }, // 351 { Intrinsic::riscv_vmfle_mask, 0x2, 0x4 }, // 352 { Intrinsic::riscv_vmflt, 0x1, 0x2 }, // 353 { Intrinsic::riscv_vmflt_mask, 0x2, 0x4 }, // 354 { Intrinsic::riscv_vmfne, 0x1, 0x2 }, // 355 { Intrinsic::riscv_vmfne_mask, 0x2, 0x4 }, // 356 { Intrinsic::riscv_vmin, 0x2, 0x3 }, // 357 { Intrinsic::riscv_vmin_mask, 0x2, 0x4 }, // 358 { Intrinsic::riscv_vminu, 0x2, 0x3 }, // 359 { Intrinsic::riscv_vminu_mask, 0x2, 0x4 }, // 360 { Intrinsic::riscv_vmnand, 0xF, 0x2 }, // 361 { Intrinsic::riscv_vmnor, 0xF, 0x2 }, // 362 { Intrinsic::riscv_vmor, 0xF, 0x2 }, // 363 { Intrinsic::riscv_vmorn, 0xF, 0x2 }, // 364 { Intrinsic::riscv_vmsbc, 0x1, 0x2 }, // 365 { Intrinsic::riscv_vmsbc_borrow_in, 0x1, 0x3 }, // 366 { Intrinsic::riscv_vmsbf, 0xF, 0x1 }, // 367 { Intrinsic::riscv_vmsbf_mask, 0xF, 0x3 }, // 368 { Intrinsic::riscv_vmseq, 0x1, 0x2 }, // 369 { Intrinsic::riscv_vmseq_mask, 0x2, 0x4 }, // 370 { Intrinsic::riscv_vmset, 0xF, 0x1 }, // 371 { Intrinsic::riscv_vmsge, 0x1, 0x2 }, // 372 { Intrinsic::riscv_vmsge_mask, 0x2, 0x4 }, // 373 { Intrinsic::riscv_vmsgeu, 0x1, 0x2 }, // 374 { Intrinsic::riscv_vmsgeu_mask, 0x2, 0x4 }, // 375 { Intrinsic::riscv_vmsgt, 0x1, 0x2 }, // 376 { Intrinsic::riscv_vmsgt_mask, 0x2, 0x4 }, // 377 { Intrinsic::riscv_vmsgtu, 0x1, 0x2 }, // 378 { Intrinsic::riscv_vmsgtu_mask, 0x2, 0x4 }, // 379 { Intrinsic::riscv_vmsif, 0xF, 0x1 }, // 380 { Intrinsic::riscv_vmsif_mask, 0xF, 0x3 }, // 381 { Intrinsic::riscv_vmsle, 0x1, 0x2 }, // 382 { Intrinsic::riscv_vmsle_mask, 0x2, 0x4 }, // 383 { Intrinsic::riscv_vmsleu, 0x1, 0x2 }, // 384 { Intrinsic::riscv_vmsleu_mask, 0x2, 0x4 }, // 385 { Intrinsic::riscv_vmslt, 0x1, 0x2 }, // 386 { Intrinsic::riscv_vmslt_mask, 0x2, 0x4 }, // 387 { Intrinsic::riscv_vmsltu, 0x1, 0x2 }, // 388 { Intrinsic::riscv_vmsltu_mask, 0x2, 0x4 }, // 389 { Intrinsic::riscv_vmsne, 0x1, 0x2 }, // 390 { Intrinsic::riscv_vmsne_mask, 0x2, 0x4 }, // 391 { Intrinsic::riscv_vmsof, 0xF, 0x1 }, // 392 { Intrinsic::riscv_vmsof_mask, 0xF, 0x3 }, // 393 { Intrinsic::riscv_vmul, 0x2, 0x3 }, // 394 { Intrinsic::riscv_vmul_mask, 0x2, 0x4 }, // 395 { Intrinsic::riscv_vmulh, 0x2, 0x3 }, // 396 { Intrinsic::riscv_vmulh_mask, 0x2, 0x4 }, // 397 { Intrinsic::riscv_vmulhsu, 0x2, 0x3 }, // 398 { Intrinsic::riscv_vmulhsu_mask, 0x2, 0x4 }, // 399 { Intrinsic::riscv_vmulhu, 0x2, 0x3 }, // 400 { Intrinsic::riscv_vmulhu_mask, 0x2, 0x4 }, // 401 { Intrinsic::riscv_vmv_s_x, 0xF, 0x2 }, // 402 { Intrinsic::riscv_vmv_v_v, 0xF, 0x2 }, // 403 { Intrinsic::riscv_vmv_v_x, 0xF, 0x2 }, // 404 { Intrinsic::riscv_vmv_x_s, 0xF, 0x1F }, // 405 { Intrinsic::riscv_vmxnor, 0xF, 0x2 }, // 406 { Intrinsic::riscv_vmxor, 0xF, 0x2 }, // 407 { Intrinsic::riscv_vnclip, 0xF, 0x4 }, // 408 { Intrinsic::riscv_vnclip_mask, 0xF, 0x5 }, // 409 { Intrinsic::riscv_vnclipu, 0xF, 0x4 }, // 410 { Intrinsic::riscv_vnclipu_mask, 0xF, 0x5 }, // 411 { Intrinsic::riscv_vnmsac, 0x1, 0x3 }, // 412 { Intrinsic::riscv_vnmsac_mask, 0x1, 0x4 }, // 413 { Intrinsic::riscv_vnmsub, 0x1, 0x3 }, // 414 { Intrinsic::riscv_vnmsub_mask, 0x1, 0x4 }, // 415 { Intrinsic::riscv_vnsra, 0xF, 0x3 }, // 416 { Intrinsic::riscv_vnsra_mask, 0xF, 0x4 }, // 417 { Intrinsic::riscv_vnsrl, 0xF, 0x3 }, // 418 { Intrinsic::riscv_vnsrl_mask, 0xF, 0x4 }, // 419 { Intrinsic::riscv_vor, 0x2, 0x3 }, // 420 { Intrinsic::riscv_vor_mask, 0x2, 0x4 }, // 421 { Intrinsic::riscv_vredand, 0xF, 0x3 }, // 422 { Intrinsic::riscv_vredand_mask, 0xF, 0x4 }, // 423 { Intrinsic::riscv_vredmax, 0xF, 0x3 }, // 424 { Intrinsic::riscv_vredmax_mask, 0xF, 0x4 }, // 425 { Intrinsic::riscv_vredmaxu, 0xF, 0x3 }, // 426 { Intrinsic::riscv_vredmaxu_mask, 0xF, 0x4 }, // 427 { Intrinsic::riscv_vredmin, 0xF, 0x3 }, // 428 { Intrinsic::riscv_vredmin_mask, 0xF, 0x4 }, // 429 { Intrinsic::riscv_vredminu, 0xF, 0x3 }, // 430 { Intrinsic::riscv_vredminu_mask, 0xF, 0x4 }, // 431 { Intrinsic::riscv_vredor, 0xF, 0x3 }, // 432 { Intrinsic::riscv_vredor_mask, 0xF, 0x4 }, // 433 { Intrinsic::riscv_vredsum, 0xF, 0x3 }, // 434 { Intrinsic::riscv_vredsum_mask, 0xF, 0x4 }, // 435 { Intrinsic::riscv_vredxor, 0xF, 0x3 }, // 436 { Intrinsic::riscv_vredxor_mask, 0xF, 0x4 }, // 437 { Intrinsic::riscv_vrem, 0x2, 0x3 }, // 438 { Intrinsic::riscv_vrem_mask, 0x2, 0x4 }, // 439 { Intrinsic::riscv_vremu, 0x2, 0x3 }, // 440 { Intrinsic::riscv_vremu_mask, 0x2, 0x4 }, // 441 { Intrinsic::riscv_vrev8, 0xF, 0x2 }, // 442 { Intrinsic::riscv_vrev8_mask, 0xF, 0x3 }, // 443 { Intrinsic::riscv_vrgather_vv, 0xF, 0x3 }, // 444 { Intrinsic::riscv_vrgather_vv_mask, 0xF, 0x4 }, // 445 { Intrinsic::riscv_vrgather_vx, 0xF, 0x3 }, // 446 { Intrinsic::riscv_vrgather_vx_mask, 0xF, 0x4 }, // 447 { Intrinsic::riscv_vrgatherei16_vv, 0xF, 0x3 }, // 448 { Intrinsic::riscv_vrgatherei16_vv_mask, 0xF, 0x4 }, // 449 { Intrinsic::riscv_vrol, 0x2, 0x3 }, // 450 { Intrinsic::riscv_vrol_mask, 0x2, 0x4 }, // 451 { Intrinsic::riscv_vror, 0x2, 0x3 }, // 452 { Intrinsic::riscv_vror_mask, 0x2, 0x4 }, // 453 { Intrinsic::riscv_vrsub, 0x2, 0x3 }, // 454 { Intrinsic::riscv_vrsub_mask, 0x2, 0x4 }, // 455 { Intrinsic::riscv_vsadd, 0x2, 0x3 }, // 456 { Intrinsic::riscv_vsadd_mask, 0x2, 0x4 }, // 457 { Intrinsic::riscv_vsaddu, 0x2, 0x3 }, // 458 { Intrinsic::riscv_vsaddu_mask, 0x2, 0x4 }, // 459 { Intrinsic::riscv_vsbc, 0x2, 0x4 }, // 460 { Intrinsic::riscv_vse, 0xF, 0x2 }, // 461 { Intrinsic::riscv_vse_mask, 0xF, 0x3 }, // 462 { Intrinsic::riscv_vsext, 0xF, 0x2 }, // 463 { Intrinsic::riscv_vsext_mask, 0xF, 0x3 }, // 464 { Intrinsic::riscv_vsha2ch, 0x2, 0x3 }, // 465 { Intrinsic::riscv_vsha2cl, 0x2, 0x3 }, // 466 { Intrinsic::riscv_vsha2ms, 0x2, 0x3 }, // 467 { Intrinsic::riscv_vslide1down, 0x2, 0x3 }, // 468 { Intrinsic::riscv_vslide1down_mask, 0x2, 0x4 }, // 469 { Intrinsic::riscv_vslide1up, 0x2, 0x3 }, // 470 { Intrinsic::riscv_vslide1up_mask, 0x2, 0x4 }, // 471 { Intrinsic::riscv_vslidedown, 0xF, 0x3 }, // 472 { Intrinsic::riscv_vslidedown_mask, 0xF, 0x4 }, // 473 { Intrinsic::riscv_vslideup, 0xF, 0x3 }, // 474 { Intrinsic::riscv_vslideup_mask, 0xF, 0x4 }, // 475 { Intrinsic::riscv_vsll, 0xF, 0x3 }, // 476 { Intrinsic::riscv_vsll_mask, 0xF, 0x4 }, // 477 { Intrinsic::riscv_vsm, 0xF, 0x2 }, // 478 { Intrinsic::riscv_vsm3c, 0x2, 0x3 }, // 479 { Intrinsic::riscv_vsm3me, 0x2, 0x3 }, // 480 { Intrinsic::riscv_vsm4k, 0x2, 0x3 }, // 481 { Intrinsic::riscv_vsm4r_vs, 0xF, 0x2 }, // 482 { Intrinsic::riscv_vsm4r_vv, 0xF, 0x2 }, // 483 { Intrinsic::riscv_vsmul, 0x2, 0x4 }, // 484 { Intrinsic::riscv_vsmul_mask, 0x2, 0x5 }, // 485 { Intrinsic::riscv_vsoxei, 0xF, 0x3 }, // 486 { Intrinsic::riscv_vsoxei_mask, 0xF, 0x4 }, // 487 { Intrinsic::riscv_vsoxseg2, 0xF, 0x3 }, // 488 { Intrinsic::riscv_vsoxseg2_mask, 0xF, 0x4 }, // 489 { Intrinsic::riscv_vsoxseg3, 0xF, 0x3 }, // 490 { Intrinsic::riscv_vsoxseg3_mask, 0xF, 0x4 }, // 491 { Intrinsic::riscv_vsoxseg4, 0xF, 0x3 }, // 492 { Intrinsic::riscv_vsoxseg4_mask, 0xF, 0x4 }, // 493 { Intrinsic::riscv_vsoxseg5, 0xF, 0x3 }, // 494 { Intrinsic::riscv_vsoxseg5_mask, 0xF, 0x4 }, // 495 { Intrinsic::riscv_vsoxseg6, 0xF, 0x3 }, // 496 { Intrinsic::riscv_vsoxseg6_mask, 0xF, 0x4 }, // 497 { Intrinsic::riscv_vsoxseg7, 0xF, 0x3 }, // 498 { Intrinsic::riscv_vsoxseg7_mask, 0xF, 0x4 }, // 499 { Intrinsic::riscv_vsoxseg8, 0xF, 0x3 }, // 500 { Intrinsic::riscv_vsoxseg8_mask, 0xF, 0x4 }, // 501 { Intrinsic::riscv_vsra, 0xF, 0x3 }, // 502 { Intrinsic::riscv_vsra_mask, 0xF, 0x4 }, // 503 { Intrinsic::riscv_vsrl, 0xF, 0x3 }, // 504 { Intrinsic::riscv_vsrl_mask, 0xF, 0x4 }, // 505 { Intrinsic::riscv_vsse, 0xF, 0x3 }, // 506 { Intrinsic::riscv_vsse_mask, 0xF, 0x4 }, // 507 { Intrinsic::riscv_vsseg2, 0xF, 0x2 }, // 508 { Intrinsic::riscv_vsseg2_mask, 0xF, 0x3 }, // 509 { Intrinsic::riscv_vsseg3, 0xF, 0x2 }, // 510 { Intrinsic::riscv_vsseg3_mask, 0xF, 0x3 }, // 511 { Intrinsic::riscv_vsseg4, 0xF, 0x2 }, // 512 { Intrinsic::riscv_vsseg4_mask, 0xF, 0x3 }, // 513 { Intrinsic::riscv_vsseg5, 0xF, 0x2 }, // 514 { Intrinsic::riscv_vsseg5_mask, 0xF, 0x3 }, // 515 { Intrinsic::riscv_vsseg6, 0xF, 0x2 }, // 516 { Intrinsic::riscv_vsseg6_mask, 0xF, 0x3 }, // 517 { Intrinsic::riscv_vsseg7, 0xF, 0x2 }, // 518 { Intrinsic::riscv_vsseg7_mask, 0xF, 0x3 }, // 519 { Intrinsic::riscv_vsseg8, 0xF, 0x2 }, // 520 { Intrinsic::riscv_vsseg8_mask, 0xF, 0x3 }, // 521 { Intrinsic::riscv_vssra, 0xF, 0x4 }, // 522 { Intrinsic::riscv_vssra_mask, 0xF, 0x5 }, // 523 { Intrinsic::riscv_vssrl, 0xF, 0x4 }, // 524 { Intrinsic::riscv_vssrl_mask, 0xF, 0x5 }, // 525 { Intrinsic::riscv_vssseg2, 0xF, 0x3 }, // 526 { Intrinsic::riscv_vssseg2_mask, 0xF, 0x4 }, // 527 { Intrinsic::riscv_vssseg3, 0xF, 0x3 }, // 528 { Intrinsic::riscv_vssseg3_mask, 0xF, 0x4 }, // 529 { Intrinsic::riscv_vssseg4, 0xF, 0x3 }, // 530 { Intrinsic::riscv_vssseg4_mask, 0xF, 0x4 }, // 531 { Intrinsic::riscv_vssseg5, 0xF, 0x3 }, // 532 { Intrinsic::riscv_vssseg5_mask, 0xF, 0x4 }, // 533 { Intrinsic::riscv_vssseg6, 0xF, 0x3 }, // 534 { Intrinsic::riscv_vssseg6_mask, 0xF, 0x4 }, // 535 { Intrinsic::riscv_vssseg7, 0xF, 0x3 }, // 536 { Intrinsic::riscv_vssseg7_mask, 0xF, 0x4 }, // 537 { Intrinsic::riscv_vssseg8, 0xF, 0x3 }, // 538 { Intrinsic::riscv_vssseg8_mask, 0xF, 0x4 }, // 539 { Intrinsic::riscv_vssub, 0x2, 0x3 }, // 540 { Intrinsic::riscv_vssub_mask, 0x2, 0x4 }, // 541 { Intrinsic::riscv_vssubu, 0x2, 0x3 }, // 542 { Intrinsic::riscv_vssubu_mask, 0x2, 0x4 }, // 543 { Intrinsic::riscv_vsub, 0x2, 0x3 }, // 544 { Intrinsic::riscv_vsub_mask, 0x2, 0x4 }, // 545 { Intrinsic::riscv_vsuxei, 0xF, 0x3 }, // 546 { Intrinsic::riscv_vsuxei_mask, 0xF, 0x4 }, // 547 { Intrinsic::riscv_vsuxseg2, 0xF, 0x3 }, // 548 { Intrinsic::riscv_vsuxseg2_mask, 0xF, 0x4 }, // 549 { Intrinsic::riscv_vsuxseg3, 0xF, 0x3 }, // 550 { Intrinsic::riscv_vsuxseg3_mask, 0xF, 0x4 }, // 551 { Intrinsic::riscv_vsuxseg4, 0xF, 0x3 }, // 552 { Intrinsic::riscv_vsuxseg4_mask, 0xF, 0x4 }, // 553 { Intrinsic::riscv_vsuxseg5, 0xF, 0x3 }, // 554 { Intrinsic::riscv_vsuxseg5_mask, 0xF, 0x4 }, // 555 { Intrinsic::riscv_vsuxseg6, 0xF, 0x3 }, // 556 { Intrinsic::riscv_vsuxseg6_mask, 0xF, 0x4 }, // 557 { Intrinsic::riscv_vsuxseg7, 0xF, 0x3 }, // 558 { Intrinsic::riscv_vsuxseg7_mask, 0xF, 0x4 }, // 559 { Intrinsic::riscv_vsuxseg8, 0xF, 0x3 }, // 560 { Intrinsic::riscv_vsuxseg8_mask, 0xF, 0x4 }, // 561 { Intrinsic::riscv_vwadd, 0x2, 0x3 }, // 562 { Intrinsic::riscv_vwadd_mask, 0x2, 0x4 }, // 563 { Intrinsic::riscv_vwadd_w, 0x2, 0x3 }, // 564 { Intrinsic::riscv_vwadd_w_mask, 0x2, 0x4 }, // 565 { Intrinsic::riscv_vwaddu, 0x2, 0x3 }, // 566 { Intrinsic::riscv_vwaddu_mask, 0x2, 0x4 }, // 567 { Intrinsic::riscv_vwaddu_w, 0x2, 0x3 }, // 568 { Intrinsic::riscv_vwaddu_w_mask, 0x2, 0x4 }, // 569 { Intrinsic::riscv_vwmacc, 0x1, 0x3 }, // 570 { Intrinsic::riscv_vwmacc_mask, 0x1, 0x4 }, // 571 { Intrinsic::riscv_vwmaccsu, 0x1, 0x3 }, // 572 { Intrinsic::riscv_vwmaccsu_mask, 0x1, 0x4 }, // 573 { Intrinsic::riscv_vwmaccu, 0x1, 0x3 }, // 574 { Intrinsic::riscv_vwmaccu_mask, 0x1, 0x4 }, // 575 { Intrinsic::riscv_vwmaccus, 0x1, 0x3 }, // 576 { Intrinsic::riscv_vwmaccus_mask, 0x1, 0x4 }, // 577 { Intrinsic::riscv_vwmul, 0x2, 0x3 }, // 578 { Intrinsic::riscv_vwmul_mask, 0x2, 0x4 }, // 579 { Intrinsic::riscv_vwmulsu, 0x2, 0x3 }, // 580 { Intrinsic::riscv_vwmulsu_mask, 0x2, 0x4 }, // 581 { Intrinsic::riscv_vwmulu, 0x2, 0x3 }, // 582 { Intrinsic::riscv_vwmulu_mask, 0x2, 0x4 }, // 583 { Intrinsic::riscv_vwredsum, 0xF, 0x3 }, // 584 { Intrinsic::riscv_vwredsum_mask, 0xF, 0x4 }, // 585 { Intrinsic::riscv_vwredsumu, 0xF, 0x3 }, // 586 { Intrinsic::riscv_vwredsumu_mask, 0xF, 0x4 }, // 587 { Intrinsic::riscv_vwsll, 0x2, 0x3 }, // 588 { Intrinsic::riscv_vwsll_mask, 0x2, 0x4 }, // 589 { Intrinsic::riscv_vwsub, 0x2, 0x3 }, // 590 { Intrinsic::riscv_vwsub_mask, 0x2, 0x4 }, // 591 { Intrinsic::riscv_vwsub_w, 0x2, 0x3 }, // 592 { Intrinsic::riscv_vwsub_w_mask, 0x2, 0x4 }, // 593 { Intrinsic::riscv_vwsubu, 0x2, 0x3 }, // 594 { Intrinsic::riscv_vwsubu_mask, 0x2, 0x4 }, // 595 { Intrinsic::riscv_vwsubu_w, 0x2, 0x3 }, // 596 { Intrinsic::riscv_vwsubu_w_mask, 0x2, 0x4 }, // 597 { Intrinsic::riscv_vxor, 0x2, 0x3 }, // 598 { Intrinsic::riscv_vxor_mask, 0x2, 0x4 }, // 599 { Intrinsic::riscv_vzext, 0xF, 0x2 }, // 600 { Intrinsic::riscv_vzext_mask, 0xF, 0x3 }, // 601 }; const RISCVVIntrinsicInfo *getRISCVVIntrinsicInfo(unsigned IntrinsicID) { struct KeyType { unsigned IntrinsicID; }; KeyType Key = {IntrinsicID}; struct Comp { bool operator()(const RISCVVIntrinsicInfo &LHS, const KeyType &RHS) const { if (LHS.IntrinsicID < RHS.IntrinsicID) return true; if (LHS.IntrinsicID > RHS.IntrinsicID) return false; return false; } }; auto Table = ArrayRef(RISCVVIntrinsicsTable); auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); if (Idx == Table.end() || Key.IntrinsicID != Idx->IntrinsicID) return nullptr; return &*Idx; } #endif #ifdef GET_RISCVVInversePseudosTable_DECL const PseudoInfo *getBaseInfo(unsigned BaseInstr, uint8_t VLMul, uint8_t SEW); #endif #ifdef GET_RISCVVInversePseudosTable_IMPL constexpr PseudoInfo RISCVVInversePseudosTable[] = { { PseudoTHVdotVMAQASU_VV_M1, THVdotVMAQASU_VV, 0x0, 0x0 }, // 0 { PseudoTHVdotVMAQASU_VV_M1_MASK, THVdotVMAQASU_VV, 0x0, 0x0 }, // 1 { PseudoTHVdotVMAQASU_VV_M2, THVdotVMAQASU_VV, 0x1, 0x0 }, // 2 { PseudoTHVdotVMAQASU_VV_M2_MASK, THVdotVMAQASU_VV, 0x1, 0x0 }, // 3 { PseudoTHVdotVMAQASU_VV_M4, THVdotVMAQASU_VV, 0x2, 0x0 }, // 4 { PseudoTHVdotVMAQASU_VV_M4_MASK, THVdotVMAQASU_VV, 0x2, 0x0 }, // 5 { PseudoTHVdotVMAQASU_VV_M8, THVdotVMAQASU_VV, 0x3, 0x0 }, // 6 { PseudoTHVdotVMAQASU_VV_M8_MASK, THVdotVMAQASU_VV, 0x3, 0x0 }, // 7 { PseudoTHVdotVMAQASU_VV_MF2, THVdotVMAQASU_VV, 0x7, 0x0 }, // 8 { PseudoTHVdotVMAQASU_VV_MF2_MASK, THVdotVMAQASU_VV, 0x7, 0x0 }, // 9 { PseudoTHVdotVMAQASU_VX_M1, THVdotVMAQASU_VX, 0x0, 0x0 }, // 10 { PseudoTHVdotVMAQASU_VX_M1_MASK, THVdotVMAQASU_VX, 0x0, 0x0 }, // 11 { PseudoTHVdotVMAQASU_VX_M2, THVdotVMAQASU_VX, 0x1, 0x0 }, // 12 { PseudoTHVdotVMAQASU_VX_M2_MASK, THVdotVMAQASU_VX, 0x1, 0x0 }, // 13 { PseudoTHVdotVMAQASU_VX_M4, THVdotVMAQASU_VX, 0x2, 0x0 }, // 14 { PseudoTHVdotVMAQASU_VX_M4_MASK, THVdotVMAQASU_VX, 0x2, 0x0 }, // 15 { PseudoTHVdotVMAQASU_VX_M8, THVdotVMAQASU_VX, 0x3, 0x0 }, // 16 { PseudoTHVdotVMAQASU_VX_M8_MASK, THVdotVMAQASU_VX, 0x3, 0x0 }, // 17 { PseudoTHVdotVMAQASU_VX_MF2, THVdotVMAQASU_VX, 0x7, 0x0 }, // 18 { PseudoTHVdotVMAQASU_VX_MF2_MASK, THVdotVMAQASU_VX, 0x7, 0x0 }, // 19 { PseudoTHVdotVMAQAUS_VX_M1, THVdotVMAQAUS_VX, 0x0, 0x0 }, // 20 { PseudoTHVdotVMAQAUS_VX_M1_MASK, THVdotVMAQAUS_VX, 0x0, 0x0 }, // 21 { PseudoTHVdotVMAQAUS_VX_M2, THVdotVMAQAUS_VX, 0x1, 0x0 }, // 22 { PseudoTHVdotVMAQAUS_VX_M2_MASK, THVdotVMAQAUS_VX, 0x1, 0x0 }, // 23 { PseudoTHVdotVMAQAUS_VX_M4, THVdotVMAQAUS_VX, 0x2, 0x0 }, // 24 { PseudoTHVdotVMAQAUS_VX_M4_MASK, THVdotVMAQAUS_VX, 0x2, 0x0 }, // 25 { PseudoTHVdotVMAQAUS_VX_M8, THVdotVMAQAUS_VX, 0x3, 0x0 }, // 26 { PseudoTHVdotVMAQAUS_VX_M8_MASK, THVdotVMAQAUS_VX, 0x3, 0x0 }, // 27 { PseudoTHVdotVMAQAUS_VX_MF2, THVdotVMAQAUS_VX, 0x7, 0x0 }, // 28 { PseudoTHVdotVMAQAUS_VX_MF2_MASK, THVdotVMAQAUS_VX, 0x7, 0x0 }, // 29 { PseudoTHVdotVMAQAU_VV_M1, THVdotVMAQAU_VV, 0x0, 0x0 }, // 30 { PseudoTHVdotVMAQAU_VV_M1_MASK, THVdotVMAQAU_VV, 0x0, 0x0 }, // 31 { PseudoTHVdotVMAQAU_VV_M2, THVdotVMAQAU_VV, 0x1, 0x0 }, // 32 { PseudoTHVdotVMAQAU_VV_M2_MASK, THVdotVMAQAU_VV, 0x1, 0x0 }, // 33 { PseudoTHVdotVMAQAU_VV_M4, THVdotVMAQAU_VV, 0x2, 0x0 }, // 34 { PseudoTHVdotVMAQAU_VV_M4_MASK, THVdotVMAQAU_VV, 0x2, 0x0 }, // 35 { PseudoTHVdotVMAQAU_VV_M8, THVdotVMAQAU_VV, 0x3, 0x0 }, // 36 { PseudoTHVdotVMAQAU_VV_M8_MASK, THVdotVMAQAU_VV, 0x3, 0x0 }, // 37 { PseudoTHVdotVMAQAU_VV_MF2, THVdotVMAQAU_VV, 0x7, 0x0 }, // 38 { PseudoTHVdotVMAQAU_VV_MF2_MASK, THVdotVMAQAU_VV, 0x7, 0x0 }, // 39 { PseudoTHVdotVMAQAU_VX_M1, THVdotVMAQAU_VX, 0x0, 0x0 }, // 40 { PseudoTHVdotVMAQAU_VX_M1_MASK, THVdotVMAQAU_VX, 0x0, 0x0 }, // 41 { PseudoTHVdotVMAQAU_VX_M2, THVdotVMAQAU_VX, 0x1, 0x0 }, // 42 { PseudoTHVdotVMAQAU_VX_M2_MASK, THVdotVMAQAU_VX, 0x1, 0x0 }, // 43 { PseudoTHVdotVMAQAU_VX_M4, THVdotVMAQAU_VX, 0x2, 0x0 }, // 44 { PseudoTHVdotVMAQAU_VX_M4_MASK, THVdotVMAQAU_VX, 0x2, 0x0 }, // 45 { PseudoTHVdotVMAQAU_VX_M8, THVdotVMAQAU_VX, 0x3, 0x0 }, // 46 { PseudoTHVdotVMAQAU_VX_M8_MASK, THVdotVMAQAU_VX, 0x3, 0x0 }, // 47 { PseudoTHVdotVMAQAU_VX_MF2, THVdotVMAQAU_VX, 0x7, 0x0 }, // 48 { PseudoTHVdotVMAQAU_VX_MF2_MASK, THVdotVMAQAU_VX, 0x7, 0x0 }, // 49 { PseudoTHVdotVMAQA_VV_M1, THVdotVMAQA_VV, 0x0, 0x0 }, // 50 { PseudoTHVdotVMAQA_VV_M1_MASK, THVdotVMAQA_VV, 0x0, 0x0 }, // 51 { PseudoTHVdotVMAQA_VV_M2, THVdotVMAQA_VV, 0x1, 0x0 }, // 52 { PseudoTHVdotVMAQA_VV_M2_MASK, THVdotVMAQA_VV, 0x1, 0x0 }, // 53 { PseudoTHVdotVMAQA_VV_M4, THVdotVMAQA_VV, 0x2, 0x0 }, // 54 { PseudoTHVdotVMAQA_VV_M4_MASK, THVdotVMAQA_VV, 0x2, 0x0 }, // 55 { PseudoTHVdotVMAQA_VV_M8, THVdotVMAQA_VV, 0x3, 0x0 }, // 56 { PseudoTHVdotVMAQA_VV_M8_MASK, THVdotVMAQA_VV, 0x3, 0x0 }, // 57 { PseudoTHVdotVMAQA_VV_MF2, THVdotVMAQA_VV, 0x7, 0x0 }, // 58 { PseudoTHVdotVMAQA_VV_MF2_MASK, THVdotVMAQA_VV, 0x7, 0x0 }, // 59 { PseudoTHVdotVMAQA_VX_M1, THVdotVMAQA_VX, 0x0, 0x0 }, // 60 { PseudoTHVdotVMAQA_VX_M1_MASK, THVdotVMAQA_VX, 0x0, 0x0 }, // 61 { PseudoTHVdotVMAQA_VX_M2, THVdotVMAQA_VX, 0x1, 0x0 }, // 62 { PseudoTHVdotVMAQA_VX_M2_MASK, THVdotVMAQA_VX, 0x1, 0x0 }, // 63 { PseudoTHVdotVMAQA_VX_M4, THVdotVMAQA_VX, 0x2, 0x0 }, // 64 { PseudoTHVdotVMAQA_VX_M4_MASK, THVdotVMAQA_VX, 0x2, 0x0 }, // 65 { PseudoTHVdotVMAQA_VX_M8, THVdotVMAQA_VX, 0x3, 0x0 }, // 66 { PseudoTHVdotVMAQA_VX_M8_MASK, THVdotVMAQA_VX, 0x3, 0x0 }, // 67 { PseudoTHVdotVMAQA_VX_MF2, THVdotVMAQA_VX, 0x7, 0x0 }, // 68 { PseudoTHVdotVMAQA_VX_MF2_MASK, THVdotVMAQA_VX, 0x7, 0x0 }, // 69 { PseudoVAADDU_VV_M1, VAADDU_VV, 0x0, 0x0 }, // 70 { PseudoVAADDU_VV_M1_MASK, VAADDU_VV, 0x0, 0x0 }, // 71 { PseudoVAADDU_VV_M2, VAADDU_VV, 0x1, 0x0 }, // 72 { PseudoVAADDU_VV_M2_MASK, VAADDU_VV, 0x1, 0x0 }, // 73 { PseudoVAADDU_VV_M4, VAADDU_VV, 0x2, 0x0 }, // 74 { PseudoVAADDU_VV_M4_MASK, VAADDU_VV, 0x2, 0x0 }, // 75 { PseudoVAADDU_VV_M8, VAADDU_VV, 0x3, 0x0 }, // 76 { PseudoVAADDU_VV_M8_MASK, VAADDU_VV, 0x3, 0x0 }, // 77 { PseudoVAADDU_VV_MF8, VAADDU_VV, 0x5, 0x0 }, // 78 { PseudoVAADDU_VV_MF8_MASK, VAADDU_VV, 0x5, 0x0 }, // 79 { PseudoVAADDU_VV_MF4, VAADDU_VV, 0x6, 0x0 }, // 80 { PseudoVAADDU_VV_MF4_MASK, VAADDU_VV, 0x6, 0x0 }, // 81 { PseudoVAADDU_VV_MF2, VAADDU_VV, 0x7, 0x0 }, // 82 { PseudoVAADDU_VV_MF2_MASK, VAADDU_VV, 0x7, 0x0 }, // 83 { PseudoVAADDU_VX_M1, VAADDU_VX, 0x0, 0x0 }, // 84 { PseudoVAADDU_VX_M1_MASK, VAADDU_VX, 0x0, 0x0 }, // 85 { PseudoVAADDU_VX_M2, VAADDU_VX, 0x1, 0x0 }, // 86 { PseudoVAADDU_VX_M2_MASK, VAADDU_VX, 0x1, 0x0 }, // 87 { PseudoVAADDU_VX_M4, VAADDU_VX, 0x2, 0x0 }, // 88 { PseudoVAADDU_VX_M4_MASK, VAADDU_VX, 0x2, 0x0 }, // 89 { PseudoVAADDU_VX_M8, VAADDU_VX, 0x3, 0x0 }, // 90 { PseudoVAADDU_VX_M8_MASK, VAADDU_VX, 0x3, 0x0 }, // 91 { PseudoVAADDU_VX_MF8, VAADDU_VX, 0x5, 0x0 }, // 92 { PseudoVAADDU_VX_MF8_MASK, VAADDU_VX, 0x5, 0x0 }, // 93 { PseudoVAADDU_VX_MF4, VAADDU_VX, 0x6, 0x0 }, // 94 { PseudoVAADDU_VX_MF4_MASK, VAADDU_VX, 0x6, 0x0 }, // 95 { PseudoVAADDU_VX_MF2, VAADDU_VX, 0x7, 0x0 }, // 96 { PseudoVAADDU_VX_MF2_MASK, VAADDU_VX, 0x7, 0x0 }, // 97 { PseudoVAADD_VV_M1, VAADD_VV, 0x0, 0x0 }, // 98 { PseudoVAADD_VV_M1_MASK, VAADD_VV, 0x0, 0x0 }, // 99 { PseudoVAADD_VV_M2, VAADD_VV, 0x1, 0x0 }, // 100 { PseudoVAADD_VV_M2_MASK, VAADD_VV, 0x1, 0x0 }, // 101 { PseudoVAADD_VV_M4, VAADD_VV, 0x2, 0x0 }, // 102 { PseudoVAADD_VV_M4_MASK, VAADD_VV, 0x2, 0x0 }, // 103 { PseudoVAADD_VV_M8, VAADD_VV, 0x3, 0x0 }, // 104 { PseudoVAADD_VV_M8_MASK, VAADD_VV, 0x3, 0x0 }, // 105 { PseudoVAADD_VV_MF8, VAADD_VV, 0x5, 0x0 }, // 106 { PseudoVAADD_VV_MF8_MASK, VAADD_VV, 0x5, 0x0 }, // 107 { PseudoVAADD_VV_MF4, VAADD_VV, 0x6, 0x0 }, // 108 { PseudoVAADD_VV_MF4_MASK, VAADD_VV, 0x6, 0x0 }, // 109 { PseudoVAADD_VV_MF2, VAADD_VV, 0x7, 0x0 }, // 110 { PseudoVAADD_VV_MF2_MASK, VAADD_VV, 0x7, 0x0 }, // 111 { PseudoVAADD_VX_M1, VAADD_VX, 0x0, 0x0 }, // 112 { PseudoVAADD_VX_M1_MASK, VAADD_VX, 0x0, 0x0 }, // 113 { PseudoVAADD_VX_M2, VAADD_VX, 0x1, 0x0 }, // 114 { PseudoVAADD_VX_M2_MASK, VAADD_VX, 0x1, 0x0 }, // 115 { PseudoVAADD_VX_M4, VAADD_VX, 0x2, 0x0 }, // 116 { PseudoVAADD_VX_M4_MASK, VAADD_VX, 0x2, 0x0 }, // 117 { PseudoVAADD_VX_M8, VAADD_VX, 0x3, 0x0 }, // 118 { PseudoVAADD_VX_M8_MASK, VAADD_VX, 0x3, 0x0 }, // 119 { PseudoVAADD_VX_MF8, VAADD_VX, 0x5, 0x0 }, // 120 { PseudoVAADD_VX_MF8_MASK, VAADD_VX, 0x5, 0x0 }, // 121 { PseudoVAADD_VX_MF4, VAADD_VX, 0x6, 0x0 }, // 122 { PseudoVAADD_VX_MF4_MASK, VAADD_VX, 0x6, 0x0 }, // 123 { PseudoVAADD_VX_MF2, VAADD_VX, 0x7, 0x0 }, // 124 { PseudoVAADD_VX_MF2_MASK, VAADD_VX, 0x7, 0x0 }, // 125 { PseudoVADC_VIM_M1, VADC_VIM, 0x0, 0x0 }, // 126 { PseudoVADC_VIM_M2, VADC_VIM, 0x1, 0x0 }, // 127 { PseudoVADC_VIM_M4, VADC_VIM, 0x2, 0x0 }, // 128 { PseudoVADC_VIM_M8, VADC_VIM, 0x3, 0x0 }, // 129 { PseudoVADC_VIM_MF8, VADC_VIM, 0x5, 0x0 }, // 130 { PseudoVADC_VIM_MF4, VADC_VIM, 0x6, 0x0 }, // 131 { PseudoVADC_VIM_MF2, VADC_VIM, 0x7, 0x0 }, // 132 { PseudoVADC_VVM_M1, VADC_VVM, 0x0, 0x0 }, // 133 { PseudoVADC_VVM_M2, VADC_VVM, 0x1, 0x0 }, // 134 { PseudoVADC_VVM_M4, VADC_VVM, 0x2, 0x0 }, // 135 { PseudoVADC_VVM_M8, VADC_VVM, 0x3, 0x0 }, // 136 { PseudoVADC_VVM_MF8, VADC_VVM, 0x5, 0x0 }, // 137 { PseudoVADC_VVM_MF4, VADC_VVM, 0x6, 0x0 }, // 138 { PseudoVADC_VVM_MF2, VADC_VVM, 0x7, 0x0 }, // 139 { PseudoVADC_VXM_M1, VADC_VXM, 0x0, 0x0 }, // 140 { PseudoVADC_VXM_M2, VADC_VXM, 0x1, 0x0 }, // 141 { PseudoVADC_VXM_M4, VADC_VXM, 0x2, 0x0 }, // 142 { PseudoVADC_VXM_M8, VADC_VXM, 0x3, 0x0 }, // 143 { PseudoVADC_VXM_MF8, VADC_VXM, 0x5, 0x0 }, // 144 { PseudoVADC_VXM_MF4, VADC_VXM, 0x6, 0x0 }, // 145 { PseudoVADC_VXM_MF2, VADC_VXM, 0x7, 0x0 }, // 146 { PseudoVADD_VI_M1, VADD_VI, 0x0, 0x0 }, // 147 { PseudoVADD_VI_M1_MASK, VADD_VI, 0x0, 0x0 }, // 148 { PseudoVADD_VI_M2, VADD_VI, 0x1, 0x0 }, // 149 { PseudoVADD_VI_M2_MASK, VADD_VI, 0x1, 0x0 }, // 150 { PseudoVADD_VI_M4, VADD_VI, 0x2, 0x0 }, // 151 { PseudoVADD_VI_M4_MASK, VADD_VI, 0x2, 0x0 }, // 152 { PseudoVADD_VI_M8, VADD_VI, 0x3, 0x0 }, // 153 { PseudoVADD_VI_M8_MASK, VADD_VI, 0x3, 0x0 }, // 154 { PseudoVADD_VI_MF8, VADD_VI, 0x5, 0x0 }, // 155 { PseudoVADD_VI_MF8_MASK, VADD_VI, 0x5, 0x0 }, // 156 { PseudoVADD_VI_MF4, VADD_VI, 0x6, 0x0 }, // 157 { PseudoVADD_VI_MF4_MASK, VADD_VI, 0x6, 0x0 }, // 158 { PseudoVADD_VI_MF2, VADD_VI, 0x7, 0x0 }, // 159 { PseudoVADD_VI_MF2_MASK, VADD_VI, 0x7, 0x0 }, // 160 { PseudoVADD_VV_M1, VADD_VV, 0x0, 0x0 }, // 161 { PseudoVADD_VV_M1_MASK, VADD_VV, 0x0, 0x0 }, // 162 { PseudoVADD_VV_M2, VADD_VV, 0x1, 0x0 }, // 163 { PseudoVADD_VV_M2_MASK, VADD_VV, 0x1, 0x0 }, // 164 { PseudoVADD_VV_M4, VADD_VV, 0x2, 0x0 }, // 165 { PseudoVADD_VV_M4_MASK, VADD_VV, 0x2, 0x0 }, // 166 { PseudoVADD_VV_M8, VADD_VV, 0x3, 0x0 }, // 167 { PseudoVADD_VV_M8_MASK, VADD_VV, 0x3, 0x0 }, // 168 { PseudoVADD_VV_MF8, VADD_VV, 0x5, 0x0 }, // 169 { PseudoVADD_VV_MF8_MASK, VADD_VV, 0x5, 0x0 }, // 170 { PseudoVADD_VV_MF4, VADD_VV, 0x6, 0x0 }, // 171 { PseudoVADD_VV_MF4_MASK, VADD_VV, 0x6, 0x0 }, // 172 { PseudoVADD_VV_MF2, VADD_VV, 0x7, 0x0 }, // 173 { PseudoVADD_VV_MF2_MASK, VADD_VV, 0x7, 0x0 }, // 174 { PseudoVADD_VX_M1, VADD_VX, 0x0, 0x0 }, // 175 { PseudoVADD_VX_M1_MASK, VADD_VX, 0x0, 0x0 }, // 176 { PseudoVADD_VX_M2, VADD_VX, 0x1, 0x0 }, // 177 { PseudoVADD_VX_M2_MASK, VADD_VX, 0x1, 0x0 }, // 178 { PseudoVADD_VX_M4, VADD_VX, 0x2, 0x0 }, // 179 { PseudoVADD_VX_M4_MASK, VADD_VX, 0x2, 0x0 }, // 180 { PseudoVADD_VX_M8, VADD_VX, 0x3, 0x0 }, // 181 { PseudoVADD_VX_M8_MASK, VADD_VX, 0x3, 0x0 }, // 182 { PseudoVADD_VX_MF8, VADD_VX, 0x5, 0x0 }, // 183 { PseudoVADD_VX_MF8_MASK, VADD_VX, 0x5, 0x0 }, // 184 { PseudoVADD_VX_MF4, VADD_VX, 0x6, 0x0 }, // 185 { PseudoVADD_VX_MF4_MASK, VADD_VX, 0x6, 0x0 }, // 186 { PseudoVADD_VX_MF2, VADD_VX, 0x7, 0x0 }, // 187 { PseudoVADD_VX_MF2_MASK, VADD_VX, 0x7, 0x0 }, // 188 { PseudoVAESDF_VS_M1_M1, VAESDF_VS, 0x0, 0x0 }, // 189 { PseudoVAESDF_VS_M1_MF2, VAESDF_VS, 0x0, 0x0 }, // 190 { PseudoVAESDF_VS_M1_MF4, VAESDF_VS, 0x0, 0x0 }, // 191 { PseudoVAESDF_VS_M1_MF8, VAESDF_VS, 0x0, 0x0 }, // 192 { PseudoVAESDF_VS_M2_M1, VAESDF_VS, 0x1, 0x0 }, // 193 { PseudoVAESDF_VS_M2_M2, VAESDF_VS, 0x1, 0x0 }, // 194 { PseudoVAESDF_VS_M2_MF2, VAESDF_VS, 0x1, 0x0 }, // 195 { PseudoVAESDF_VS_M2_MF4, VAESDF_VS, 0x1, 0x0 }, // 196 { PseudoVAESDF_VS_M2_MF8, VAESDF_VS, 0x1, 0x0 }, // 197 { PseudoVAESDF_VS_M4_M1, VAESDF_VS, 0x2, 0x0 }, // 198 { PseudoVAESDF_VS_M4_M2, VAESDF_VS, 0x2, 0x0 }, // 199 { PseudoVAESDF_VS_M4_M4, VAESDF_VS, 0x2, 0x0 }, // 200 { PseudoVAESDF_VS_M4_MF2, VAESDF_VS, 0x2, 0x0 }, // 201 { PseudoVAESDF_VS_M4_MF4, VAESDF_VS, 0x2, 0x0 }, // 202 { PseudoVAESDF_VS_M4_MF8, VAESDF_VS, 0x2, 0x0 }, // 203 { PseudoVAESDF_VS_M8_M1, VAESDF_VS, 0x3, 0x0 }, // 204 { PseudoVAESDF_VS_M8_M2, VAESDF_VS, 0x3, 0x0 }, // 205 { PseudoVAESDF_VS_M8_M4, VAESDF_VS, 0x3, 0x0 }, // 206 { PseudoVAESDF_VS_M8_MF2, VAESDF_VS, 0x3, 0x0 }, // 207 { PseudoVAESDF_VS_M8_MF4, VAESDF_VS, 0x3, 0x0 }, // 208 { PseudoVAESDF_VS_M8_MF8, VAESDF_VS, 0x3, 0x0 }, // 209 { PseudoVAESDF_VS_MF2_MF2, VAESDF_VS, 0x7, 0x0 }, // 210 { PseudoVAESDF_VS_MF2_MF4, VAESDF_VS, 0x7, 0x0 }, // 211 { PseudoVAESDF_VS_MF2_MF8, VAESDF_VS, 0x7, 0x0 }, // 212 { PseudoVAESDF_VV_M1, VAESDF_VV, 0x0, 0x0 }, // 213 { PseudoVAESDF_VV_M2, VAESDF_VV, 0x1, 0x0 }, // 214 { PseudoVAESDF_VV_M4, VAESDF_VV, 0x2, 0x0 }, // 215 { PseudoVAESDF_VV_M8, VAESDF_VV, 0x3, 0x0 }, // 216 { PseudoVAESDF_VV_MF2, VAESDF_VV, 0x7, 0x0 }, // 217 { PseudoVAESDM_VS_M1_M1, VAESDM_VS, 0x0, 0x0 }, // 218 { PseudoVAESDM_VS_M1_MF2, VAESDM_VS, 0x0, 0x0 }, // 219 { PseudoVAESDM_VS_M1_MF4, VAESDM_VS, 0x0, 0x0 }, // 220 { PseudoVAESDM_VS_M1_MF8, VAESDM_VS, 0x0, 0x0 }, // 221 { PseudoVAESDM_VS_M2_M1, VAESDM_VS, 0x1, 0x0 }, // 222 { PseudoVAESDM_VS_M2_M2, VAESDM_VS, 0x1, 0x0 }, // 223 { PseudoVAESDM_VS_M2_MF2, VAESDM_VS, 0x1, 0x0 }, // 224 { PseudoVAESDM_VS_M2_MF4, VAESDM_VS, 0x1, 0x0 }, // 225 { PseudoVAESDM_VS_M2_MF8, VAESDM_VS, 0x1, 0x0 }, // 226 { PseudoVAESDM_VS_M4_M1, VAESDM_VS, 0x2, 0x0 }, // 227 { PseudoVAESDM_VS_M4_M2, VAESDM_VS, 0x2, 0x0 }, // 228 { PseudoVAESDM_VS_M4_M4, VAESDM_VS, 0x2, 0x0 }, // 229 { PseudoVAESDM_VS_M4_MF2, VAESDM_VS, 0x2, 0x0 }, // 230 { PseudoVAESDM_VS_M4_MF4, VAESDM_VS, 0x2, 0x0 }, // 231 { PseudoVAESDM_VS_M4_MF8, VAESDM_VS, 0x2, 0x0 }, // 232 { PseudoVAESDM_VS_M8_M1, VAESDM_VS, 0x3, 0x0 }, // 233 { PseudoVAESDM_VS_M8_M2, VAESDM_VS, 0x3, 0x0 }, // 234 { PseudoVAESDM_VS_M8_M4, VAESDM_VS, 0x3, 0x0 }, // 235 { PseudoVAESDM_VS_M8_MF2, VAESDM_VS, 0x3, 0x0 }, // 236 { PseudoVAESDM_VS_M8_MF4, VAESDM_VS, 0x3, 0x0 }, // 237 { PseudoVAESDM_VS_M8_MF8, VAESDM_VS, 0x3, 0x0 }, // 238 { PseudoVAESDM_VS_MF2_MF2, VAESDM_VS, 0x7, 0x0 }, // 239 { PseudoVAESDM_VS_MF2_MF4, VAESDM_VS, 0x7, 0x0 }, // 240 { PseudoVAESDM_VS_MF2_MF8, VAESDM_VS, 0x7, 0x0 }, // 241 { PseudoVAESDM_VV_M1, VAESDM_VV, 0x0, 0x0 }, // 242 { PseudoVAESDM_VV_M2, VAESDM_VV, 0x1, 0x0 }, // 243 { PseudoVAESDM_VV_M4, VAESDM_VV, 0x2, 0x0 }, // 244 { PseudoVAESDM_VV_M8, VAESDM_VV, 0x3, 0x0 }, // 245 { PseudoVAESDM_VV_MF2, VAESDM_VV, 0x7, 0x0 }, // 246 { PseudoVAESEF_VS_M1_M1, VAESEF_VS, 0x0, 0x0 }, // 247 { PseudoVAESEF_VS_M1_MF2, VAESEF_VS, 0x0, 0x0 }, // 248 { PseudoVAESEF_VS_M1_MF4, VAESEF_VS, 0x0, 0x0 }, // 249 { PseudoVAESEF_VS_M1_MF8, VAESEF_VS, 0x0, 0x0 }, // 250 { PseudoVAESEF_VS_M2_M1, VAESEF_VS, 0x1, 0x0 }, // 251 { PseudoVAESEF_VS_M2_M2, VAESEF_VS, 0x1, 0x0 }, // 252 { PseudoVAESEF_VS_M2_MF2, VAESEF_VS, 0x1, 0x0 }, // 253 { PseudoVAESEF_VS_M2_MF4, VAESEF_VS, 0x1, 0x0 }, // 254 { PseudoVAESEF_VS_M2_MF8, VAESEF_VS, 0x1, 0x0 }, // 255 { PseudoVAESEF_VS_M4_M1, VAESEF_VS, 0x2, 0x0 }, // 256 { PseudoVAESEF_VS_M4_M2, VAESEF_VS, 0x2, 0x0 }, // 257 { PseudoVAESEF_VS_M4_M4, VAESEF_VS, 0x2, 0x0 }, // 258 { PseudoVAESEF_VS_M4_MF2, VAESEF_VS, 0x2, 0x0 }, // 259 { PseudoVAESEF_VS_M4_MF4, VAESEF_VS, 0x2, 0x0 }, // 260 { PseudoVAESEF_VS_M4_MF8, VAESEF_VS, 0x2, 0x0 }, // 261 { PseudoVAESEF_VS_M8_M1, VAESEF_VS, 0x3, 0x0 }, // 262 { PseudoVAESEF_VS_M8_M2, VAESEF_VS, 0x3, 0x0 }, // 263 { PseudoVAESEF_VS_M8_M4, VAESEF_VS, 0x3, 0x0 }, // 264 { PseudoVAESEF_VS_M8_MF2, VAESEF_VS, 0x3, 0x0 }, // 265 { PseudoVAESEF_VS_M8_MF4, VAESEF_VS, 0x3, 0x0 }, // 266 { PseudoVAESEF_VS_M8_MF8, VAESEF_VS, 0x3, 0x0 }, // 267 { PseudoVAESEF_VS_MF2_MF2, VAESEF_VS, 0x7, 0x0 }, // 268 { PseudoVAESEF_VS_MF2_MF4, VAESEF_VS, 0x7, 0x0 }, // 269 { PseudoVAESEF_VS_MF2_MF8, VAESEF_VS, 0x7, 0x0 }, // 270 { PseudoVAESEF_VV_M1, VAESEF_VV, 0x0, 0x0 }, // 271 { PseudoVAESEF_VV_M2, VAESEF_VV, 0x1, 0x0 }, // 272 { PseudoVAESEF_VV_M4, VAESEF_VV, 0x2, 0x0 }, // 273 { PseudoVAESEF_VV_M8, VAESEF_VV, 0x3, 0x0 }, // 274 { PseudoVAESEF_VV_MF2, VAESEF_VV, 0x7, 0x0 }, // 275 { PseudoVAESEM_VS_M1_M1, VAESEM_VS, 0x0, 0x0 }, // 276 { PseudoVAESEM_VS_M1_MF2, VAESEM_VS, 0x0, 0x0 }, // 277 { PseudoVAESEM_VS_M1_MF4, VAESEM_VS, 0x0, 0x0 }, // 278 { PseudoVAESEM_VS_M1_MF8, VAESEM_VS, 0x0, 0x0 }, // 279 { PseudoVAESEM_VS_M2_M1, VAESEM_VS, 0x1, 0x0 }, // 280 { PseudoVAESEM_VS_M2_M2, VAESEM_VS, 0x1, 0x0 }, // 281 { PseudoVAESEM_VS_M2_MF2, VAESEM_VS, 0x1, 0x0 }, // 282 { PseudoVAESEM_VS_M2_MF4, VAESEM_VS, 0x1, 0x0 }, // 283 { PseudoVAESEM_VS_M2_MF8, VAESEM_VS, 0x1, 0x0 }, // 284 { PseudoVAESEM_VS_M4_M1, VAESEM_VS, 0x2, 0x0 }, // 285 { PseudoVAESEM_VS_M4_M2, VAESEM_VS, 0x2, 0x0 }, // 286 { PseudoVAESEM_VS_M4_M4, VAESEM_VS, 0x2, 0x0 }, // 287 { PseudoVAESEM_VS_M4_MF2, VAESEM_VS, 0x2, 0x0 }, // 288 { PseudoVAESEM_VS_M4_MF4, VAESEM_VS, 0x2, 0x0 }, // 289 { PseudoVAESEM_VS_M4_MF8, VAESEM_VS, 0x2, 0x0 }, // 290 { PseudoVAESEM_VS_M8_M1, VAESEM_VS, 0x3, 0x0 }, // 291 { PseudoVAESEM_VS_M8_M2, VAESEM_VS, 0x3, 0x0 }, // 292 { PseudoVAESEM_VS_M8_M4, VAESEM_VS, 0x3, 0x0 }, // 293 { PseudoVAESEM_VS_M8_MF2, VAESEM_VS, 0x3, 0x0 }, // 294 { PseudoVAESEM_VS_M8_MF4, VAESEM_VS, 0x3, 0x0 }, // 295 { PseudoVAESEM_VS_M8_MF8, VAESEM_VS, 0x3, 0x0 }, // 296 { PseudoVAESEM_VS_MF2_MF2, VAESEM_VS, 0x7, 0x0 }, // 297 { PseudoVAESEM_VS_MF2_MF4, VAESEM_VS, 0x7, 0x0 }, // 298 { PseudoVAESEM_VS_MF2_MF8, VAESEM_VS, 0x7, 0x0 }, // 299 { PseudoVAESEM_VV_M1, VAESEM_VV, 0x0, 0x0 }, // 300 { PseudoVAESEM_VV_M2, VAESEM_VV, 0x1, 0x0 }, // 301 { PseudoVAESEM_VV_M4, VAESEM_VV, 0x2, 0x0 }, // 302 { PseudoVAESEM_VV_M8, VAESEM_VV, 0x3, 0x0 }, // 303 { PseudoVAESEM_VV_MF2, VAESEM_VV, 0x7, 0x0 }, // 304 { PseudoVAESKF1_VI_M1, VAESKF1_VI, 0x0, 0x0 }, // 305 { PseudoVAESKF1_VI_M2, VAESKF1_VI, 0x1, 0x0 }, // 306 { PseudoVAESKF1_VI_M4, VAESKF1_VI, 0x2, 0x0 }, // 307 { PseudoVAESKF1_VI_M8, VAESKF1_VI, 0x3, 0x0 }, // 308 { PseudoVAESKF1_VI_MF2, VAESKF1_VI, 0x7, 0x0 }, // 309 { PseudoVAESKF2_VI_M1, VAESKF2_VI, 0x0, 0x0 }, // 310 { PseudoVAESKF2_VI_M2, VAESKF2_VI, 0x1, 0x0 }, // 311 { PseudoVAESKF2_VI_M4, VAESKF2_VI, 0x2, 0x0 }, // 312 { PseudoVAESKF2_VI_M8, VAESKF2_VI, 0x3, 0x0 }, // 313 { PseudoVAESKF2_VI_MF2, VAESKF2_VI, 0x7, 0x0 }, // 314 { PseudoVAESZ_VS_M1_M1, VAESZ_VS, 0x0, 0x0 }, // 315 { PseudoVAESZ_VS_M1_MF2, VAESZ_VS, 0x0, 0x0 }, // 316 { PseudoVAESZ_VS_M1_MF4, VAESZ_VS, 0x0, 0x0 }, // 317 { PseudoVAESZ_VS_M1_MF8, VAESZ_VS, 0x0, 0x0 }, // 318 { PseudoVAESZ_VS_M2_M1, VAESZ_VS, 0x1, 0x0 }, // 319 { PseudoVAESZ_VS_M2_M2, VAESZ_VS, 0x1, 0x0 }, // 320 { PseudoVAESZ_VS_M2_MF2, VAESZ_VS, 0x1, 0x0 }, // 321 { PseudoVAESZ_VS_M2_MF4, VAESZ_VS, 0x1, 0x0 }, // 322 { PseudoVAESZ_VS_M2_MF8, VAESZ_VS, 0x1, 0x0 }, // 323 { PseudoVAESZ_VS_M4_M1, VAESZ_VS, 0x2, 0x0 }, // 324 { PseudoVAESZ_VS_M4_M2, VAESZ_VS, 0x2, 0x0 }, // 325 { PseudoVAESZ_VS_M4_M4, VAESZ_VS, 0x2, 0x0 }, // 326 { PseudoVAESZ_VS_M4_MF2, VAESZ_VS, 0x2, 0x0 }, // 327 { PseudoVAESZ_VS_M4_MF4, VAESZ_VS, 0x2, 0x0 }, // 328 { PseudoVAESZ_VS_M4_MF8, VAESZ_VS, 0x2, 0x0 }, // 329 { PseudoVAESZ_VS_M8_M1, VAESZ_VS, 0x3, 0x0 }, // 330 { PseudoVAESZ_VS_M8_M2, VAESZ_VS, 0x3, 0x0 }, // 331 { PseudoVAESZ_VS_M8_M4, VAESZ_VS, 0x3, 0x0 }, // 332 { PseudoVAESZ_VS_M8_MF2, VAESZ_VS, 0x3, 0x0 }, // 333 { PseudoVAESZ_VS_M8_MF4, VAESZ_VS, 0x3, 0x0 }, // 334 { PseudoVAESZ_VS_M8_MF8, VAESZ_VS, 0x3, 0x0 }, // 335 { PseudoVAESZ_VS_MF2_MF2, VAESZ_VS, 0x7, 0x0 }, // 336 { PseudoVAESZ_VS_MF2_MF4, VAESZ_VS, 0x7, 0x0 }, // 337 { PseudoVAESZ_VS_MF2_MF8, VAESZ_VS, 0x7, 0x0 }, // 338 { PseudoVANDN_VV_M1, VANDN_VV, 0x0, 0x0 }, // 339 { PseudoVANDN_VV_M1_MASK, VANDN_VV, 0x0, 0x0 }, // 340 { PseudoVANDN_VV_M2, VANDN_VV, 0x1, 0x0 }, // 341 { PseudoVANDN_VV_M2_MASK, VANDN_VV, 0x1, 0x0 }, // 342 { PseudoVANDN_VV_M4, VANDN_VV, 0x2, 0x0 }, // 343 { PseudoVANDN_VV_M4_MASK, VANDN_VV, 0x2, 0x0 }, // 344 { PseudoVANDN_VV_M8, VANDN_VV, 0x3, 0x0 }, // 345 { PseudoVANDN_VV_M8_MASK, VANDN_VV, 0x3, 0x0 }, // 346 { PseudoVANDN_VV_MF8, VANDN_VV, 0x5, 0x0 }, // 347 { PseudoVANDN_VV_MF8_MASK, VANDN_VV, 0x5, 0x0 }, // 348 { PseudoVANDN_VV_MF4, VANDN_VV, 0x6, 0x0 }, // 349 { PseudoVANDN_VV_MF4_MASK, VANDN_VV, 0x6, 0x0 }, // 350 { PseudoVANDN_VV_MF2, VANDN_VV, 0x7, 0x0 }, // 351 { PseudoVANDN_VV_MF2_MASK, VANDN_VV, 0x7, 0x0 }, // 352 { PseudoVANDN_VX_M1, VANDN_VX, 0x0, 0x0 }, // 353 { PseudoVANDN_VX_M1_MASK, VANDN_VX, 0x0, 0x0 }, // 354 { PseudoVANDN_VX_M2, VANDN_VX, 0x1, 0x0 }, // 355 { PseudoVANDN_VX_M2_MASK, VANDN_VX, 0x1, 0x0 }, // 356 { PseudoVANDN_VX_M4, VANDN_VX, 0x2, 0x0 }, // 357 { PseudoVANDN_VX_M4_MASK, VANDN_VX, 0x2, 0x0 }, // 358 { PseudoVANDN_VX_M8, VANDN_VX, 0x3, 0x0 }, // 359 { PseudoVANDN_VX_M8_MASK, VANDN_VX, 0x3, 0x0 }, // 360 { PseudoVANDN_VX_MF8, VANDN_VX, 0x5, 0x0 }, // 361 { PseudoVANDN_VX_MF8_MASK, VANDN_VX, 0x5, 0x0 }, // 362 { PseudoVANDN_VX_MF4, VANDN_VX, 0x6, 0x0 }, // 363 { PseudoVANDN_VX_MF4_MASK, VANDN_VX, 0x6, 0x0 }, // 364 { PseudoVANDN_VX_MF2, VANDN_VX, 0x7, 0x0 }, // 365 { PseudoVANDN_VX_MF2_MASK, VANDN_VX, 0x7, 0x0 }, // 366 { PseudoVAND_VI_M1, VAND_VI, 0x0, 0x0 }, // 367 { PseudoVAND_VI_M1_MASK, VAND_VI, 0x0, 0x0 }, // 368 { PseudoVAND_VI_M2, VAND_VI, 0x1, 0x0 }, // 369 { PseudoVAND_VI_M2_MASK, VAND_VI, 0x1, 0x0 }, // 370 { PseudoVAND_VI_M4, VAND_VI, 0x2, 0x0 }, // 371 { PseudoVAND_VI_M4_MASK, VAND_VI, 0x2, 0x0 }, // 372 { PseudoVAND_VI_M8, VAND_VI, 0x3, 0x0 }, // 373 { PseudoVAND_VI_M8_MASK, VAND_VI, 0x3, 0x0 }, // 374 { PseudoVAND_VI_MF8, VAND_VI, 0x5, 0x0 }, // 375 { PseudoVAND_VI_MF8_MASK, VAND_VI, 0x5, 0x0 }, // 376 { PseudoVAND_VI_MF4, VAND_VI, 0x6, 0x0 }, // 377 { PseudoVAND_VI_MF4_MASK, VAND_VI, 0x6, 0x0 }, // 378 { PseudoVAND_VI_MF2, VAND_VI, 0x7, 0x0 }, // 379 { PseudoVAND_VI_MF2_MASK, VAND_VI, 0x7, 0x0 }, // 380 { PseudoVAND_VV_M1, VAND_VV, 0x0, 0x0 }, // 381 { PseudoVAND_VV_M1_MASK, VAND_VV, 0x0, 0x0 }, // 382 { PseudoVAND_VV_M2, VAND_VV, 0x1, 0x0 }, // 383 { PseudoVAND_VV_M2_MASK, VAND_VV, 0x1, 0x0 }, // 384 { PseudoVAND_VV_M4, VAND_VV, 0x2, 0x0 }, // 385 { PseudoVAND_VV_M4_MASK, VAND_VV, 0x2, 0x0 }, // 386 { PseudoVAND_VV_M8, VAND_VV, 0x3, 0x0 }, // 387 { PseudoVAND_VV_M8_MASK, VAND_VV, 0x3, 0x0 }, // 388 { PseudoVAND_VV_MF8, VAND_VV, 0x5, 0x0 }, // 389 { PseudoVAND_VV_MF8_MASK, VAND_VV, 0x5, 0x0 }, // 390 { PseudoVAND_VV_MF4, VAND_VV, 0x6, 0x0 }, // 391 { PseudoVAND_VV_MF4_MASK, VAND_VV, 0x6, 0x0 }, // 392 { PseudoVAND_VV_MF2, VAND_VV, 0x7, 0x0 }, // 393 { PseudoVAND_VV_MF2_MASK, VAND_VV, 0x7, 0x0 }, // 394 { PseudoVAND_VX_M1, VAND_VX, 0x0, 0x0 }, // 395 { PseudoVAND_VX_M1_MASK, VAND_VX, 0x0, 0x0 }, // 396 { PseudoVAND_VX_M2, VAND_VX, 0x1, 0x0 }, // 397 { PseudoVAND_VX_M2_MASK, VAND_VX, 0x1, 0x0 }, // 398 { PseudoVAND_VX_M4, VAND_VX, 0x2, 0x0 }, // 399 { PseudoVAND_VX_M4_MASK, VAND_VX, 0x2, 0x0 }, // 400 { PseudoVAND_VX_M8, VAND_VX, 0x3, 0x0 }, // 401 { PseudoVAND_VX_M8_MASK, VAND_VX, 0x3, 0x0 }, // 402 { PseudoVAND_VX_MF8, VAND_VX, 0x5, 0x0 }, // 403 { PseudoVAND_VX_MF8_MASK, VAND_VX, 0x5, 0x0 }, // 404 { PseudoVAND_VX_MF4, VAND_VX, 0x6, 0x0 }, // 405 { PseudoVAND_VX_MF4_MASK, VAND_VX, 0x6, 0x0 }, // 406 { PseudoVAND_VX_MF2, VAND_VX, 0x7, 0x0 }, // 407 { PseudoVAND_VX_MF2_MASK, VAND_VX, 0x7, 0x0 }, // 408 { PseudoVASUBU_VV_M1, VASUBU_VV, 0x0, 0x0 }, // 409 { PseudoVASUBU_VV_M1_MASK, VASUBU_VV, 0x0, 0x0 }, // 410 { PseudoVASUBU_VV_M2, VASUBU_VV, 0x1, 0x0 }, // 411 { PseudoVASUBU_VV_M2_MASK, VASUBU_VV, 0x1, 0x0 }, // 412 { PseudoVASUBU_VV_M4, VASUBU_VV, 0x2, 0x0 }, // 413 { PseudoVASUBU_VV_M4_MASK, VASUBU_VV, 0x2, 0x0 }, // 414 { PseudoVASUBU_VV_M8, VASUBU_VV, 0x3, 0x0 }, // 415 { PseudoVASUBU_VV_M8_MASK, VASUBU_VV, 0x3, 0x0 }, // 416 { PseudoVASUBU_VV_MF8, VASUBU_VV, 0x5, 0x0 }, // 417 { PseudoVASUBU_VV_MF8_MASK, VASUBU_VV, 0x5, 0x0 }, // 418 { PseudoVASUBU_VV_MF4, VASUBU_VV, 0x6, 0x0 }, // 419 { PseudoVASUBU_VV_MF4_MASK, VASUBU_VV, 0x6, 0x0 }, // 420 { PseudoVASUBU_VV_MF2, VASUBU_VV, 0x7, 0x0 }, // 421 { PseudoVASUBU_VV_MF2_MASK, VASUBU_VV, 0x7, 0x0 }, // 422 { PseudoVASUBU_VX_M1, VASUBU_VX, 0x0, 0x0 }, // 423 { PseudoVASUBU_VX_M1_MASK, VASUBU_VX, 0x0, 0x0 }, // 424 { PseudoVASUBU_VX_M2, VASUBU_VX, 0x1, 0x0 }, // 425 { PseudoVASUBU_VX_M2_MASK, VASUBU_VX, 0x1, 0x0 }, // 426 { PseudoVASUBU_VX_M4, VASUBU_VX, 0x2, 0x0 }, // 427 { PseudoVASUBU_VX_M4_MASK, VASUBU_VX, 0x2, 0x0 }, // 428 { PseudoVASUBU_VX_M8, VASUBU_VX, 0x3, 0x0 }, // 429 { PseudoVASUBU_VX_M8_MASK, VASUBU_VX, 0x3, 0x0 }, // 430 { PseudoVASUBU_VX_MF8, VASUBU_VX, 0x5, 0x0 }, // 431 { PseudoVASUBU_VX_MF8_MASK, VASUBU_VX, 0x5, 0x0 }, // 432 { PseudoVASUBU_VX_MF4, VASUBU_VX, 0x6, 0x0 }, // 433 { PseudoVASUBU_VX_MF4_MASK, VASUBU_VX, 0x6, 0x0 }, // 434 { PseudoVASUBU_VX_MF2, VASUBU_VX, 0x7, 0x0 }, // 435 { PseudoVASUBU_VX_MF2_MASK, VASUBU_VX, 0x7, 0x0 }, // 436 { PseudoVASUB_VV_M1, VASUB_VV, 0x0, 0x0 }, // 437 { PseudoVASUB_VV_M1_MASK, VASUB_VV, 0x0, 0x0 }, // 438 { PseudoVASUB_VV_M2, VASUB_VV, 0x1, 0x0 }, // 439 { PseudoVASUB_VV_M2_MASK, VASUB_VV, 0x1, 0x0 }, // 440 { PseudoVASUB_VV_M4, VASUB_VV, 0x2, 0x0 }, // 441 { PseudoVASUB_VV_M4_MASK, VASUB_VV, 0x2, 0x0 }, // 442 { PseudoVASUB_VV_M8, VASUB_VV, 0x3, 0x0 }, // 443 { PseudoVASUB_VV_M8_MASK, VASUB_VV, 0x3, 0x0 }, // 444 { PseudoVASUB_VV_MF8, VASUB_VV, 0x5, 0x0 }, // 445 { PseudoVASUB_VV_MF8_MASK, VASUB_VV, 0x5, 0x0 }, // 446 { PseudoVASUB_VV_MF4, VASUB_VV, 0x6, 0x0 }, // 447 { PseudoVASUB_VV_MF4_MASK, VASUB_VV, 0x6, 0x0 }, // 448 { PseudoVASUB_VV_MF2, VASUB_VV, 0x7, 0x0 }, // 449 { PseudoVASUB_VV_MF2_MASK, VASUB_VV, 0x7, 0x0 }, // 450 { PseudoVASUB_VX_M1, VASUB_VX, 0x0, 0x0 }, // 451 { PseudoVASUB_VX_M1_MASK, VASUB_VX, 0x0, 0x0 }, // 452 { PseudoVASUB_VX_M2, VASUB_VX, 0x1, 0x0 }, // 453 { PseudoVASUB_VX_M2_MASK, VASUB_VX, 0x1, 0x0 }, // 454 { PseudoVASUB_VX_M4, VASUB_VX, 0x2, 0x0 }, // 455 { PseudoVASUB_VX_M4_MASK, VASUB_VX, 0x2, 0x0 }, // 456 { PseudoVASUB_VX_M8, VASUB_VX, 0x3, 0x0 }, // 457 { PseudoVASUB_VX_M8_MASK, VASUB_VX, 0x3, 0x0 }, // 458 { PseudoVASUB_VX_MF8, VASUB_VX, 0x5, 0x0 }, // 459 { PseudoVASUB_VX_MF8_MASK, VASUB_VX, 0x5, 0x0 }, // 460 { PseudoVASUB_VX_MF4, VASUB_VX, 0x6, 0x0 }, // 461 { PseudoVASUB_VX_MF4_MASK, VASUB_VX, 0x6, 0x0 }, // 462 { PseudoVASUB_VX_MF2, VASUB_VX, 0x7, 0x0 }, // 463 { PseudoVASUB_VX_MF2_MASK, VASUB_VX, 0x7, 0x0 }, // 464 { PseudoVBREV8_V_M1, VBREV8_V, 0x0, 0x0 }, // 465 { PseudoVBREV8_V_M1_MASK, VBREV8_V, 0x0, 0x0 }, // 466 { PseudoVBREV8_V_M2, VBREV8_V, 0x1, 0x0 }, // 467 { PseudoVBREV8_V_M2_MASK, VBREV8_V, 0x1, 0x0 }, // 468 { PseudoVBREV8_V_M4, VBREV8_V, 0x2, 0x0 }, // 469 { PseudoVBREV8_V_M4_MASK, VBREV8_V, 0x2, 0x0 }, // 470 { PseudoVBREV8_V_M8, VBREV8_V, 0x3, 0x0 }, // 471 { PseudoVBREV8_V_M8_MASK, VBREV8_V, 0x3, 0x0 }, // 472 { PseudoVBREV8_V_MF8, VBREV8_V, 0x5, 0x0 }, // 473 { PseudoVBREV8_V_MF8_MASK, VBREV8_V, 0x5, 0x0 }, // 474 { PseudoVBREV8_V_MF4, VBREV8_V, 0x6, 0x0 }, // 475 { PseudoVBREV8_V_MF4_MASK, VBREV8_V, 0x6, 0x0 }, // 476 { PseudoVBREV8_V_MF2, VBREV8_V, 0x7, 0x0 }, // 477 { PseudoVBREV8_V_MF2_MASK, VBREV8_V, 0x7, 0x0 }, // 478 { PseudoVBREV_V_M1, VBREV_V, 0x0, 0x0 }, // 479 { PseudoVBREV_V_M1_MASK, VBREV_V, 0x0, 0x0 }, // 480 { PseudoVBREV_V_M2, VBREV_V, 0x1, 0x0 }, // 481 { PseudoVBREV_V_M2_MASK, VBREV_V, 0x1, 0x0 }, // 482 { PseudoVBREV_V_M4, VBREV_V, 0x2, 0x0 }, // 483 { PseudoVBREV_V_M4_MASK, VBREV_V, 0x2, 0x0 }, // 484 { PseudoVBREV_V_M8, VBREV_V, 0x3, 0x0 }, // 485 { PseudoVBREV_V_M8_MASK, VBREV_V, 0x3, 0x0 }, // 486 { PseudoVBREV_V_MF8, VBREV_V, 0x5, 0x0 }, // 487 { PseudoVBREV_V_MF8_MASK, VBREV_V, 0x5, 0x0 }, // 488 { PseudoVBREV_V_MF4, VBREV_V, 0x6, 0x0 }, // 489 { PseudoVBREV_V_MF4_MASK, VBREV_V, 0x6, 0x0 }, // 490 { PseudoVBREV_V_MF2, VBREV_V, 0x7, 0x0 }, // 491 { PseudoVBREV_V_MF2_MASK, VBREV_V, 0x7, 0x0 }, // 492 { PseudoVCLMULH_VV_M1, VCLMULH_VV, 0x0, 0x0 }, // 493 { PseudoVCLMULH_VV_M1_MASK, VCLMULH_VV, 0x0, 0x0 }, // 494 { PseudoVCLMULH_VV_M2, VCLMULH_VV, 0x1, 0x0 }, // 495 { PseudoVCLMULH_VV_M2_MASK, VCLMULH_VV, 0x1, 0x0 }, // 496 { PseudoVCLMULH_VV_M4, VCLMULH_VV, 0x2, 0x0 }, // 497 { PseudoVCLMULH_VV_M4_MASK, VCLMULH_VV, 0x2, 0x0 }, // 498 { PseudoVCLMULH_VV_M8, VCLMULH_VV, 0x3, 0x0 }, // 499 { PseudoVCLMULH_VV_M8_MASK, VCLMULH_VV, 0x3, 0x0 }, // 500 { PseudoVCLMULH_VV_MF8, VCLMULH_VV, 0x5, 0x0 }, // 501 { PseudoVCLMULH_VV_MF8_MASK, VCLMULH_VV, 0x5, 0x0 }, // 502 { PseudoVCLMULH_VV_MF4, VCLMULH_VV, 0x6, 0x0 }, // 503 { PseudoVCLMULH_VV_MF4_MASK, VCLMULH_VV, 0x6, 0x0 }, // 504 { PseudoVCLMULH_VV_MF2, VCLMULH_VV, 0x7, 0x0 }, // 505 { PseudoVCLMULH_VV_MF2_MASK, VCLMULH_VV, 0x7, 0x0 }, // 506 { PseudoVCLMULH_VX_M1, VCLMULH_VX, 0x0, 0x0 }, // 507 { PseudoVCLMULH_VX_M1_MASK, VCLMULH_VX, 0x0, 0x0 }, // 508 { PseudoVCLMULH_VX_M2, VCLMULH_VX, 0x1, 0x0 }, // 509 { PseudoVCLMULH_VX_M2_MASK, VCLMULH_VX, 0x1, 0x0 }, // 510 { PseudoVCLMULH_VX_M4, VCLMULH_VX, 0x2, 0x0 }, // 511 { PseudoVCLMULH_VX_M4_MASK, VCLMULH_VX, 0x2, 0x0 }, // 512 { PseudoVCLMULH_VX_M8, VCLMULH_VX, 0x3, 0x0 }, // 513 { PseudoVCLMULH_VX_M8_MASK, VCLMULH_VX, 0x3, 0x0 }, // 514 { PseudoVCLMULH_VX_MF8, VCLMULH_VX, 0x5, 0x0 }, // 515 { PseudoVCLMULH_VX_MF8_MASK, VCLMULH_VX, 0x5, 0x0 }, // 516 { PseudoVCLMULH_VX_MF4, VCLMULH_VX, 0x6, 0x0 }, // 517 { PseudoVCLMULH_VX_MF4_MASK, VCLMULH_VX, 0x6, 0x0 }, // 518 { PseudoVCLMULH_VX_MF2, VCLMULH_VX, 0x7, 0x0 }, // 519 { PseudoVCLMULH_VX_MF2_MASK, VCLMULH_VX, 0x7, 0x0 }, // 520 { PseudoVCLMUL_VV_M1, VCLMUL_VV, 0x0, 0x0 }, // 521 { PseudoVCLMUL_VV_M1_MASK, VCLMUL_VV, 0x0, 0x0 }, // 522 { PseudoVCLMUL_VV_M2, VCLMUL_VV, 0x1, 0x0 }, // 523 { PseudoVCLMUL_VV_M2_MASK, VCLMUL_VV, 0x1, 0x0 }, // 524 { PseudoVCLMUL_VV_M4, VCLMUL_VV, 0x2, 0x0 }, // 525 { PseudoVCLMUL_VV_M4_MASK, VCLMUL_VV, 0x2, 0x0 }, // 526 { PseudoVCLMUL_VV_M8, VCLMUL_VV, 0x3, 0x0 }, // 527 { PseudoVCLMUL_VV_M8_MASK, VCLMUL_VV, 0x3, 0x0 }, // 528 { PseudoVCLMUL_VV_MF8, VCLMUL_VV, 0x5, 0x0 }, // 529 { PseudoVCLMUL_VV_MF8_MASK, VCLMUL_VV, 0x5, 0x0 }, // 530 { PseudoVCLMUL_VV_MF4, VCLMUL_VV, 0x6, 0x0 }, // 531 { PseudoVCLMUL_VV_MF4_MASK, VCLMUL_VV, 0x6, 0x0 }, // 532 { PseudoVCLMUL_VV_MF2, VCLMUL_VV, 0x7, 0x0 }, // 533 { PseudoVCLMUL_VV_MF2_MASK, VCLMUL_VV, 0x7, 0x0 }, // 534 { PseudoVCLMUL_VX_M1, VCLMUL_VX, 0x0, 0x0 }, // 535 { PseudoVCLMUL_VX_M1_MASK, VCLMUL_VX, 0x0, 0x0 }, // 536 { PseudoVCLMUL_VX_M2, VCLMUL_VX, 0x1, 0x0 }, // 537 { PseudoVCLMUL_VX_M2_MASK, VCLMUL_VX, 0x1, 0x0 }, // 538 { PseudoVCLMUL_VX_M4, VCLMUL_VX, 0x2, 0x0 }, // 539 { PseudoVCLMUL_VX_M4_MASK, VCLMUL_VX, 0x2, 0x0 }, // 540 { PseudoVCLMUL_VX_M8, VCLMUL_VX, 0x3, 0x0 }, // 541 { PseudoVCLMUL_VX_M8_MASK, VCLMUL_VX, 0x3, 0x0 }, // 542 { PseudoVCLMUL_VX_MF8, VCLMUL_VX, 0x5, 0x0 }, // 543 { PseudoVCLMUL_VX_MF8_MASK, VCLMUL_VX, 0x5, 0x0 }, // 544 { PseudoVCLMUL_VX_MF4, VCLMUL_VX, 0x6, 0x0 }, // 545 { PseudoVCLMUL_VX_MF4_MASK, VCLMUL_VX, 0x6, 0x0 }, // 546 { PseudoVCLMUL_VX_MF2, VCLMUL_VX, 0x7, 0x0 }, // 547 { PseudoVCLMUL_VX_MF2_MASK, VCLMUL_VX, 0x7, 0x0 }, // 548 { PseudoVCLZ_V_M1, VCLZ_V, 0x0, 0x0 }, // 549 { PseudoVCLZ_V_M1_MASK, VCLZ_V, 0x0, 0x0 }, // 550 { PseudoVCLZ_V_M2, VCLZ_V, 0x1, 0x0 }, // 551 { PseudoVCLZ_V_M2_MASK, VCLZ_V, 0x1, 0x0 }, // 552 { PseudoVCLZ_V_M4, VCLZ_V, 0x2, 0x0 }, // 553 { PseudoVCLZ_V_M4_MASK, VCLZ_V, 0x2, 0x0 }, // 554 { PseudoVCLZ_V_M8, VCLZ_V, 0x3, 0x0 }, // 555 { PseudoVCLZ_V_M8_MASK, VCLZ_V, 0x3, 0x0 }, // 556 { PseudoVCLZ_V_MF8, VCLZ_V, 0x5, 0x0 }, // 557 { PseudoVCLZ_V_MF8_MASK, VCLZ_V, 0x5, 0x0 }, // 558 { PseudoVCLZ_V_MF4, VCLZ_V, 0x6, 0x0 }, // 559 { PseudoVCLZ_V_MF4_MASK, VCLZ_V, 0x6, 0x0 }, // 560 { PseudoVCLZ_V_MF2, VCLZ_V, 0x7, 0x0 }, // 561 { PseudoVCLZ_V_MF2_MASK, VCLZ_V, 0x7, 0x0 }, // 562 { PseudoVCOMPRESS_VM_M1_E8, VCOMPRESS_VM, 0x0, 0x8 }, // 563 { PseudoVCOMPRESS_VM_M1_E16, VCOMPRESS_VM, 0x0, 0x10 }, // 564 { PseudoVCOMPRESS_VM_M1_E32, VCOMPRESS_VM, 0x0, 0x20 }, // 565 { PseudoVCOMPRESS_VM_M1_E64, VCOMPRESS_VM, 0x0, 0x40 }, // 566 { PseudoVCOMPRESS_VM_M2_E8, VCOMPRESS_VM, 0x1, 0x8 }, // 567 { PseudoVCOMPRESS_VM_M2_E16, VCOMPRESS_VM, 0x1, 0x10 }, // 568 { PseudoVCOMPRESS_VM_M2_E32, VCOMPRESS_VM, 0x1, 0x20 }, // 569 { PseudoVCOMPRESS_VM_M2_E64, VCOMPRESS_VM, 0x1, 0x40 }, // 570 { PseudoVCOMPRESS_VM_M4_E8, VCOMPRESS_VM, 0x2, 0x8 }, // 571 { PseudoVCOMPRESS_VM_M4_E16, VCOMPRESS_VM, 0x2, 0x10 }, // 572 { PseudoVCOMPRESS_VM_M4_E32, VCOMPRESS_VM, 0x2, 0x20 }, // 573 { PseudoVCOMPRESS_VM_M4_E64, VCOMPRESS_VM, 0x2, 0x40 }, // 574 { PseudoVCOMPRESS_VM_M8_E8, VCOMPRESS_VM, 0x3, 0x8 }, // 575 { PseudoVCOMPRESS_VM_M8_E16, VCOMPRESS_VM, 0x3, 0x10 }, // 576 { PseudoVCOMPRESS_VM_M8_E32, VCOMPRESS_VM, 0x3, 0x20 }, // 577 { PseudoVCOMPRESS_VM_M8_E64, VCOMPRESS_VM, 0x3, 0x40 }, // 578 { PseudoVCOMPRESS_VM_MF8_E8, VCOMPRESS_VM, 0x5, 0x8 }, // 579 { PseudoVCOMPRESS_VM_MF4_E8, VCOMPRESS_VM, 0x6, 0x8 }, // 580 { PseudoVCOMPRESS_VM_MF4_E16, VCOMPRESS_VM, 0x6, 0x10 }, // 581 { PseudoVCOMPRESS_VM_MF2_E8, VCOMPRESS_VM, 0x7, 0x8 }, // 582 { PseudoVCOMPRESS_VM_MF2_E16, VCOMPRESS_VM, 0x7, 0x10 }, // 583 { PseudoVCOMPRESS_VM_MF2_E32, VCOMPRESS_VM, 0x7, 0x20 }, // 584 { PseudoVCPOP_M_B8, VCPOP_M, 0x0, 0x0 }, // 585 { PseudoVCPOP_M_B8_MASK, VCPOP_M, 0x0, 0x0 }, // 586 { PseudoVCPOP_M_B16, VCPOP_M, 0x1, 0x0 }, // 587 { PseudoVCPOP_M_B16_MASK, VCPOP_M, 0x1, 0x0 }, // 588 { PseudoVCPOP_M_B32, VCPOP_M, 0x2, 0x0 }, // 589 { PseudoVCPOP_M_B32_MASK, VCPOP_M, 0x2, 0x0 }, // 590 { PseudoVCPOP_M_B64, VCPOP_M, 0x3, 0x0 }, // 591 { PseudoVCPOP_M_B64_MASK, VCPOP_M, 0x3, 0x0 }, // 592 { PseudoVCPOP_M_B1, VCPOP_M, 0x5, 0x0 }, // 593 { PseudoVCPOP_M_B1_MASK, VCPOP_M, 0x5, 0x0 }, // 594 { PseudoVCPOP_M_B2, VCPOP_M, 0x6, 0x0 }, // 595 { PseudoVCPOP_M_B2_MASK, VCPOP_M, 0x6, 0x0 }, // 596 { PseudoVCPOP_M_B4, VCPOP_M, 0x7, 0x0 }, // 597 { PseudoVCPOP_M_B4_MASK, VCPOP_M, 0x7, 0x0 }, // 598 { PseudoVCPOP_V_M1, VCPOP_V, 0x0, 0x0 }, // 599 { PseudoVCPOP_V_M1_MASK, VCPOP_V, 0x0, 0x0 }, // 600 { PseudoVCPOP_V_M2, VCPOP_V, 0x1, 0x0 }, // 601 { PseudoVCPOP_V_M2_MASK, VCPOP_V, 0x1, 0x0 }, // 602 { PseudoVCPOP_V_M4, VCPOP_V, 0x2, 0x0 }, // 603 { PseudoVCPOP_V_M4_MASK, VCPOP_V, 0x2, 0x0 }, // 604 { PseudoVCPOP_V_M8, VCPOP_V, 0x3, 0x0 }, // 605 { PseudoVCPOP_V_M8_MASK, VCPOP_V, 0x3, 0x0 }, // 606 { PseudoVCPOP_V_MF8, VCPOP_V, 0x5, 0x0 }, // 607 { PseudoVCPOP_V_MF8_MASK, VCPOP_V, 0x5, 0x0 }, // 608 { PseudoVCPOP_V_MF4, VCPOP_V, 0x6, 0x0 }, // 609 { PseudoVCPOP_V_MF4_MASK, VCPOP_V, 0x6, 0x0 }, // 610 { PseudoVCPOP_V_MF2, VCPOP_V, 0x7, 0x0 }, // 611 { PseudoVCPOP_V_MF2_MASK, VCPOP_V, 0x7, 0x0 }, // 612 { PseudoVCTZ_V_M1, VCTZ_V, 0x0, 0x0 }, // 613 { PseudoVCTZ_V_M1_MASK, VCTZ_V, 0x0, 0x0 }, // 614 { PseudoVCTZ_V_M2, VCTZ_V, 0x1, 0x0 }, // 615 { PseudoVCTZ_V_M2_MASK, VCTZ_V, 0x1, 0x0 }, // 616 { PseudoVCTZ_V_M4, VCTZ_V, 0x2, 0x0 }, // 617 { PseudoVCTZ_V_M4_MASK, VCTZ_V, 0x2, 0x0 }, // 618 { PseudoVCTZ_V_M8, VCTZ_V, 0x3, 0x0 }, // 619 { PseudoVCTZ_V_M8_MASK, VCTZ_V, 0x3, 0x0 }, // 620 { PseudoVCTZ_V_MF8, VCTZ_V, 0x5, 0x0 }, // 621 { PseudoVCTZ_V_MF8_MASK, VCTZ_V, 0x5, 0x0 }, // 622 { PseudoVCTZ_V_MF4, VCTZ_V, 0x6, 0x0 }, // 623 { PseudoVCTZ_V_MF4_MASK, VCTZ_V, 0x6, 0x0 }, // 624 { PseudoVCTZ_V_MF2, VCTZ_V, 0x7, 0x0 }, // 625 { PseudoVCTZ_V_MF2_MASK, VCTZ_V, 0x7, 0x0 }, // 626 { PseudoVC_FPR16V_SE_M1, VC_FV, 0x0, 0x0 }, // 627 { PseudoVC_FPR32V_SE_M1, VC_FV, 0x0, 0x0 }, // 628 { PseudoVC_FPR64V_SE_M1, VC_FV, 0x0, 0x0 }, // 629 { PseudoVC_FPR16V_SE_M2, VC_FV, 0x1, 0x0 }, // 630 { PseudoVC_FPR32V_SE_M2, VC_FV, 0x1, 0x0 }, // 631 { PseudoVC_FPR64V_SE_M2, VC_FV, 0x1, 0x0 }, // 632 { PseudoVC_FPR16V_SE_M4, VC_FV, 0x2, 0x0 }, // 633 { PseudoVC_FPR32V_SE_M4, VC_FV, 0x2, 0x0 }, // 634 { PseudoVC_FPR64V_SE_M4, VC_FV, 0x2, 0x0 }, // 635 { PseudoVC_FPR16V_SE_M8, VC_FV, 0x3, 0x0 }, // 636 { PseudoVC_FPR32V_SE_M8, VC_FV, 0x3, 0x0 }, // 637 { PseudoVC_FPR64V_SE_M8, VC_FV, 0x3, 0x0 }, // 638 { PseudoVC_FPR16V_SE_MF4, VC_FV, 0x6, 0x0 }, // 639 { PseudoVC_FPR16V_SE_MF2, VC_FV, 0x7, 0x0 }, // 640 { PseudoVC_FPR32V_SE_MF2, VC_FV, 0x7, 0x0 }, // 641 { PseudoVC_FPR16VV_SE_M1, VC_FVV, 0x0, 0x0 }, // 642 { PseudoVC_FPR32VV_SE_M1, VC_FVV, 0x0, 0x0 }, // 643 { PseudoVC_FPR64VV_SE_M1, VC_FVV, 0x0, 0x0 }, // 644 { PseudoVC_FPR16VV_SE_M2, VC_FVV, 0x1, 0x0 }, // 645 { PseudoVC_FPR32VV_SE_M2, VC_FVV, 0x1, 0x0 }, // 646 { PseudoVC_FPR64VV_SE_M2, VC_FVV, 0x1, 0x0 }, // 647 { PseudoVC_FPR16VV_SE_M4, VC_FVV, 0x2, 0x0 }, // 648 { PseudoVC_FPR32VV_SE_M4, VC_FVV, 0x2, 0x0 }, // 649 { PseudoVC_FPR64VV_SE_M4, VC_FVV, 0x2, 0x0 }, // 650 { PseudoVC_FPR16VV_SE_M8, VC_FVV, 0x3, 0x0 }, // 651 { PseudoVC_FPR32VV_SE_M8, VC_FVV, 0x3, 0x0 }, // 652 { PseudoVC_FPR64VV_SE_M8, VC_FVV, 0x3, 0x0 }, // 653 { PseudoVC_FPR16VV_SE_MF4, VC_FVV, 0x6, 0x0 }, // 654 { PseudoVC_FPR16VV_SE_MF2, VC_FVV, 0x7, 0x0 }, // 655 { PseudoVC_FPR32VV_SE_MF2, VC_FVV, 0x7, 0x0 }, // 656 { PseudoVC_FPR16VW_SE_M1, VC_FVW, 0x0, 0x0 }, // 657 { PseudoVC_FPR32VW_SE_M1, VC_FVW, 0x0, 0x0 }, // 658 { PseudoVC_FPR16VW_SE_M2, VC_FVW, 0x1, 0x0 }, // 659 { PseudoVC_FPR32VW_SE_M2, VC_FVW, 0x1, 0x0 }, // 660 { PseudoVC_FPR16VW_SE_M4, VC_FVW, 0x2, 0x0 }, // 661 { PseudoVC_FPR32VW_SE_M4, VC_FVW, 0x2, 0x0 }, // 662 { PseudoVC_FPR16VW_SE_M8, VC_FVW, 0x3, 0x0 }, // 663 { PseudoVC_FPR32VW_SE_M8, VC_FVW, 0x3, 0x0 }, // 664 { PseudoVC_FPR16VW_SE_MF4, VC_FVW, 0x6, 0x0 }, // 665 { PseudoVC_FPR16VW_SE_MF2, VC_FVW, 0x7, 0x0 }, // 666 { PseudoVC_FPR32VW_SE_MF2, VC_FVW, 0x7, 0x0 }, // 667 { PseudoVC_I_SE_M1, VC_I, 0x0, 0x0 }, // 668 { PseudoVC_I_SE_M2, VC_I, 0x1, 0x0 }, // 669 { PseudoVC_I_SE_M4, VC_I, 0x2, 0x0 }, // 670 { PseudoVC_I_SE_M8, VC_I, 0x3, 0x0 }, // 671 { PseudoVC_I_SE_MF8, VC_I, 0x5, 0x0 }, // 672 { PseudoVC_I_SE_MF4, VC_I, 0x6, 0x0 }, // 673 { PseudoVC_I_SE_MF2, VC_I, 0x7, 0x0 }, // 674 { PseudoVC_IV_SE_M1, VC_IV, 0x0, 0x0 }, // 675 { PseudoVC_IV_SE_M2, VC_IV, 0x1, 0x0 }, // 676 { PseudoVC_IV_SE_M4, VC_IV, 0x2, 0x0 }, // 677 { PseudoVC_IV_SE_M8, VC_IV, 0x3, 0x0 }, // 678 { PseudoVC_IV_SE_MF8, VC_IV, 0x5, 0x0 }, // 679 { PseudoVC_IV_SE_MF4, VC_IV, 0x6, 0x0 }, // 680 { PseudoVC_IV_SE_MF2, VC_IV, 0x7, 0x0 }, // 681 { PseudoVC_IVV_SE_M1, VC_IVV, 0x0, 0x0 }, // 682 { PseudoVC_IVV_SE_M2, VC_IVV, 0x1, 0x0 }, // 683 { PseudoVC_IVV_SE_M4, VC_IVV, 0x2, 0x0 }, // 684 { PseudoVC_IVV_SE_M8, VC_IVV, 0x3, 0x0 }, // 685 { PseudoVC_IVV_SE_MF8, VC_IVV, 0x5, 0x0 }, // 686 { PseudoVC_IVV_SE_MF4, VC_IVV, 0x6, 0x0 }, // 687 { PseudoVC_IVV_SE_MF2, VC_IVV, 0x7, 0x0 }, // 688 { PseudoVC_IVW_SE_M1, VC_IVW, 0x0, 0x0 }, // 689 { PseudoVC_IVW_SE_M2, VC_IVW, 0x1, 0x0 }, // 690 { PseudoVC_IVW_SE_M4, VC_IVW, 0x2, 0x0 }, // 691 { PseudoVC_IVW_SE_MF8, VC_IVW, 0x5, 0x0 }, // 692 { PseudoVC_IVW_SE_MF4, VC_IVW, 0x6, 0x0 }, // 693 { PseudoVC_IVW_SE_MF2, VC_IVW, 0x7, 0x0 }, // 694 { PseudoVC_VV_SE_M1, VC_VV, 0x0, 0x0 }, // 695 { PseudoVC_VV_SE_M2, VC_VV, 0x1, 0x0 }, // 696 { PseudoVC_VV_SE_M4, VC_VV, 0x2, 0x0 }, // 697 { PseudoVC_VV_SE_M8, VC_VV, 0x3, 0x0 }, // 698 { PseudoVC_VV_SE_MF8, VC_VV, 0x5, 0x0 }, // 699 { PseudoVC_VV_SE_MF4, VC_VV, 0x6, 0x0 }, // 700 { PseudoVC_VV_SE_MF2, VC_VV, 0x7, 0x0 }, // 701 { PseudoVC_VVV_SE_M1, VC_VVV, 0x0, 0x0 }, // 702 { PseudoVC_VVV_SE_M2, VC_VVV, 0x1, 0x0 }, // 703 { PseudoVC_VVV_SE_M4, VC_VVV, 0x2, 0x0 }, // 704 { PseudoVC_VVV_SE_M8, VC_VVV, 0x3, 0x0 }, // 705 { PseudoVC_VVV_SE_MF8, VC_VVV, 0x5, 0x0 }, // 706 { PseudoVC_VVV_SE_MF4, VC_VVV, 0x6, 0x0 }, // 707 { PseudoVC_VVV_SE_MF2, VC_VVV, 0x7, 0x0 }, // 708 { PseudoVC_VVW_SE_M1, VC_VVW, 0x0, 0x0 }, // 709 { PseudoVC_VVW_SE_M2, VC_VVW, 0x1, 0x0 }, // 710 { PseudoVC_VVW_SE_M4, VC_VVW, 0x2, 0x0 }, // 711 { PseudoVC_VVW_SE_MF8, VC_VVW, 0x5, 0x0 }, // 712 { PseudoVC_VVW_SE_MF4, VC_VVW, 0x6, 0x0 }, // 713 { PseudoVC_VVW_SE_MF2, VC_VVW, 0x7, 0x0 }, // 714 { PseudoVC_V_FPR16V_M1, VC_V_FV, 0x0, 0x0 }, // 715 { PseudoVC_V_FPR16V_SE_M1, VC_V_FV, 0x0, 0x0 }, // 716 { PseudoVC_V_FPR32V_M1, VC_V_FV, 0x0, 0x0 }, // 717 { PseudoVC_V_FPR32V_SE_M1, VC_V_FV, 0x0, 0x0 }, // 718 { PseudoVC_V_FPR64V_M1, VC_V_FV, 0x0, 0x0 }, // 719 { PseudoVC_V_FPR64V_SE_M1, VC_V_FV, 0x0, 0x0 }, // 720 { PseudoVC_V_FPR16V_M2, VC_V_FV, 0x1, 0x0 }, // 721 { PseudoVC_V_FPR16V_SE_M2, VC_V_FV, 0x1, 0x0 }, // 722 { PseudoVC_V_FPR32V_M2, VC_V_FV, 0x1, 0x0 }, // 723 { PseudoVC_V_FPR32V_SE_M2, VC_V_FV, 0x1, 0x0 }, // 724 { PseudoVC_V_FPR64V_M2, VC_V_FV, 0x1, 0x0 }, // 725 { PseudoVC_V_FPR64V_SE_M2, VC_V_FV, 0x1, 0x0 }, // 726 { PseudoVC_V_FPR16V_M4, VC_V_FV, 0x2, 0x0 }, // 727 { PseudoVC_V_FPR16V_SE_M4, VC_V_FV, 0x2, 0x0 }, // 728 { PseudoVC_V_FPR32V_M4, VC_V_FV, 0x2, 0x0 }, // 729 { PseudoVC_V_FPR32V_SE_M4, VC_V_FV, 0x2, 0x0 }, // 730 { PseudoVC_V_FPR64V_M4, VC_V_FV, 0x2, 0x0 }, // 731 { PseudoVC_V_FPR64V_SE_M4, VC_V_FV, 0x2, 0x0 }, // 732 { PseudoVC_V_FPR16V_M8, VC_V_FV, 0x3, 0x0 }, // 733 { PseudoVC_V_FPR16V_SE_M8, VC_V_FV, 0x3, 0x0 }, // 734 { PseudoVC_V_FPR32V_M8, VC_V_FV, 0x3, 0x0 }, // 735 { PseudoVC_V_FPR32V_SE_M8, VC_V_FV, 0x3, 0x0 }, // 736 { PseudoVC_V_FPR64V_M8, VC_V_FV, 0x3, 0x0 }, // 737 { PseudoVC_V_FPR64V_SE_M8, VC_V_FV, 0x3, 0x0 }, // 738 { PseudoVC_V_FPR16V_MF4, VC_V_FV, 0x6, 0x0 }, // 739 { PseudoVC_V_FPR16V_SE_MF4, VC_V_FV, 0x6, 0x0 }, // 740 { PseudoVC_V_FPR16V_MF2, VC_V_FV, 0x7, 0x0 }, // 741 { PseudoVC_V_FPR16V_SE_MF2, VC_V_FV, 0x7, 0x0 }, // 742 { PseudoVC_V_FPR32V_MF2, VC_V_FV, 0x7, 0x0 }, // 743 { PseudoVC_V_FPR32V_SE_MF2, VC_V_FV, 0x7, 0x0 }, // 744 { PseudoVC_V_FPR16VV_M1, VC_V_FVV, 0x0, 0x0 }, // 745 { PseudoVC_V_FPR16VV_SE_M1, VC_V_FVV, 0x0, 0x0 }, // 746 { PseudoVC_V_FPR32VV_M1, VC_V_FVV, 0x0, 0x0 }, // 747 { PseudoVC_V_FPR32VV_SE_M1, VC_V_FVV, 0x0, 0x0 }, // 748 { PseudoVC_V_FPR64VV_M1, VC_V_FVV, 0x0, 0x0 }, // 749 { PseudoVC_V_FPR64VV_SE_M1, VC_V_FVV, 0x0, 0x0 }, // 750 { PseudoVC_V_FPR16VV_M2, VC_V_FVV, 0x1, 0x0 }, // 751 { PseudoVC_V_FPR16VV_SE_M2, VC_V_FVV, 0x1, 0x0 }, // 752 { PseudoVC_V_FPR32VV_M2, VC_V_FVV, 0x1, 0x0 }, // 753 { PseudoVC_V_FPR32VV_SE_M2, VC_V_FVV, 0x1, 0x0 }, // 754 { PseudoVC_V_FPR64VV_M2, VC_V_FVV, 0x1, 0x0 }, // 755 { PseudoVC_V_FPR64VV_SE_M2, VC_V_FVV, 0x1, 0x0 }, // 756 { PseudoVC_V_FPR16VV_M4, VC_V_FVV, 0x2, 0x0 }, // 757 { PseudoVC_V_FPR16VV_SE_M4, VC_V_FVV, 0x2, 0x0 }, // 758 { PseudoVC_V_FPR32VV_M4, VC_V_FVV, 0x2, 0x0 }, // 759 { PseudoVC_V_FPR32VV_SE_M4, VC_V_FVV, 0x2, 0x0 }, // 760 { PseudoVC_V_FPR64VV_M4, VC_V_FVV, 0x2, 0x0 }, // 761 { PseudoVC_V_FPR64VV_SE_M4, VC_V_FVV, 0x2, 0x0 }, // 762 { PseudoVC_V_FPR16VV_M8, VC_V_FVV, 0x3, 0x0 }, // 763 { PseudoVC_V_FPR16VV_SE_M8, VC_V_FVV, 0x3, 0x0 }, // 764 { PseudoVC_V_FPR32VV_M8, VC_V_FVV, 0x3, 0x0 }, // 765 { PseudoVC_V_FPR32VV_SE_M8, VC_V_FVV, 0x3, 0x0 }, // 766 { PseudoVC_V_FPR64VV_M8, VC_V_FVV, 0x3, 0x0 }, // 767 { PseudoVC_V_FPR64VV_SE_M8, VC_V_FVV, 0x3, 0x0 }, // 768 { PseudoVC_V_FPR16VV_MF4, VC_V_FVV, 0x6, 0x0 }, // 769 { PseudoVC_V_FPR16VV_SE_MF4, VC_V_FVV, 0x6, 0x0 }, // 770 { PseudoVC_V_FPR16VV_MF2, VC_V_FVV, 0x7, 0x0 }, // 771 { PseudoVC_V_FPR16VV_SE_MF2, VC_V_FVV, 0x7, 0x0 }, // 772 { PseudoVC_V_FPR32VV_MF2, VC_V_FVV, 0x7, 0x0 }, // 773 { PseudoVC_V_FPR32VV_SE_MF2, VC_V_FVV, 0x7, 0x0 }, // 774 { PseudoVC_V_FPR16VW_M1, VC_V_FVW, 0x0, 0x0 }, // 775 { PseudoVC_V_FPR16VW_SE_M1, VC_V_FVW, 0x0, 0x0 }, // 776 { PseudoVC_V_FPR32VW_M1, VC_V_FVW, 0x0, 0x0 }, // 777 { PseudoVC_V_FPR32VW_SE_M1, VC_V_FVW, 0x0, 0x0 }, // 778 { PseudoVC_V_FPR16VW_M2, VC_V_FVW, 0x1, 0x0 }, // 779 { PseudoVC_V_FPR16VW_SE_M2, VC_V_FVW, 0x1, 0x0 }, // 780 { PseudoVC_V_FPR32VW_M2, VC_V_FVW, 0x1, 0x0 }, // 781 { PseudoVC_V_FPR32VW_SE_M2, VC_V_FVW, 0x1, 0x0 }, // 782 { PseudoVC_V_FPR16VW_M4, VC_V_FVW, 0x2, 0x0 }, // 783 { PseudoVC_V_FPR16VW_SE_M4, VC_V_FVW, 0x2, 0x0 }, // 784 { PseudoVC_V_FPR32VW_M4, VC_V_FVW, 0x2, 0x0 }, // 785 { PseudoVC_V_FPR32VW_SE_M4, VC_V_FVW, 0x2, 0x0 }, // 786 { PseudoVC_V_FPR16VW_M8, VC_V_FVW, 0x3, 0x0 }, // 787 { PseudoVC_V_FPR16VW_SE_M8, VC_V_FVW, 0x3, 0x0 }, // 788 { PseudoVC_V_FPR32VW_M8, VC_V_FVW, 0x3, 0x0 }, // 789 { PseudoVC_V_FPR32VW_SE_M8, VC_V_FVW, 0x3, 0x0 }, // 790 { PseudoVC_V_FPR16VW_MF4, VC_V_FVW, 0x6, 0x0 }, // 791 { PseudoVC_V_FPR16VW_SE_MF4, VC_V_FVW, 0x6, 0x0 }, // 792 { PseudoVC_V_FPR16VW_MF2, VC_V_FVW, 0x7, 0x0 }, // 793 { PseudoVC_V_FPR16VW_SE_MF2, VC_V_FVW, 0x7, 0x0 }, // 794 { PseudoVC_V_FPR32VW_MF2, VC_V_FVW, 0x7, 0x0 }, // 795 { PseudoVC_V_FPR32VW_SE_MF2, VC_V_FVW, 0x7, 0x0 }, // 796 { PseudoVC_V_I_M1, VC_V_I, 0x0, 0x0 }, // 797 { PseudoVC_V_I_SE_M1, VC_V_I, 0x0, 0x0 }, // 798 { PseudoVC_V_I_M2, VC_V_I, 0x1, 0x0 }, // 799 { PseudoVC_V_I_SE_M2, VC_V_I, 0x1, 0x0 }, // 800 { PseudoVC_V_I_M4, VC_V_I, 0x2, 0x0 }, // 801 { PseudoVC_V_I_SE_M4, VC_V_I, 0x2, 0x0 }, // 802 { PseudoVC_V_I_M8, VC_V_I, 0x3, 0x0 }, // 803 { PseudoVC_V_I_SE_M8, VC_V_I, 0x3, 0x0 }, // 804 { PseudoVC_V_I_MF8, VC_V_I, 0x5, 0x0 }, // 805 { PseudoVC_V_I_SE_MF8, VC_V_I, 0x5, 0x0 }, // 806 { PseudoVC_V_I_MF4, VC_V_I, 0x6, 0x0 }, // 807 { PseudoVC_V_I_SE_MF4, VC_V_I, 0x6, 0x0 }, // 808 { PseudoVC_V_I_MF2, VC_V_I, 0x7, 0x0 }, // 809 { PseudoVC_V_I_SE_MF2, VC_V_I, 0x7, 0x0 }, // 810 { PseudoVC_V_IV_M1, VC_V_IV, 0x0, 0x0 }, // 811 { PseudoVC_V_IV_SE_M1, VC_V_IV, 0x0, 0x0 }, // 812 { PseudoVC_V_IV_M2, VC_V_IV, 0x1, 0x0 }, // 813 { PseudoVC_V_IV_SE_M2, VC_V_IV, 0x1, 0x0 }, // 814 { PseudoVC_V_IV_M4, VC_V_IV, 0x2, 0x0 }, // 815 { PseudoVC_V_IV_SE_M4, VC_V_IV, 0x2, 0x0 }, // 816 { PseudoVC_V_IV_M8, VC_V_IV, 0x3, 0x0 }, // 817 { PseudoVC_V_IV_SE_M8, VC_V_IV, 0x3, 0x0 }, // 818 { PseudoVC_V_IV_MF8, VC_V_IV, 0x5, 0x0 }, // 819 { PseudoVC_V_IV_SE_MF8, VC_V_IV, 0x5, 0x0 }, // 820 { PseudoVC_V_IV_MF4, VC_V_IV, 0x6, 0x0 }, // 821 { PseudoVC_V_IV_SE_MF4, VC_V_IV, 0x6, 0x0 }, // 822 { PseudoVC_V_IV_MF2, VC_V_IV, 0x7, 0x0 }, // 823 { PseudoVC_V_IV_SE_MF2, VC_V_IV, 0x7, 0x0 }, // 824 { PseudoVC_V_IVV_M1, VC_V_IVV, 0x0, 0x0 }, // 825 { PseudoVC_V_IVV_SE_M1, VC_V_IVV, 0x0, 0x0 }, // 826 { PseudoVC_V_IVV_M2, VC_V_IVV, 0x1, 0x0 }, // 827 { PseudoVC_V_IVV_SE_M2, VC_V_IVV, 0x1, 0x0 }, // 828 { PseudoVC_V_IVV_M4, VC_V_IVV, 0x2, 0x0 }, // 829 { PseudoVC_V_IVV_SE_M4, VC_V_IVV, 0x2, 0x0 }, // 830 { PseudoVC_V_IVV_M8, VC_V_IVV, 0x3, 0x0 }, // 831 { PseudoVC_V_IVV_SE_M8, VC_V_IVV, 0x3, 0x0 }, // 832 { PseudoVC_V_IVV_MF8, VC_V_IVV, 0x5, 0x0 }, // 833 { PseudoVC_V_IVV_SE_MF8, VC_V_IVV, 0x5, 0x0 }, // 834 { PseudoVC_V_IVV_MF4, VC_V_IVV, 0x6, 0x0 }, // 835 { PseudoVC_V_IVV_SE_MF4, VC_V_IVV, 0x6, 0x0 }, // 836 { PseudoVC_V_IVV_MF2, VC_V_IVV, 0x7, 0x0 }, // 837 { PseudoVC_V_IVV_SE_MF2, VC_V_IVV, 0x7, 0x0 }, // 838 { PseudoVC_V_IVW_M1, VC_V_IVW, 0x0, 0x0 }, // 839 { PseudoVC_V_IVW_SE_M1, VC_V_IVW, 0x0, 0x0 }, // 840 { PseudoVC_V_IVW_M2, VC_V_IVW, 0x1, 0x0 }, // 841 { PseudoVC_V_IVW_SE_M2, VC_V_IVW, 0x1, 0x0 }, // 842 { PseudoVC_V_IVW_M4, VC_V_IVW, 0x2, 0x0 }, // 843 { PseudoVC_V_IVW_SE_M4, VC_V_IVW, 0x2, 0x0 }, // 844 { PseudoVC_V_IVW_MF8, VC_V_IVW, 0x5, 0x0 }, // 845 { PseudoVC_V_IVW_SE_MF8, VC_V_IVW, 0x5, 0x0 }, // 846 { PseudoVC_V_IVW_MF4, VC_V_IVW, 0x6, 0x0 }, // 847 { PseudoVC_V_IVW_SE_MF4, VC_V_IVW, 0x6, 0x0 }, // 848 { PseudoVC_V_IVW_MF2, VC_V_IVW, 0x7, 0x0 }, // 849 { PseudoVC_V_IVW_SE_MF2, VC_V_IVW, 0x7, 0x0 }, // 850 { PseudoVC_V_VV_M1, VC_V_VV, 0x0, 0x0 }, // 851 { PseudoVC_V_VV_SE_M1, VC_V_VV, 0x0, 0x0 }, // 852 { PseudoVC_V_VV_M2, VC_V_VV, 0x1, 0x0 }, // 853 { PseudoVC_V_VV_SE_M2, VC_V_VV, 0x1, 0x0 }, // 854 { PseudoVC_V_VV_M4, VC_V_VV, 0x2, 0x0 }, // 855 { PseudoVC_V_VV_SE_M4, VC_V_VV, 0x2, 0x0 }, // 856 { PseudoVC_V_VV_M8, VC_V_VV, 0x3, 0x0 }, // 857 { PseudoVC_V_VV_SE_M8, VC_V_VV, 0x3, 0x0 }, // 858 { PseudoVC_V_VV_MF8, VC_V_VV, 0x5, 0x0 }, // 859 { PseudoVC_V_VV_SE_MF8, VC_V_VV, 0x5, 0x0 }, // 860 { PseudoVC_V_VV_MF4, VC_V_VV, 0x6, 0x0 }, // 861 { PseudoVC_V_VV_SE_MF4, VC_V_VV, 0x6, 0x0 }, // 862 { PseudoVC_V_VV_MF2, VC_V_VV, 0x7, 0x0 }, // 863 { PseudoVC_V_VV_SE_MF2, VC_V_VV, 0x7, 0x0 }, // 864 { PseudoVC_V_VVV_M1, VC_V_VVV, 0x0, 0x0 }, // 865 { PseudoVC_V_VVV_SE_M1, VC_V_VVV, 0x0, 0x0 }, // 866 { PseudoVC_V_VVV_M2, VC_V_VVV, 0x1, 0x0 }, // 867 { PseudoVC_V_VVV_SE_M2, VC_V_VVV, 0x1, 0x0 }, // 868 { PseudoVC_V_VVV_M4, VC_V_VVV, 0x2, 0x0 }, // 869 { PseudoVC_V_VVV_SE_M4, VC_V_VVV, 0x2, 0x0 }, // 870 { PseudoVC_V_VVV_M8, VC_V_VVV, 0x3, 0x0 }, // 871 { PseudoVC_V_VVV_SE_M8, VC_V_VVV, 0x3, 0x0 }, // 872 { PseudoVC_V_VVV_MF8, VC_V_VVV, 0x5, 0x0 }, // 873 { PseudoVC_V_VVV_SE_MF8, VC_V_VVV, 0x5, 0x0 }, // 874 { PseudoVC_V_VVV_MF4, VC_V_VVV, 0x6, 0x0 }, // 875 { PseudoVC_V_VVV_SE_MF4, VC_V_VVV, 0x6, 0x0 }, // 876 { PseudoVC_V_VVV_MF2, VC_V_VVV, 0x7, 0x0 }, // 877 { PseudoVC_V_VVV_SE_MF2, VC_V_VVV, 0x7, 0x0 }, // 878 { PseudoVC_V_VVW_M1, VC_V_VVW, 0x0, 0x0 }, // 879 { PseudoVC_V_VVW_SE_M1, VC_V_VVW, 0x0, 0x0 }, // 880 { PseudoVC_V_VVW_M2, VC_V_VVW, 0x1, 0x0 }, // 881 { PseudoVC_V_VVW_SE_M2, VC_V_VVW, 0x1, 0x0 }, // 882 { PseudoVC_V_VVW_M4, VC_V_VVW, 0x2, 0x0 }, // 883 { PseudoVC_V_VVW_SE_M4, VC_V_VVW, 0x2, 0x0 }, // 884 { PseudoVC_V_VVW_MF8, VC_V_VVW, 0x5, 0x0 }, // 885 { PseudoVC_V_VVW_SE_MF8, VC_V_VVW, 0x5, 0x0 }, // 886 { PseudoVC_V_VVW_MF4, VC_V_VVW, 0x6, 0x0 }, // 887 { PseudoVC_V_VVW_SE_MF4, VC_V_VVW, 0x6, 0x0 }, // 888 { PseudoVC_V_VVW_MF2, VC_V_VVW, 0x7, 0x0 }, // 889 { PseudoVC_V_VVW_SE_MF2, VC_V_VVW, 0x7, 0x0 }, // 890 { PseudoVC_V_X_M1, VC_V_X, 0x0, 0x0 }, // 891 { PseudoVC_V_X_SE_M1, VC_V_X, 0x0, 0x0 }, // 892 { PseudoVC_V_X_M2, VC_V_X, 0x1, 0x0 }, // 893 { PseudoVC_V_X_SE_M2, VC_V_X, 0x1, 0x0 }, // 894 { PseudoVC_V_X_M4, VC_V_X, 0x2, 0x0 }, // 895 { PseudoVC_V_X_SE_M4, VC_V_X, 0x2, 0x0 }, // 896 { PseudoVC_V_X_M8, VC_V_X, 0x3, 0x0 }, // 897 { PseudoVC_V_X_SE_M8, VC_V_X, 0x3, 0x0 }, // 898 { PseudoVC_V_X_MF8, VC_V_X, 0x5, 0x0 }, // 899 { PseudoVC_V_X_SE_MF8, VC_V_X, 0x5, 0x0 }, // 900 { PseudoVC_V_X_MF4, VC_V_X, 0x6, 0x0 }, // 901 { PseudoVC_V_X_SE_MF4, VC_V_X, 0x6, 0x0 }, // 902 { PseudoVC_V_X_MF2, VC_V_X, 0x7, 0x0 }, // 903 { PseudoVC_V_X_SE_MF2, VC_V_X, 0x7, 0x0 }, // 904 { PseudoVC_V_XV_M1, VC_V_XV, 0x0, 0x0 }, // 905 { PseudoVC_V_XV_SE_M1, VC_V_XV, 0x0, 0x0 }, // 906 { PseudoVC_V_XV_M2, VC_V_XV, 0x1, 0x0 }, // 907 { PseudoVC_V_XV_SE_M2, VC_V_XV, 0x1, 0x0 }, // 908 { PseudoVC_V_XV_M4, VC_V_XV, 0x2, 0x0 }, // 909 { PseudoVC_V_XV_SE_M4, VC_V_XV, 0x2, 0x0 }, // 910 { PseudoVC_V_XV_M8, VC_V_XV, 0x3, 0x0 }, // 911 { PseudoVC_V_XV_SE_M8, VC_V_XV, 0x3, 0x0 }, // 912 { PseudoVC_V_XV_MF8, VC_V_XV, 0x5, 0x0 }, // 913 { PseudoVC_V_XV_SE_MF8, VC_V_XV, 0x5, 0x0 }, // 914 { PseudoVC_V_XV_MF4, VC_V_XV, 0x6, 0x0 }, // 915 { PseudoVC_V_XV_SE_MF4, VC_V_XV, 0x6, 0x0 }, // 916 { PseudoVC_V_XV_MF2, VC_V_XV, 0x7, 0x0 }, // 917 { PseudoVC_V_XV_SE_MF2, VC_V_XV, 0x7, 0x0 }, // 918 { PseudoVC_V_XVV_M1, VC_V_XVV, 0x0, 0x0 }, // 919 { PseudoVC_V_XVV_SE_M1, VC_V_XVV, 0x0, 0x0 }, // 920 { PseudoVC_V_XVV_M2, VC_V_XVV, 0x1, 0x0 }, // 921 { PseudoVC_V_XVV_SE_M2, VC_V_XVV, 0x1, 0x0 }, // 922 { PseudoVC_V_XVV_M4, VC_V_XVV, 0x2, 0x0 }, // 923 { PseudoVC_V_XVV_SE_M4, VC_V_XVV, 0x2, 0x0 }, // 924 { PseudoVC_V_XVV_M8, VC_V_XVV, 0x3, 0x0 }, // 925 { PseudoVC_V_XVV_SE_M8, VC_V_XVV, 0x3, 0x0 }, // 926 { PseudoVC_V_XVV_MF8, VC_V_XVV, 0x5, 0x0 }, // 927 { PseudoVC_V_XVV_SE_MF8, VC_V_XVV, 0x5, 0x0 }, // 928 { PseudoVC_V_XVV_MF4, VC_V_XVV, 0x6, 0x0 }, // 929 { PseudoVC_V_XVV_SE_MF4, VC_V_XVV, 0x6, 0x0 }, // 930 { PseudoVC_V_XVV_MF2, VC_V_XVV, 0x7, 0x0 }, // 931 { PseudoVC_V_XVV_SE_MF2, VC_V_XVV, 0x7, 0x0 }, // 932 { PseudoVC_V_XVW_M1, VC_V_XVW, 0x0, 0x0 }, // 933 { PseudoVC_V_XVW_SE_M1, VC_V_XVW, 0x0, 0x0 }, // 934 { PseudoVC_V_XVW_M2, VC_V_XVW, 0x1, 0x0 }, // 935 { PseudoVC_V_XVW_SE_M2, VC_V_XVW, 0x1, 0x0 }, // 936 { PseudoVC_V_XVW_M4, VC_V_XVW, 0x2, 0x0 }, // 937 { PseudoVC_V_XVW_SE_M4, VC_V_XVW, 0x2, 0x0 }, // 938 { PseudoVC_V_XVW_MF8, VC_V_XVW, 0x5, 0x0 }, // 939 { PseudoVC_V_XVW_SE_MF8, VC_V_XVW, 0x5, 0x0 }, // 940 { PseudoVC_V_XVW_MF4, VC_V_XVW, 0x6, 0x0 }, // 941 { PseudoVC_V_XVW_SE_MF4, VC_V_XVW, 0x6, 0x0 }, // 942 { PseudoVC_V_XVW_MF2, VC_V_XVW, 0x7, 0x0 }, // 943 { PseudoVC_V_XVW_SE_MF2, VC_V_XVW, 0x7, 0x0 }, // 944 { PseudoVC_X_SE_M1, VC_X, 0x0, 0x0 }, // 945 { PseudoVC_X_SE_M2, VC_X, 0x1, 0x0 }, // 946 { PseudoVC_X_SE_M4, VC_X, 0x2, 0x0 }, // 947 { PseudoVC_X_SE_M8, VC_X, 0x3, 0x0 }, // 948 { PseudoVC_X_SE_MF8, VC_X, 0x5, 0x0 }, // 949 { PseudoVC_X_SE_MF4, VC_X, 0x6, 0x0 }, // 950 { PseudoVC_X_SE_MF2, VC_X, 0x7, 0x0 }, // 951 { PseudoVC_XV_SE_M1, VC_XV, 0x0, 0x0 }, // 952 { PseudoVC_XV_SE_M2, VC_XV, 0x1, 0x0 }, // 953 { PseudoVC_XV_SE_M4, VC_XV, 0x2, 0x0 }, // 954 { PseudoVC_XV_SE_M8, VC_XV, 0x3, 0x0 }, // 955 { PseudoVC_XV_SE_MF8, VC_XV, 0x5, 0x0 }, // 956 { PseudoVC_XV_SE_MF4, VC_XV, 0x6, 0x0 }, // 957 { PseudoVC_XV_SE_MF2, VC_XV, 0x7, 0x0 }, // 958 { PseudoVC_XVV_SE_M1, VC_XVV, 0x0, 0x0 }, // 959 { PseudoVC_XVV_SE_M2, VC_XVV, 0x1, 0x0 }, // 960 { PseudoVC_XVV_SE_M4, VC_XVV, 0x2, 0x0 }, // 961 { PseudoVC_XVV_SE_M8, VC_XVV, 0x3, 0x0 }, // 962 { PseudoVC_XVV_SE_MF8, VC_XVV, 0x5, 0x0 }, // 963 { PseudoVC_XVV_SE_MF4, VC_XVV, 0x6, 0x0 }, // 964 { PseudoVC_XVV_SE_MF2, VC_XVV, 0x7, 0x0 }, // 965 { PseudoVC_XVW_SE_M1, VC_XVW, 0x0, 0x0 }, // 966 { PseudoVC_XVW_SE_M2, VC_XVW, 0x1, 0x0 }, // 967 { PseudoVC_XVW_SE_M4, VC_XVW, 0x2, 0x0 }, // 968 { PseudoVC_XVW_SE_MF8, VC_XVW, 0x5, 0x0 }, // 969 { PseudoVC_XVW_SE_MF4, VC_XVW, 0x6, 0x0 }, // 970 { PseudoVC_XVW_SE_MF2, VC_XVW, 0x7, 0x0 }, // 971 { PseudoVDIVU_VV_M1_E8, VDIVU_VV, 0x0, 0x8 }, // 972 { PseudoVDIVU_VV_M1_E8_MASK, VDIVU_VV, 0x0, 0x8 }, // 973 { PseudoVDIVU_VV_M1_E16, VDIVU_VV, 0x0, 0x10 }, // 974 { PseudoVDIVU_VV_M1_E16_MASK, VDIVU_VV, 0x0, 0x10 }, // 975 { PseudoVDIVU_VV_M1_E32, VDIVU_VV, 0x0, 0x20 }, // 976 { PseudoVDIVU_VV_M1_E32_MASK, VDIVU_VV, 0x0, 0x20 }, // 977 { PseudoVDIVU_VV_M1_E64, VDIVU_VV, 0x0, 0x40 }, // 978 { PseudoVDIVU_VV_M1_E64_MASK, VDIVU_VV, 0x0, 0x40 }, // 979 { PseudoVDIVU_VV_M2_E8, VDIVU_VV, 0x1, 0x8 }, // 980 { PseudoVDIVU_VV_M2_E8_MASK, VDIVU_VV, 0x1, 0x8 }, // 981 { PseudoVDIVU_VV_M2_E16, VDIVU_VV, 0x1, 0x10 }, // 982 { PseudoVDIVU_VV_M2_E16_MASK, VDIVU_VV, 0x1, 0x10 }, // 983 { PseudoVDIVU_VV_M2_E32, VDIVU_VV, 0x1, 0x20 }, // 984 { PseudoVDIVU_VV_M2_E32_MASK, VDIVU_VV, 0x1, 0x20 }, // 985 { PseudoVDIVU_VV_M2_E64, VDIVU_VV, 0x1, 0x40 }, // 986 { PseudoVDIVU_VV_M2_E64_MASK, VDIVU_VV, 0x1, 0x40 }, // 987 { PseudoVDIVU_VV_M4_E8, VDIVU_VV, 0x2, 0x8 }, // 988 { PseudoVDIVU_VV_M4_E8_MASK, VDIVU_VV, 0x2, 0x8 }, // 989 { PseudoVDIVU_VV_M4_E16, VDIVU_VV, 0x2, 0x10 }, // 990 { PseudoVDIVU_VV_M4_E16_MASK, VDIVU_VV, 0x2, 0x10 }, // 991 { PseudoVDIVU_VV_M4_E32, VDIVU_VV, 0x2, 0x20 }, // 992 { PseudoVDIVU_VV_M4_E32_MASK, VDIVU_VV, 0x2, 0x20 }, // 993 { PseudoVDIVU_VV_M4_E64, VDIVU_VV, 0x2, 0x40 }, // 994 { PseudoVDIVU_VV_M4_E64_MASK, VDIVU_VV, 0x2, 0x40 }, // 995 { PseudoVDIVU_VV_M8_E8, VDIVU_VV, 0x3, 0x8 }, // 996 { PseudoVDIVU_VV_M8_E8_MASK, VDIVU_VV, 0x3, 0x8 }, // 997 { PseudoVDIVU_VV_M8_E16, VDIVU_VV, 0x3, 0x10 }, // 998 { PseudoVDIVU_VV_M8_E16_MASK, VDIVU_VV, 0x3, 0x10 }, // 999 { PseudoVDIVU_VV_M8_E32, VDIVU_VV, 0x3, 0x20 }, // 1000 { PseudoVDIVU_VV_M8_E32_MASK, VDIVU_VV, 0x3, 0x20 }, // 1001 { PseudoVDIVU_VV_M8_E64, VDIVU_VV, 0x3, 0x40 }, // 1002 { PseudoVDIVU_VV_M8_E64_MASK, VDIVU_VV, 0x3, 0x40 }, // 1003 { PseudoVDIVU_VV_MF8_E8, VDIVU_VV, 0x5, 0x8 }, // 1004 { PseudoVDIVU_VV_MF8_E8_MASK, VDIVU_VV, 0x5, 0x8 }, // 1005 { PseudoVDIVU_VV_MF4_E8, VDIVU_VV, 0x6, 0x8 }, // 1006 { PseudoVDIVU_VV_MF4_E8_MASK, VDIVU_VV, 0x6, 0x8 }, // 1007 { PseudoVDIVU_VV_MF4_E16, VDIVU_VV, 0x6, 0x10 }, // 1008 { PseudoVDIVU_VV_MF4_E16_MASK, VDIVU_VV, 0x6, 0x10 }, // 1009 { PseudoVDIVU_VV_MF2_E8, VDIVU_VV, 0x7, 0x8 }, // 1010 { PseudoVDIVU_VV_MF2_E8_MASK, VDIVU_VV, 0x7, 0x8 }, // 1011 { PseudoVDIVU_VV_MF2_E16, VDIVU_VV, 0x7, 0x10 }, // 1012 { PseudoVDIVU_VV_MF2_E16_MASK, VDIVU_VV, 0x7, 0x10 }, // 1013 { PseudoVDIVU_VV_MF2_E32, VDIVU_VV, 0x7, 0x20 }, // 1014 { PseudoVDIVU_VV_MF2_E32_MASK, VDIVU_VV, 0x7, 0x20 }, // 1015 { PseudoVDIVU_VX_M1_E8, VDIVU_VX, 0x0, 0x8 }, // 1016 { PseudoVDIVU_VX_M1_E8_MASK, VDIVU_VX, 0x0, 0x8 }, // 1017 { PseudoVDIVU_VX_M1_E16, VDIVU_VX, 0x0, 0x10 }, // 1018 { PseudoVDIVU_VX_M1_E16_MASK, VDIVU_VX, 0x0, 0x10 }, // 1019 { PseudoVDIVU_VX_M1_E32, VDIVU_VX, 0x0, 0x20 }, // 1020 { PseudoVDIVU_VX_M1_E32_MASK, VDIVU_VX, 0x0, 0x20 }, // 1021 { PseudoVDIVU_VX_M1_E64, VDIVU_VX, 0x0, 0x40 }, // 1022 { PseudoVDIVU_VX_M1_E64_MASK, VDIVU_VX, 0x0, 0x40 }, // 1023 { PseudoVDIVU_VX_M2_E8, VDIVU_VX, 0x1, 0x8 }, // 1024 { PseudoVDIVU_VX_M2_E8_MASK, VDIVU_VX, 0x1, 0x8 }, // 1025 { PseudoVDIVU_VX_M2_E16, VDIVU_VX, 0x1, 0x10 }, // 1026 { PseudoVDIVU_VX_M2_E16_MASK, VDIVU_VX, 0x1, 0x10 }, // 1027 { PseudoVDIVU_VX_M2_E32, VDIVU_VX, 0x1, 0x20 }, // 1028 { PseudoVDIVU_VX_M2_E32_MASK, VDIVU_VX, 0x1, 0x20 }, // 1029 { PseudoVDIVU_VX_M2_E64, VDIVU_VX, 0x1, 0x40 }, // 1030 { PseudoVDIVU_VX_M2_E64_MASK, VDIVU_VX, 0x1, 0x40 }, // 1031 { PseudoVDIVU_VX_M4_E8, VDIVU_VX, 0x2, 0x8 }, // 1032 { PseudoVDIVU_VX_M4_E8_MASK, VDIVU_VX, 0x2, 0x8 }, // 1033 { PseudoVDIVU_VX_M4_E16, VDIVU_VX, 0x2, 0x10 }, // 1034 { PseudoVDIVU_VX_M4_E16_MASK, VDIVU_VX, 0x2, 0x10 }, // 1035 { PseudoVDIVU_VX_M4_E32, VDIVU_VX, 0x2, 0x20 }, // 1036 { PseudoVDIVU_VX_M4_E32_MASK, VDIVU_VX, 0x2, 0x20 }, // 1037 { PseudoVDIVU_VX_M4_E64, VDIVU_VX, 0x2, 0x40 }, // 1038 { PseudoVDIVU_VX_M4_E64_MASK, VDIVU_VX, 0x2, 0x40 }, // 1039 { PseudoVDIVU_VX_M8_E8, VDIVU_VX, 0x3, 0x8 }, // 1040 { PseudoVDIVU_VX_M8_E8_MASK, VDIVU_VX, 0x3, 0x8 }, // 1041 { PseudoVDIVU_VX_M8_E16, VDIVU_VX, 0x3, 0x10 }, // 1042 { PseudoVDIVU_VX_M8_E16_MASK, VDIVU_VX, 0x3, 0x10 }, // 1043 { PseudoVDIVU_VX_M8_E32, VDIVU_VX, 0x3, 0x20 }, // 1044 { PseudoVDIVU_VX_M8_E32_MASK, VDIVU_VX, 0x3, 0x20 }, // 1045 { PseudoVDIVU_VX_M8_E64, VDIVU_VX, 0x3, 0x40 }, // 1046 { PseudoVDIVU_VX_M8_E64_MASK, VDIVU_VX, 0x3, 0x40 }, // 1047 { PseudoVDIVU_VX_MF8_E8, VDIVU_VX, 0x5, 0x8 }, // 1048 { PseudoVDIVU_VX_MF8_E8_MASK, VDIVU_VX, 0x5, 0x8 }, // 1049 { PseudoVDIVU_VX_MF4_E8, VDIVU_VX, 0x6, 0x8 }, // 1050 { PseudoVDIVU_VX_MF4_E8_MASK, VDIVU_VX, 0x6, 0x8 }, // 1051 { PseudoVDIVU_VX_MF4_E16, VDIVU_VX, 0x6, 0x10 }, // 1052 { PseudoVDIVU_VX_MF4_E16_MASK, VDIVU_VX, 0x6, 0x10 }, // 1053 { PseudoVDIVU_VX_MF2_E8, VDIVU_VX, 0x7, 0x8 }, // 1054 { PseudoVDIVU_VX_MF2_E8_MASK, VDIVU_VX, 0x7, 0x8 }, // 1055 { PseudoVDIVU_VX_MF2_E16, VDIVU_VX, 0x7, 0x10 }, // 1056 { PseudoVDIVU_VX_MF2_E16_MASK, VDIVU_VX, 0x7, 0x10 }, // 1057 { PseudoVDIVU_VX_MF2_E32, VDIVU_VX, 0x7, 0x20 }, // 1058 { PseudoVDIVU_VX_MF2_E32_MASK, VDIVU_VX, 0x7, 0x20 }, // 1059 { PseudoVDIV_VV_M1_E8, VDIV_VV, 0x0, 0x8 }, // 1060 { PseudoVDIV_VV_M1_E8_MASK, VDIV_VV, 0x0, 0x8 }, // 1061 { PseudoVDIV_VV_M1_E16, VDIV_VV, 0x0, 0x10 }, // 1062 { PseudoVDIV_VV_M1_E16_MASK, VDIV_VV, 0x0, 0x10 }, // 1063 { PseudoVDIV_VV_M1_E32, VDIV_VV, 0x0, 0x20 }, // 1064 { PseudoVDIV_VV_M1_E32_MASK, VDIV_VV, 0x0, 0x20 }, // 1065 { PseudoVDIV_VV_M1_E64, VDIV_VV, 0x0, 0x40 }, // 1066 { PseudoVDIV_VV_M1_E64_MASK, VDIV_VV, 0x0, 0x40 }, // 1067 { PseudoVDIV_VV_M2_E8, VDIV_VV, 0x1, 0x8 }, // 1068 { PseudoVDIV_VV_M2_E8_MASK, VDIV_VV, 0x1, 0x8 }, // 1069 { PseudoVDIV_VV_M2_E16, VDIV_VV, 0x1, 0x10 }, // 1070 { PseudoVDIV_VV_M2_E16_MASK, VDIV_VV, 0x1, 0x10 }, // 1071 { PseudoVDIV_VV_M2_E32, VDIV_VV, 0x1, 0x20 }, // 1072 { PseudoVDIV_VV_M2_E32_MASK, VDIV_VV, 0x1, 0x20 }, // 1073 { PseudoVDIV_VV_M2_E64, VDIV_VV, 0x1, 0x40 }, // 1074 { PseudoVDIV_VV_M2_E64_MASK, VDIV_VV, 0x1, 0x40 }, // 1075 { PseudoVDIV_VV_M4_E8, VDIV_VV, 0x2, 0x8 }, // 1076 { PseudoVDIV_VV_M4_E8_MASK, VDIV_VV, 0x2, 0x8 }, // 1077 { PseudoVDIV_VV_M4_E16, VDIV_VV, 0x2, 0x10 }, // 1078 { PseudoVDIV_VV_M4_E16_MASK, VDIV_VV, 0x2, 0x10 }, // 1079 { PseudoVDIV_VV_M4_E32, VDIV_VV, 0x2, 0x20 }, // 1080 { PseudoVDIV_VV_M4_E32_MASK, VDIV_VV, 0x2, 0x20 }, // 1081 { PseudoVDIV_VV_M4_E64, VDIV_VV, 0x2, 0x40 }, // 1082 { PseudoVDIV_VV_M4_E64_MASK, VDIV_VV, 0x2, 0x40 }, // 1083 { PseudoVDIV_VV_M8_E8, VDIV_VV, 0x3, 0x8 }, // 1084 { PseudoVDIV_VV_M8_E8_MASK, VDIV_VV, 0x3, 0x8 }, // 1085 { PseudoVDIV_VV_M8_E16, VDIV_VV, 0x3, 0x10 }, // 1086 { PseudoVDIV_VV_M8_E16_MASK, VDIV_VV, 0x3, 0x10 }, // 1087 { PseudoVDIV_VV_M8_E32, VDIV_VV, 0x3, 0x20 }, // 1088 { PseudoVDIV_VV_M8_E32_MASK, VDIV_VV, 0x3, 0x20 }, // 1089 { PseudoVDIV_VV_M8_E64, VDIV_VV, 0x3, 0x40 }, // 1090 { PseudoVDIV_VV_M8_E64_MASK, VDIV_VV, 0x3, 0x40 }, // 1091 { PseudoVDIV_VV_MF8_E8, VDIV_VV, 0x5, 0x8 }, // 1092 { PseudoVDIV_VV_MF8_E8_MASK, VDIV_VV, 0x5, 0x8 }, // 1093 { PseudoVDIV_VV_MF4_E8, VDIV_VV, 0x6, 0x8 }, // 1094 { PseudoVDIV_VV_MF4_E8_MASK, VDIV_VV, 0x6, 0x8 }, // 1095 { PseudoVDIV_VV_MF4_E16, VDIV_VV, 0x6, 0x10 }, // 1096 { PseudoVDIV_VV_MF4_E16_MASK, VDIV_VV, 0x6, 0x10 }, // 1097 { PseudoVDIV_VV_MF2_E8, VDIV_VV, 0x7, 0x8 }, // 1098 { PseudoVDIV_VV_MF2_E8_MASK, VDIV_VV, 0x7, 0x8 }, // 1099 { PseudoVDIV_VV_MF2_E16, VDIV_VV, 0x7, 0x10 }, // 1100 { PseudoVDIV_VV_MF2_E16_MASK, VDIV_VV, 0x7, 0x10 }, // 1101 { PseudoVDIV_VV_MF2_E32, VDIV_VV, 0x7, 0x20 }, // 1102 { PseudoVDIV_VV_MF2_E32_MASK, VDIV_VV, 0x7, 0x20 }, // 1103 { PseudoVDIV_VX_M1_E8, VDIV_VX, 0x0, 0x8 }, // 1104 { PseudoVDIV_VX_M1_E8_MASK, VDIV_VX, 0x0, 0x8 }, // 1105 { PseudoVDIV_VX_M1_E16, VDIV_VX, 0x0, 0x10 }, // 1106 { PseudoVDIV_VX_M1_E16_MASK, VDIV_VX, 0x0, 0x10 }, // 1107 { PseudoVDIV_VX_M1_E32, VDIV_VX, 0x0, 0x20 }, // 1108 { PseudoVDIV_VX_M1_E32_MASK, VDIV_VX, 0x0, 0x20 }, // 1109 { PseudoVDIV_VX_M1_E64, VDIV_VX, 0x0, 0x40 }, // 1110 { PseudoVDIV_VX_M1_E64_MASK, VDIV_VX, 0x0, 0x40 }, // 1111 { PseudoVDIV_VX_M2_E8, VDIV_VX, 0x1, 0x8 }, // 1112 { PseudoVDIV_VX_M2_E8_MASK, VDIV_VX, 0x1, 0x8 }, // 1113 { PseudoVDIV_VX_M2_E16, VDIV_VX, 0x1, 0x10 }, // 1114 { PseudoVDIV_VX_M2_E16_MASK, VDIV_VX, 0x1, 0x10 }, // 1115 { PseudoVDIV_VX_M2_E32, VDIV_VX, 0x1, 0x20 }, // 1116 { PseudoVDIV_VX_M2_E32_MASK, VDIV_VX, 0x1, 0x20 }, // 1117 { PseudoVDIV_VX_M2_E64, VDIV_VX, 0x1, 0x40 }, // 1118 { PseudoVDIV_VX_M2_E64_MASK, VDIV_VX, 0x1, 0x40 }, // 1119 { PseudoVDIV_VX_M4_E8, VDIV_VX, 0x2, 0x8 }, // 1120 { PseudoVDIV_VX_M4_E8_MASK, VDIV_VX, 0x2, 0x8 }, // 1121 { PseudoVDIV_VX_M4_E16, VDIV_VX, 0x2, 0x10 }, // 1122 { PseudoVDIV_VX_M4_E16_MASK, VDIV_VX, 0x2, 0x10 }, // 1123 { PseudoVDIV_VX_M4_E32, VDIV_VX, 0x2, 0x20 }, // 1124 { PseudoVDIV_VX_M4_E32_MASK, VDIV_VX, 0x2, 0x20 }, // 1125 { PseudoVDIV_VX_M4_E64, VDIV_VX, 0x2, 0x40 }, // 1126 { PseudoVDIV_VX_M4_E64_MASK, VDIV_VX, 0x2, 0x40 }, // 1127 { PseudoVDIV_VX_M8_E8, VDIV_VX, 0x3, 0x8 }, // 1128 { PseudoVDIV_VX_M8_E8_MASK, VDIV_VX, 0x3, 0x8 }, // 1129 { PseudoVDIV_VX_M8_E16, VDIV_VX, 0x3, 0x10 }, // 1130 { PseudoVDIV_VX_M8_E16_MASK, VDIV_VX, 0x3, 0x10 }, // 1131 { PseudoVDIV_VX_M8_E32, VDIV_VX, 0x3, 0x20 }, // 1132 { PseudoVDIV_VX_M8_E32_MASK, VDIV_VX, 0x3, 0x20 }, // 1133 { PseudoVDIV_VX_M8_E64, VDIV_VX, 0x3, 0x40 }, // 1134 { PseudoVDIV_VX_M8_E64_MASK, VDIV_VX, 0x3, 0x40 }, // 1135 { PseudoVDIV_VX_MF8_E8, VDIV_VX, 0x5, 0x8 }, // 1136 { PseudoVDIV_VX_MF8_E8_MASK, VDIV_VX, 0x5, 0x8 }, // 1137 { PseudoVDIV_VX_MF4_E8, VDIV_VX, 0x6, 0x8 }, // 1138 { PseudoVDIV_VX_MF4_E8_MASK, VDIV_VX, 0x6, 0x8 }, // 1139 { PseudoVDIV_VX_MF4_E16, VDIV_VX, 0x6, 0x10 }, // 1140 { PseudoVDIV_VX_MF4_E16_MASK, VDIV_VX, 0x6, 0x10 }, // 1141 { PseudoVDIV_VX_MF2_E8, VDIV_VX, 0x7, 0x8 }, // 1142 { PseudoVDIV_VX_MF2_E8_MASK, VDIV_VX, 0x7, 0x8 }, // 1143 { PseudoVDIV_VX_MF2_E16, VDIV_VX, 0x7, 0x10 }, // 1144 { PseudoVDIV_VX_MF2_E16_MASK, VDIV_VX, 0x7, 0x10 }, // 1145 { PseudoVDIV_VX_MF2_E32, VDIV_VX, 0x7, 0x20 }, // 1146 { PseudoVDIV_VX_MF2_E32_MASK, VDIV_VX, 0x7, 0x20 }, // 1147 { PseudoVFADD_VFPR16_M1_E16, VFADD_VF, 0x0, 0x10 }, // 1148 { PseudoVFADD_VFPR16_M1_E16_MASK, VFADD_VF, 0x0, 0x10 }, // 1149 { PseudoVFADD_VFPR32_M1_E32, VFADD_VF, 0x0, 0x20 }, // 1150 { PseudoVFADD_VFPR32_M1_E32_MASK, VFADD_VF, 0x0, 0x20 }, // 1151 { PseudoVFADD_VFPR64_M1_E64, VFADD_VF, 0x0, 0x40 }, // 1152 { PseudoVFADD_VFPR64_M1_E64_MASK, VFADD_VF, 0x0, 0x40 }, // 1153 { PseudoVFADD_VFPR16_M2_E16, VFADD_VF, 0x1, 0x10 }, // 1154 { PseudoVFADD_VFPR16_M2_E16_MASK, VFADD_VF, 0x1, 0x10 }, // 1155 { PseudoVFADD_VFPR32_M2_E32, VFADD_VF, 0x1, 0x20 }, // 1156 { PseudoVFADD_VFPR32_M2_E32_MASK, VFADD_VF, 0x1, 0x20 }, // 1157 { PseudoVFADD_VFPR64_M2_E64, VFADD_VF, 0x1, 0x40 }, // 1158 { PseudoVFADD_VFPR64_M2_E64_MASK, VFADD_VF, 0x1, 0x40 }, // 1159 { PseudoVFADD_VFPR16_M4_E16, VFADD_VF, 0x2, 0x10 }, // 1160 { PseudoVFADD_VFPR16_M4_E16_MASK, VFADD_VF, 0x2, 0x10 }, // 1161 { PseudoVFADD_VFPR32_M4_E32, VFADD_VF, 0x2, 0x20 }, // 1162 { PseudoVFADD_VFPR32_M4_E32_MASK, VFADD_VF, 0x2, 0x20 }, // 1163 { PseudoVFADD_VFPR64_M4_E64, VFADD_VF, 0x2, 0x40 }, // 1164 { PseudoVFADD_VFPR64_M4_E64_MASK, VFADD_VF, 0x2, 0x40 }, // 1165 { PseudoVFADD_VFPR16_M8_E16, VFADD_VF, 0x3, 0x10 }, // 1166 { PseudoVFADD_VFPR16_M8_E16_MASK, VFADD_VF, 0x3, 0x10 }, // 1167 { PseudoVFADD_VFPR32_M8_E32, VFADD_VF, 0x3, 0x20 }, // 1168 { PseudoVFADD_VFPR32_M8_E32_MASK, VFADD_VF, 0x3, 0x20 }, // 1169 { PseudoVFADD_VFPR64_M8_E64, VFADD_VF, 0x3, 0x40 }, // 1170 { PseudoVFADD_VFPR64_M8_E64_MASK, VFADD_VF, 0x3, 0x40 }, // 1171 { PseudoVFADD_VFPR16_MF4_E16, VFADD_VF, 0x6, 0x10 }, // 1172 { PseudoVFADD_VFPR16_MF4_E16_MASK, VFADD_VF, 0x6, 0x10 }, // 1173 { PseudoVFADD_VFPR16_MF2_E16, VFADD_VF, 0x7, 0x10 }, // 1174 { PseudoVFADD_VFPR16_MF2_E16_MASK, VFADD_VF, 0x7, 0x10 }, // 1175 { PseudoVFADD_VFPR32_MF2_E32, VFADD_VF, 0x7, 0x20 }, // 1176 { PseudoVFADD_VFPR32_MF2_E32_MASK, VFADD_VF, 0x7, 0x20 }, // 1177 { PseudoVFADD_VV_M1_E16, VFADD_VV, 0x0, 0x10 }, // 1178 { PseudoVFADD_VV_M1_E16_MASK, VFADD_VV, 0x0, 0x10 }, // 1179 { PseudoVFADD_VV_M1_E32, VFADD_VV, 0x0, 0x20 }, // 1180 { PseudoVFADD_VV_M1_E32_MASK, VFADD_VV, 0x0, 0x20 }, // 1181 { PseudoVFADD_VV_M1_E64, VFADD_VV, 0x0, 0x40 }, // 1182 { PseudoVFADD_VV_M1_E64_MASK, VFADD_VV, 0x0, 0x40 }, // 1183 { PseudoVFADD_VV_M2_E16, VFADD_VV, 0x1, 0x10 }, // 1184 { PseudoVFADD_VV_M2_E16_MASK, VFADD_VV, 0x1, 0x10 }, // 1185 { PseudoVFADD_VV_M2_E32, VFADD_VV, 0x1, 0x20 }, // 1186 { PseudoVFADD_VV_M2_E32_MASK, VFADD_VV, 0x1, 0x20 }, // 1187 { PseudoVFADD_VV_M2_E64, VFADD_VV, 0x1, 0x40 }, // 1188 { PseudoVFADD_VV_M2_E64_MASK, VFADD_VV, 0x1, 0x40 }, // 1189 { PseudoVFADD_VV_M4_E16, VFADD_VV, 0x2, 0x10 }, // 1190 { PseudoVFADD_VV_M4_E16_MASK, VFADD_VV, 0x2, 0x10 }, // 1191 { PseudoVFADD_VV_M4_E32, VFADD_VV, 0x2, 0x20 }, // 1192 { PseudoVFADD_VV_M4_E32_MASK, VFADD_VV, 0x2, 0x20 }, // 1193 { PseudoVFADD_VV_M4_E64, VFADD_VV, 0x2, 0x40 }, // 1194 { PseudoVFADD_VV_M4_E64_MASK, VFADD_VV, 0x2, 0x40 }, // 1195 { PseudoVFADD_VV_M8_E16, VFADD_VV, 0x3, 0x10 }, // 1196 { PseudoVFADD_VV_M8_E16_MASK, VFADD_VV, 0x3, 0x10 }, // 1197 { PseudoVFADD_VV_M8_E32, VFADD_VV, 0x3, 0x20 }, // 1198 { PseudoVFADD_VV_M8_E32_MASK, VFADD_VV, 0x3, 0x20 }, // 1199 { PseudoVFADD_VV_M8_E64, VFADD_VV, 0x3, 0x40 }, // 1200 { PseudoVFADD_VV_M8_E64_MASK, VFADD_VV, 0x3, 0x40 }, // 1201 { PseudoVFADD_VV_MF4_E16, VFADD_VV, 0x6, 0x10 }, // 1202 { PseudoVFADD_VV_MF4_E16_MASK, VFADD_VV, 0x6, 0x10 }, // 1203 { PseudoVFADD_VV_MF2_E16, VFADD_VV, 0x7, 0x10 }, // 1204 { PseudoVFADD_VV_MF2_E16_MASK, VFADD_VV, 0x7, 0x10 }, // 1205 { PseudoVFADD_VV_MF2_E32, VFADD_VV, 0x7, 0x20 }, // 1206 { PseudoVFADD_VV_MF2_E32_MASK, VFADD_VV, 0x7, 0x20 }, // 1207 { PseudoVFCLASS_V_M1, VFCLASS_V, 0x0, 0x0 }, // 1208 { PseudoVFCLASS_V_M1_MASK, VFCLASS_V, 0x0, 0x0 }, // 1209 { PseudoVFCLASS_V_M2, VFCLASS_V, 0x1, 0x0 }, // 1210 { PseudoVFCLASS_V_M2_MASK, VFCLASS_V, 0x1, 0x0 }, // 1211 { PseudoVFCLASS_V_M4, VFCLASS_V, 0x2, 0x0 }, // 1212 { PseudoVFCLASS_V_M4_MASK, VFCLASS_V, 0x2, 0x0 }, // 1213 { PseudoVFCLASS_V_M8, VFCLASS_V, 0x3, 0x0 }, // 1214 { PseudoVFCLASS_V_M8_MASK, VFCLASS_V, 0x3, 0x0 }, // 1215 { PseudoVFCLASS_V_MF4, VFCLASS_V, 0x6, 0x0 }, // 1216 { PseudoVFCLASS_V_MF4_MASK, VFCLASS_V, 0x6, 0x0 }, // 1217 { PseudoVFCLASS_V_MF2, VFCLASS_V, 0x7, 0x0 }, // 1218 { PseudoVFCLASS_V_MF2_MASK, VFCLASS_V, 0x7, 0x0 }, // 1219 { PseudoVFCVT_F_XU_V_M1_E16, VFCVT_F_XU_V, 0x0, 0x10 }, // 1220 { PseudoVFCVT_F_XU_V_M1_E16_MASK, VFCVT_F_XU_V, 0x0, 0x10 }, // 1221 { PseudoVFCVT_RM_F_XU_V_M1_E16, VFCVT_F_XU_V, 0x0, 0x10 }, // 1222 { PseudoVFCVT_RM_F_XU_V_M1_E16_MASK, VFCVT_F_XU_V, 0x0, 0x10 }, // 1223 { PseudoVFCVT_F_XU_V_M1_E32, VFCVT_F_XU_V, 0x0, 0x20 }, // 1224 { PseudoVFCVT_F_XU_V_M1_E32_MASK, VFCVT_F_XU_V, 0x0, 0x20 }, // 1225 { PseudoVFCVT_RM_F_XU_V_M1_E32, VFCVT_F_XU_V, 0x0, 0x20 }, // 1226 { PseudoVFCVT_RM_F_XU_V_M1_E32_MASK, VFCVT_F_XU_V, 0x0, 0x20 }, // 1227 { PseudoVFCVT_F_XU_V_M1_E64, VFCVT_F_XU_V, 0x0, 0x40 }, // 1228 { PseudoVFCVT_F_XU_V_M1_E64_MASK, VFCVT_F_XU_V, 0x0, 0x40 }, // 1229 { PseudoVFCVT_RM_F_XU_V_M1_E64, VFCVT_F_XU_V, 0x0, 0x40 }, // 1230 { PseudoVFCVT_RM_F_XU_V_M1_E64_MASK, VFCVT_F_XU_V, 0x0, 0x40 }, // 1231 { PseudoVFCVT_F_XU_V_M2_E16, VFCVT_F_XU_V, 0x1, 0x10 }, // 1232 { PseudoVFCVT_F_XU_V_M2_E16_MASK, VFCVT_F_XU_V, 0x1, 0x10 }, // 1233 { PseudoVFCVT_RM_F_XU_V_M2_E16, VFCVT_F_XU_V, 0x1, 0x10 }, // 1234 { PseudoVFCVT_RM_F_XU_V_M2_E16_MASK, VFCVT_F_XU_V, 0x1, 0x10 }, // 1235 { PseudoVFCVT_F_XU_V_M2_E32, VFCVT_F_XU_V, 0x1, 0x20 }, // 1236 { PseudoVFCVT_F_XU_V_M2_E32_MASK, VFCVT_F_XU_V, 0x1, 0x20 }, // 1237 { PseudoVFCVT_RM_F_XU_V_M2_E32, VFCVT_F_XU_V, 0x1, 0x20 }, // 1238 { PseudoVFCVT_RM_F_XU_V_M2_E32_MASK, VFCVT_F_XU_V, 0x1, 0x20 }, // 1239 { PseudoVFCVT_F_XU_V_M2_E64, VFCVT_F_XU_V, 0x1, 0x40 }, // 1240 { PseudoVFCVT_F_XU_V_M2_E64_MASK, VFCVT_F_XU_V, 0x1, 0x40 }, // 1241 { PseudoVFCVT_RM_F_XU_V_M2_E64, VFCVT_F_XU_V, 0x1, 0x40 }, // 1242 { PseudoVFCVT_RM_F_XU_V_M2_E64_MASK, VFCVT_F_XU_V, 0x1, 0x40 }, // 1243 { PseudoVFCVT_F_XU_V_M4_E16, VFCVT_F_XU_V, 0x2, 0x10 }, // 1244 { PseudoVFCVT_F_XU_V_M4_E16_MASK, VFCVT_F_XU_V, 0x2, 0x10 }, // 1245 { PseudoVFCVT_RM_F_XU_V_M4_E16, VFCVT_F_XU_V, 0x2, 0x10 }, // 1246 { PseudoVFCVT_RM_F_XU_V_M4_E16_MASK, VFCVT_F_XU_V, 0x2, 0x10 }, // 1247 { PseudoVFCVT_F_XU_V_M4_E32, VFCVT_F_XU_V, 0x2, 0x20 }, // 1248 { PseudoVFCVT_F_XU_V_M4_E32_MASK, VFCVT_F_XU_V, 0x2, 0x20 }, // 1249 { PseudoVFCVT_RM_F_XU_V_M4_E32, VFCVT_F_XU_V, 0x2, 0x20 }, // 1250 { PseudoVFCVT_RM_F_XU_V_M4_E32_MASK, VFCVT_F_XU_V, 0x2, 0x20 }, // 1251 { PseudoVFCVT_F_XU_V_M4_E64, VFCVT_F_XU_V, 0x2, 0x40 }, // 1252 { PseudoVFCVT_F_XU_V_M4_E64_MASK, VFCVT_F_XU_V, 0x2, 0x40 }, // 1253 { PseudoVFCVT_RM_F_XU_V_M4_E64, VFCVT_F_XU_V, 0x2, 0x40 }, // 1254 { PseudoVFCVT_RM_F_XU_V_M4_E64_MASK, VFCVT_F_XU_V, 0x2, 0x40 }, // 1255 { PseudoVFCVT_F_XU_V_M8_E16, VFCVT_F_XU_V, 0x3, 0x10 }, // 1256 { PseudoVFCVT_F_XU_V_M8_E16_MASK, VFCVT_F_XU_V, 0x3, 0x10 }, // 1257 { PseudoVFCVT_RM_F_XU_V_M8_E16, VFCVT_F_XU_V, 0x3, 0x10 }, // 1258 { PseudoVFCVT_RM_F_XU_V_M8_E16_MASK, VFCVT_F_XU_V, 0x3, 0x10 }, // 1259 { PseudoVFCVT_F_XU_V_M8_E32, VFCVT_F_XU_V, 0x3, 0x20 }, // 1260 { PseudoVFCVT_F_XU_V_M8_E32_MASK, VFCVT_F_XU_V, 0x3, 0x20 }, // 1261 { PseudoVFCVT_RM_F_XU_V_M8_E32, VFCVT_F_XU_V, 0x3, 0x20 }, // 1262 { PseudoVFCVT_RM_F_XU_V_M8_E32_MASK, VFCVT_F_XU_V, 0x3, 0x20 }, // 1263 { PseudoVFCVT_F_XU_V_M8_E64, VFCVT_F_XU_V, 0x3, 0x40 }, // 1264 { PseudoVFCVT_F_XU_V_M8_E64_MASK, VFCVT_F_XU_V, 0x3, 0x40 }, // 1265 { PseudoVFCVT_RM_F_XU_V_M8_E64, VFCVT_F_XU_V, 0x3, 0x40 }, // 1266 { PseudoVFCVT_RM_F_XU_V_M8_E64_MASK, VFCVT_F_XU_V, 0x3, 0x40 }, // 1267 { PseudoVFCVT_F_XU_V_MF4_E16, VFCVT_F_XU_V, 0x6, 0x10 }, // 1268 { PseudoVFCVT_F_XU_V_MF4_E16_MASK, VFCVT_F_XU_V, 0x6, 0x10 }, // 1269 { PseudoVFCVT_RM_F_XU_V_MF4_E16, VFCVT_F_XU_V, 0x6, 0x10 }, // 1270 { PseudoVFCVT_RM_F_XU_V_MF4_E16_MASK, VFCVT_F_XU_V, 0x6, 0x10 }, // 1271 { PseudoVFCVT_F_XU_V_MF2_E16, VFCVT_F_XU_V, 0x7, 0x10 }, // 1272 { PseudoVFCVT_F_XU_V_MF2_E16_MASK, VFCVT_F_XU_V, 0x7, 0x10 }, // 1273 { PseudoVFCVT_RM_F_XU_V_MF2_E16, VFCVT_F_XU_V, 0x7, 0x10 }, // 1274 { PseudoVFCVT_RM_F_XU_V_MF2_E16_MASK, VFCVT_F_XU_V, 0x7, 0x10 }, // 1275 { PseudoVFCVT_F_XU_V_MF2_E32, VFCVT_F_XU_V, 0x7, 0x20 }, // 1276 { PseudoVFCVT_F_XU_V_MF2_E32_MASK, VFCVT_F_XU_V, 0x7, 0x20 }, // 1277 { PseudoVFCVT_RM_F_XU_V_MF2_E32, VFCVT_F_XU_V, 0x7, 0x20 }, // 1278 { PseudoVFCVT_RM_F_XU_V_MF2_E32_MASK, VFCVT_F_XU_V, 0x7, 0x20 }, // 1279 { PseudoVFCVT_F_X_V_M1_E16, VFCVT_F_X_V, 0x0, 0x10 }, // 1280 { PseudoVFCVT_F_X_V_M1_E16_MASK, VFCVT_F_X_V, 0x0, 0x10 }, // 1281 { PseudoVFCVT_RM_F_X_V_M1_E16, VFCVT_F_X_V, 0x0, 0x10 }, // 1282 { PseudoVFCVT_RM_F_X_V_M1_E16_MASK, VFCVT_F_X_V, 0x0, 0x10 }, // 1283 { PseudoVFCVT_F_X_V_M1_E32, VFCVT_F_X_V, 0x0, 0x20 }, // 1284 { PseudoVFCVT_F_X_V_M1_E32_MASK, VFCVT_F_X_V, 0x0, 0x20 }, // 1285 { PseudoVFCVT_RM_F_X_V_M1_E32, VFCVT_F_X_V, 0x0, 0x20 }, // 1286 { PseudoVFCVT_RM_F_X_V_M1_E32_MASK, VFCVT_F_X_V, 0x0, 0x20 }, // 1287 { PseudoVFCVT_F_X_V_M1_E64, VFCVT_F_X_V, 0x0, 0x40 }, // 1288 { PseudoVFCVT_F_X_V_M1_E64_MASK, VFCVT_F_X_V, 0x0, 0x40 }, // 1289 { PseudoVFCVT_RM_F_X_V_M1_E64, VFCVT_F_X_V, 0x0, 0x40 }, // 1290 { PseudoVFCVT_RM_F_X_V_M1_E64_MASK, VFCVT_F_X_V, 0x0, 0x40 }, // 1291 { PseudoVFCVT_F_X_V_M2_E16, VFCVT_F_X_V, 0x1, 0x10 }, // 1292 { PseudoVFCVT_F_X_V_M2_E16_MASK, VFCVT_F_X_V, 0x1, 0x10 }, // 1293 { PseudoVFCVT_RM_F_X_V_M2_E16, VFCVT_F_X_V, 0x1, 0x10 }, // 1294 { PseudoVFCVT_RM_F_X_V_M2_E16_MASK, VFCVT_F_X_V, 0x1, 0x10 }, // 1295 { PseudoVFCVT_F_X_V_M2_E32, VFCVT_F_X_V, 0x1, 0x20 }, // 1296 { PseudoVFCVT_F_X_V_M2_E32_MASK, VFCVT_F_X_V, 0x1, 0x20 }, // 1297 { PseudoVFCVT_RM_F_X_V_M2_E32, VFCVT_F_X_V, 0x1, 0x20 }, // 1298 { PseudoVFCVT_RM_F_X_V_M2_E32_MASK, VFCVT_F_X_V, 0x1, 0x20 }, // 1299 { PseudoVFCVT_F_X_V_M2_E64, VFCVT_F_X_V, 0x1, 0x40 }, // 1300 { PseudoVFCVT_F_X_V_M2_E64_MASK, VFCVT_F_X_V, 0x1, 0x40 }, // 1301 { PseudoVFCVT_RM_F_X_V_M2_E64, VFCVT_F_X_V, 0x1, 0x40 }, // 1302 { PseudoVFCVT_RM_F_X_V_M2_E64_MASK, VFCVT_F_X_V, 0x1, 0x40 }, // 1303 { PseudoVFCVT_F_X_V_M4_E16, VFCVT_F_X_V, 0x2, 0x10 }, // 1304 { PseudoVFCVT_F_X_V_M4_E16_MASK, VFCVT_F_X_V, 0x2, 0x10 }, // 1305 { PseudoVFCVT_RM_F_X_V_M4_E16, VFCVT_F_X_V, 0x2, 0x10 }, // 1306 { PseudoVFCVT_RM_F_X_V_M4_E16_MASK, VFCVT_F_X_V, 0x2, 0x10 }, // 1307 { PseudoVFCVT_F_X_V_M4_E32, VFCVT_F_X_V, 0x2, 0x20 }, // 1308 { PseudoVFCVT_F_X_V_M4_E32_MASK, VFCVT_F_X_V, 0x2, 0x20 }, // 1309 { PseudoVFCVT_RM_F_X_V_M4_E32, VFCVT_F_X_V, 0x2, 0x20 }, // 1310 { PseudoVFCVT_RM_F_X_V_M4_E32_MASK, VFCVT_F_X_V, 0x2, 0x20 }, // 1311 { PseudoVFCVT_F_X_V_M4_E64, VFCVT_F_X_V, 0x2, 0x40 }, // 1312 { PseudoVFCVT_F_X_V_M4_E64_MASK, VFCVT_F_X_V, 0x2, 0x40 }, // 1313 { PseudoVFCVT_RM_F_X_V_M4_E64, VFCVT_F_X_V, 0x2, 0x40 }, // 1314 { PseudoVFCVT_RM_F_X_V_M4_E64_MASK, VFCVT_F_X_V, 0x2, 0x40 }, // 1315 { PseudoVFCVT_F_X_V_M8_E16, VFCVT_F_X_V, 0x3, 0x10 }, // 1316 { PseudoVFCVT_F_X_V_M8_E16_MASK, VFCVT_F_X_V, 0x3, 0x10 }, // 1317 { PseudoVFCVT_RM_F_X_V_M8_E16, VFCVT_F_X_V, 0x3, 0x10 }, // 1318 { PseudoVFCVT_RM_F_X_V_M8_E16_MASK, VFCVT_F_X_V, 0x3, 0x10 }, // 1319 { PseudoVFCVT_F_X_V_M8_E32, VFCVT_F_X_V, 0x3, 0x20 }, // 1320 { PseudoVFCVT_F_X_V_M8_E32_MASK, VFCVT_F_X_V, 0x3, 0x20 }, // 1321 { PseudoVFCVT_RM_F_X_V_M8_E32, VFCVT_F_X_V, 0x3, 0x20 }, // 1322 { PseudoVFCVT_RM_F_X_V_M8_E32_MASK, VFCVT_F_X_V, 0x3, 0x20 }, // 1323 { PseudoVFCVT_F_X_V_M8_E64, VFCVT_F_X_V, 0x3, 0x40 }, // 1324 { PseudoVFCVT_F_X_V_M8_E64_MASK, VFCVT_F_X_V, 0x3, 0x40 }, // 1325 { PseudoVFCVT_RM_F_X_V_M8_E64, VFCVT_F_X_V, 0x3, 0x40 }, // 1326 { PseudoVFCVT_RM_F_X_V_M8_E64_MASK, VFCVT_F_X_V, 0x3, 0x40 }, // 1327 { PseudoVFCVT_F_X_V_MF4_E16, VFCVT_F_X_V, 0x6, 0x10 }, // 1328 { PseudoVFCVT_F_X_V_MF4_E16_MASK, VFCVT_F_X_V, 0x6, 0x10 }, // 1329 { PseudoVFCVT_RM_F_X_V_MF4_E16, VFCVT_F_X_V, 0x6, 0x10 }, // 1330 { PseudoVFCVT_RM_F_X_V_MF4_E16_MASK, VFCVT_F_X_V, 0x6, 0x10 }, // 1331 { PseudoVFCVT_F_X_V_MF2_E16, VFCVT_F_X_V, 0x7, 0x10 }, // 1332 { PseudoVFCVT_F_X_V_MF2_E16_MASK, VFCVT_F_X_V, 0x7, 0x10 }, // 1333 { PseudoVFCVT_RM_F_X_V_MF2_E16, VFCVT_F_X_V, 0x7, 0x10 }, // 1334 { PseudoVFCVT_RM_F_X_V_MF2_E16_MASK, VFCVT_F_X_V, 0x7, 0x10 }, // 1335 { PseudoVFCVT_F_X_V_MF2_E32, VFCVT_F_X_V, 0x7, 0x20 }, // 1336 { PseudoVFCVT_F_X_V_MF2_E32_MASK, VFCVT_F_X_V, 0x7, 0x20 }, // 1337 { PseudoVFCVT_RM_F_X_V_MF2_E32, VFCVT_F_X_V, 0x7, 0x20 }, // 1338 { PseudoVFCVT_RM_F_X_V_MF2_E32_MASK, VFCVT_F_X_V, 0x7, 0x20 }, // 1339 { PseudoVFCVT_RTZ_XU_F_V_M1, VFCVT_RTZ_XU_F_V, 0x0, 0x0 }, // 1340 { PseudoVFCVT_RTZ_XU_F_V_M1_MASK, VFCVT_RTZ_XU_F_V, 0x0, 0x0 }, // 1341 { PseudoVFCVT_RTZ_XU_F_V_M2, VFCVT_RTZ_XU_F_V, 0x1, 0x0 }, // 1342 { PseudoVFCVT_RTZ_XU_F_V_M2_MASK, VFCVT_RTZ_XU_F_V, 0x1, 0x0 }, // 1343 { PseudoVFCVT_RTZ_XU_F_V_M4, VFCVT_RTZ_XU_F_V, 0x2, 0x0 }, // 1344 { PseudoVFCVT_RTZ_XU_F_V_M4_MASK, VFCVT_RTZ_XU_F_V, 0x2, 0x0 }, // 1345 { PseudoVFCVT_RTZ_XU_F_V_M8, VFCVT_RTZ_XU_F_V, 0x3, 0x0 }, // 1346 { PseudoVFCVT_RTZ_XU_F_V_M8_MASK, VFCVT_RTZ_XU_F_V, 0x3, 0x0 }, // 1347 { PseudoVFCVT_RTZ_XU_F_V_MF4, VFCVT_RTZ_XU_F_V, 0x6, 0x0 }, // 1348 { PseudoVFCVT_RTZ_XU_F_V_MF4_MASK, VFCVT_RTZ_XU_F_V, 0x6, 0x0 }, // 1349 { PseudoVFCVT_RTZ_XU_F_V_MF2, VFCVT_RTZ_XU_F_V, 0x7, 0x0 }, // 1350 { PseudoVFCVT_RTZ_XU_F_V_MF2_MASK, VFCVT_RTZ_XU_F_V, 0x7, 0x0 }, // 1351 { PseudoVFCVT_RTZ_X_F_V_M1, VFCVT_RTZ_X_F_V, 0x0, 0x0 }, // 1352 { PseudoVFCVT_RTZ_X_F_V_M1_MASK, VFCVT_RTZ_X_F_V, 0x0, 0x0 }, // 1353 { PseudoVFCVT_RTZ_X_F_V_M2, VFCVT_RTZ_X_F_V, 0x1, 0x0 }, // 1354 { PseudoVFCVT_RTZ_X_F_V_M2_MASK, VFCVT_RTZ_X_F_V, 0x1, 0x0 }, // 1355 { PseudoVFCVT_RTZ_X_F_V_M4, VFCVT_RTZ_X_F_V, 0x2, 0x0 }, // 1356 { PseudoVFCVT_RTZ_X_F_V_M4_MASK, VFCVT_RTZ_X_F_V, 0x2, 0x0 }, // 1357 { PseudoVFCVT_RTZ_X_F_V_M8, VFCVT_RTZ_X_F_V, 0x3, 0x0 }, // 1358 { PseudoVFCVT_RTZ_X_F_V_M8_MASK, VFCVT_RTZ_X_F_V, 0x3, 0x0 }, // 1359 { PseudoVFCVT_RTZ_X_F_V_MF4, VFCVT_RTZ_X_F_V, 0x6, 0x0 }, // 1360 { PseudoVFCVT_RTZ_X_F_V_MF4_MASK, VFCVT_RTZ_X_F_V, 0x6, 0x0 }, // 1361 { PseudoVFCVT_RTZ_X_F_V_MF2, VFCVT_RTZ_X_F_V, 0x7, 0x0 }, // 1362 { PseudoVFCVT_RTZ_X_F_V_MF2_MASK, VFCVT_RTZ_X_F_V, 0x7, 0x0 }, // 1363 { PseudoVFCVT_RM_XU_F_V_M1, VFCVT_XU_F_V, 0x0, 0x0 }, // 1364 { PseudoVFCVT_RM_XU_F_V_M1_MASK, VFCVT_XU_F_V, 0x0, 0x0 }, // 1365 { PseudoVFCVT_XU_F_V_M1, VFCVT_XU_F_V, 0x0, 0x0 }, // 1366 { PseudoVFCVT_XU_F_V_M1_MASK, VFCVT_XU_F_V, 0x0, 0x0 }, // 1367 { PseudoVFCVT_RM_XU_F_V_M2, VFCVT_XU_F_V, 0x1, 0x0 }, // 1368 { PseudoVFCVT_RM_XU_F_V_M2_MASK, VFCVT_XU_F_V, 0x1, 0x0 }, // 1369 { PseudoVFCVT_XU_F_V_M2, VFCVT_XU_F_V, 0x1, 0x0 }, // 1370 { PseudoVFCVT_XU_F_V_M2_MASK, VFCVT_XU_F_V, 0x1, 0x0 }, // 1371 { PseudoVFCVT_RM_XU_F_V_M4, VFCVT_XU_F_V, 0x2, 0x0 }, // 1372 { PseudoVFCVT_RM_XU_F_V_M4_MASK, VFCVT_XU_F_V, 0x2, 0x0 }, // 1373 { PseudoVFCVT_XU_F_V_M4, VFCVT_XU_F_V, 0x2, 0x0 }, // 1374 { PseudoVFCVT_XU_F_V_M4_MASK, VFCVT_XU_F_V, 0x2, 0x0 }, // 1375 { PseudoVFCVT_RM_XU_F_V_M8, VFCVT_XU_F_V, 0x3, 0x0 }, // 1376 { PseudoVFCVT_RM_XU_F_V_M8_MASK, VFCVT_XU_F_V, 0x3, 0x0 }, // 1377 { PseudoVFCVT_XU_F_V_M8, VFCVT_XU_F_V, 0x3, 0x0 }, // 1378 { PseudoVFCVT_XU_F_V_M8_MASK, VFCVT_XU_F_V, 0x3, 0x0 }, // 1379 { PseudoVFCVT_RM_XU_F_V_MF4, VFCVT_XU_F_V, 0x6, 0x0 }, // 1380 { PseudoVFCVT_RM_XU_F_V_MF4_MASK, VFCVT_XU_F_V, 0x6, 0x0 }, // 1381 { PseudoVFCVT_XU_F_V_MF4, VFCVT_XU_F_V, 0x6, 0x0 }, // 1382 { PseudoVFCVT_XU_F_V_MF4_MASK, VFCVT_XU_F_V, 0x6, 0x0 }, // 1383 { PseudoVFCVT_RM_XU_F_V_MF2, VFCVT_XU_F_V, 0x7, 0x0 }, // 1384 { PseudoVFCVT_RM_XU_F_V_MF2_MASK, VFCVT_XU_F_V, 0x7, 0x0 }, // 1385 { PseudoVFCVT_XU_F_V_MF2, VFCVT_XU_F_V, 0x7, 0x0 }, // 1386 { PseudoVFCVT_XU_F_V_MF2_MASK, VFCVT_XU_F_V, 0x7, 0x0 }, // 1387 { PseudoVFCVT_RM_X_F_V_M1, VFCVT_X_F_V, 0x0, 0x0 }, // 1388 { PseudoVFCVT_RM_X_F_V_M1_MASK, VFCVT_X_F_V, 0x0, 0x0 }, // 1389 { PseudoVFCVT_X_F_V_M1, VFCVT_X_F_V, 0x0, 0x0 }, // 1390 { PseudoVFCVT_X_F_V_M1_MASK, VFCVT_X_F_V, 0x0, 0x0 }, // 1391 { PseudoVFCVT_RM_X_F_V_M2, VFCVT_X_F_V, 0x1, 0x0 }, // 1392 { PseudoVFCVT_RM_X_F_V_M2_MASK, VFCVT_X_F_V, 0x1, 0x0 }, // 1393 { PseudoVFCVT_X_F_V_M2, VFCVT_X_F_V, 0x1, 0x0 }, // 1394 { PseudoVFCVT_X_F_V_M2_MASK, VFCVT_X_F_V, 0x1, 0x0 }, // 1395 { PseudoVFCVT_RM_X_F_V_M4, VFCVT_X_F_V, 0x2, 0x0 }, // 1396 { PseudoVFCVT_RM_X_F_V_M4_MASK, VFCVT_X_F_V, 0x2, 0x0 }, // 1397 { PseudoVFCVT_X_F_V_M4, VFCVT_X_F_V, 0x2, 0x0 }, // 1398 { PseudoVFCVT_X_F_V_M4_MASK, VFCVT_X_F_V, 0x2, 0x0 }, // 1399 { PseudoVFCVT_RM_X_F_V_M8, VFCVT_X_F_V, 0x3, 0x0 }, // 1400 { PseudoVFCVT_RM_X_F_V_M8_MASK, VFCVT_X_F_V, 0x3, 0x0 }, // 1401 { PseudoVFCVT_X_F_V_M8, VFCVT_X_F_V, 0x3, 0x0 }, // 1402 { PseudoVFCVT_X_F_V_M8_MASK, VFCVT_X_F_V, 0x3, 0x0 }, // 1403 { PseudoVFCVT_RM_X_F_V_MF4, VFCVT_X_F_V, 0x6, 0x0 }, // 1404 { PseudoVFCVT_RM_X_F_V_MF4_MASK, VFCVT_X_F_V, 0x6, 0x0 }, // 1405 { PseudoVFCVT_X_F_V_MF4, VFCVT_X_F_V, 0x6, 0x0 }, // 1406 { PseudoVFCVT_X_F_V_MF4_MASK, VFCVT_X_F_V, 0x6, 0x0 }, // 1407 { PseudoVFCVT_RM_X_F_V_MF2, VFCVT_X_F_V, 0x7, 0x0 }, // 1408 { PseudoVFCVT_RM_X_F_V_MF2_MASK, VFCVT_X_F_V, 0x7, 0x0 }, // 1409 { PseudoVFCVT_X_F_V_MF2, VFCVT_X_F_V, 0x7, 0x0 }, // 1410 { PseudoVFCVT_X_F_V_MF2_MASK, VFCVT_X_F_V, 0x7, 0x0 }, // 1411 { PseudoVFDIV_VFPR16_M1_E16, VFDIV_VF, 0x0, 0x10 }, // 1412 { PseudoVFDIV_VFPR16_M1_E16_MASK, VFDIV_VF, 0x0, 0x10 }, // 1413 { PseudoVFDIV_VFPR32_M1_E32, VFDIV_VF, 0x0, 0x20 }, // 1414 { PseudoVFDIV_VFPR32_M1_E32_MASK, VFDIV_VF, 0x0, 0x20 }, // 1415 { PseudoVFDIV_VFPR64_M1_E64, VFDIV_VF, 0x0, 0x40 }, // 1416 { PseudoVFDIV_VFPR64_M1_E64_MASK, VFDIV_VF, 0x0, 0x40 }, // 1417 { PseudoVFDIV_VFPR16_M2_E16, VFDIV_VF, 0x1, 0x10 }, // 1418 { PseudoVFDIV_VFPR16_M2_E16_MASK, VFDIV_VF, 0x1, 0x10 }, // 1419 { PseudoVFDIV_VFPR32_M2_E32, VFDIV_VF, 0x1, 0x20 }, // 1420 { PseudoVFDIV_VFPR32_M2_E32_MASK, VFDIV_VF, 0x1, 0x20 }, // 1421 { PseudoVFDIV_VFPR64_M2_E64, VFDIV_VF, 0x1, 0x40 }, // 1422 { PseudoVFDIV_VFPR64_M2_E64_MASK, VFDIV_VF, 0x1, 0x40 }, // 1423 { PseudoVFDIV_VFPR16_M4_E16, VFDIV_VF, 0x2, 0x10 }, // 1424 { PseudoVFDIV_VFPR16_M4_E16_MASK, VFDIV_VF, 0x2, 0x10 }, // 1425 { PseudoVFDIV_VFPR32_M4_E32, VFDIV_VF, 0x2, 0x20 }, // 1426 { PseudoVFDIV_VFPR32_M4_E32_MASK, VFDIV_VF, 0x2, 0x20 }, // 1427 { PseudoVFDIV_VFPR64_M4_E64, VFDIV_VF, 0x2, 0x40 }, // 1428 { PseudoVFDIV_VFPR64_M4_E64_MASK, VFDIV_VF, 0x2, 0x40 }, // 1429 { PseudoVFDIV_VFPR16_M8_E16, VFDIV_VF, 0x3, 0x10 }, // 1430 { PseudoVFDIV_VFPR16_M8_E16_MASK, VFDIV_VF, 0x3, 0x10 }, // 1431 { PseudoVFDIV_VFPR32_M8_E32, VFDIV_VF, 0x3, 0x20 }, // 1432 { PseudoVFDIV_VFPR32_M8_E32_MASK, VFDIV_VF, 0x3, 0x20 }, // 1433 { PseudoVFDIV_VFPR64_M8_E64, VFDIV_VF, 0x3, 0x40 }, // 1434 { PseudoVFDIV_VFPR64_M8_E64_MASK, VFDIV_VF, 0x3, 0x40 }, // 1435 { PseudoVFDIV_VFPR16_MF4_E16, VFDIV_VF, 0x6, 0x10 }, // 1436 { PseudoVFDIV_VFPR16_MF4_E16_MASK, VFDIV_VF, 0x6, 0x10 }, // 1437 { PseudoVFDIV_VFPR16_MF2_E16, VFDIV_VF, 0x7, 0x10 }, // 1438 { PseudoVFDIV_VFPR16_MF2_E16_MASK, VFDIV_VF, 0x7, 0x10 }, // 1439 { PseudoVFDIV_VFPR32_MF2_E32, VFDIV_VF, 0x7, 0x20 }, // 1440 { PseudoVFDIV_VFPR32_MF2_E32_MASK, VFDIV_VF, 0x7, 0x20 }, // 1441 { PseudoVFDIV_VV_M1_E16, VFDIV_VV, 0x0, 0x10 }, // 1442 { PseudoVFDIV_VV_M1_E16_MASK, VFDIV_VV, 0x0, 0x10 }, // 1443 { PseudoVFDIV_VV_M1_E32, VFDIV_VV, 0x0, 0x20 }, // 1444 { PseudoVFDIV_VV_M1_E32_MASK, VFDIV_VV, 0x0, 0x20 }, // 1445 { PseudoVFDIV_VV_M1_E64, VFDIV_VV, 0x0, 0x40 }, // 1446 { PseudoVFDIV_VV_M1_E64_MASK, VFDIV_VV, 0x0, 0x40 }, // 1447 { PseudoVFDIV_VV_M2_E16, VFDIV_VV, 0x1, 0x10 }, // 1448 { PseudoVFDIV_VV_M2_E16_MASK, VFDIV_VV, 0x1, 0x10 }, // 1449 { PseudoVFDIV_VV_M2_E32, VFDIV_VV, 0x1, 0x20 }, // 1450 { PseudoVFDIV_VV_M2_E32_MASK, VFDIV_VV, 0x1, 0x20 }, // 1451 { PseudoVFDIV_VV_M2_E64, VFDIV_VV, 0x1, 0x40 }, // 1452 { PseudoVFDIV_VV_M2_E64_MASK, VFDIV_VV, 0x1, 0x40 }, // 1453 { PseudoVFDIV_VV_M4_E16, VFDIV_VV, 0x2, 0x10 }, // 1454 { PseudoVFDIV_VV_M4_E16_MASK, VFDIV_VV, 0x2, 0x10 }, // 1455 { PseudoVFDIV_VV_M4_E32, VFDIV_VV, 0x2, 0x20 }, // 1456 { PseudoVFDIV_VV_M4_E32_MASK, VFDIV_VV, 0x2, 0x20 }, // 1457 { PseudoVFDIV_VV_M4_E64, VFDIV_VV, 0x2, 0x40 }, // 1458 { PseudoVFDIV_VV_M4_E64_MASK, VFDIV_VV, 0x2, 0x40 }, // 1459 { PseudoVFDIV_VV_M8_E16, VFDIV_VV, 0x3, 0x10 }, // 1460 { PseudoVFDIV_VV_M8_E16_MASK, VFDIV_VV, 0x3, 0x10 }, // 1461 { PseudoVFDIV_VV_M8_E32, VFDIV_VV, 0x3, 0x20 }, // 1462 { PseudoVFDIV_VV_M8_E32_MASK, VFDIV_VV, 0x3, 0x20 }, // 1463 { PseudoVFDIV_VV_M8_E64, VFDIV_VV, 0x3, 0x40 }, // 1464 { PseudoVFDIV_VV_M8_E64_MASK, VFDIV_VV, 0x3, 0x40 }, // 1465 { PseudoVFDIV_VV_MF4_E16, VFDIV_VV, 0x6, 0x10 }, // 1466 { PseudoVFDIV_VV_MF4_E16_MASK, VFDIV_VV, 0x6, 0x10 }, // 1467 { PseudoVFDIV_VV_MF2_E16, VFDIV_VV, 0x7, 0x10 }, // 1468 { PseudoVFDIV_VV_MF2_E16_MASK, VFDIV_VV, 0x7, 0x10 }, // 1469 { PseudoVFDIV_VV_MF2_E32, VFDIV_VV, 0x7, 0x20 }, // 1470 { PseudoVFDIV_VV_MF2_E32_MASK, VFDIV_VV, 0x7, 0x20 }, // 1471 { PseudoVFIRST_M_B8, VFIRST_M, 0x0, 0x0 }, // 1472 { PseudoVFIRST_M_B8_MASK, VFIRST_M, 0x0, 0x0 }, // 1473 { PseudoVFIRST_M_B16, VFIRST_M, 0x1, 0x0 }, // 1474 { PseudoVFIRST_M_B16_MASK, VFIRST_M, 0x1, 0x0 }, // 1475 { PseudoVFIRST_M_B32, VFIRST_M, 0x2, 0x0 }, // 1476 { PseudoVFIRST_M_B32_MASK, VFIRST_M, 0x2, 0x0 }, // 1477 { PseudoVFIRST_M_B64, VFIRST_M, 0x3, 0x0 }, // 1478 { PseudoVFIRST_M_B64_MASK, VFIRST_M, 0x3, 0x0 }, // 1479 { PseudoVFIRST_M_B1, VFIRST_M, 0x5, 0x0 }, // 1480 { PseudoVFIRST_M_B1_MASK, VFIRST_M, 0x5, 0x0 }, // 1481 { PseudoVFIRST_M_B2, VFIRST_M, 0x6, 0x0 }, // 1482 { PseudoVFIRST_M_B2_MASK, VFIRST_M, 0x6, 0x0 }, // 1483 { PseudoVFIRST_M_B4, VFIRST_M, 0x7, 0x0 }, // 1484 { PseudoVFIRST_M_B4_MASK, VFIRST_M, 0x7, 0x0 }, // 1485 { PseudoVFMACC_VFPR16_M1_E16, VFMACC_VF, 0x0, 0x0 }, // 1486 { PseudoVFMACC_VFPR16_M1_E16_MASK, VFMACC_VF, 0x0, 0x0 }, // 1487 { PseudoVFMACC_VFPR32_M1_E32, VFMACC_VF, 0x0, 0x0 }, // 1488 { PseudoVFMACC_VFPR32_M1_E32_MASK, VFMACC_VF, 0x0, 0x0 }, // 1489 { PseudoVFMACC_VFPR64_M1_E64, VFMACC_VF, 0x0, 0x0 }, // 1490 { PseudoVFMACC_VFPR64_M1_E64_MASK, VFMACC_VF, 0x0, 0x0 }, // 1491 { PseudoVFMACC_VFPR16_M2_E16, VFMACC_VF, 0x1, 0x0 }, // 1492 { PseudoVFMACC_VFPR16_M2_E16_MASK, VFMACC_VF, 0x1, 0x0 }, // 1493 { PseudoVFMACC_VFPR32_M2_E32, VFMACC_VF, 0x1, 0x0 }, // 1494 { PseudoVFMACC_VFPR32_M2_E32_MASK, VFMACC_VF, 0x1, 0x0 }, // 1495 { PseudoVFMACC_VFPR64_M2_E64, VFMACC_VF, 0x1, 0x0 }, // 1496 { PseudoVFMACC_VFPR64_M2_E64_MASK, VFMACC_VF, 0x1, 0x0 }, // 1497 { PseudoVFMACC_VFPR16_M4_E16, VFMACC_VF, 0x2, 0x0 }, // 1498 { PseudoVFMACC_VFPR16_M4_E16_MASK, VFMACC_VF, 0x2, 0x0 }, // 1499 { PseudoVFMACC_VFPR32_M4_E32, VFMACC_VF, 0x2, 0x0 }, // 1500 { PseudoVFMACC_VFPR32_M4_E32_MASK, VFMACC_VF, 0x2, 0x0 }, // 1501 { PseudoVFMACC_VFPR64_M4_E64, VFMACC_VF, 0x2, 0x0 }, // 1502 { PseudoVFMACC_VFPR64_M4_E64_MASK, VFMACC_VF, 0x2, 0x0 }, // 1503 { PseudoVFMACC_VFPR16_M8_E16, VFMACC_VF, 0x3, 0x0 }, // 1504 { PseudoVFMACC_VFPR16_M8_E16_MASK, VFMACC_VF, 0x3, 0x0 }, // 1505 { PseudoVFMACC_VFPR32_M8_E32, VFMACC_VF, 0x3, 0x0 }, // 1506 { PseudoVFMACC_VFPR32_M8_E32_MASK, VFMACC_VF, 0x3, 0x0 }, // 1507 { PseudoVFMACC_VFPR64_M8_E64, VFMACC_VF, 0x3, 0x0 }, // 1508 { PseudoVFMACC_VFPR64_M8_E64_MASK, VFMACC_VF, 0x3, 0x0 }, // 1509 { PseudoVFMACC_VFPR16_MF4_E16, VFMACC_VF, 0x6, 0x0 }, // 1510 { PseudoVFMACC_VFPR16_MF4_E16_MASK, VFMACC_VF, 0x6, 0x0 }, // 1511 { PseudoVFMACC_VFPR16_MF2_E16, VFMACC_VF, 0x7, 0x0 }, // 1512 { PseudoVFMACC_VFPR16_MF2_E16_MASK, VFMACC_VF, 0x7, 0x0 }, // 1513 { PseudoVFMACC_VFPR32_MF2_E32, VFMACC_VF, 0x7, 0x0 }, // 1514 { PseudoVFMACC_VFPR32_MF2_E32_MASK, VFMACC_VF, 0x7, 0x0 }, // 1515 { PseudoVFMACC_VV_M1_E16, VFMACC_VV, 0x0, 0x0 }, // 1516 { PseudoVFMACC_VV_M1_E16_MASK, VFMACC_VV, 0x0, 0x0 }, // 1517 { PseudoVFMACC_VV_M1_E32, VFMACC_VV, 0x0, 0x0 }, // 1518 { PseudoVFMACC_VV_M1_E32_MASK, VFMACC_VV, 0x0, 0x0 }, // 1519 { PseudoVFMACC_VV_M1_E64, VFMACC_VV, 0x0, 0x0 }, // 1520 { PseudoVFMACC_VV_M1_E64_MASK, VFMACC_VV, 0x0, 0x0 }, // 1521 { PseudoVFMACC_VV_M2_E16, VFMACC_VV, 0x1, 0x0 }, // 1522 { PseudoVFMACC_VV_M2_E16_MASK, VFMACC_VV, 0x1, 0x0 }, // 1523 { PseudoVFMACC_VV_M2_E32, VFMACC_VV, 0x1, 0x0 }, // 1524 { PseudoVFMACC_VV_M2_E32_MASK, VFMACC_VV, 0x1, 0x0 }, // 1525 { PseudoVFMACC_VV_M2_E64, VFMACC_VV, 0x1, 0x0 }, // 1526 { PseudoVFMACC_VV_M2_E64_MASK, VFMACC_VV, 0x1, 0x0 }, // 1527 { PseudoVFMACC_VV_M4_E16, VFMACC_VV, 0x2, 0x0 }, // 1528 { PseudoVFMACC_VV_M4_E16_MASK, VFMACC_VV, 0x2, 0x0 }, // 1529 { PseudoVFMACC_VV_M4_E32, VFMACC_VV, 0x2, 0x0 }, // 1530 { PseudoVFMACC_VV_M4_E32_MASK, VFMACC_VV, 0x2, 0x0 }, // 1531 { PseudoVFMACC_VV_M4_E64, VFMACC_VV, 0x2, 0x0 }, // 1532 { PseudoVFMACC_VV_M4_E64_MASK, VFMACC_VV, 0x2, 0x0 }, // 1533 { PseudoVFMACC_VV_M8_E16, VFMACC_VV, 0x3, 0x0 }, // 1534 { PseudoVFMACC_VV_M8_E16_MASK, VFMACC_VV, 0x3, 0x0 }, // 1535 { PseudoVFMACC_VV_M8_E32, VFMACC_VV, 0x3, 0x0 }, // 1536 { PseudoVFMACC_VV_M8_E32_MASK, VFMACC_VV, 0x3, 0x0 }, // 1537 { PseudoVFMACC_VV_M8_E64, VFMACC_VV, 0x3, 0x0 }, // 1538 { PseudoVFMACC_VV_M8_E64_MASK, VFMACC_VV, 0x3, 0x0 }, // 1539 { PseudoVFMACC_VV_MF4_E16, VFMACC_VV, 0x6, 0x0 }, // 1540 { PseudoVFMACC_VV_MF4_E16_MASK, VFMACC_VV, 0x6, 0x0 }, // 1541 { PseudoVFMACC_VV_MF2_E16, VFMACC_VV, 0x7, 0x0 }, // 1542 { PseudoVFMACC_VV_MF2_E16_MASK, VFMACC_VV, 0x7, 0x0 }, // 1543 { PseudoVFMACC_VV_MF2_E32, VFMACC_VV, 0x7, 0x0 }, // 1544 { PseudoVFMACC_VV_MF2_E32_MASK, VFMACC_VV, 0x7, 0x0 }, // 1545 { PseudoVFMADD_VFPR16_M1_E16, VFMADD_VF, 0x0, 0x0 }, // 1546 { PseudoVFMADD_VFPR16_M1_E16_MASK, VFMADD_VF, 0x0, 0x0 }, // 1547 { PseudoVFMADD_VFPR32_M1_E32, VFMADD_VF, 0x0, 0x0 }, // 1548 { PseudoVFMADD_VFPR32_M1_E32_MASK, VFMADD_VF, 0x0, 0x0 }, // 1549 { PseudoVFMADD_VFPR64_M1_E64, VFMADD_VF, 0x0, 0x0 }, // 1550 { PseudoVFMADD_VFPR64_M1_E64_MASK, VFMADD_VF, 0x0, 0x0 }, // 1551 { PseudoVFMADD_VFPR16_M2_E16, VFMADD_VF, 0x1, 0x0 }, // 1552 { PseudoVFMADD_VFPR16_M2_E16_MASK, VFMADD_VF, 0x1, 0x0 }, // 1553 { PseudoVFMADD_VFPR32_M2_E32, VFMADD_VF, 0x1, 0x0 }, // 1554 { PseudoVFMADD_VFPR32_M2_E32_MASK, VFMADD_VF, 0x1, 0x0 }, // 1555 { PseudoVFMADD_VFPR64_M2_E64, VFMADD_VF, 0x1, 0x0 }, // 1556 { PseudoVFMADD_VFPR64_M2_E64_MASK, VFMADD_VF, 0x1, 0x0 }, // 1557 { PseudoVFMADD_VFPR16_M4_E16, VFMADD_VF, 0x2, 0x0 }, // 1558 { PseudoVFMADD_VFPR16_M4_E16_MASK, VFMADD_VF, 0x2, 0x0 }, // 1559 { PseudoVFMADD_VFPR32_M4_E32, VFMADD_VF, 0x2, 0x0 }, // 1560 { PseudoVFMADD_VFPR32_M4_E32_MASK, VFMADD_VF, 0x2, 0x0 }, // 1561 { PseudoVFMADD_VFPR64_M4_E64, VFMADD_VF, 0x2, 0x0 }, // 1562 { PseudoVFMADD_VFPR64_M4_E64_MASK, VFMADD_VF, 0x2, 0x0 }, // 1563 { PseudoVFMADD_VFPR16_M8_E16, VFMADD_VF, 0x3, 0x0 }, // 1564 { PseudoVFMADD_VFPR16_M8_E16_MASK, VFMADD_VF, 0x3, 0x0 }, // 1565 { PseudoVFMADD_VFPR32_M8_E32, VFMADD_VF, 0x3, 0x0 }, // 1566 { PseudoVFMADD_VFPR32_M8_E32_MASK, VFMADD_VF, 0x3, 0x0 }, // 1567 { PseudoVFMADD_VFPR64_M8_E64, VFMADD_VF, 0x3, 0x0 }, // 1568 { PseudoVFMADD_VFPR64_M8_E64_MASK, VFMADD_VF, 0x3, 0x0 }, // 1569 { PseudoVFMADD_VFPR16_MF4_E16, VFMADD_VF, 0x6, 0x0 }, // 1570 { PseudoVFMADD_VFPR16_MF4_E16_MASK, VFMADD_VF, 0x6, 0x0 }, // 1571 { PseudoVFMADD_VFPR16_MF2_E16, VFMADD_VF, 0x7, 0x0 }, // 1572 { PseudoVFMADD_VFPR16_MF2_E16_MASK, VFMADD_VF, 0x7, 0x0 }, // 1573 { PseudoVFMADD_VFPR32_MF2_E32, VFMADD_VF, 0x7, 0x0 }, // 1574 { PseudoVFMADD_VFPR32_MF2_E32_MASK, VFMADD_VF, 0x7, 0x0 }, // 1575 { PseudoVFMADD_VV_M1_E16, VFMADD_VV, 0x0, 0x0 }, // 1576 { PseudoVFMADD_VV_M1_E16_MASK, VFMADD_VV, 0x0, 0x0 }, // 1577 { PseudoVFMADD_VV_M1_E32, VFMADD_VV, 0x0, 0x0 }, // 1578 { PseudoVFMADD_VV_M1_E32_MASK, VFMADD_VV, 0x0, 0x0 }, // 1579 { PseudoVFMADD_VV_M1_E64, VFMADD_VV, 0x0, 0x0 }, // 1580 { PseudoVFMADD_VV_M1_E64_MASK, VFMADD_VV, 0x0, 0x0 }, // 1581 { PseudoVFMADD_VV_M2_E16, VFMADD_VV, 0x1, 0x0 }, // 1582 { PseudoVFMADD_VV_M2_E16_MASK, VFMADD_VV, 0x1, 0x0 }, // 1583 { PseudoVFMADD_VV_M2_E32, VFMADD_VV, 0x1, 0x0 }, // 1584 { PseudoVFMADD_VV_M2_E32_MASK, VFMADD_VV, 0x1, 0x0 }, // 1585 { PseudoVFMADD_VV_M2_E64, VFMADD_VV, 0x1, 0x0 }, // 1586 { PseudoVFMADD_VV_M2_E64_MASK, VFMADD_VV, 0x1, 0x0 }, // 1587 { PseudoVFMADD_VV_M4_E16, VFMADD_VV, 0x2, 0x0 }, // 1588 { PseudoVFMADD_VV_M4_E16_MASK, VFMADD_VV, 0x2, 0x0 }, // 1589 { PseudoVFMADD_VV_M4_E32, VFMADD_VV, 0x2, 0x0 }, // 1590 { PseudoVFMADD_VV_M4_E32_MASK, VFMADD_VV, 0x2, 0x0 }, // 1591 { PseudoVFMADD_VV_M4_E64, VFMADD_VV, 0x2, 0x0 }, // 1592 { PseudoVFMADD_VV_M4_E64_MASK, VFMADD_VV, 0x2, 0x0 }, // 1593 { PseudoVFMADD_VV_M8_E16, VFMADD_VV, 0x3, 0x0 }, // 1594 { PseudoVFMADD_VV_M8_E16_MASK, VFMADD_VV, 0x3, 0x0 }, // 1595 { PseudoVFMADD_VV_M8_E32, VFMADD_VV, 0x3, 0x0 }, // 1596 { PseudoVFMADD_VV_M8_E32_MASK, VFMADD_VV, 0x3, 0x0 }, // 1597 { PseudoVFMADD_VV_M8_E64, VFMADD_VV, 0x3, 0x0 }, // 1598 { PseudoVFMADD_VV_M8_E64_MASK, VFMADD_VV, 0x3, 0x0 }, // 1599 { PseudoVFMADD_VV_MF4_E16, VFMADD_VV, 0x6, 0x0 }, // 1600 { PseudoVFMADD_VV_MF4_E16_MASK, VFMADD_VV, 0x6, 0x0 }, // 1601 { PseudoVFMADD_VV_MF2_E16, VFMADD_VV, 0x7, 0x0 }, // 1602 { PseudoVFMADD_VV_MF2_E16_MASK, VFMADD_VV, 0x7, 0x0 }, // 1603 { PseudoVFMADD_VV_MF2_E32, VFMADD_VV, 0x7, 0x0 }, // 1604 { PseudoVFMADD_VV_MF2_E32_MASK, VFMADD_VV, 0x7, 0x0 }, // 1605 { PseudoVFMAX_VFPR16_M1_E16, VFMAX_VF, 0x0, 0x10 }, // 1606 { PseudoVFMAX_VFPR16_M1_E16_MASK, VFMAX_VF, 0x0, 0x10 }, // 1607 { PseudoVFMAX_VFPR32_M1_E32, VFMAX_VF, 0x0, 0x20 }, // 1608 { PseudoVFMAX_VFPR32_M1_E32_MASK, VFMAX_VF, 0x0, 0x20 }, // 1609 { PseudoVFMAX_VFPR64_M1_E64, VFMAX_VF, 0x0, 0x40 }, // 1610 { PseudoVFMAX_VFPR64_M1_E64_MASK, VFMAX_VF, 0x0, 0x40 }, // 1611 { PseudoVFMAX_VFPR16_M2_E16, VFMAX_VF, 0x1, 0x10 }, // 1612 { PseudoVFMAX_VFPR16_M2_E16_MASK, VFMAX_VF, 0x1, 0x10 }, // 1613 { PseudoVFMAX_VFPR32_M2_E32, VFMAX_VF, 0x1, 0x20 }, // 1614 { PseudoVFMAX_VFPR32_M2_E32_MASK, VFMAX_VF, 0x1, 0x20 }, // 1615 { PseudoVFMAX_VFPR64_M2_E64, VFMAX_VF, 0x1, 0x40 }, // 1616 { PseudoVFMAX_VFPR64_M2_E64_MASK, VFMAX_VF, 0x1, 0x40 }, // 1617 { PseudoVFMAX_VFPR16_M4_E16, VFMAX_VF, 0x2, 0x10 }, // 1618 { PseudoVFMAX_VFPR16_M4_E16_MASK, VFMAX_VF, 0x2, 0x10 }, // 1619 { PseudoVFMAX_VFPR32_M4_E32, VFMAX_VF, 0x2, 0x20 }, // 1620 { PseudoVFMAX_VFPR32_M4_E32_MASK, VFMAX_VF, 0x2, 0x20 }, // 1621 { PseudoVFMAX_VFPR64_M4_E64, VFMAX_VF, 0x2, 0x40 }, // 1622 { PseudoVFMAX_VFPR64_M4_E64_MASK, VFMAX_VF, 0x2, 0x40 }, // 1623 { PseudoVFMAX_VFPR16_M8_E16, VFMAX_VF, 0x3, 0x10 }, // 1624 { PseudoVFMAX_VFPR16_M8_E16_MASK, VFMAX_VF, 0x3, 0x10 }, // 1625 { PseudoVFMAX_VFPR32_M8_E32, VFMAX_VF, 0x3, 0x20 }, // 1626 { PseudoVFMAX_VFPR32_M8_E32_MASK, VFMAX_VF, 0x3, 0x20 }, // 1627 { PseudoVFMAX_VFPR64_M8_E64, VFMAX_VF, 0x3, 0x40 }, // 1628 { PseudoVFMAX_VFPR64_M8_E64_MASK, VFMAX_VF, 0x3, 0x40 }, // 1629 { PseudoVFMAX_VFPR16_MF4_E16, VFMAX_VF, 0x6, 0x10 }, // 1630 { PseudoVFMAX_VFPR16_MF4_E16_MASK, VFMAX_VF, 0x6, 0x10 }, // 1631 { PseudoVFMAX_VFPR16_MF2_E16, VFMAX_VF, 0x7, 0x10 }, // 1632 { PseudoVFMAX_VFPR16_MF2_E16_MASK, VFMAX_VF, 0x7, 0x10 }, // 1633 { PseudoVFMAX_VFPR32_MF2_E32, VFMAX_VF, 0x7, 0x20 }, // 1634 { PseudoVFMAX_VFPR32_MF2_E32_MASK, VFMAX_VF, 0x7, 0x20 }, // 1635 { PseudoVFMAX_VV_M1_E16, VFMAX_VV, 0x0, 0x10 }, // 1636 { PseudoVFMAX_VV_M1_E16_MASK, VFMAX_VV, 0x0, 0x10 }, // 1637 { PseudoVFMAX_VV_M1_E32, VFMAX_VV, 0x0, 0x20 }, // 1638 { PseudoVFMAX_VV_M1_E32_MASK, VFMAX_VV, 0x0, 0x20 }, // 1639 { PseudoVFMAX_VV_M1_E64, VFMAX_VV, 0x0, 0x40 }, // 1640 { PseudoVFMAX_VV_M1_E64_MASK, VFMAX_VV, 0x0, 0x40 }, // 1641 { PseudoVFMAX_VV_M2_E16, VFMAX_VV, 0x1, 0x10 }, // 1642 { PseudoVFMAX_VV_M2_E16_MASK, VFMAX_VV, 0x1, 0x10 }, // 1643 { PseudoVFMAX_VV_M2_E32, VFMAX_VV, 0x1, 0x20 }, // 1644 { PseudoVFMAX_VV_M2_E32_MASK, VFMAX_VV, 0x1, 0x20 }, // 1645 { PseudoVFMAX_VV_M2_E64, VFMAX_VV, 0x1, 0x40 }, // 1646 { PseudoVFMAX_VV_M2_E64_MASK, VFMAX_VV, 0x1, 0x40 }, // 1647 { PseudoVFMAX_VV_M4_E16, VFMAX_VV, 0x2, 0x10 }, // 1648 { PseudoVFMAX_VV_M4_E16_MASK, VFMAX_VV, 0x2, 0x10 }, // 1649 { PseudoVFMAX_VV_M4_E32, VFMAX_VV, 0x2, 0x20 }, // 1650 { PseudoVFMAX_VV_M4_E32_MASK, VFMAX_VV, 0x2, 0x20 }, // 1651 { PseudoVFMAX_VV_M4_E64, VFMAX_VV, 0x2, 0x40 }, // 1652 { PseudoVFMAX_VV_M4_E64_MASK, VFMAX_VV, 0x2, 0x40 }, // 1653 { PseudoVFMAX_VV_M8_E16, VFMAX_VV, 0x3, 0x10 }, // 1654 { PseudoVFMAX_VV_M8_E16_MASK, VFMAX_VV, 0x3, 0x10 }, // 1655 { PseudoVFMAX_VV_M8_E32, VFMAX_VV, 0x3, 0x20 }, // 1656 { PseudoVFMAX_VV_M8_E32_MASK, VFMAX_VV, 0x3, 0x20 }, // 1657 { PseudoVFMAX_VV_M8_E64, VFMAX_VV, 0x3, 0x40 }, // 1658 { PseudoVFMAX_VV_M8_E64_MASK, VFMAX_VV, 0x3, 0x40 }, // 1659 { PseudoVFMAX_VV_MF4_E16, VFMAX_VV, 0x6, 0x10 }, // 1660 { PseudoVFMAX_VV_MF4_E16_MASK, VFMAX_VV, 0x6, 0x10 }, // 1661 { PseudoVFMAX_VV_MF2_E16, VFMAX_VV, 0x7, 0x10 }, // 1662 { PseudoVFMAX_VV_MF2_E16_MASK, VFMAX_VV, 0x7, 0x10 }, // 1663 { PseudoVFMAX_VV_MF2_E32, VFMAX_VV, 0x7, 0x20 }, // 1664 { PseudoVFMAX_VV_MF2_E32_MASK, VFMAX_VV, 0x7, 0x20 }, // 1665 { PseudoVFMERGE_VFPR16M_M1, VFMERGE_VFM, 0x0, 0x0 }, // 1666 { PseudoVFMERGE_VFPR32M_M1, VFMERGE_VFM, 0x0, 0x0 }, // 1667 { PseudoVFMERGE_VFPR64M_M1, VFMERGE_VFM, 0x0, 0x0 }, // 1668 { PseudoVFMERGE_VFPR16M_M2, VFMERGE_VFM, 0x1, 0x0 }, // 1669 { PseudoVFMERGE_VFPR32M_M2, VFMERGE_VFM, 0x1, 0x0 }, // 1670 { PseudoVFMERGE_VFPR64M_M2, VFMERGE_VFM, 0x1, 0x0 }, // 1671 { PseudoVFMERGE_VFPR16M_M4, VFMERGE_VFM, 0x2, 0x0 }, // 1672 { PseudoVFMERGE_VFPR32M_M4, VFMERGE_VFM, 0x2, 0x0 }, // 1673 { PseudoVFMERGE_VFPR64M_M4, VFMERGE_VFM, 0x2, 0x0 }, // 1674 { PseudoVFMERGE_VFPR16M_M8, VFMERGE_VFM, 0x3, 0x0 }, // 1675 { PseudoVFMERGE_VFPR32M_M8, VFMERGE_VFM, 0x3, 0x0 }, // 1676 { PseudoVFMERGE_VFPR64M_M8, VFMERGE_VFM, 0x3, 0x0 }, // 1677 { PseudoVFMERGE_VFPR16M_MF4, VFMERGE_VFM, 0x6, 0x0 }, // 1678 { PseudoVFMERGE_VFPR16M_MF2, VFMERGE_VFM, 0x7, 0x0 }, // 1679 { PseudoVFMERGE_VFPR32M_MF2, VFMERGE_VFM, 0x7, 0x0 }, // 1680 { PseudoVFMIN_VFPR16_M1_E16, VFMIN_VF, 0x0, 0x10 }, // 1681 { PseudoVFMIN_VFPR16_M1_E16_MASK, VFMIN_VF, 0x0, 0x10 }, // 1682 { PseudoVFMIN_VFPR32_M1_E32, VFMIN_VF, 0x0, 0x20 }, // 1683 { PseudoVFMIN_VFPR32_M1_E32_MASK, VFMIN_VF, 0x0, 0x20 }, // 1684 { PseudoVFMIN_VFPR64_M1_E64, VFMIN_VF, 0x0, 0x40 }, // 1685 { PseudoVFMIN_VFPR64_M1_E64_MASK, VFMIN_VF, 0x0, 0x40 }, // 1686 { PseudoVFMIN_VFPR16_M2_E16, VFMIN_VF, 0x1, 0x10 }, // 1687 { PseudoVFMIN_VFPR16_M2_E16_MASK, VFMIN_VF, 0x1, 0x10 }, // 1688 { PseudoVFMIN_VFPR32_M2_E32, VFMIN_VF, 0x1, 0x20 }, // 1689 { PseudoVFMIN_VFPR32_M2_E32_MASK, VFMIN_VF, 0x1, 0x20 }, // 1690 { PseudoVFMIN_VFPR64_M2_E64, VFMIN_VF, 0x1, 0x40 }, // 1691 { PseudoVFMIN_VFPR64_M2_E64_MASK, VFMIN_VF, 0x1, 0x40 }, // 1692 { PseudoVFMIN_VFPR16_M4_E16, VFMIN_VF, 0x2, 0x10 }, // 1693 { PseudoVFMIN_VFPR16_M4_E16_MASK, VFMIN_VF, 0x2, 0x10 }, // 1694 { PseudoVFMIN_VFPR32_M4_E32, VFMIN_VF, 0x2, 0x20 }, // 1695 { PseudoVFMIN_VFPR32_M4_E32_MASK, VFMIN_VF, 0x2, 0x20 }, // 1696 { PseudoVFMIN_VFPR64_M4_E64, VFMIN_VF, 0x2, 0x40 }, // 1697 { PseudoVFMIN_VFPR64_M4_E64_MASK, VFMIN_VF, 0x2, 0x40 }, // 1698 { PseudoVFMIN_VFPR16_M8_E16, VFMIN_VF, 0x3, 0x10 }, // 1699 { PseudoVFMIN_VFPR16_M8_E16_MASK, VFMIN_VF, 0x3, 0x10 }, // 1700 { PseudoVFMIN_VFPR32_M8_E32, VFMIN_VF, 0x3, 0x20 }, // 1701 { PseudoVFMIN_VFPR32_M8_E32_MASK, VFMIN_VF, 0x3, 0x20 }, // 1702 { PseudoVFMIN_VFPR64_M8_E64, VFMIN_VF, 0x3, 0x40 }, // 1703 { PseudoVFMIN_VFPR64_M8_E64_MASK, VFMIN_VF, 0x3, 0x40 }, // 1704 { PseudoVFMIN_VFPR16_MF4_E16, VFMIN_VF, 0x6, 0x10 }, // 1705 { PseudoVFMIN_VFPR16_MF4_E16_MASK, VFMIN_VF, 0x6, 0x10 }, // 1706 { PseudoVFMIN_VFPR16_MF2_E16, VFMIN_VF, 0x7, 0x10 }, // 1707 { PseudoVFMIN_VFPR16_MF2_E16_MASK, VFMIN_VF, 0x7, 0x10 }, // 1708 { PseudoVFMIN_VFPR32_MF2_E32, VFMIN_VF, 0x7, 0x20 }, // 1709 { PseudoVFMIN_VFPR32_MF2_E32_MASK, VFMIN_VF, 0x7, 0x20 }, // 1710 { PseudoVFMIN_VV_M1_E16, VFMIN_VV, 0x0, 0x10 }, // 1711 { PseudoVFMIN_VV_M1_E16_MASK, VFMIN_VV, 0x0, 0x10 }, // 1712 { PseudoVFMIN_VV_M1_E32, VFMIN_VV, 0x0, 0x20 }, // 1713 { PseudoVFMIN_VV_M1_E32_MASK, VFMIN_VV, 0x0, 0x20 }, // 1714 { PseudoVFMIN_VV_M1_E64, VFMIN_VV, 0x0, 0x40 }, // 1715 { PseudoVFMIN_VV_M1_E64_MASK, VFMIN_VV, 0x0, 0x40 }, // 1716 { PseudoVFMIN_VV_M2_E16, VFMIN_VV, 0x1, 0x10 }, // 1717 { PseudoVFMIN_VV_M2_E16_MASK, VFMIN_VV, 0x1, 0x10 }, // 1718 { PseudoVFMIN_VV_M2_E32, VFMIN_VV, 0x1, 0x20 }, // 1719 { PseudoVFMIN_VV_M2_E32_MASK, VFMIN_VV, 0x1, 0x20 }, // 1720 { PseudoVFMIN_VV_M2_E64, VFMIN_VV, 0x1, 0x40 }, // 1721 { PseudoVFMIN_VV_M2_E64_MASK, VFMIN_VV, 0x1, 0x40 }, // 1722 { PseudoVFMIN_VV_M4_E16, VFMIN_VV, 0x2, 0x10 }, // 1723 { PseudoVFMIN_VV_M4_E16_MASK, VFMIN_VV, 0x2, 0x10 }, // 1724 { PseudoVFMIN_VV_M4_E32, VFMIN_VV, 0x2, 0x20 }, // 1725 { PseudoVFMIN_VV_M4_E32_MASK, VFMIN_VV, 0x2, 0x20 }, // 1726 { PseudoVFMIN_VV_M4_E64, VFMIN_VV, 0x2, 0x40 }, // 1727 { PseudoVFMIN_VV_M4_E64_MASK, VFMIN_VV, 0x2, 0x40 }, // 1728 { PseudoVFMIN_VV_M8_E16, VFMIN_VV, 0x3, 0x10 }, // 1729 { PseudoVFMIN_VV_M8_E16_MASK, VFMIN_VV, 0x3, 0x10 }, // 1730 { PseudoVFMIN_VV_M8_E32, VFMIN_VV, 0x3, 0x20 }, // 1731 { PseudoVFMIN_VV_M8_E32_MASK, VFMIN_VV, 0x3, 0x20 }, // 1732 { PseudoVFMIN_VV_M8_E64, VFMIN_VV, 0x3, 0x40 }, // 1733 { PseudoVFMIN_VV_M8_E64_MASK, VFMIN_VV, 0x3, 0x40 }, // 1734 { PseudoVFMIN_VV_MF4_E16, VFMIN_VV, 0x6, 0x10 }, // 1735 { PseudoVFMIN_VV_MF4_E16_MASK, VFMIN_VV, 0x6, 0x10 }, // 1736 { PseudoVFMIN_VV_MF2_E16, VFMIN_VV, 0x7, 0x10 }, // 1737 { PseudoVFMIN_VV_MF2_E16_MASK, VFMIN_VV, 0x7, 0x10 }, // 1738 { PseudoVFMIN_VV_MF2_E32, VFMIN_VV, 0x7, 0x20 }, // 1739 { PseudoVFMIN_VV_MF2_E32_MASK, VFMIN_VV, 0x7, 0x20 }, // 1740 { PseudoVFMSAC_VFPR16_M1_E16, VFMSAC_VF, 0x0, 0x0 }, // 1741 { PseudoVFMSAC_VFPR16_M1_E16_MASK, VFMSAC_VF, 0x0, 0x0 }, // 1742 { PseudoVFMSAC_VFPR32_M1_E32, VFMSAC_VF, 0x0, 0x0 }, // 1743 { PseudoVFMSAC_VFPR32_M1_E32_MASK, VFMSAC_VF, 0x0, 0x0 }, // 1744 { PseudoVFMSAC_VFPR64_M1_E64, VFMSAC_VF, 0x0, 0x0 }, // 1745 { PseudoVFMSAC_VFPR64_M1_E64_MASK, VFMSAC_VF, 0x0, 0x0 }, // 1746 { PseudoVFMSAC_VFPR16_M2_E16, VFMSAC_VF, 0x1, 0x0 }, // 1747 { PseudoVFMSAC_VFPR16_M2_E16_MASK, VFMSAC_VF, 0x1, 0x0 }, // 1748 { PseudoVFMSAC_VFPR32_M2_E32, VFMSAC_VF, 0x1, 0x0 }, // 1749 { PseudoVFMSAC_VFPR32_M2_E32_MASK, VFMSAC_VF, 0x1, 0x0 }, // 1750 { PseudoVFMSAC_VFPR64_M2_E64, VFMSAC_VF, 0x1, 0x0 }, // 1751 { PseudoVFMSAC_VFPR64_M2_E64_MASK, VFMSAC_VF, 0x1, 0x0 }, // 1752 { PseudoVFMSAC_VFPR16_M4_E16, VFMSAC_VF, 0x2, 0x0 }, // 1753 { PseudoVFMSAC_VFPR16_M4_E16_MASK, VFMSAC_VF, 0x2, 0x0 }, // 1754 { PseudoVFMSAC_VFPR32_M4_E32, VFMSAC_VF, 0x2, 0x0 }, // 1755 { PseudoVFMSAC_VFPR32_M4_E32_MASK, VFMSAC_VF, 0x2, 0x0 }, // 1756 { PseudoVFMSAC_VFPR64_M4_E64, VFMSAC_VF, 0x2, 0x0 }, // 1757 { PseudoVFMSAC_VFPR64_M4_E64_MASK, VFMSAC_VF, 0x2, 0x0 }, // 1758 { PseudoVFMSAC_VFPR16_M8_E16, VFMSAC_VF, 0x3, 0x0 }, // 1759 { PseudoVFMSAC_VFPR16_M8_E16_MASK, VFMSAC_VF, 0x3, 0x0 }, // 1760 { PseudoVFMSAC_VFPR32_M8_E32, VFMSAC_VF, 0x3, 0x0 }, // 1761 { PseudoVFMSAC_VFPR32_M8_E32_MASK, VFMSAC_VF, 0x3, 0x0 }, // 1762 { PseudoVFMSAC_VFPR64_M8_E64, VFMSAC_VF, 0x3, 0x0 }, // 1763 { PseudoVFMSAC_VFPR64_M8_E64_MASK, VFMSAC_VF, 0x3, 0x0 }, // 1764 { PseudoVFMSAC_VFPR16_MF4_E16, VFMSAC_VF, 0x6, 0x0 }, // 1765 { PseudoVFMSAC_VFPR16_MF4_E16_MASK, VFMSAC_VF, 0x6, 0x0 }, // 1766 { PseudoVFMSAC_VFPR16_MF2_E16, VFMSAC_VF, 0x7, 0x0 }, // 1767 { PseudoVFMSAC_VFPR16_MF2_E16_MASK, VFMSAC_VF, 0x7, 0x0 }, // 1768 { PseudoVFMSAC_VFPR32_MF2_E32, VFMSAC_VF, 0x7, 0x0 }, // 1769 { PseudoVFMSAC_VFPR32_MF2_E32_MASK, VFMSAC_VF, 0x7, 0x0 }, // 1770 { PseudoVFMSAC_VV_M1_E16, VFMSAC_VV, 0x0, 0x0 }, // 1771 { PseudoVFMSAC_VV_M1_E16_MASK, VFMSAC_VV, 0x0, 0x0 }, // 1772 { PseudoVFMSAC_VV_M1_E32, VFMSAC_VV, 0x0, 0x0 }, // 1773 { PseudoVFMSAC_VV_M1_E32_MASK, VFMSAC_VV, 0x0, 0x0 }, // 1774 { PseudoVFMSAC_VV_M1_E64, VFMSAC_VV, 0x0, 0x0 }, // 1775 { PseudoVFMSAC_VV_M1_E64_MASK, VFMSAC_VV, 0x0, 0x0 }, // 1776 { PseudoVFMSAC_VV_M2_E16, VFMSAC_VV, 0x1, 0x0 }, // 1777 { PseudoVFMSAC_VV_M2_E16_MASK, VFMSAC_VV, 0x1, 0x0 }, // 1778 { PseudoVFMSAC_VV_M2_E32, VFMSAC_VV, 0x1, 0x0 }, // 1779 { PseudoVFMSAC_VV_M2_E32_MASK, VFMSAC_VV, 0x1, 0x0 }, // 1780 { PseudoVFMSAC_VV_M2_E64, VFMSAC_VV, 0x1, 0x0 }, // 1781 { PseudoVFMSAC_VV_M2_E64_MASK, VFMSAC_VV, 0x1, 0x0 }, // 1782 { PseudoVFMSAC_VV_M4_E16, VFMSAC_VV, 0x2, 0x0 }, // 1783 { PseudoVFMSAC_VV_M4_E16_MASK, VFMSAC_VV, 0x2, 0x0 }, // 1784 { PseudoVFMSAC_VV_M4_E32, VFMSAC_VV, 0x2, 0x0 }, // 1785 { PseudoVFMSAC_VV_M4_E32_MASK, VFMSAC_VV, 0x2, 0x0 }, // 1786 { PseudoVFMSAC_VV_M4_E64, VFMSAC_VV, 0x2, 0x0 }, // 1787 { PseudoVFMSAC_VV_M4_E64_MASK, VFMSAC_VV, 0x2, 0x0 }, // 1788 { PseudoVFMSAC_VV_M8_E16, VFMSAC_VV, 0x3, 0x0 }, // 1789 { PseudoVFMSAC_VV_M8_E16_MASK, VFMSAC_VV, 0x3, 0x0 }, // 1790 { PseudoVFMSAC_VV_M8_E32, VFMSAC_VV, 0x3, 0x0 }, // 1791 { PseudoVFMSAC_VV_M8_E32_MASK, VFMSAC_VV, 0x3, 0x0 }, // 1792 { PseudoVFMSAC_VV_M8_E64, VFMSAC_VV, 0x3, 0x0 }, // 1793 { PseudoVFMSAC_VV_M8_E64_MASK, VFMSAC_VV, 0x3, 0x0 }, // 1794 { PseudoVFMSAC_VV_MF4_E16, VFMSAC_VV, 0x6, 0x0 }, // 1795 { PseudoVFMSAC_VV_MF4_E16_MASK, VFMSAC_VV, 0x6, 0x0 }, // 1796 { PseudoVFMSAC_VV_MF2_E16, VFMSAC_VV, 0x7, 0x0 }, // 1797 { PseudoVFMSAC_VV_MF2_E16_MASK, VFMSAC_VV, 0x7, 0x0 }, // 1798 { PseudoVFMSAC_VV_MF2_E32, VFMSAC_VV, 0x7, 0x0 }, // 1799 { PseudoVFMSAC_VV_MF2_E32_MASK, VFMSAC_VV, 0x7, 0x0 }, // 1800 { PseudoVFMSUB_VFPR16_M1_E16, VFMSUB_VF, 0x0, 0x0 }, // 1801 { PseudoVFMSUB_VFPR16_M1_E16_MASK, VFMSUB_VF, 0x0, 0x0 }, // 1802 { PseudoVFMSUB_VFPR32_M1_E32, VFMSUB_VF, 0x0, 0x0 }, // 1803 { PseudoVFMSUB_VFPR32_M1_E32_MASK, VFMSUB_VF, 0x0, 0x0 }, // 1804 { PseudoVFMSUB_VFPR64_M1_E64, VFMSUB_VF, 0x0, 0x0 }, // 1805 { PseudoVFMSUB_VFPR64_M1_E64_MASK, VFMSUB_VF, 0x0, 0x0 }, // 1806 { PseudoVFMSUB_VFPR16_M2_E16, VFMSUB_VF, 0x1, 0x0 }, // 1807 { PseudoVFMSUB_VFPR16_M2_E16_MASK, VFMSUB_VF, 0x1, 0x0 }, // 1808 { PseudoVFMSUB_VFPR32_M2_E32, VFMSUB_VF, 0x1, 0x0 }, // 1809 { PseudoVFMSUB_VFPR32_M2_E32_MASK, VFMSUB_VF, 0x1, 0x0 }, // 1810 { PseudoVFMSUB_VFPR64_M2_E64, VFMSUB_VF, 0x1, 0x0 }, // 1811 { PseudoVFMSUB_VFPR64_M2_E64_MASK, VFMSUB_VF, 0x1, 0x0 }, // 1812 { PseudoVFMSUB_VFPR16_M4_E16, VFMSUB_VF, 0x2, 0x0 }, // 1813 { PseudoVFMSUB_VFPR16_M4_E16_MASK, VFMSUB_VF, 0x2, 0x0 }, // 1814 { PseudoVFMSUB_VFPR32_M4_E32, VFMSUB_VF, 0x2, 0x0 }, // 1815 { PseudoVFMSUB_VFPR32_M4_E32_MASK, VFMSUB_VF, 0x2, 0x0 }, // 1816 { PseudoVFMSUB_VFPR64_M4_E64, VFMSUB_VF, 0x2, 0x0 }, // 1817 { PseudoVFMSUB_VFPR64_M4_E64_MASK, VFMSUB_VF, 0x2, 0x0 }, // 1818 { PseudoVFMSUB_VFPR16_M8_E16, VFMSUB_VF, 0x3, 0x0 }, // 1819 { PseudoVFMSUB_VFPR16_M8_E16_MASK, VFMSUB_VF, 0x3, 0x0 }, // 1820 { PseudoVFMSUB_VFPR32_M8_E32, VFMSUB_VF, 0x3, 0x0 }, // 1821 { PseudoVFMSUB_VFPR32_M8_E32_MASK, VFMSUB_VF, 0x3, 0x0 }, // 1822 { PseudoVFMSUB_VFPR64_M8_E64, VFMSUB_VF, 0x3, 0x0 }, // 1823 { PseudoVFMSUB_VFPR64_M8_E64_MASK, VFMSUB_VF, 0x3, 0x0 }, // 1824 { PseudoVFMSUB_VFPR16_MF4_E16, VFMSUB_VF, 0x6, 0x0 }, // 1825 { PseudoVFMSUB_VFPR16_MF4_E16_MASK, VFMSUB_VF, 0x6, 0x0 }, // 1826 { PseudoVFMSUB_VFPR16_MF2_E16, VFMSUB_VF, 0x7, 0x0 }, // 1827 { PseudoVFMSUB_VFPR16_MF2_E16_MASK, VFMSUB_VF, 0x7, 0x0 }, // 1828 { PseudoVFMSUB_VFPR32_MF2_E32, VFMSUB_VF, 0x7, 0x0 }, // 1829 { PseudoVFMSUB_VFPR32_MF2_E32_MASK, VFMSUB_VF, 0x7, 0x0 }, // 1830 { PseudoVFMSUB_VV_M1_E16, VFMSUB_VV, 0x0, 0x0 }, // 1831 { PseudoVFMSUB_VV_M1_E16_MASK, VFMSUB_VV, 0x0, 0x0 }, // 1832 { PseudoVFMSUB_VV_M1_E32, VFMSUB_VV, 0x0, 0x0 }, // 1833 { PseudoVFMSUB_VV_M1_E32_MASK, VFMSUB_VV, 0x0, 0x0 }, // 1834 { PseudoVFMSUB_VV_M1_E64, VFMSUB_VV, 0x0, 0x0 }, // 1835 { PseudoVFMSUB_VV_M1_E64_MASK, VFMSUB_VV, 0x0, 0x0 }, // 1836 { PseudoVFMSUB_VV_M2_E16, VFMSUB_VV, 0x1, 0x0 }, // 1837 { PseudoVFMSUB_VV_M2_E16_MASK, VFMSUB_VV, 0x1, 0x0 }, // 1838 { PseudoVFMSUB_VV_M2_E32, VFMSUB_VV, 0x1, 0x0 }, // 1839 { PseudoVFMSUB_VV_M2_E32_MASK, VFMSUB_VV, 0x1, 0x0 }, // 1840 { PseudoVFMSUB_VV_M2_E64, VFMSUB_VV, 0x1, 0x0 }, // 1841 { PseudoVFMSUB_VV_M2_E64_MASK, VFMSUB_VV, 0x1, 0x0 }, // 1842 { PseudoVFMSUB_VV_M4_E16, VFMSUB_VV, 0x2, 0x0 }, // 1843 { PseudoVFMSUB_VV_M4_E16_MASK, VFMSUB_VV, 0x2, 0x0 }, // 1844 { PseudoVFMSUB_VV_M4_E32, VFMSUB_VV, 0x2, 0x0 }, // 1845 { PseudoVFMSUB_VV_M4_E32_MASK, VFMSUB_VV, 0x2, 0x0 }, // 1846 { PseudoVFMSUB_VV_M4_E64, VFMSUB_VV, 0x2, 0x0 }, // 1847 { PseudoVFMSUB_VV_M4_E64_MASK, VFMSUB_VV, 0x2, 0x0 }, // 1848 { PseudoVFMSUB_VV_M8_E16, VFMSUB_VV, 0x3, 0x0 }, // 1849 { PseudoVFMSUB_VV_M8_E16_MASK, VFMSUB_VV, 0x3, 0x0 }, // 1850 { PseudoVFMSUB_VV_M8_E32, VFMSUB_VV, 0x3, 0x0 }, // 1851 { PseudoVFMSUB_VV_M8_E32_MASK, VFMSUB_VV, 0x3, 0x0 }, // 1852 { PseudoVFMSUB_VV_M8_E64, VFMSUB_VV, 0x3, 0x0 }, // 1853 { PseudoVFMSUB_VV_M8_E64_MASK, VFMSUB_VV, 0x3, 0x0 }, // 1854 { PseudoVFMSUB_VV_MF4_E16, VFMSUB_VV, 0x6, 0x0 }, // 1855 { PseudoVFMSUB_VV_MF4_E16_MASK, VFMSUB_VV, 0x6, 0x0 }, // 1856 { PseudoVFMSUB_VV_MF2_E16, VFMSUB_VV, 0x7, 0x0 }, // 1857 { PseudoVFMSUB_VV_MF2_E16_MASK, VFMSUB_VV, 0x7, 0x0 }, // 1858 { PseudoVFMSUB_VV_MF2_E32, VFMSUB_VV, 0x7, 0x0 }, // 1859 { PseudoVFMSUB_VV_MF2_E32_MASK, VFMSUB_VV, 0x7, 0x0 }, // 1860 { PseudoVFMUL_VFPR16_M1_E16, VFMUL_VF, 0x0, 0x10 }, // 1861 { PseudoVFMUL_VFPR16_M1_E16_MASK, VFMUL_VF, 0x0, 0x10 }, // 1862 { PseudoVFMUL_VFPR32_M1_E32, VFMUL_VF, 0x0, 0x20 }, // 1863 { PseudoVFMUL_VFPR32_M1_E32_MASK, VFMUL_VF, 0x0, 0x20 }, // 1864 { PseudoVFMUL_VFPR64_M1_E64, VFMUL_VF, 0x0, 0x40 }, // 1865 { PseudoVFMUL_VFPR64_M1_E64_MASK, VFMUL_VF, 0x0, 0x40 }, // 1866 { PseudoVFMUL_VFPR16_M2_E16, VFMUL_VF, 0x1, 0x10 }, // 1867 { PseudoVFMUL_VFPR16_M2_E16_MASK, VFMUL_VF, 0x1, 0x10 }, // 1868 { PseudoVFMUL_VFPR32_M2_E32, VFMUL_VF, 0x1, 0x20 }, // 1869 { PseudoVFMUL_VFPR32_M2_E32_MASK, VFMUL_VF, 0x1, 0x20 }, // 1870 { PseudoVFMUL_VFPR64_M2_E64, VFMUL_VF, 0x1, 0x40 }, // 1871 { PseudoVFMUL_VFPR64_M2_E64_MASK, VFMUL_VF, 0x1, 0x40 }, // 1872 { PseudoVFMUL_VFPR16_M4_E16, VFMUL_VF, 0x2, 0x10 }, // 1873 { PseudoVFMUL_VFPR16_M4_E16_MASK, VFMUL_VF, 0x2, 0x10 }, // 1874 { PseudoVFMUL_VFPR32_M4_E32, VFMUL_VF, 0x2, 0x20 }, // 1875 { PseudoVFMUL_VFPR32_M4_E32_MASK, VFMUL_VF, 0x2, 0x20 }, // 1876 { PseudoVFMUL_VFPR64_M4_E64, VFMUL_VF, 0x2, 0x40 }, // 1877 { PseudoVFMUL_VFPR64_M4_E64_MASK, VFMUL_VF, 0x2, 0x40 }, // 1878 { PseudoVFMUL_VFPR16_M8_E16, VFMUL_VF, 0x3, 0x10 }, // 1879 { PseudoVFMUL_VFPR16_M8_E16_MASK, VFMUL_VF, 0x3, 0x10 }, // 1880 { PseudoVFMUL_VFPR32_M8_E32, VFMUL_VF, 0x3, 0x20 }, // 1881 { PseudoVFMUL_VFPR32_M8_E32_MASK, VFMUL_VF, 0x3, 0x20 }, // 1882 { PseudoVFMUL_VFPR64_M8_E64, VFMUL_VF, 0x3, 0x40 }, // 1883 { PseudoVFMUL_VFPR64_M8_E64_MASK, VFMUL_VF, 0x3, 0x40 }, // 1884 { PseudoVFMUL_VFPR16_MF4_E16, VFMUL_VF, 0x6, 0x10 }, // 1885 { PseudoVFMUL_VFPR16_MF4_E16_MASK, VFMUL_VF, 0x6, 0x10 }, // 1886 { PseudoVFMUL_VFPR16_MF2_E16, VFMUL_VF, 0x7, 0x10 }, // 1887 { PseudoVFMUL_VFPR16_MF2_E16_MASK, VFMUL_VF, 0x7, 0x10 }, // 1888 { PseudoVFMUL_VFPR32_MF2_E32, VFMUL_VF, 0x7, 0x20 }, // 1889 { PseudoVFMUL_VFPR32_MF2_E32_MASK, VFMUL_VF, 0x7, 0x20 }, // 1890 { PseudoVFMUL_VV_M1_E16, VFMUL_VV, 0x0, 0x10 }, // 1891 { PseudoVFMUL_VV_M1_E16_MASK, VFMUL_VV, 0x0, 0x10 }, // 1892 { PseudoVFMUL_VV_M1_E32, VFMUL_VV, 0x0, 0x20 }, // 1893 { PseudoVFMUL_VV_M1_E32_MASK, VFMUL_VV, 0x0, 0x20 }, // 1894 { PseudoVFMUL_VV_M1_E64, VFMUL_VV, 0x0, 0x40 }, // 1895 { PseudoVFMUL_VV_M1_E64_MASK, VFMUL_VV, 0x0, 0x40 }, // 1896 { PseudoVFMUL_VV_M2_E16, VFMUL_VV, 0x1, 0x10 }, // 1897 { PseudoVFMUL_VV_M2_E16_MASK, VFMUL_VV, 0x1, 0x10 }, // 1898 { PseudoVFMUL_VV_M2_E32, VFMUL_VV, 0x1, 0x20 }, // 1899 { PseudoVFMUL_VV_M2_E32_MASK, VFMUL_VV, 0x1, 0x20 }, // 1900 { PseudoVFMUL_VV_M2_E64, VFMUL_VV, 0x1, 0x40 }, // 1901 { PseudoVFMUL_VV_M2_E64_MASK, VFMUL_VV, 0x1, 0x40 }, // 1902 { PseudoVFMUL_VV_M4_E16, VFMUL_VV, 0x2, 0x10 }, // 1903 { PseudoVFMUL_VV_M4_E16_MASK, VFMUL_VV, 0x2, 0x10 }, // 1904 { PseudoVFMUL_VV_M4_E32, VFMUL_VV, 0x2, 0x20 }, // 1905 { PseudoVFMUL_VV_M4_E32_MASK, VFMUL_VV, 0x2, 0x20 }, // 1906 { PseudoVFMUL_VV_M4_E64, VFMUL_VV, 0x2, 0x40 }, // 1907 { PseudoVFMUL_VV_M4_E64_MASK, VFMUL_VV, 0x2, 0x40 }, // 1908 { PseudoVFMUL_VV_M8_E16, VFMUL_VV, 0x3, 0x10 }, // 1909 { PseudoVFMUL_VV_M8_E16_MASK, VFMUL_VV, 0x3, 0x10 }, // 1910 { PseudoVFMUL_VV_M8_E32, VFMUL_VV, 0x3, 0x20 }, // 1911 { PseudoVFMUL_VV_M8_E32_MASK, VFMUL_VV, 0x3, 0x20 }, // 1912 { PseudoVFMUL_VV_M8_E64, VFMUL_VV, 0x3, 0x40 }, // 1913 { PseudoVFMUL_VV_M8_E64_MASK, VFMUL_VV, 0x3, 0x40 }, // 1914 { PseudoVFMUL_VV_MF4_E16, VFMUL_VV, 0x6, 0x10 }, // 1915 { PseudoVFMUL_VV_MF4_E16_MASK, VFMUL_VV, 0x6, 0x10 }, // 1916 { PseudoVFMUL_VV_MF2_E16, VFMUL_VV, 0x7, 0x10 }, // 1917 { PseudoVFMUL_VV_MF2_E16_MASK, VFMUL_VV, 0x7, 0x10 }, // 1918 { PseudoVFMUL_VV_MF2_E32, VFMUL_VV, 0x7, 0x20 }, // 1919 { PseudoVFMUL_VV_MF2_E32_MASK, VFMUL_VV, 0x7, 0x20 }, // 1920 { PseudoVFMV_FPR16_S, VFMV_F_S, 0x0, 0x0 }, // 1921 { PseudoVFMV_FPR32_S, VFMV_F_S, 0x0, 0x0 }, // 1922 { PseudoVFMV_FPR64_S, VFMV_F_S, 0x0, 0x0 }, // 1923 { PseudoVFMV_S_FPR16, VFMV_S_F, 0x0, 0x0 }, // 1924 { PseudoVFMV_S_FPR32, VFMV_S_F, 0x0, 0x0 }, // 1925 { PseudoVFMV_S_FPR64, VFMV_S_F, 0x0, 0x0 }, // 1926 { PseudoVFMV_V_FPR16_M1, VFMV_V_F, 0x0, 0x0 }, // 1927 { PseudoVFMV_V_FPR32_M1, VFMV_V_F, 0x0, 0x0 }, // 1928 { PseudoVFMV_V_FPR64_M1, VFMV_V_F, 0x0, 0x0 }, // 1929 { PseudoVFMV_V_FPR16_M2, VFMV_V_F, 0x1, 0x0 }, // 1930 { PseudoVFMV_V_FPR32_M2, VFMV_V_F, 0x1, 0x0 }, // 1931 { PseudoVFMV_V_FPR64_M2, VFMV_V_F, 0x1, 0x0 }, // 1932 { PseudoVFMV_V_FPR16_M4, VFMV_V_F, 0x2, 0x0 }, // 1933 { PseudoVFMV_V_FPR32_M4, VFMV_V_F, 0x2, 0x0 }, // 1934 { PseudoVFMV_V_FPR64_M4, VFMV_V_F, 0x2, 0x0 }, // 1935 { PseudoVFMV_V_FPR16_M8, VFMV_V_F, 0x3, 0x0 }, // 1936 { PseudoVFMV_V_FPR32_M8, VFMV_V_F, 0x3, 0x0 }, // 1937 { PseudoVFMV_V_FPR64_M8, VFMV_V_F, 0x3, 0x0 }, // 1938 { PseudoVFMV_V_FPR16_MF4, VFMV_V_F, 0x6, 0x0 }, // 1939 { PseudoVFMV_V_FPR16_MF2, VFMV_V_F, 0x7, 0x0 }, // 1940 { PseudoVFMV_V_FPR32_MF2, VFMV_V_F, 0x7, 0x0 }, // 1941 { PseudoVFNCVTBF16_F_F_W_M1_E16, VFNCVTBF16_F_F_W, 0x0, 0x10 }, // 1942 { PseudoVFNCVTBF16_F_F_W_M1_E16_MASK, VFNCVTBF16_F_F_W, 0x0, 0x10 }, // 1943 { PseudoVFNCVTBF16_F_F_W_M1_E32, VFNCVTBF16_F_F_W, 0x0, 0x20 }, // 1944 { PseudoVFNCVTBF16_F_F_W_M1_E32_MASK, VFNCVTBF16_F_F_W, 0x0, 0x20 }, // 1945 { PseudoVFNCVTBF16_F_F_W_M2_E16, VFNCVTBF16_F_F_W, 0x1, 0x10 }, // 1946 { PseudoVFNCVTBF16_F_F_W_M2_E16_MASK, VFNCVTBF16_F_F_W, 0x1, 0x10 }, // 1947 { PseudoVFNCVTBF16_F_F_W_M2_E32, VFNCVTBF16_F_F_W, 0x1, 0x20 }, // 1948 { PseudoVFNCVTBF16_F_F_W_M2_E32_MASK, VFNCVTBF16_F_F_W, 0x1, 0x20 }, // 1949 { PseudoVFNCVTBF16_F_F_W_M4_E16, VFNCVTBF16_F_F_W, 0x2, 0x10 }, // 1950 { PseudoVFNCVTBF16_F_F_W_M4_E16_MASK, VFNCVTBF16_F_F_W, 0x2, 0x10 }, // 1951 { PseudoVFNCVTBF16_F_F_W_M4_E32, VFNCVTBF16_F_F_W, 0x2, 0x20 }, // 1952 { PseudoVFNCVTBF16_F_F_W_M4_E32_MASK, VFNCVTBF16_F_F_W, 0x2, 0x20 }, // 1953 { PseudoVFNCVTBF16_F_F_W_MF4_E16, VFNCVTBF16_F_F_W, 0x6, 0x10 }, // 1954 { PseudoVFNCVTBF16_F_F_W_MF4_E16_MASK, VFNCVTBF16_F_F_W, 0x6, 0x10 }, // 1955 { PseudoVFNCVTBF16_F_F_W_MF2_E16, VFNCVTBF16_F_F_W, 0x7, 0x10 }, // 1956 { PseudoVFNCVTBF16_F_F_W_MF2_E16_MASK, VFNCVTBF16_F_F_W, 0x7, 0x10 }, // 1957 { PseudoVFNCVTBF16_F_F_W_MF2_E32, VFNCVTBF16_F_F_W, 0x7, 0x20 }, // 1958 { PseudoVFNCVTBF16_F_F_W_MF2_E32_MASK, VFNCVTBF16_F_F_W, 0x7, 0x20 }, // 1959 { PseudoVFNCVT_F_F_W_M1_E16, VFNCVT_F_F_W, 0x0, 0x10 }, // 1960 { PseudoVFNCVT_F_F_W_M1_E16_MASK, VFNCVT_F_F_W, 0x0, 0x10 }, // 1961 { PseudoVFNCVT_F_F_W_M1_E32, VFNCVT_F_F_W, 0x0, 0x20 }, // 1962 { PseudoVFNCVT_F_F_W_M1_E32_MASK, VFNCVT_F_F_W, 0x0, 0x20 }, // 1963 { PseudoVFNCVT_F_F_W_M2_E16, VFNCVT_F_F_W, 0x1, 0x10 }, // 1964 { PseudoVFNCVT_F_F_W_M2_E16_MASK, VFNCVT_F_F_W, 0x1, 0x10 }, // 1965 { PseudoVFNCVT_F_F_W_M2_E32, VFNCVT_F_F_W, 0x1, 0x20 }, // 1966 { PseudoVFNCVT_F_F_W_M2_E32_MASK, VFNCVT_F_F_W, 0x1, 0x20 }, // 1967 { PseudoVFNCVT_F_F_W_M4_E16, VFNCVT_F_F_W, 0x2, 0x10 }, // 1968 { PseudoVFNCVT_F_F_W_M4_E16_MASK, VFNCVT_F_F_W, 0x2, 0x10 }, // 1969 { PseudoVFNCVT_F_F_W_M4_E32, VFNCVT_F_F_W, 0x2, 0x20 }, // 1970 { PseudoVFNCVT_F_F_W_M4_E32_MASK, VFNCVT_F_F_W, 0x2, 0x20 }, // 1971 { PseudoVFNCVT_F_F_W_MF4_E16, VFNCVT_F_F_W, 0x6, 0x10 }, // 1972 { PseudoVFNCVT_F_F_W_MF4_E16_MASK, VFNCVT_F_F_W, 0x6, 0x10 }, // 1973 { PseudoVFNCVT_F_F_W_MF2_E16, VFNCVT_F_F_W, 0x7, 0x10 }, // 1974 { PseudoVFNCVT_F_F_W_MF2_E16_MASK, VFNCVT_F_F_W, 0x7, 0x10 }, // 1975 { PseudoVFNCVT_F_F_W_MF2_E32, VFNCVT_F_F_W, 0x7, 0x20 }, // 1976 { PseudoVFNCVT_F_F_W_MF2_E32_MASK, VFNCVT_F_F_W, 0x7, 0x20 }, // 1977 { PseudoVFNCVT_F_XU_W_M1_E16, VFNCVT_F_XU_W, 0x0, 0x10 }, // 1978 { PseudoVFNCVT_F_XU_W_M1_E16_MASK, VFNCVT_F_XU_W, 0x0, 0x10 }, // 1979 { PseudoVFNCVT_RM_F_XU_W_M1_E16, VFNCVT_F_XU_W, 0x0, 0x10 }, // 1980 { PseudoVFNCVT_RM_F_XU_W_M1_E16_MASK, VFNCVT_F_XU_W, 0x0, 0x10 }, // 1981 { PseudoVFNCVT_F_XU_W_M1_E32, VFNCVT_F_XU_W, 0x0, 0x20 }, // 1982 { PseudoVFNCVT_F_XU_W_M1_E32_MASK, VFNCVT_F_XU_W, 0x0, 0x20 }, // 1983 { PseudoVFNCVT_RM_F_XU_W_M1_E32, VFNCVT_F_XU_W, 0x0, 0x20 }, // 1984 { PseudoVFNCVT_RM_F_XU_W_M1_E32_MASK, VFNCVT_F_XU_W, 0x0, 0x20 }, // 1985 { PseudoVFNCVT_F_XU_W_M2_E16, VFNCVT_F_XU_W, 0x1, 0x10 }, // 1986 { PseudoVFNCVT_F_XU_W_M2_E16_MASK, VFNCVT_F_XU_W, 0x1, 0x10 }, // 1987 { PseudoVFNCVT_RM_F_XU_W_M2_E16, VFNCVT_F_XU_W, 0x1, 0x10 }, // 1988 { PseudoVFNCVT_RM_F_XU_W_M2_E16_MASK, VFNCVT_F_XU_W, 0x1, 0x10 }, // 1989 { PseudoVFNCVT_F_XU_W_M2_E32, VFNCVT_F_XU_W, 0x1, 0x20 }, // 1990 { PseudoVFNCVT_F_XU_W_M2_E32_MASK, VFNCVT_F_XU_W, 0x1, 0x20 }, // 1991 { PseudoVFNCVT_RM_F_XU_W_M2_E32, VFNCVT_F_XU_W, 0x1, 0x20 }, // 1992 { PseudoVFNCVT_RM_F_XU_W_M2_E32_MASK, VFNCVT_F_XU_W, 0x1, 0x20 }, // 1993 { PseudoVFNCVT_F_XU_W_M4_E16, VFNCVT_F_XU_W, 0x2, 0x10 }, // 1994 { PseudoVFNCVT_F_XU_W_M4_E16_MASK, VFNCVT_F_XU_W, 0x2, 0x10 }, // 1995 { PseudoVFNCVT_RM_F_XU_W_M4_E16, VFNCVT_F_XU_W, 0x2, 0x10 }, // 1996 { PseudoVFNCVT_RM_F_XU_W_M4_E16_MASK, VFNCVT_F_XU_W, 0x2, 0x10 }, // 1997 { PseudoVFNCVT_F_XU_W_M4_E32, VFNCVT_F_XU_W, 0x2, 0x20 }, // 1998 { PseudoVFNCVT_F_XU_W_M4_E32_MASK, VFNCVT_F_XU_W, 0x2, 0x20 }, // 1999 { PseudoVFNCVT_RM_F_XU_W_M4_E32, VFNCVT_F_XU_W, 0x2, 0x20 }, // 2000 { PseudoVFNCVT_RM_F_XU_W_M4_E32_MASK, VFNCVT_F_XU_W, 0x2, 0x20 }, // 2001 { PseudoVFNCVT_F_XU_W_MF4_E16, VFNCVT_F_XU_W, 0x6, 0x10 }, // 2002 { PseudoVFNCVT_F_XU_W_MF4_E16_MASK, VFNCVT_F_XU_W, 0x6, 0x10 }, // 2003 { PseudoVFNCVT_RM_F_XU_W_MF4_E16, VFNCVT_F_XU_W, 0x6, 0x10 }, // 2004 { PseudoVFNCVT_RM_F_XU_W_MF4_E16_MASK, VFNCVT_F_XU_W, 0x6, 0x10 }, // 2005 { PseudoVFNCVT_F_XU_W_MF2_E16, VFNCVT_F_XU_W, 0x7, 0x10 }, // 2006 { PseudoVFNCVT_F_XU_W_MF2_E16_MASK, VFNCVT_F_XU_W, 0x7, 0x10 }, // 2007 { PseudoVFNCVT_RM_F_XU_W_MF2_E16, VFNCVT_F_XU_W, 0x7, 0x10 }, // 2008 { PseudoVFNCVT_RM_F_XU_W_MF2_E16_MASK, VFNCVT_F_XU_W, 0x7, 0x10 }, // 2009 { PseudoVFNCVT_F_XU_W_MF2_E32, VFNCVT_F_XU_W, 0x7, 0x20 }, // 2010 { PseudoVFNCVT_F_XU_W_MF2_E32_MASK, VFNCVT_F_XU_W, 0x7, 0x20 }, // 2011 { PseudoVFNCVT_RM_F_XU_W_MF2_E32, VFNCVT_F_XU_W, 0x7, 0x20 }, // 2012 { PseudoVFNCVT_RM_F_XU_W_MF2_E32_MASK, VFNCVT_F_XU_W, 0x7, 0x20 }, // 2013 { PseudoVFNCVT_F_X_W_M1_E16, VFNCVT_F_X_W, 0x0, 0x10 }, // 2014 { PseudoVFNCVT_F_X_W_M1_E16_MASK, VFNCVT_F_X_W, 0x0, 0x10 }, // 2015 { PseudoVFNCVT_RM_F_X_W_M1_E16, VFNCVT_F_X_W, 0x0, 0x10 }, // 2016 { PseudoVFNCVT_RM_F_X_W_M1_E16_MASK, VFNCVT_F_X_W, 0x0, 0x10 }, // 2017 { PseudoVFNCVT_F_X_W_M1_E32, VFNCVT_F_X_W, 0x0, 0x20 }, // 2018 { PseudoVFNCVT_F_X_W_M1_E32_MASK, VFNCVT_F_X_W, 0x0, 0x20 }, // 2019 { PseudoVFNCVT_RM_F_X_W_M1_E32, VFNCVT_F_X_W, 0x0, 0x20 }, // 2020 { PseudoVFNCVT_RM_F_X_W_M1_E32_MASK, VFNCVT_F_X_W, 0x0, 0x20 }, // 2021 { PseudoVFNCVT_F_X_W_M2_E16, VFNCVT_F_X_W, 0x1, 0x10 }, // 2022 { PseudoVFNCVT_F_X_W_M2_E16_MASK, VFNCVT_F_X_W, 0x1, 0x10 }, // 2023 { PseudoVFNCVT_RM_F_X_W_M2_E16, VFNCVT_F_X_W, 0x1, 0x10 }, // 2024 { PseudoVFNCVT_RM_F_X_W_M2_E16_MASK, VFNCVT_F_X_W, 0x1, 0x10 }, // 2025 { PseudoVFNCVT_F_X_W_M2_E32, VFNCVT_F_X_W, 0x1, 0x20 }, // 2026 { PseudoVFNCVT_F_X_W_M2_E32_MASK, VFNCVT_F_X_W, 0x1, 0x20 }, // 2027 { PseudoVFNCVT_RM_F_X_W_M2_E32, VFNCVT_F_X_W, 0x1, 0x20 }, // 2028 { PseudoVFNCVT_RM_F_X_W_M2_E32_MASK, VFNCVT_F_X_W, 0x1, 0x20 }, // 2029 { PseudoVFNCVT_F_X_W_M4_E16, VFNCVT_F_X_W, 0x2, 0x10 }, // 2030 { PseudoVFNCVT_F_X_W_M4_E16_MASK, VFNCVT_F_X_W, 0x2, 0x10 }, // 2031 { PseudoVFNCVT_RM_F_X_W_M4_E16, VFNCVT_F_X_W, 0x2, 0x10 }, // 2032 { PseudoVFNCVT_RM_F_X_W_M4_E16_MASK, VFNCVT_F_X_W, 0x2, 0x10 }, // 2033 { PseudoVFNCVT_F_X_W_M4_E32, VFNCVT_F_X_W, 0x2, 0x20 }, // 2034 { PseudoVFNCVT_F_X_W_M4_E32_MASK, VFNCVT_F_X_W, 0x2, 0x20 }, // 2035 { PseudoVFNCVT_RM_F_X_W_M4_E32, VFNCVT_F_X_W, 0x2, 0x20 }, // 2036 { PseudoVFNCVT_RM_F_X_W_M4_E32_MASK, VFNCVT_F_X_W, 0x2, 0x20 }, // 2037 { PseudoVFNCVT_F_X_W_MF4_E16, VFNCVT_F_X_W, 0x6, 0x10 }, // 2038 { PseudoVFNCVT_F_X_W_MF4_E16_MASK, VFNCVT_F_X_W, 0x6, 0x10 }, // 2039 { PseudoVFNCVT_RM_F_X_W_MF4_E16, VFNCVT_F_X_W, 0x6, 0x10 }, // 2040 { PseudoVFNCVT_RM_F_X_W_MF4_E16_MASK, VFNCVT_F_X_W, 0x6, 0x10 }, // 2041 { PseudoVFNCVT_F_X_W_MF2_E16, VFNCVT_F_X_W, 0x7, 0x10 }, // 2042 { PseudoVFNCVT_F_X_W_MF2_E16_MASK, VFNCVT_F_X_W, 0x7, 0x10 }, // 2043 { PseudoVFNCVT_RM_F_X_W_MF2_E16, VFNCVT_F_X_W, 0x7, 0x10 }, // 2044 { PseudoVFNCVT_RM_F_X_W_MF2_E16_MASK, VFNCVT_F_X_W, 0x7, 0x10 }, // 2045 { PseudoVFNCVT_F_X_W_MF2_E32, VFNCVT_F_X_W, 0x7, 0x20 }, // 2046 { PseudoVFNCVT_F_X_W_MF2_E32_MASK, VFNCVT_F_X_W, 0x7, 0x20 }, // 2047 { PseudoVFNCVT_RM_F_X_W_MF2_E32, VFNCVT_F_X_W, 0x7, 0x20 }, // 2048 { PseudoVFNCVT_RM_F_X_W_MF2_E32_MASK, VFNCVT_F_X_W, 0x7, 0x20 }, // 2049 { PseudoVFNCVT_ROD_F_F_W_M1_E16, VFNCVT_ROD_F_F_W, 0x0, 0x10 }, // 2050 { PseudoVFNCVT_ROD_F_F_W_M1_E16_MASK, VFNCVT_ROD_F_F_W, 0x0, 0x10 }, // 2051 { PseudoVFNCVT_ROD_F_F_W_M1_E32, VFNCVT_ROD_F_F_W, 0x0, 0x20 }, // 2052 { PseudoVFNCVT_ROD_F_F_W_M1_E32_MASK, VFNCVT_ROD_F_F_W, 0x0, 0x20 }, // 2053 { PseudoVFNCVT_ROD_F_F_W_M2_E16, VFNCVT_ROD_F_F_W, 0x1, 0x10 }, // 2054 { PseudoVFNCVT_ROD_F_F_W_M2_E16_MASK, VFNCVT_ROD_F_F_W, 0x1, 0x10 }, // 2055 { PseudoVFNCVT_ROD_F_F_W_M2_E32, VFNCVT_ROD_F_F_W, 0x1, 0x20 }, // 2056 { PseudoVFNCVT_ROD_F_F_W_M2_E32_MASK, VFNCVT_ROD_F_F_W, 0x1, 0x20 }, // 2057 { PseudoVFNCVT_ROD_F_F_W_M4_E16, VFNCVT_ROD_F_F_W, 0x2, 0x10 }, // 2058 { PseudoVFNCVT_ROD_F_F_W_M4_E16_MASK, VFNCVT_ROD_F_F_W, 0x2, 0x10 }, // 2059 { PseudoVFNCVT_ROD_F_F_W_M4_E32, VFNCVT_ROD_F_F_W, 0x2, 0x20 }, // 2060 { PseudoVFNCVT_ROD_F_F_W_M4_E32_MASK, VFNCVT_ROD_F_F_W, 0x2, 0x20 }, // 2061 { PseudoVFNCVT_ROD_F_F_W_MF4_E16, VFNCVT_ROD_F_F_W, 0x6, 0x10 }, // 2062 { PseudoVFNCVT_ROD_F_F_W_MF4_E16_MASK, VFNCVT_ROD_F_F_W, 0x6, 0x10 }, // 2063 { PseudoVFNCVT_ROD_F_F_W_MF2_E16, VFNCVT_ROD_F_F_W, 0x7, 0x10 }, // 2064 { PseudoVFNCVT_ROD_F_F_W_MF2_E16_MASK, VFNCVT_ROD_F_F_W, 0x7, 0x10 }, // 2065 { PseudoVFNCVT_ROD_F_F_W_MF2_E32, VFNCVT_ROD_F_F_W, 0x7, 0x20 }, // 2066 { PseudoVFNCVT_ROD_F_F_W_MF2_E32_MASK, VFNCVT_ROD_F_F_W, 0x7, 0x20 }, // 2067 { PseudoVFNCVT_RTZ_XU_F_W_M1, VFNCVT_RTZ_XU_F_W, 0x0, 0x0 }, // 2068 { PseudoVFNCVT_RTZ_XU_F_W_M1_MASK, VFNCVT_RTZ_XU_F_W, 0x0, 0x0 }, // 2069 { PseudoVFNCVT_RTZ_XU_F_W_M2, VFNCVT_RTZ_XU_F_W, 0x1, 0x0 }, // 2070 { PseudoVFNCVT_RTZ_XU_F_W_M2_MASK, VFNCVT_RTZ_XU_F_W, 0x1, 0x0 }, // 2071 { PseudoVFNCVT_RTZ_XU_F_W_M4, VFNCVT_RTZ_XU_F_W, 0x2, 0x0 }, // 2072 { PseudoVFNCVT_RTZ_XU_F_W_M4_MASK, VFNCVT_RTZ_XU_F_W, 0x2, 0x0 }, // 2073 { PseudoVFNCVT_RTZ_XU_F_W_MF8, VFNCVT_RTZ_XU_F_W, 0x5, 0x0 }, // 2074 { PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK, VFNCVT_RTZ_XU_F_W, 0x5, 0x0 }, // 2075 { PseudoVFNCVT_RTZ_XU_F_W_MF4, VFNCVT_RTZ_XU_F_W, 0x6, 0x0 }, // 2076 { PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK, VFNCVT_RTZ_XU_F_W, 0x6, 0x0 }, // 2077 { PseudoVFNCVT_RTZ_XU_F_W_MF2, VFNCVT_RTZ_XU_F_W, 0x7, 0x0 }, // 2078 { PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK, VFNCVT_RTZ_XU_F_W, 0x7, 0x0 }, // 2079 { PseudoVFNCVT_RTZ_X_F_W_M1, VFNCVT_RTZ_X_F_W, 0x0, 0x0 }, // 2080 { PseudoVFNCVT_RTZ_X_F_W_M1_MASK, VFNCVT_RTZ_X_F_W, 0x0, 0x0 }, // 2081 { PseudoVFNCVT_RTZ_X_F_W_M2, VFNCVT_RTZ_X_F_W, 0x1, 0x0 }, // 2082 { PseudoVFNCVT_RTZ_X_F_W_M2_MASK, VFNCVT_RTZ_X_F_W, 0x1, 0x0 }, // 2083 { PseudoVFNCVT_RTZ_X_F_W_M4, VFNCVT_RTZ_X_F_W, 0x2, 0x0 }, // 2084 { PseudoVFNCVT_RTZ_X_F_W_M4_MASK, VFNCVT_RTZ_X_F_W, 0x2, 0x0 }, // 2085 { PseudoVFNCVT_RTZ_X_F_W_MF8, VFNCVT_RTZ_X_F_W, 0x5, 0x0 }, // 2086 { PseudoVFNCVT_RTZ_X_F_W_MF8_MASK, VFNCVT_RTZ_X_F_W, 0x5, 0x0 }, // 2087 { PseudoVFNCVT_RTZ_X_F_W_MF4, VFNCVT_RTZ_X_F_W, 0x6, 0x0 }, // 2088 { PseudoVFNCVT_RTZ_X_F_W_MF4_MASK, VFNCVT_RTZ_X_F_W, 0x6, 0x0 }, // 2089 { PseudoVFNCVT_RTZ_X_F_W_MF2, VFNCVT_RTZ_X_F_W, 0x7, 0x0 }, // 2090 { PseudoVFNCVT_RTZ_X_F_W_MF2_MASK, VFNCVT_RTZ_X_F_W, 0x7, 0x0 }, // 2091 { PseudoVFNCVT_RM_XU_F_W_M1, VFNCVT_XU_F_W, 0x0, 0x0 }, // 2092 { PseudoVFNCVT_RM_XU_F_W_M1_MASK, VFNCVT_XU_F_W, 0x0, 0x0 }, // 2093 { PseudoVFNCVT_XU_F_W_M1, VFNCVT_XU_F_W, 0x0, 0x0 }, // 2094 { PseudoVFNCVT_XU_F_W_M1_MASK, VFNCVT_XU_F_W, 0x0, 0x0 }, // 2095 { PseudoVFNCVT_RM_XU_F_W_M2, VFNCVT_XU_F_W, 0x1, 0x0 }, // 2096 { PseudoVFNCVT_RM_XU_F_W_M2_MASK, VFNCVT_XU_F_W, 0x1, 0x0 }, // 2097 { PseudoVFNCVT_XU_F_W_M2, VFNCVT_XU_F_W, 0x1, 0x0 }, // 2098 { PseudoVFNCVT_XU_F_W_M2_MASK, VFNCVT_XU_F_W, 0x1, 0x0 }, // 2099 { PseudoVFNCVT_RM_XU_F_W_M4, VFNCVT_XU_F_W, 0x2, 0x0 }, // 2100 { PseudoVFNCVT_RM_XU_F_W_M4_MASK, VFNCVT_XU_F_W, 0x2, 0x0 }, // 2101 { PseudoVFNCVT_XU_F_W_M4, VFNCVT_XU_F_W, 0x2, 0x0 }, // 2102 { PseudoVFNCVT_XU_F_W_M4_MASK, VFNCVT_XU_F_W, 0x2, 0x0 }, // 2103 { PseudoVFNCVT_RM_XU_F_W_MF8, VFNCVT_XU_F_W, 0x5, 0x0 }, // 2104 { PseudoVFNCVT_RM_XU_F_W_MF8_MASK, VFNCVT_XU_F_W, 0x5, 0x0 }, // 2105 { PseudoVFNCVT_XU_F_W_MF8, VFNCVT_XU_F_W, 0x5, 0x0 }, // 2106 { PseudoVFNCVT_XU_F_W_MF8_MASK, VFNCVT_XU_F_W, 0x5, 0x0 }, // 2107 { PseudoVFNCVT_RM_XU_F_W_MF4, VFNCVT_XU_F_W, 0x6, 0x0 }, // 2108 { PseudoVFNCVT_RM_XU_F_W_MF4_MASK, VFNCVT_XU_F_W, 0x6, 0x0 }, // 2109 { PseudoVFNCVT_XU_F_W_MF4, VFNCVT_XU_F_W, 0x6, 0x0 }, // 2110 { PseudoVFNCVT_XU_F_W_MF4_MASK, VFNCVT_XU_F_W, 0x6, 0x0 }, // 2111 { PseudoVFNCVT_RM_XU_F_W_MF2, VFNCVT_XU_F_W, 0x7, 0x0 }, // 2112 { PseudoVFNCVT_RM_XU_F_W_MF2_MASK, VFNCVT_XU_F_W, 0x7, 0x0 }, // 2113 { PseudoVFNCVT_XU_F_W_MF2, VFNCVT_XU_F_W, 0x7, 0x0 }, // 2114 { PseudoVFNCVT_XU_F_W_MF2_MASK, VFNCVT_XU_F_W, 0x7, 0x0 }, // 2115 { PseudoVFNCVT_RM_X_F_W_M1, VFNCVT_X_F_W, 0x0, 0x0 }, // 2116 { PseudoVFNCVT_RM_X_F_W_M1_MASK, VFNCVT_X_F_W, 0x0, 0x0 }, // 2117 { PseudoVFNCVT_X_F_W_M1, VFNCVT_X_F_W, 0x0, 0x0 }, // 2118 { PseudoVFNCVT_X_F_W_M1_MASK, VFNCVT_X_F_W, 0x0, 0x0 }, // 2119 { PseudoVFNCVT_RM_X_F_W_M2, VFNCVT_X_F_W, 0x1, 0x0 }, // 2120 { PseudoVFNCVT_RM_X_F_W_M2_MASK, VFNCVT_X_F_W, 0x1, 0x0 }, // 2121 { PseudoVFNCVT_X_F_W_M2, VFNCVT_X_F_W, 0x1, 0x0 }, // 2122 { PseudoVFNCVT_X_F_W_M2_MASK, VFNCVT_X_F_W, 0x1, 0x0 }, // 2123 { PseudoVFNCVT_RM_X_F_W_M4, VFNCVT_X_F_W, 0x2, 0x0 }, // 2124 { PseudoVFNCVT_RM_X_F_W_M4_MASK, VFNCVT_X_F_W, 0x2, 0x0 }, // 2125 { PseudoVFNCVT_X_F_W_M4, VFNCVT_X_F_W, 0x2, 0x0 }, // 2126 { PseudoVFNCVT_X_F_W_M4_MASK, VFNCVT_X_F_W, 0x2, 0x0 }, // 2127 { PseudoVFNCVT_RM_X_F_W_MF8, VFNCVT_X_F_W, 0x5, 0x0 }, // 2128 { PseudoVFNCVT_RM_X_F_W_MF8_MASK, VFNCVT_X_F_W, 0x5, 0x0 }, // 2129 { PseudoVFNCVT_X_F_W_MF8, VFNCVT_X_F_W, 0x5, 0x0 }, // 2130 { PseudoVFNCVT_X_F_W_MF8_MASK, VFNCVT_X_F_W, 0x5, 0x0 }, // 2131 { PseudoVFNCVT_RM_X_F_W_MF4, VFNCVT_X_F_W, 0x6, 0x0 }, // 2132 { PseudoVFNCVT_RM_X_F_W_MF4_MASK, VFNCVT_X_F_W, 0x6, 0x0 }, // 2133 { PseudoVFNCVT_X_F_W_MF4, VFNCVT_X_F_W, 0x6, 0x0 }, // 2134 { PseudoVFNCVT_X_F_W_MF4_MASK, VFNCVT_X_F_W, 0x6, 0x0 }, // 2135 { PseudoVFNCVT_RM_X_F_W_MF2, VFNCVT_X_F_W, 0x7, 0x0 }, // 2136 { PseudoVFNCVT_RM_X_F_W_MF2_MASK, VFNCVT_X_F_W, 0x7, 0x0 }, // 2137 { PseudoVFNCVT_X_F_W_MF2, VFNCVT_X_F_W, 0x7, 0x0 }, // 2138 { PseudoVFNCVT_X_F_W_MF2_MASK, VFNCVT_X_F_W, 0x7, 0x0 }, // 2139 { PseudoVFNMACC_VFPR16_M1_E16, VFNMACC_VF, 0x0, 0x0 }, // 2140 { PseudoVFNMACC_VFPR16_M1_E16_MASK, VFNMACC_VF, 0x0, 0x0 }, // 2141 { PseudoVFNMACC_VFPR32_M1_E32, VFNMACC_VF, 0x0, 0x0 }, // 2142 { PseudoVFNMACC_VFPR32_M1_E32_MASK, VFNMACC_VF, 0x0, 0x0 }, // 2143 { PseudoVFNMACC_VFPR64_M1_E64, VFNMACC_VF, 0x0, 0x0 }, // 2144 { PseudoVFNMACC_VFPR64_M1_E64_MASK, VFNMACC_VF, 0x0, 0x0 }, // 2145 { PseudoVFNMACC_VFPR16_M2_E16, VFNMACC_VF, 0x1, 0x0 }, // 2146 { PseudoVFNMACC_VFPR16_M2_E16_MASK, VFNMACC_VF, 0x1, 0x0 }, // 2147 { PseudoVFNMACC_VFPR32_M2_E32, VFNMACC_VF, 0x1, 0x0 }, // 2148 { PseudoVFNMACC_VFPR32_M2_E32_MASK, VFNMACC_VF, 0x1, 0x0 }, // 2149 { PseudoVFNMACC_VFPR64_M2_E64, VFNMACC_VF, 0x1, 0x0 }, // 2150 { PseudoVFNMACC_VFPR64_M2_E64_MASK, VFNMACC_VF, 0x1, 0x0 }, // 2151 { PseudoVFNMACC_VFPR16_M4_E16, VFNMACC_VF, 0x2, 0x0 }, // 2152 { PseudoVFNMACC_VFPR16_M4_E16_MASK, VFNMACC_VF, 0x2, 0x0 }, // 2153 { PseudoVFNMACC_VFPR32_M4_E32, VFNMACC_VF, 0x2, 0x0 }, // 2154 { PseudoVFNMACC_VFPR32_M4_E32_MASK, VFNMACC_VF, 0x2, 0x0 }, // 2155 { PseudoVFNMACC_VFPR64_M4_E64, VFNMACC_VF, 0x2, 0x0 }, // 2156 { PseudoVFNMACC_VFPR64_M4_E64_MASK, VFNMACC_VF, 0x2, 0x0 }, // 2157 { PseudoVFNMACC_VFPR16_M8_E16, VFNMACC_VF, 0x3, 0x0 }, // 2158 { PseudoVFNMACC_VFPR16_M8_E16_MASK, VFNMACC_VF, 0x3, 0x0 }, // 2159 { PseudoVFNMACC_VFPR32_M8_E32, VFNMACC_VF, 0x3, 0x0 }, // 2160 { PseudoVFNMACC_VFPR32_M8_E32_MASK, VFNMACC_VF, 0x3, 0x0 }, // 2161 { PseudoVFNMACC_VFPR64_M8_E64, VFNMACC_VF, 0x3, 0x0 }, // 2162 { PseudoVFNMACC_VFPR64_M8_E64_MASK, VFNMACC_VF, 0x3, 0x0 }, // 2163 { PseudoVFNMACC_VFPR16_MF4_E16, VFNMACC_VF, 0x6, 0x0 }, // 2164 { PseudoVFNMACC_VFPR16_MF4_E16_MASK, VFNMACC_VF, 0x6, 0x0 }, // 2165 { PseudoVFNMACC_VFPR16_MF2_E16, VFNMACC_VF, 0x7, 0x0 }, // 2166 { PseudoVFNMACC_VFPR16_MF2_E16_MASK, VFNMACC_VF, 0x7, 0x0 }, // 2167 { PseudoVFNMACC_VFPR32_MF2_E32, VFNMACC_VF, 0x7, 0x0 }, // 2168 { PseudoVFNMACC_VFPR32_MF2_E32_MASK, VFNMACC_VF, 0x7, 0x0 }, // 2169 { PseudoVFNMACC_VV_M1_E16, VFNMACC_VV, 0x0, 0x0 }, // 2170 { PseudoVFNMACC_VV_M1_E16_MASK, VFNMACC_VV, 0x0, 0x0 }, // 2171 { PseudoVFNMACC_VV_M1_E32, VFNMACC_VV, 0x0, 0x0 }, // 2172 { PseudoVFNMACC_VV_M1_E32_MASK, VFNMACC_VV, 0x0, 0x0 }, // 2173 { PseudoVFNMACC_VV_M1_E64, VFNMACC_VV, 0x0, 0x0 }, // 2174 { PseudoVFNMACC_VV_M1_E64_MASK, VFNMACC_VV, 0x0, 0x0 }, // 2175 { PseudoVFNMACC_VV_M2_E16, VFNMACC_VV, 0x1, 0x0 }, // 2176 { PseudoVFNMACC_VV_M2_E16_MASK, VFNMACC_VV, 0x1, 0x0 }, // 2177 { PseudoVFNMACC_VV_M2_E32, VFNMACC_VV, 0x1, 0x0 }, // 2178 { PseudoVFNMACC_VV_M2_E32_MASK, VFNMACC_VV, 0x1, 0x0 }, // 2179 { PseudoVFNMACC_VV_M2_E64, VFNMACC_VV, 0x1, 0x0 }, // 2180 { PseudoVFNMACC_VV_M2_E64_MASK, VFNMACC_VV, 0x1, 0x0 }, // 2181 { PseudoVFNMACC_VV_M4_E16, VFNMACC_VV, 0x2, 0x0 }, // 2182 { PseudoVFNMACC_VV_M4_E16_MASK, VFNMACC_VV, 0x2, 0x0 }, // 2183 { PseudoVFNMACC_VV_M4_E32, VFNMACC_VV, 0x2, 0x0 }, // 2184 { PseudoVFNMACC_VV_M4_E32_MASK, VFNMACC_VV, 0x2, 0x0 }, // 2185 { PseudoVFNMACC_VV_M4_E64, VFNMACC_VV, 0x2, 0x0 }, // 2186 { PseudoVFNMACC_VV_M4_E64_MASK, VFNMACC_VV, 0x2, 0x0 }, // 2187 { PseudoVFNMACC_VV_M8_E16, VFNMACC_VV, 0x3, 0x0 }, // 2188 { PseudoVFNMACC_VV_M8_E16_MASK, VFNMACC_VV, 0x3, 0x0 }, // 2189 { PseudoVFNMACC_VV_M8_E32, VFNMACC_VV, 0x3, 0x0 }, // 2190 { PseudoVFNMACC_VV_M8_E32_MASK, VFNMACC_VV, 0x3, 0x0 }, // 2191 { PseudoVFNMACC_VV_M8_E64, VFNMACC_VV, 0x3, 0x0 }, // 2192 { PseudoVFNMACC_VV_M8_E64_MASK, VFNMACC_VV, 0x3, 0x0 }, // 2193 { PseudoVFNMACC_VV_MF4_E16, VFNMACC_VV, 0x6, 0x0 }, // 2194 { PseudoVFNMACC_VV_MF4_E16_MASK, VFNMACC_VV, 0x6, 0x0 }, // 2195 { PseudoVFNMACC_VV_MF2_E16, VFNMACC_VV, 0x7, 0x0 }, // 2196 { PseudoVFNMACC_VV_MF2_E16_MASK, VFNMACC_VV, 0x7, 0x0 }, // 2197 { PseudoVFNMACC_VV_MF2_E32, VFNMACC_VV, 0x7, 0x0 }, // 2198 { PseudoVFNMACC_VV_MF2_E32_MASK, VFNMACC_VV, 0x7, 0x0 }, // 2199 { PseudoVFNMADD_VFPR16_M1_E16, VFNMADD_VF, 0x0, 0x0 }, // 2200 { PseudoVFNMADD_VFPR16_M1_E16_MASK, VFNMADD_VF, 0x0, 0x0 }, // 2201 { PseudoVFNMADD_VFPR32_M1_E32, VFNMADD_VF, 0x0, 0x0 }, // 2202 { PseudoVFNMADD_VFPR32_M1_E32_MASK, VFNMADD_VF, 0x0, 0x0 }, // 2203 { PseudoVFNMADD_VFPR64_M1_E64, VFNMADD_VF, 0x0, 0x0 }, // 2204 { PseudoVFNMADD_VFPR64_M1_E64_MASK, VFNMADD_VF, 0x0, 0x0 }, // 2205 { PseudoVFNMADD_VFPR16_M2_E16, VFNMADD_VF, 0x1, 0x0 }, // 2206 { PseudoVFNMADD_VFPR16_M2_E16_MASK, VFNMADD_VF, 0x1, 0x0 }, // 2207 { PseudoVFNMADD_VFPR32_M2_E32, VFNMADD_VF, 0x1, 0x0 }, // 2208 { PseudoVFNMADD_VFPR32_M2_E32_MASK, VFNMADD_VF, 0x1, 0x0 }, // 2209 { PseudoVFNMADD_VFPR64_M2_E64, VFNMADD_VF, 0x1, 0x0 }, // 2210 { PseudoVFNMADD_VFPR64_M2_E64_MASK, VFNMADD_VF, 0x1, 0x0 }, // 2211 { PseudoVFNMADD_VFPR16_M4_E16, VFNMADD_VF, 0x2, 0x0 }, // 2212 { PseudoVFNMADD_VFPR16_M4_E16_MASK, VFNMADD_VF, 0x2, 0x0 }, // 2213 { PseudoVFNMADD_VFPR32_M4_E32, VFNMADD_VF, 0x2, 0x0 }, // 2214 { PseudoVFNMADD_VFPR32_M4_E32_MASK, VFNMADD_VF, 0x2, 0x0 }, // 2215 { PseudoVFNMADD_VFPR64_M4_E64, VFNMADD_VF, 0x2, 0x0 }, // 2216 { PseudoVFNMADD_VFPR64_M4_E64_MASK, VFNMADD_VF, 0x2, 0x0 }, // 2217 { PseudoVFNMADD_VFPR16_M8_E16, VFNMADD_VF, 0x3, 0x0 }, // 2218 { PseudoVFNMADD_VFPR16_M8_E16_MASK, VFNMADD_VF, 0x3, 0x0 }, // 2219 { PseudoVFNMADD_VFPR32_M8_E32, VFNMADD_VF, 0x3, 0x0 }, // 2220 { PseudoVFNMADD_VFPR32_M8_E32_MASK, VFNMADD_VF, 0x3, 0x0 }, // 2221 { PseudoVFNMADD_VFPR64_M8_E64, VFNMADD_VF, 0x3, 0x0 }, // 2222 { PseudoVFNMADD_VFPR64_M8_E64_MASK, VFNMADD_VF, 0x3, 0x0 }, // 2223 { PseudoVFNMADD_VFPR16_MF4_E16, VFNMADD_VF, 0x6, 0x0 }, // 2224 { PseudoVFNMADD_VFPR16_MF4_E16_MASK, VFNMADD_VF, 0x6, 0x0 }, // 2225 { PseudoVFNMADD_VFPR16_MF2_E16, VFNMADD_VF, 0x7, 0x0 }, // 2226 { PseudoVFNMADD_VFPR16_MF2_E16_MASK, VFNMADD_VF, 0x7, 0x0 }, // 2227 { PseudoVFNMADD_VFPR32_MF2_E32, VFNMADD_VF, 0x7, 0x0 }, // 2228 { PseudoVFNMADD_VFPR32_MF2_E32_MASK, VFNMADD_VF, 0x7, 0x0 }, // 2229 { PseudoVFNMADD_VV_M1_E16, VFNMADD_VV, 0x0, 0x0 }, // 2230 { PseudoVFNMADD_VV_M1_E16_MASK, VFNMADD_VV, 0x0, 0x0 }, // 2231 { PseudoVFNMADD_VV_M1_E32, VFNMADD_VV, 0x0, 0x0 }, // 2232 { PseudoVFNMADD_VV_M1_E32_MASK, VFNMADD_VV, 0x0, 0x0 }, // 2233 { PseudoVFNMADD_VV_M1_E64, VFNMADD_VV, 0x0, 0x0 }, // 2234 { PseudoVFNMADD_VV_M1_E64_MASK, VFNMADD_VV, 0x0, 0x0 }, // 2235 { PseudoVFNMADD_VV_M2_E16, VFNMADD_VV, 0x1, 0x0 }, // 2236 { PseudoVFNMADD_VV_M2_E16_MASK, VFNMADD_VV, 0x1, 0x0 }, // 2237 { PseudoVFNMADD_VV_M2_E32, VFNMADD_VV, 0x1, 0x0 }, // 2238 { PseudoVFNMADD_VV_M2_E32_MASK, VFNMADD_VV, 0x1, 0x0 }, // 2239 { PseudoVFNMADD_VV_M2_E64, VFNMADD_VV, 0x1, 0x0 }, // 2240 { PseudoVFNMADD_VV_M2_E64_MASK, VFNMADD_VV, 0x1, 0x0 }, // 2241 { PseudoVFNMADD_VV_M4_E16, VFNMADD_VV, 0x2, 0x0 }, // 2242 { PseudoVFNMADD_VV_M4_E16_MASK, VFNMADD_VV, 0x2, 0x0 }, // 2243 { PseudoVFNMADD_VV_M4_E32, VFNMADD_VV, 0x2, 0x0 }, // 2244 { PseudoVFNMADD_VV_M4_E32_MASK, VFNMADD_VV, 0x2, 0x0 }, // 2245 { PseudoVFNMADD_VV_M4_E64, VFNMADD_VV, 0x2, 0x0 }, // 2246 { PseudoVFNMADD_VV_M4_E64_MASK, VFNMADD_VV, 0x2, 0x0 }, // 2247 { PseudoVFNMADD_VV_M8_E16, VFNMADD_VV, 0x3, 0x0 }, // 2248 { PseudoVFNMADD_VV_M8_E16_MASK, VFNMADD_VV, 0x3, 0x0 }, // 2249 { PseudoVFNMADD_VV_M8_E32, VFNMADD_VV, 0x3, 0x0 }, // 2250 { PseudoVFNMADD_VV_M8_E32_MASK, VFNMADD_VV, 0x3, 0x0 }, // 2251 { PseudoVFNMADD_VV_M8_E64, VFNMADD_VV, 0x3, 0x0 }, // 2252 { PseudoVFNMADD_VV_M8_E64_MASK, VFNMADD_VV, 0x3, 0x0 }, // 2253 { PseudoVFNMADD_VV_MF4_E16, VFNMADD_VV, 0x6, 0x0 }, // 2254 { PseudoVFNMADD_VV_MF4_E16_MASK, VFNMADD_VV, 0x6, 0x0 }, // 2255 { PseudoVFNMADD_VV_MF2_E16, VFNMADD_VV, 0x7, 0x0 }, // 2256 { PseudoVFNMADD_VV_MF2_E16_MASK, VFNMADD_VV, 0x7, 0x0 }, // 2257 { PseudoVFNMADD_VV_MF2_E32, VFNMADD_VV, 0x7, 0x0 }, // 2258 { PseudoVFNMADD_VV_MF2_E32_MASK, VFNMADD_VV, 0x7, 0x0 }, // 2259 { PseudoVFNMSAC_VFPR16_M1_E16, VFNMSAC_VF, 0x0, 0x0 }, // 2260 { PseudoVFNMSAC_VFPR16_M1_E16_MASK, VFNMSAC_VF, 0x0, 0x0 }, // 2261 { PseudoVFNMSAC_VFPR32_M1_E32, VFNMSAC_VF, 0x0, 0x0 }, // 2262 { PseudoVFNMSAC_VFPR32_M1_E32_MASK, VFNMSAC_VF, 0x0, 0x0 }, // 2263 { PseudoVFNMSAC_VFPR64_M1_E64, VFNMSAC_VF, 0x0, 0x0 }, // 2264 { PseudoVFNMSAC_VFPR64_M1_E64_MASK, VFNMSAC_VF, 0x0, 0x0 }, // 2265 { PseudoVFNMSAC_VFPR16_M2_E16, VFNMSAC_VF, 0x1, 0x0 }, // 2266 { PseudoVFNMSAC_VFPR16_M2_E16_MASK, VFNMSAC_VF, 0x1, 0x0 }, // 2267 { PseudoVFNMSAC_VFPR32_M2_E32, VFNMSAC_VF, 0x1, 0x0 }, // 2268 { PseudoVFNMSAC_VFPR32_M2_E32_MASK, VFNMSAC_VF, 0x1, 0x0 }, // 2269 { PseudoVFNMSAC_VFPR64_M2_E64, VFNMSAC_VF, 0x1, 0x0 }, // 2270 { PseudoVFNMSAC_VFPR64_M2_E64_MASK, VFNMSAC_VF, 0x1, 0x0 }, // 2271 { PseudoVFNMSAC_VFPR16_M4_E16, VFNMSAC_VF, 0x2, 0x0 }, // 2272 { PseudoVFNMSAC_VFPR16_M4_E16_MASK, VFNMSAC_VF, 0x2, 0x0 }, // 2273 { PseudoVFNMSAC_VFPR32_M4_E32, VFNMSAC_VF, 0x2, 0x0 }, // 2274 { PseudoVFNMSAC_VFPR32_M4_E32_MASK, VFNMSAC_VF, 0x2, 0x0 }, // 2275 { PseudoVFNMSAC_VFPR64_M4_E64, VFNMSAC_VF, 0x2, 0x0 }, // 2276 { PseudoVFNMSAC_VFPR64_M4_E64_MASK, VFNMSAC_VF, 0x2, 0x0 }, // 2277 { PseudoVFNMSAC_VFPR16_M8_E16, VFNMSAC_VF, 0x3, 0x0 }, // 2278 { PseudoVFNMSAC_VFPR16_M8_E16_MASK, VFNMSAC_VF, 0x3, 0x0 }, // 2279 { PseudoVFNMSAC_VFPR32_M8_E32, VFNMSAC_VF, 0x3, 0x0 }, // 2280 { PseudoVFNMSAC_VFPR32_M8_E32_MASK, VFNMSAC_VF, 0x3, 0x0 }, // 2281 { PseudoVFNMSAC_VFPR64_M8_E64, VFNMSAC_VF, 0x3, 0x0 }, // 2282 { PseudoVFNMSAC_VFPR64_M8_E64_MASK, VFNMSAC_VF, 0x3, 0x0 }, // 2283 { PseudoVFNMSAC_VFPR16_MF4_E16, VFNMSAC_VF, 0x6, 0x0 }, // 2284 { PseudoVFNMSAC_VFPR16_MF4_E16_MASK, VFNMSAC_VF, 0x6, 0x0 }, // 2285 { PseudoVFNMSAC_VFPR16_MF2_E16, VFNMSAC_VF, 0x7, 0x0 }, // 2286 { PseudoVFNMSAC_VFPR16_MF2_E16_MASK, VFNMSAC_VF, 0x7, 0x0 }, // 2287 { PseudoVFNMSAC_VFPR32_MF2_E32, VFNMSAC_VF, 0x7, 0x0 }, // 2288 { PseudoVFNMSAC_VFPR32_MF2_E32_MASK, VFNMSAC_VF, 0x7, 0x0 }, // 2289 { PseudoVFNMSAC_VV_M1_E16, VFNMSAC_VV, 0x0, 0x0 }, // 2290 { PseudoVFNMSAC_VV_M1_E16_MASK, VFNMSAC_VV, 0x0, 0x0 }, // 2291 { PseudoVFNMSAC_VV_M1_E32, VFNMSAC_VV, 0x0, 0x0 }, // 2292 { PseudoVFNMSAC_VV_M1_E32_MASK, VFNMSAC_VV, 0x0, 0x0 }, // 2293 { PseudoVFNMSAC_VV_M1_E64, VFNMSAC_VV, 0x0, 0x0 }, // 2294 { PseudoVFNMSAC_VV_M1_E64_MASK, VFNMSAC_VV, 0x0, 0x0 }, // 2295 { PseudoVFNMSAC_VV_M2_E16, VFNMSAC_VV, 0x1, 0x0 }, // 2296 { PseudoVFNMSAC_VV_M2_E16_MASK, VFNMSAC_VV, 0x1, 0x0 }, // 2297 { PseudoVFNMSAC_VV_M2_E32, VFNMSAC_VV, 0x1, 0x0 }, // 2298 { PseudoVFNMSAC_VV_M2_E32_MASK, VFNMSAC_VV, 0x1, 0x0 }, // 2299 { PseudoVFNMSAC_VV_M2_E64, VFNMSAC_VV, 0x1, 0x0 }, // 2300 { PseudoVFNMSAC_VV_M2_E64_MASK, VFNMSAC_VV, 0x1, 0x0 }, // 2301 { PseudoVFNMSAC_VV_M4_E16, VFNMSAC_VV, 0x2, 0x0 }, // 2302 { PseudoVFNMSAC_VV_M4_E16_MASK, VFNMSAC_VV, 0x2, 0x0 }, // 2303 { PseudoVFNMSAC_VV_M4_E32, VFNMSAC_VV, 0x2, 0x0 }, // 2304 { PseudoVFNMSAC_VV_M4_E32_MASK, VFNMSAC_VV, 0x2, 0x0 }, // 2305 { PseudoVFNMSAC_VV_M4_E64, VFNMSAC_VV, 0x2, 0x0 }, // 2306 { PseudoVFNMSAC_VV_M4_E64_MASK, VFNMSAC_VV, 0x2, 0x0 }, // 2307 { PseudoVFNMSAC_VV_M8_E16, VFNMSAC_VV, 0x3, 0x0 }, // 2308 { PseudoVFNMSAC_VV_M8_E16_MASK, VFNMSAC_VV, 0x3, 0x0 }, // 2309 { PseudoVFNMSAC_VV_M8_E32, VFNMSAC_VV, 0x3, 0x0 }, // 2310 { PseudoVFNMSAC_VV_M8_E32_MASK, VFNMSAC_VV, 0x3, 0x0 }, // 2311 { PseudoVFNMSAC_VV_M8_E64, VFNMSAC_VV, 0x3, 0x0 }, // 2312 { PseudoVFNMSAC_VV_M8_E64_MASK, VFNMSAC_VV, 0x3, 0x0 }, // 2313 { PseudoVFNMSAC_VV_MF4_E16, VFNMSAC_VV, 0x6, 0x0 }, // 2314 { PseudoVFNMSAC_VV_MF4_E16_MASK, VFNMSAC_VV, 0x6, 0x0 }, // 2315 { PseudoVFNMSAC_VV_MF2_E16, VFNMSAC_VV, 0x7, 0x0 }, // 2316 { PseudoVFNMSAC_VV_MF2_E16_MASK, VFNMSAC_VV, 0x7, 0x0 }, // 2317 { PseudoVFNMSAC_VV_MF2_E32, VFNMSAC_VV, 0x7, 0x0 }, // 2318 { PseudoVFNMSAC_VV_MF2_E32_MASK, VFNMSAC_VV, 0x7, 0x0 }, // 2319 { PseudoVFNMSUB_VFPR16_M1_E16, VFNMSUB_VF, 0x0, 0x0 }, // 2320 { PseudoVFNMSUB_VFPR16_M1_E16_MASK, VFNMSUB_VF, 0x0, 0x0 }, // 2321 { PseudoVFNMSUB_VFPR32_M1_E32, VFNMSUB_VF, 0x0, 0x0 }, // 2322 { PseudoVFNMSUB_VFPR32_M1_E32_MASK, VFNMSUB_VF, 0x0, 0x0 }, // 2323 { PseudoVFNMSUB_VFPR64_M1_E64, VFNMSUB_VF, 0x0, 0x0 }, // 2324 { PseudoVFNMSUB_VFPR64_M1_E64_MASK, VFNMSUB_VF, 0x0, 0x0 }, // 2325 { PseudoVFNMSUB_VFPR16_M2_E16, VFNMSUB_VF, 0x1, 0x0 }, // 2326 { PseudoVFNMSUB_VFPR16_M2_E16_MASK, VFNMSUB_VF, 0x1, 0x0 }, // 2327 { PseudoVFNMSUB_VFPR32_M2_E32, VFNMSUB_VF, 0x1, 0x0 }, // 2328 { PseudoVFNMSUB_VFPR32_M2_E32_MASK, VFNMSUB_VF, 0x1, 0x0 }, // 2329 { PseudoVFNMSUB_VFPR64_M2_E64, VFNMSUB_VF, 0x1, 0x0 }, // 2330 { PseudoVFNMSUB_VFPR64_M2_E64_MASK, VFNMSUB_VF, 0x1, 0x0 }, // 2331 { PseudoVFNMSUB_VFPR16_M4_E16, VFNMSUB_VF, 0x2, 0x0 }, // 2332 { PseudoVFNMSUB_VFPR16_M4_E16_MASK, VFNMSUB_VF, 0x2, 0x0 }, // 2333 { PseudoVFNMSUB_VFPR32_M4_E32, VFNMSUB_VF, 0x2, 0x0 }, // 2334 { PseudoVFNMSUB_VFPR32_M4_E32_MASK, VFNMSUB_VF, 0x2, 0x0 }, // 2335 { PseudoVFNMSUB_VFPR64_M4_E64, VFNMSUB_VF, 0x2, 0x0 }, // 2336 { PseudoVFNMSUB_VFPR64_M4_E64_MASK, VFNMSUB_VF, 0x2, 0x0 }, // 2337 { PseudoVFNMSUB_VFPR16_M8_E16, VFNMSUB_VF, 0x3, 0x0 }, // 2338 { PseudoVFNMSUB_VFPR16_M8_E16_MASK, VFNMSUB_VF, 0x3, 0x0 }, // 2339 { PseudoVFNMSUB_VFPR32_M8_E32, VFNMSUB_VF, 0x3, 0x0 }, // 2340 { PseudoVFNMSUB_VFPR32_M8_E32_MASK, VFNMSUB_VF, 0x3, 0x0 }, // 2341 { PseudoVFNMSUB_VFPR64_M8_E64, VFNMSUB_VF, 0x3, 0x0 }, // 2342 { PseudoVFNMSUB_VFPR64_M8_E64_MASK, VFNMSUB_VF, 0x3, 0x0 }, // 2343 { PseudoVFNMSUB_VFPR16_MF4_E16, VFNMSUB_VF, 0x6, 0x0 }, // 2344 { PseudoVFNMSUB_VFPR16_MF4_E16_MASK, VFNMSUB_VF, 0x6, 0x0 }, // 2345 { PseudoVFNMSUB_VFPR16_MF2_E16, VFNMSUB_VF, 0x7, 0x0 }, // 2346 { PseudoVFNMSUB_VFPR16_MF2_E16_MASK, VFNMSUB_VF, 0x7, 0x0 }, // 2347 { PseudoVFNMSUB_VFPR32_MF2_E32, VFNMSUB_VF, 0x7, 0x0 }, // 2348 { PseudoVFNMSUB_VFPR32_MF2_E32_MASK, VFNMSUB_VF, 0x7, 0x0 }, // 2349 { PseudoVFNMSUB_VV_M1_E16, VFNMSUB_VV, 0x0, 0x0 }, // 2350 { PseudoVFNMSUB_VV_M1_E16_MASK, VFNMSUB_VV, 0x0, 0x0 }, // 2351 { PseudoVFNMSUB_VV_M1_E32, VFNMSUB_VV, 0x0, 0x0 }, // 2352 { PseudoVFNMSUB_VV_M1_E32_MASK, VFNMSUB_VV, 0x0, 0x0 }, // 2353 { PseudoVFNMSUB_VV_M1_E64, VFNMSUB_VV, 0x0, 0x0 }, // 2354 { PseudoVFNMSUB_VV_M1_E64_MASK, VFNMSUB_VV, 0x0, 0x0 }, // 2355 { PseudoVFNMSUB_VV_M2_E16, VFNMSUB_VV, 0x1, 0x0 }, // 2356 { PseudoVFNMSUB_VV_M2_E16_MASK, VFNMSUB_VV, 0x1, 0x0 }, // 2357 { PseudoVFNMSUB_VV_M2_E32, VFNMSUB_VV, 0x1, 0x0 }, // 2358 { PseudoVFNMSUB_VV_M2_E32_MASK, VFNMSUB_VV, 0x1, 0x0 }, // 2359 { PseudoVFNMSUB_VV_M2_E64, VFNMSUB_VV, 0x1, 0x0 }, // 2360 { PseudoVFNMSUB_VV_M2_E64_MASK, VFNMSUB_VV, 0x1, 0x0 }, // 2361 { PseudoVFNMSUB_VV_M4_E16, VFNMSUB_VV, 0x2, 0x0 }, // 2362 { PseudoVFNMSUB_VV_M4_E16_MASK, VFNMSUB_VV, 0x2, 0x0 }, // 2363 { PseudoVFNMSUB_VV_M4_E32, VFNMSUB_VV, 0x2, 0x0 }, // 2364 { PseudoVFNMSUB_VV_M4_E32_MASK, VFNMSUB_VV, 0x2, 0x0 }, // 2365 { PseudoVFNMSUB_VV_M4_E64, VFNMSUB_VV, 0x2, 0x0 }, // 2366 { PseudoVFNMSUB_VV_M4_E64_MASK, VFNMSUB_VV, 0x2, 0x0 }, // 2367 { PseudoVFNMSUB_VV_M8_E16, VFNMSUB_VV, 0x3, 0x0 }, // 2368 { PseudoVFNMSUB_VV_M8_E16_MASK, VFNMSUB_VV, 0x3, 0x0 }, // 2369 { PseudoVFNMSUB_VV_M8_E32, VFNMSUB_VV, 0x3, 0x0 }, // 2370 { PseudoVFNMSUB_VV_M8_E32_MASK, VFNMSUB_VV, 0x3, 0x0 }, // 2371 { PseudoVFNMSUB_VV_M8_E64, VFNMSUB_VV, 0x3, 0x0 }, // 2372 { PseudoVFNMSUB_VV_M8_E64_MASK, VFNMSUB_VV, 0x3, 0x0 }, // 2373 { PseudoVFNMSUB_VV_MF4_E16, VFNMSUB_VV, 0x6, 0x0 }, // 2374 { PseudoVFNMSUB_VV_MF4_E16_MASK, VFNMSUB_VV, 0x6, 0x0 }, // 2375 { PseudoVFNMSUB_VV_MF2_E16, VFNMSUB_VV, 0x7, 0x0 }, // 2376 { PseudoVFNMSUB_VV_MF2_E16_MASK, VFNMSUB_VV, 0x7, 0x0 }, // 2377 { PseudoVFNMSUB_VV_MF2_E32, VFNMSUB_VV, 0x7, 0x0 }, // 2378 { PseudoVFNMSUB_VV_MF2_E32_MASK, VFNMSUB_VV, 0x7, 0x0 }, // 2379 { PseudoVFNRCLIP_XU_F_QF_M1, VFNRCLIP_XU_F_QF, 0x0, 0x0 }, // 2380 { PseudoVFNRCLIP_XU_F_QF_M1_MASK, VFNRCLIP_XU_F_QF, 0x0, 0x0 }, // 2381 { PseudoVFNRCLIP_XU_F_QF_M2, VFNRCLIP_XU_F_QF, 0x1, 0x0 }, // 2382 { PseudoVFNRCLIP_XU_F_QF_M2_MASK, VFNRCLIP_XU_F_QF, 0x1, 0x0 }, // 2383 { PseudoVFNRCLIP_XU_F_QF_MF8, VFNRCLIP_XU_F_QF, 0x5, 0x0 }, // 2384 { PseudoVFNRCLIP_XU_F_QF_MF8_MASK, VFNRCLIP_XU_F_QF, 0x5, 0x0 }, // 2385 { PseudoVFNRCLIP_XU_F_QF_MF4, VFNRCLIP_XU_F_QF, 0x6, 0x0 }, // 2386 { PseudoVFNRCLIP_XU_F_QF_MF4_MASK, VFNRCLIP_XU_F_QF, 0x6, 0x0 }, // 2387 { PseudoVFNRCLIP_XU_F_QF_MF2, VFNRCLIP_XU_F_QF, 0x7, 0x0 }, // 2388 { PseudoVFNRCLIP_XU_F_QF_MF2_MASK, VFNRCLIP_XU_F_QF, 0x7, 0x0 }, // 2389 { PseudoVFNRCLIP_X_F_QF_M1, VFNRCLIP_X_F_QF, 0x0, 0x0 }, // 2390 { PseudoVFNRCLIP_X_F_QF_M1_MASK, VFNRCLIP_X_F_QF, 0x0, 0x0 }, // 2391 { PseudoVFNRCLIP_X_F_QF_M2, VFNRCLIP_X_F_QF, 0x1, 0x0 }, // 2392 { PseudoVFNRCLIP_X_F_QF_M2_MASK, VFNRCLIP_X_F_QF, 0x1, 0x0 }, // 2393 { PseudoVFNRCLIP_X_F_QF_MF8, VFNRCLIP_X_F_QF, 0x5, 0x0 }, // 2394 { PseudoVFNRCLIP_X_F_QF_MF8_MASK, VFNRCLIP_X_F_QF, 0x5, 0x0 }, // 2395 { PseudoVFNRCLIP_X_F_QF_MF4, VFNRCLIP_X_F_QF, 0x6, 0x0 }, // 2396 { PseudoVFNRCLIP_X_F_QF_MF4_MASK, VFNRCLIP_X_F_QF, 0x6, 0x0 }, // 2397 { PseudoVFNRCLIP_X_F_QF_MF2, VFNRCLIP_X_F_QF, 0x7, 0x0 }, // 2398 { PseudoVFNRCLIP_X_F_QF_MF2_MASK, VFNRCLIP_X_F_QF, 0x7, 0x0 }, // 2399 { PseudoVFRDIV_VFPR16_M1_E16, VFRDIV_VF, 0x0, 0x10 }, // 2400 { PseudoVFRDIV_VFPR16_M1_E16_MASK, VFRDIV_VF, 0x0, 0x10 }, // 2401 { PseudoVFRDIV_VFPR32_M1_E32, VFRDIV_VF, 0x0, 0x20 }, // 2402 { PseudoVFRDIV_VFPR32_M1_E32_MASK, VFRDIV_VF, 0x0, 0x20 }, // 2403 { PseudoVFRDIV_VFPR64_M1_E64, VFRDIV_VF, 0x0, 0x40 }, // 2404 { PseudoVFRDIV_VFPR64_M1_E64_MASK, VFRDIV_VF, 0x0, 0x40 }, // 2405 { PseudoVFRDIV_VFPR16_M2_E16, VFRDIV_VF, 0x1, 0x10 }, // 2406 { PseudoVFRDIV_VFPR16_M2_E16_MASK, VFRDIV_VF, 0x1, 0x10 }, // 2407 { PseudoVFRDIV_VFPR32_M2_E32, VFRDIV_VF, 0x1, 0x20 }, // 2408 { PseudoVFRDIV_VFPR32_M2_E32_MASK, VFRDIV_VF, 0x1, 0x20 }, // 2409 { PseudoVFRDIV_VFPR64_M2_E64, VFRDIV_VF, 0x1, 0x40 }, // 2410 { PseudoVFRDIV_VFPR64_M2_E64_MASK, VFRDIV_VF, 0x1, 0x40 }, // 2411 { PseudoVFRDIV_VFPR16_M4_E16, VFRDIV_VF, 0x2, 0x10 }, // 2412 { PseudoVFRDIV_VFPR16_M4_E16_MASK, VFRDIV_VF, 0x2, 0x10 }, // 2413 { PseudoVFRDIV_VFPR32_M4_E32, VFRDIV_VF, 0x2, 0x20 }, // 2414 { PseudoVFRDIV_VFPR32_M4_E32_MASK, VFRDIV_VF, 0x2, 0x20 }, // 2415 { PseudoVFRDIV_VFPR64_M4_E64, VFRDIV_VF, 0x2, 0x40 }, // 2416 { PseudoVFRDIV_VFPR64_M4_E64_MASK, VFRDIV_VF, 0x2, 0x40 }, // 2417 { PseudoVFRDIV_VFPR16_M8_E16, VFRDIV_VF, 0x3, 0x10 }, // 2418 { PseudoVFRDIV_VFPR16_M8_E16_MASK, VFRDIV_VF, 0x3, 0x10 }, // 2419 { PseudoVFRDIV_VFPR32_M8_E32, VFRDIV_VF, 0x3, 0x20 }, // 2420 { PseudoVFRDIV_VFPR32_M8_E32_MASK, VFRDIV_VF, 0x3, 0x20 }, // 2421 { PseudoVFRDIV_VFPR64_M8_E64, VFRDIV_VF, 0x3, 0x40 }, // 2422 { PseudoVFRDIV_VFPR64_M8_E64_MASK, VFRDIV_VF, 0x3, 0x40 }, // 2423 { PseudoVFRDIV_VFPR16_MF4_E16, VFRDIV_VF, 0x6, 0x10 }, // 2424 { PseudoVFRDIV_VFPR16_MF4_E16_MASK, VFRDIV_VF, 0x6, 0x10 }, // 2425 { PseudoVFRDIV_VFPR16_MF2_E16, VFRDIV_VF, 0x7, 0x10 }, // 2426 { PseudoVFRDIV_VFPR16_MF2_E16_MASK, VFRDIV_VF, 0x7, 0x10 }, // 2427 { PseudoVFRDIV_VFPR32_MF2_E32, VFRDIV_VF, 0x7, 0x20 }, // 2428 { PseudoVFRDIV_VFPR32_MF2_E32_MASK, VFRDIV_VF, 0x7, 0x20 }, // 2429 { PseudoVFREC7_V_M1_E16, VFREC7_V, 0x0, 0x0 }, // 2430 { PseudoVFREC7_V_M1_E16_MASK, VFREC7_V, 0x0, 0x0 }, // 2431 { PseudoVFREC7_V_M1_E32, VFREC7_V, 0x0, 0x0 }, // 2432 { PseudoVFREC7_V_M1_E32_MASK, VFREC7_V, 0x0, 0x0 }, // 2433 { PseudoVFREC7_V_M1_E64, VFREC7_V, 0x0, 0x0 }, // 2434 { PseudoVFREC7_V_M1_E64_MASK, VFREC7_V, 0x0, 0x0 }, // 2435 { PseudoVFREC7_V_M2_E16, VFREC7_V, 0x1, 0x0 }, // 2436 { PseudoVFREC7_V_M2_E16_MASK, VFREC7_V, 0x1, 0x0 }, // 2437 { PseudoVFREC7_V_M2_E32, VFREC7_V, 0x1, 0x0 }, // 2438 { PseudoVFREC7_V_M2_E32_MASK, VFREC7_V, 0x1, 0x0 }, // 2439 { PseudoVFREC7_V_M2_E64, VFREC7_V, 0x1, 0x0 }, // 2440 { PseudoVFREC7_V_M2_E64_MASK, VFREC7_V, 0x1, 0x0 }, // 2441 { PseudoVFREC7_V_M4_E16, VFREC7_V, 0x2, 0x0 }, // 2442 { PseudoVFREC7_V_M4_E16_MASK, VFREC7_V, 0x2, 0x0 }, // 2443 { PseudoVFREC7_V_M4_E32, VFREC7_V, 0x2, 0x0 }, // 2444 { PseudoVFREC7_V_M4_E32_MASK, VFREC7_V, 0x2, 0x0 }, // 2445 { PseudoVFREC7_V_M4_E64, VFREC7_V, 0x2, 0x0 }, // 2446 { PseudoVFREC7_V_M4_E64_MASK, VFREC7_V, 0x2, 0x0 }, // 2447 { PseudoVFREC7_V_M8_E16, VFREC7_V, 0x3, 0x0 }, // 2448 { PseudoVFREC7_V_M8_E16_MASK, VFREC7_V, 0x3, 0x0 }, // 2449 { PseudoVFREC7_V_M8_E32, VFREC7_V, 0x3, 0x0 }, // 2450 { PseudoVFREC7_V_M8_E32_MASK, VFREC7_V, 0x3, 0x0 }, // 2451 { PseudoVFREC7_V_M8_E64, VFREC7_V, 0x3, 0x0 }, // 2452 { PseudoVFREC7_V_M8_E64_MASK, VFREC7_V, 0x3, 0x0 }, // 2453 { PseudoVFREC7_V_MF4_E16, VFREC7_V, 0x6, 0x0 }, // 2454 { PseudoVFREC7_V_MF4_E16_MASK, VFREC7_V, 0x6, 0x0 }, // 2455 { PseudoVFREC7_V_MF2_E16, VFREC7_V, 0x7, 0x0 }, // 2456 { PseudoVFREC7_V_MF2_E16_MASK, VFREC7_V, 0x7, 0x0 }, // 2457 { PseudoVFREC7_V_MF2_E32, VFREC7_V, 0x7, 0x0 }, // 2458 { PseudoVFREC7_V_MF2_E32_MASK, VFREC7_V, 0x7, 0x0 }, // 2459 { PseudoVFREDMAX_VS_M1_E16, VFREDMAX_VS, 0x0, 0x10 }, // 2460 { PseudoVFREDMAX_VS_M1_E16_MASK, VFREDMAX_VS, 0x0, 0x10 }, // 2461 { PseudoVFREDMAX_VS_M1_E32, VFREDMAX_VS, 0x0, 0x20 }, // 2462 { PseudoVFREDMAX_VS_M1_E32_MASK, VFREDMAX_VS, 0x0, 0x20 }, // 2463 { PseudoVFREDMAX_VS_M1_E64, VFREDMAX_VS, 0x0, 0x40 }, // 2464 { PseudoVFREDMAX_VS_M1_E64_MASK, VFREDMAX_VS, 0x0, 0x40 }, // 2465 { PseudoVFREDMAX_VS_M2_E16, VFREDMAX_VS, 0x1, 0x10 }, // 2466 { PseudoVFREDMAX_VS_M2_E16_MASK, VFREDMAX_VS, 0x1, 0x10 }, // 2467 { PseudoVFREDMAX_VS_M2_E32, VFREDMAX_VS, 0x1, 0x20 }, // 2468 { PseudoVFREDMAX_VS_M2_E32_MASK, VFREDMAX_VS, 0x1, 0x20 }, // 2469 { PseudoVFREDMAX_VS_M2_E64, VFREDMAX_VS, 0x1, 0x40 }, // 2470 { PseudoVFREDMAX_VS_M2_E64_MASK, VFREDMAX_VS, 0x1, 0x40 }, // 2471 { PseudoVFREDMAX_VS_M4_E16, VFREDMAX_VS, 0x2, 0x10 }, // 2472 { PseudoVFREDMAX_VS_M4_E16_MASK, VFREDMAX_VS, 0x2, 0x10 }, // 2473 { PseudoVFREDMAX_VS_M4_E32, VFREDMAX_VS, 0x2, 0x20 }, // 2474 { PseudoVFREDMAX_VS_M4_E32_MASK, VFREDMAX_VS, 0x2, 0x20 }, // 2475 { PseudoVFREDMAX_VS_M4_E64, VFREDMAX_VS, 0x2, 0x40 }, // 2476 { PseudoVFREDMAX_VS_M4_E64_MASK, VFREDMAX_VS, 0x2, 0x40 }, // 2477 { PseudoVFREDMAX_VS_M8_E16, VFREDMAX_VS, 0x3, 0x10 }, // 2478 { PseudoVFREDMAX_VS_M8_E16_MASK, VFREDMAX_VS, 0x3, 0x10 }, // 2479 { PseudoVFREDMAX_VS_M8_E32, VFREDMAX_VS, 0x3, 0x20 }, // 2480 { PseudoVFREDMAX_VS_M8_E32_MASK, VFREDMAX_VS, 0x3, 0x20 }, // 2481 { PseudoVFREDMAX_VS_M8_E64, VFREDMAX_VS, 0x3, 0x40 }, // 2482 { PseudoVFREDMAX_VS_M8_E64_MASK, VFREDMAX_VS, 0x3, 0x40 }, // 2483 { PseudoVFREDMAX_VS_MF4_E16, VFREDMAX_VS, 0x6, 0x10 }, // 2484 { PseudoVFREDMAX_VS_MF4_E16_MASK, VFREDMAX_VS, 0x6, 0x10 }, // 2485 { PseudoVFREDMAX_VS_MF2_E16, VFREDMAX_VS, 0x7, 0x10 }, // 2486 { PseudoVFREDMAX_VS_MF2_E16_MASK, VFREDMAX_VS, 0x7, 0x10 }, // 2487 { PseudoVFREDMAX_VS_MF2_E32, VFREDMAX_VS, 0x7, 0x20 }, // 2488 { PseudoVFREDMAX_VS_MF2_E32_MASK, VFREDMAX_VS, 0x7, 0x20 }, // 2489 { PseudoVFREDMIN_VS_M1_E16, VFREDMIN_VS, 0x0, 0x10 }, // 2490 { PseudoVFREDMIN_VS_M1_E16_MASK, VFREDMIN_VS, 0x0, 0x10 }, // 2491 { PseudoVFREDMIN_VS_M1_E32, VFREDMIN_VS, 0x0, 0x20 }, // 2492 { PseudoVFREDMIN_VS_M1_E32_MASK, VFREDMIN_VS, 0x0, 0x20 }, // 2493 { PseudoVFREDMIN_VS_M1_E64, VFREDMIN_VS, 0x0, 0x40 }, // 2494 { PseudoVFREDMIN_VS_M1_E64_MASK, VFREDMIN_VS, 0x0, 0x40 }, // 2495 { PseudoVFREDMIN_VS_M2_E16, VFREDMIN_VS, 0x1, 0x10 }, // 2496 { PseudoVFREDMIN_VS_M2_E16_MASK, VFREDMIN_VS, 0x1, 0x10 }, // 2497 { PseudoVFREDMIN_VS_M2_E32, VFREDMIN_VS, 0x1, 0x20 }, // 2498 { PseudoVFREDMIN_VS_M2_E32_MASK, VFREDMIN_VS, 0x1, 0x20 }, // 2499 { PseudoVFREDMIN_VS_M2_E64, VFREDMIN_VS, 0x1, 0x40 }, // 2500 { PseudoVFREDMIN_VS_M2_E64_MASK, VFREDMIN_VS, 0x1, 0x40 }, // 2501 { PseudoVFREDMIN_VS_M4_E16, VFREDMIN_VS, 0x2, 0x10 }, // 2502 { PseudoVFREDMIN_VS_M4_E16_MASK, VFREDMIN_VS, 0x2, 0x10 }, // 2503 { PseudoVFREDMIN_VS_M4_E32, VFREDMIN_VS, 0x2, 0x20 }, // 2504 { PseudoVFREDMIN_VS_M4_E32_MASK, VFREDMIN_VS, 0x2, 0x20 }, // 2505 { PseudoVFREDMIN_VS_M4_E64, VFREDMIN_VS, 0x2, 0x40 }, // 2506 { PseudoVFREDMIN_VS_M4_E64_MASK, VFREDMIN_VS, 0x2, 0x40 }, // 2507 { PseudoVFREDMIN_VS_M8_E16, VFREDMIN_VS, 0x3, 0x10 }, // 2508 { PseudoVFREDMIN_VS_M8_E16_MASK, VFREDMIN_VS, 0x3, 0x10 }, // 2509 { PseudoVFREDMIN_VS_M8_E32, VFREDMIN_VS, 0x3, 0x20 }, // 2510 { PseudoVFREDMIN_VS_M8_E32_MASK, VFREDMIN_VS, 0x3, 0x20 }, // 2511 { PseudoVFREDMIN_VS_M8_E64, VFREDMIN_VS, 0x3, 0x40 }, // 2512 { PseudoVFREDMIN_VS_M8_E64_MASK, VFREDMIN_VS, 0x3, 0x40 }, // 2513 { PseudoVFREDMIN_VS_MF4_E16, VFREDMIN_VS, 0x6, 0x10 }, // 2514 { PseudoVFREDMIN_VS_MF4_E16_MASK, VFREDMIN_VS, 0x6, 0x10 }, // 2515 { PseudoVFREDMIN_VS_MF2_E16, VFREDMIN_VS, 0x7, 0x10 }, // 2516 { PseudoVFREDMIN_VS_MF2_E16_MASK, VFREDMIN_VS, 0x7, 0x10 }, // 2517 { PseudoVFREDMIN_VS_MF2_E32, VFREDMIN_VS, 0x7, 0x20 }, // 2518 { PseudoVFREDMIN_VS_MF2_E32_MASK, VFREDMIN_VS, 0x7, 0x20 }, // 2519 { PseudoVFREDOSUM_VS_M1_E16, VFREDOSUM_VS, 0x0, 0x10 }, // 2520 { PseudoVFREDOSUM_VS_M1_E16_MASK, VFREDOSUM_VS, 0x0, 0x10 }, // 2521 { PseudoVFREDOSUM_VS_M1_E32, VFREDOSUM_VS, 0x0, 0x20 }, // 2522 { PseudoVFREDOSUM_VS_M1_E32_MASK, VFREDOSUM_VS, 0x0, 0x20 }, // 2523 { PseudoVFREDOSUM_VS_M1_E64, VFREDOSUM_VS, 0x0, 0x40 }, // 2524 { PseudoVFREDOSUM_VS_M1_E64_MASK, VFREDOSUM_VS, 0x0, 0x40 }, // 2525 { PseudoVFREDOSUM_VS_M2_E16, VFREDOSUM_VS, 0x1, 0x10 }, // 2526 { PseudoVFREDOSUM_VS_M2_E16_MASK, VFREDOSUM_VS, 0x1, 0x10 }, // 2527 { PseudoVFREDOSUM_VS_M2_E32, VFREDOSUM_VS, 0x1, 0x20 }, // 2528 { PseudoVFREDOSUM_VS_M2_E32_MASK, VFREDOSUM_VS, 0x1, 0x20 }, // 2529 { PseudoVFREDOSUM_VS_M2_E64, VFREDOSUM_VS, 0x1, 0x40 }, // 2530 { PseudoVFREDOSUM_VS_M2_E64_MASK, VFREDOSUM_VS, 0x1, 0x40 }, // 2531 { PseudoVFREDOSUM_VS_M4_E16, VFREDOSUM_VS, 0x2, 0x10 }, // 2532 { PseudoVFREDOSUM_VS_M4_E16_MASK, VFREDOSUM_VS, 0x2, 0x10 }, // 2533 { PseudoVFREDOSUM_VS_M4_E32, VFREDOSUM_VS, 0x2, 0x20 }, // 2534 { PseudoVFREDOSUM_VS_M4_E32_MASK, VFREDOSUM_VS, 0x2, 0x20 }, // 2535 { PseudoVFREDOSUM_VS_M4_E64, VFREDOSUM_VS, 0x2, 0x40 }, // 2536 { PseudoVFREDOSUM_VS_M4_E64_MASK, VFREDOSUM_VS, 0x2, 0x40 }, // 2537 { PseudoVFREDOSUM_VS_M8_E16, VFREDOSUM_VS, 0x3, 0x10 }, // 2538 { PseudoVFREDOSUM_VS_M8_E16_MASK, VFREDOSUM_VS, 0x3, 0x10 }, // 2539 { PseudoVFREDOSUM_VS_M8_E32, VFREDOSUM_VS, 0x3, 0x20 }, // 2540 { PseudoVFREDOSUM_VS_M8_E32_MASK, VFREDOSUM_VS, 0x3, 0x20 }, // 2541 { PseudoVFREDOSUM_VS_M8_E64, VFREDOSUM_VS, 0x3, 0x40 }, // 2542 { PseudoVFREDOSUM_VS_M8_E64_MASK, VFREDOSUM_VS, 0x3, 0x40 }, // 2543 { PseudoVFREDOSUM_VS_MF4_E16, VFREDOSUM_VS, 0x6, 0x10 }, // 2544 { PseudoVFREDOSUM_VS_MF4_E16_MASK, VFREDOSUM_VS, 0x6, 0x10 }, // 2545 { PseudoVFREDOSUM_VS_MF2_E16, VFREDOSUM_VS, 0x7, 0x10 }, // 2546 { PseudoVFREDOSUM_VS_MF2_E16_MASK, VFREDOSUM_VS, 0x7, 0x10 }, // 2547 { PseudoVFREDOSUM_VS_MF2_E32, VFREDOSUM_VS, 0x7, 0x20 }, // 2548 { PseudoVFREDOSUM_VS_MF2_E32_MASK, VFREDOSUM_VS, 0x7, 0x20 }, // 2549 { PseudoVFREDUSUM_VS_M1_E16, VFREDUSUM_VS, 0x0, 0x10 }, // 2550 { PseudoVFREDUSUM_VS_M1_E16_MASK, VFREDUSUM_VS, 0x0, 0x10 }, // 2551 { PseudoVFREDUSUM_VS_M1_E32, VFREDUSUM_VS, 0x0, 0x20 }, // 2552 { PseudoVFREDUSUM_VS_M1_E32_MASK, VFREDUSUM_VS, 0x0, 0x20 }, // 2553 { PseudoVFREDUSUM_VS_M1_E64, VFREDUSUM_VS, 0x0, 0x40 }, // 2554 { PseudoVFREDUSUM_VS_M1_E64_MASK, VFREDUSUM_VS, 0x0, 0x40 }, // 2555 { PseudoVFREDUSUM_VS_M2_E16, VFREDUSUM_VS, 0x1, 0x10 }, // 2556 { PseudoVFREDUSUM_VS_M2_E16_MASK, VFREDUSUM_VS, 0x1, 0x10 }, // 2557 { PseudoVFREDUSUM_VS_M2_E32, VFREDUSUM_VS, 0x1, 0x20 }, // 2558 { PseudoVFREDUSUM_VS_M2_E32_MASK, VFREDUSUM_VS, 0x1, 0x20 }, // 2559 { PseudoVFREDUSUM_VS_M2_E64, VFREDUSUM_VS, 0x1, 0x40 }, // 2560 { PseudoVFREDUSUM_VS_M2_E64_MASK, VFREDUSUM_VS, 0x1, 0x40 }, // 2561 { PseudoVFREDUSUM_VS_M4_E16, VFREDUSUM_VS, 0x2, 0x10 }, // 2562 { PseudoVFREDUSUM_VS_M4_E16_MASK, VFREDUSUM_VS, 0x2, 0x10 }, // 2563 { PseudoVFREDUSUM_VS_M4_E32, VFREDUSUM_VS, 0x2, 0x20 }, // 2564 { PseudoVFREDUSUM_VS_M4_E32_MASK, VFREDUSUM_VS, 0x2, 0x20 }, // 2565 { PseudoVFREDUSUM_VS_M4_E64, VFREDUSUM_VS, 0x2, 0x40 }, // 2566 { PseudoVFREDUSUM_VS_M4_E64_MASK, VFREDUSUM_VS, 0x2, 0x40 }, // 2567 { PseudoVFREDUSUM_VS_M8_E16, VFREDUSUM_VS, 0x3, 0x10 }, // 2568 { PseudoVFREDUSUM_VS_M8_E16_MASK, VFREDUSUM_VS, 0x3, 0x10 }, // 2569 { PseudoVFREDUSUM_VS_M8_E32, VFREDUSUM_VS, 0x3, 0x20 }, // 2570 { PseudoVFREDUSUM_VS_M8_E32_MASK, VFREDUSUM_VS, 0x3, 0x20 }, // 2571 { PseudoVFREDUSUM_VS_M8_E64, VFREDUSUM_VS, 0x3, 0x40 }, // 2572 { PseudoVFREDUSUM_VS_M8_E64_MASK, VFREDUSUM_VS, 0x3, 0x40 }, // 2573 { PseudoVFREDUSUM_VS_MF4_E16, VFREDUSUM_VS, 0x6, 0x10 }, // 2574 { PseudoVFREDUSUM_VS_MF4_E16_MASK, VFREDUSUM_VS, 0x6, 0x10 }, // 2575 { PseudoVFREDUSUM_VS_MF2_E16, VFREDUSUM_VS, 0x7, 0x10 }, // 2576 { PseudoVFREDUSUM_VS_MF2_E16_MASK, VFREDUSUM_VS, 0x7, 0x10 }, // 2577 { PseudoVFREDUSUM_VS_MF2_E32, VFREDUSUM_VS, 0x7, 0x20 }, // 2578 { PseudoVFREDUSUM_VS_MF2_E32_MASK, VFREDUSUM_VS, 0x7, 0x20 }, // 2579 { PseudoVFRSQRT7_V_M1_E16, VFRSQRT7_V, 0x0, 0x0 }, // 2580 { PseudoVFRSQRT7_V_M1_E16_MASK, VFRSQRT7_V, 0x0, 0x0 }, // 2581 { PseudoVFRSQRT7_V_M1_E32, VFRSQRT7_V, 0x0, 0x0 }, // 2582 { PseudoVFRSQRT7_V_M1_E32_MASK, VFRSQRT7_V, 0x0, 0x0 }, // 2583 { PseudoVFRSQRT7_V_M1_E64, VFRSQRT7_V, 0x0, 0x0 }, // 2584 { PseudoVFRSQRT7_V_M1_E64_MASK, VFRSQRT7_V, 0x0, 0x0 }, // 2585 { PseudoVFRSQRT7_V_M2_E16, VFRSQRT7_V, 0x1, 0x0 }, // 2586 { PseudoVFRSQRT7_V_M2_E16_MASK, VFRSQRT7_V, 0x1, 0x0 }, // 2587 { PseudoVFRSQRT7_V_M2_E32, VFRSQRT7_V, 0x1, 0x0 }, // 2588 { PseudoVFRSQRT7_V_M2_E32_MASK, VFRSQRT7_V, 0x1, 0x0 }, // 2589 { PseudoVFRSQRT7_V_M2_E64, VFRSQRT7_V, 0x1, 0x0 }, // 2590 { PseudoVFRSQRT7_V_M2_E64_MASK, VFRSQRT7_V, 0x1, 0x0 }, // 2591 { PseudoVFRSQRT7_V_M4_E16, VFRSQRT7_V, 0x2, 0x0 }, // 2592 { PseudoVFRSQRT7_V_M4_E16_MASK, VFRSQRT7_V, 0x2, 0x0 }, // 2593 { PseudoVFRSQRT7_V_M4_E32, VFRSQRT7_V, 0x2, 0x0 }, // 2594 { PseudoVFRSQRT7_V_M4_E32_MASK, VFRSQRT7_V, 0x2, 0x0 }, // 2595 { PseudoVFRSQRT7_V_M4_E64, VFRSQRT7_V, 0x2, 0x0 }, // 2596 { PseudoVFRSQRT7_V_M4_E64_MASK, VFRSQRT7_V, 0x2, 0x0 }, // 2597 { PseudoVFRSQRT7_V_M8_E16, VFRSQRT7_V, 0x3, 0x0 }, // 2598 { PseudoVFRSQRT7_V_M8_E16_MASK, VFRSQRT7_V, 0x3, 0x0 }, // 2599 { PseudoVFRSQRT7_V_M8_E32, VFRSQRT7_V, 0x3, 0x0 }, // 2600 { PseudoVFRSQRT7_V_M8_E32_MASK, VFRSQRT7_V, 0x3, 0x0 }, // 2601 { PseudoVFRSQRT7_V_M8_E64, VFRSQRT7_V, 0x3, 0x0 }, // 2602 { PseudoVFRSQRT7_V_M8_E64_MASK, VFRSQRT7_V, 0x3, 0x0 }, // 2603 { PseudoVFRSQRT7_V_MF4_E16, VFRSQRT7_V, 0x6, 0x0 }, // 2604 { PseudoVFRSQRT7_V_MF4_E16_MASK, VFRSQRT7_V, 0x6, 0x0 }, // 2605 { PseudoVFRSQRT7_V_MF2_E16, VFRSQRT7_V, 0x7, 0x0 }, // 2606 { PseudoVFRSQRT7_V_MF2_E16_MASK, VFRSQRT7_V, 0x7, 0x0 }, // 2607 { PseudoVFRSQRT7_V_MF2_E32, VFRSQRT7_V, 0x7, 0x0 }, // 2608 { PseudoVFRSQRT7_V_MF2_E32_MASK, VFRSQRT7_V, 0x7, 0x0 }, // 2609 { PseudoVFRSUB_VFPR16_M1_E16, VFRSUB_VF, 0x0, 0x10 }, // 2610 { PseudoVFRSUB_VFPR16_M1_E16_MASK, VFRSUB_VF, 0x0, 0x10 }, // 2611 { PseudoVFRSUB_VFPR32_M1_E32, VFRSUB_VF, 0x0, 0x20 }, // 2612 { PseudoVFRSUB_VFPR32_M1_E32_MASK, VFRSUB_VF, 0x0, 0x20 }, // 2613 { PseudoVFRSUB_VFPR64_M1_E64, VFRSUB_VF, 0x0, 0x40 }, // 2614 { PseudoVFRSUB_VFPR64_M1_E64_MASK, VFRSUB_VF, 0x0, 0x40 }, // 2615 { PseudoVFRSUB_VFPR16_M2_E16, VFRSUB_VF, 0x1, 0x10 }, // 2616 { PseudoVFRSUB_VFPR16_M2_E16_MASK, VFRSUB_VF, 0x1, 0x10 }, // 2617 { PseudoVFRSUB_VFPR32_M2_E32, VFRSUB_VF, 0x1, 0x20 }, // 2618 { PseudoVFRSUB_VFPR32_M2_E32_MASK, VFRSUB_VF, 0x1, 0x20 }, // 2619 { PseudoVFRSUB_VFPR64_M2_E64, VFRSUB_VF, 0x1, 0x40 }, // 2620 { PseudoVFRSUB_VFPR64_M2_E64_MASK, VFRSUB_VF, 0x1, 0x40 }, // 2621 { PseudoVFRSUB_VFPR16_M4_E16, VFRSUB_VF, 0x2, 0x10 }, // 2622 { PseudoVFRSUB_VFPR16_M4_E16_MASK, VFRSUB_VF, 0x2, 0x10 }, // 2623 { PseudoVFRSUB_VFPR32_M4_E32, VFRSUB_VF, 0x2, 0x20 }, // 2624 { PseudoVFRSUB_VFPR32_M4_E32_MASK, VFRSUB_VF, 0x2, 0x20 }, // 2625 { PseudoVFRSUB_VFPR64_M4_E64, VFRSUB_VF, 0x2, 0x40 }, // 2626 { PseudoVFRSUB_VFPR64_M4_E64_MASK, VFRSUB_VF, 0x2, 0x40 }, // 2627 { PseudoVFRSUB_VFPR16_M8_E16, VFRSUB_VF, 0x3, 0x10 }, // 2628 { PseudoVFRSUB_VFPR16_M8_E16_MASK, VFRSUB_VF, 0x3, 0x10 }, // 2629 { PseudoVFRSUB_VFPR32_M8_E32, VFRSUB_VF, 0x3, 0x20 }, // 2630 { PseudoVFRSUB_VFPR32_M8_E32_MASK, VFRSUB_VF, 0x3, 0x20 }, // 2631 { PseudoVFRSUB_VFPR64_M8_E64, VFRSUB_VF, 0x3, 0x40 }, // 2632 { PseudoVFRSUB_VFPR64_M8_E64_MASK, VFRSUB_VF, 0x3, 0x40 }, // 2633 { PseudoVFRSUB_VFPR16_MF4_E16, VFRSUB_VF, 0x6, 0x10 }, // 2634 { PseudoVFRSUB_VFPR16_MF4_E16_MASK, VFRSUB_VF, 0x6, 0x10 }, // 2635 { PseudoVFRSUB_VFPR16_MF2_E16, VFRSUB_VF, 0x7, 0x10 }, // 2636 { PseudoVFRSUB_VFPR16_MF2_E16_MASK, VFRSUB_VF, 0x7, 0x10 }, // 2637 { PseudoVFRSUB_VFPR32_MF2_E32, VFRSUB_VF, 0x7, 0x20 }, // 2638 { PseudoVFRSUB_VFPR32_MF2_E32_MASK, VFRSUB_VF, 0x7, 0x20 }, // 2639 { PseudoVFSGNJN_VFPR16_M1_E16, VFSGNJN_VF, 0x0, 0x10 }, // 2640 { PseudoVFSGNJN_VFPR16_M1_E16_MASK, VFSGNJN_VF, 0x0, 0x10 }, // 2641 { PseudoVFSGNJN_VFPR32_M1_E32, VFSGNJN_VF, 0x0, 0x20 }, // 2642 { PseudoVFSGNJN_VFPR32_M1_E32_MASK, VFSGNJN_VF, 0x0, 0x20 }, // 2643 { PseudoVFSGNJN_VFPR64_M1_E64, VFSGNJN_VF, 0x0, 0x40 }, // 2644 { PseudoVFSGNJN_VFPR64_M1_E64_MASK, VFSGNJN_VF, 0x0, 0x40 }, // 2645 { PseudoVFSGNJN_VFPR16_M2_E16, VFSGNJN_VF, 0x1, 0x10 }, // 2646 { PseudoVFSGNJN_VFPR16_M2_E16_MASK, VFSGNJN_VF, 0x1, 0x10 }, // 2647 { PseudoVFSGNJN_VFPR32_M2_E32, VFSGNJN_VF, 0x1, 0x20 }, // 2648 { PseudoVFSGNJN_VFPR32_M2_E32_MASK, VFSGNJN_VF, 0x1, 0x20 }, // 2649 { PseudoVFSGNJN_VFPR64_M2_E64, VFSGNJN_VF, 0x1, 0x40 }, // 2650 { PseudoVFSGNJN_VFPR64_M2_E64_MASK, VFSGNJN_VF, 0x1, 0x40 }, // 2651 { PseudoVFSGNJN_VFPR16_M4_E16, VFSGNJN_VF, 0x2, 0x10 }, // 2652 { PseudoVFSGNJN_VFPR16_M4_E16_MASK, VFSGNJN_VF, 0x2, 0x10 }, // 2653 { PseudoVFSGNJN_VFPR32_M4_E32, VFSGNJN_VF, 0x2, 0x20 }, // 2654 { PseudoVFSGNJN_VFPR32_M4_E32_MASK, VFSGNJN_VF, 0x2, 0x20 }, // 2655 { PseudoVFSGNJN_VFPR64_M4_E64, VFSGNJN_VF, 0x2, 0x40 }, // 2656 { PseudoVFSGNJN_VFPR64_M4_E64_MASK, VFSGNJN_VF, 0x2, 0x40 }, // 2657 { PseudoVFSGNJN_VFPR16_M8_E16, VFSGNJN_VF, 0x3, 0x10 }, // 2658 { PseudoVFSGNJN_VFPR16_M8_E16_MASK, VFSGNJN_VF, 0x3, 0x10 }, // 2659 { PseudoVFSGNJN_VFPR32_M8_E32, VFSGNJN_VF, 0x3, 0x20 }, // 2660 { PseudoVFSGNJN_VFPR32_M8_E32_MASK, VFSGNJN_VF, 0x3, 0x20 }, // 2661 { PseudoVFSGNJN_VFPR64_M8_E64, VFSGNJN_VF, 0x3, 0x40 }, // 2662 { PseudoVFSGNJN_VFPR64_M8_E64_MASK, VFSGNJN_VF, 0x3, 0x40 }, // 2663 { PseudoVFSGNJN_VFPR16_MF4_E16, VFSGNJN_VF, 0x6, 0x10 }, // 2664 { PseudoVFSGNJN_VFPR16_MF4_E16_MASK, VFSGNJN_VF, 0x6, 0x10 }, // 2665 { PseudoVFSGNJN_VFPR16_MF2_E16, VFSGNJN_VF, 0x7, 0x10 }, // 2666 { PseudoVFSGNJN_VFPR16_MF2_E16_MASK, VFSGNJN_VF, 0x7, 0x10 }, // 2667 { PseudoVFSGNJN_VFPR32_MF2_E32, VFSGNJN_VF, 0x7, 0x20 }, // 2668 { PseudoVFSGNJN_VFPR32_MF2_E32_MASK, VFSGNJN_VF, 0x7, 0x20 }, // 2669 { PseudoVFSGNJN_VV_M1_E16, VFSGNJN_VV, 0x0, 0x10 }, // 2670 { PseudoVFSGNJN_VV_M1_E16_MASK, VFSGNJN_VV, 0x0, 0x10 }, // 2671 { PseudoVFSGNJN_VV_M1_E32, VFSGNJN_VV, 0x0, 0x20 }, // 2672 { PseudoVFSGNJN_VV_M1_E32_MASK, VFSGNJN_VV, 0x0, 0x20 }, // 2673 { PseudoVFSGNJN_VV_M1_E64, VFSGNJN_VV, 0x0, 0x40 }, // 2674 { PseudoVFSGNJN_VV_M1_E64_MASK, VFSGNJN_VV, 0x0, 0x40 }, // 2675 { PseudoVFSGNJN_VV_M2_E16, VFSGNJN_VV, 0x1, 0x10 }, // 2676 { PseudoVFSGNJN_VV_M2_E16_MASK, VFSGNJN_VV, 0x1, 0x10 }, // 2677 { PseudoVFSGNJN_VV_M2_E32, VFSGNJN_VV, 0x1, 0x20 }, // 2678 { PseudoVFSGNJN_VV_M2_E32_MASK, VFSGNJN_VV, 0x1, 0x20 }, // 2679 { PseudoVFSGNJN_VV_M2_E64, VFSGNJN_VV, 0x1, 0x40 }, // 2680 { PseudoVFSGNJN_VV_M2_E64_MASK, VFSGNJN_VV, 0x1, 0x40 }, // 2681 { PseudoVFSGNJN_VV_M4_E16, VFSGNJN_VV, 0x2, 0x10 }, // 2682 { PseudoVFSGNJN_VV_M4_E16_MASK, VFSGNJN_VV, 0x2, 0x10 }, // 2683 { PseudoVFSGNJN_VV_M4_E32, VFSGNJN_VV, 0x2, 0x20 }, // 2684 { PseudoVFSGNJN_VV_M4_E32_MASK, VFSGNJN_VV, 0x2, 0x20 }, // 2685 { PseudoVFSGNJN_VV_M4_E64, VFSGNJN_VV, 0x2, 0x40 }, // 2686 { PseudoVFSGNJN_VV_M4_E64_MASK, VFSGNJN_VV, 0x2, 0x40 }, // 2687 { PseudoVFSGNJN_VV_M8_E16, VFSGNJN_VV, 0x3, 0x10 }, // 2688 { PseudoVFSGNJN_VV_M8_E16_MASK, VFSGNJN_VV, 0x3, 0x10 }, // 2689 { PseudoVFSGNJN_VV_M8_E32, VFSGNJN_VV, 0x3, 0x20 }, // 2690 { PseudoVFSGNJN_VV_M8_E32_MASK, VFSGNJN_VV, 0x3, 0x20 }, // 2691 { PseudoVFSGNJN_VV_M8_E64, VFSGNJN_VV, 0x3, 0x40 }, // 2692 { PseudoVFSGNJN_VV_M8_E64_MASK, VFSGNJN_VV, 0x3, 0x40 }, // 2693 { PseudoVFSGNJN_VV_MF4_E16, VFSGNJN_VV, 0x6, 0x10 }, // 2694 { PseudoVFSGNJN_VV_MF4_E16_MASK, VFSGNJN_VV, 0x6, 0x10 }, // 2695 { PseudoVFSGNJN_VV_MF2_E16, VFSGNJN_VV, 0x7, 0x10 }, // 2696 { PseudoVFSGNJN_VV_MF2_E16_MASK, VFSGNJN_VV, 0x7, 0x10 }, // 2697 { PseudoVFSGNJN_VV_MF2_E32, VFSGNJN_VV, 0x7, 0x20 }, // 2698 { PseudoVFSGNJN_VV_MF2_E32_MASK, VFSGNJN_VV, 0x7, 0x20 }, // 2699 { PseudoVFSGNJX_VFPR16_M1_E16, VFSGNJX_VF, 0x0, 0x10 }, // 2700 { PseudoVFSGNJX_VFPR16_M1_E16_MASK, VFSGNJX_VF, 0x0, 0x10 }, // 2701 { PseudoVFSGNJX_VFPR32_M1_E32, VFSGNJX_VF, 0x0, 0x20 }, // 2702 { PseudoVFSGNJX_VFPR32_M1_E32_MASK, VFSGNJX_VF, 0x0, 0x20 }, // 2703 { PseudoVFSGNJX_VFPR64_M1_E64, VFSGNJX_VF, 0x0, 0x40 }, // 2704 { PseudoVFSGNJX_VFPR64_M1_E64_MASK, VFSGNJX_VF, 0x0, 0x40 }, // 2705 { PseudoVFSGNJX_VFPR16_M2_E16, VFSGNJX_VF, 0x1, 0x10 }, // 2706 { PseudoVFSGNJX_VFPR16_M2_E16_MASK, VFSGNJX_VF, 0x1, 0x10 }, // 2707 { PseudoVFSGNJX_VFPR32_M2_E32, VFSGNJX_VF, 0x1, 0x20 }, // 2708 { PseudoVFSGNJX_VFPR32_M2_E32_MASK, VFSGNJX_VF, 0x1, 0x20 }, // 2709 { PseudoVFSGNJX_VFPR64_M2_E64, VFSGNJX_VF, 0x1, 0x40 }, // 2710 { PseudoVFSGNJX_VFPR64_M2_E64_MASK, VFSGNJX_VF, 0x1, 0x40 }, // 2711 { PseudoVFSGNJX_VFPR16_M4_E16, VFSGNJX_VF, 0x2, 0x10 }, // 2712 { PseudoVFSGNJX_VFPR16_M4_E16_MASK, VFSGNJX_VF, 0x2, 0x10 }, // 2713 { PseudoVFSGNJX_VFPR32_M4_E32, VFSGNJX_VF, 0x2, 0x20 }, // 2714 { PseudoVFSGNJX_VFPR32_M4_E32_MASK, VFSGNJX_VF, 0x2, 0x20 }, // 2715 { PseudoVFSGNJX_VFPR64_M4_E64, VFSGNJX_VF, 0x2, 0x40 }, // 2716 { PseudoVFSGNJX_VFPR64_M4_E64_MASK, VFSGNJX_VF, 0x2, 0x40 }, // 2717 { PseudoVFSGNJX_VFPR16_M8_E16, VFSGNJX_VF, 0x3, 0x10 }, // 2718 { PseudoVFSGNJX_VFPR16_M8_E16_MASK, VFSGNJX_VF, 0x3, 0x10 }, // 2719 { PseudoVFSGNJX_VFPR32_M8_E32, VFSGNJX_VF, 0x3, 0x20 }, // 2720 { PseudoVFSGNJX_VFPR32_M8_E32_MASK, VFSGNJX_VF, 0x3, 0x20 }, // 2721 { PseudoVFSGNJX_VFPR64_M8_E64, VFSGNJX_VF, 0x3, 0x40 }, // 2722 { PseudoVFSGNJX_VFPR64_M8_E64_MASK, VFSGNJX_VF, 0x3, 0x40 }, // 2723 { PseudoVFSGNJX_VFPR16_MF4_E16, VFSGNJX_VF, 0x6, 0x10 }, // 2724 { PseudoVFSGNJX_VFPR16_MF4_E16_MASK, VFSGNJX_VF, 0x6, 0x10 }, // 2725 { PseudoVFSGNJX_VFPR16_MF2_E16, VFSGNJX_VF, 0x7, 0x10 }, // 2726 { PseudoVFSGNJX_VFPR16_MF2_E16_MASK, VFSGNJX_VF, 0x7, 0x10 }, // 2727 { PseudoVFSGNJX_VFPR32_MF2_E32, VFSGNJX_VF, 0x7, 0x20 }, // 2728 { PseudoVFSGNJX_VFPR32_MF2_E32_MASK, VFSGNJX_VF, 0x7, 0x20 }, // 2729 { PseudoVFSGNJX_VV_M1_E16, VFSGNJX_VV, 0x0, 0x10 }, // 2730 { PseudoVFSGNJX_VV_M1_E16_MASK, VFSGNJX_VV, 0x0, 0x10 }, // 2731 { PseudoVFSGNJX_VV_M1_E32, VFSGNJX_VV, 0x0, 0x20 }, // 2732 { PseudoVFSGNJX_VV_M1_E32_MASK, VFSGNJX_VV, 0x0, 0x20 }, // 2733 { PseudoVFSGNJX_VV_M1_E64, VFSGNJX_VV, 0x0, 0x40 }, // 2734 { PseudoVFSGNJX_VV_M1_E64_MASK, VFSGNJX_VV, 0x0, 0x40 }, // 2735 { PseudoVFSGNJX_VV_M2_E16, VFSGNJX_VV, 0x1, 0x10 }, // 2736 { PseudoVFSGNJX_VV_M2_E16_MASK, VFSGNJX_VV, 0x1, 0x10 }, // 2737 { PseudoVFSGNJX_VV_M2_E32, VFSGNJX_VV, 0x1, 0x20 }, // 2738 { PseudoVFSGNJX_VV_M2_E32_MASK, VFSGNJX_VV, 0x1, 0x20 }, // 2739 { PseudoVFSGNJX_VV_M2_E64, VFSGNJX_VV, 0x1, 0x40 }, // 2740 { PseudoVFSGNJX_VV_M2_E64_MASK, VFSGNJX_VV, 0x1, 0x40 }, // 2741 { PseudoVFSGNJX_VV_M4_E16, VFSGNJX_VV, 0x2, 0x10 }, // 2742 { PseudoVFSGNJX_VV_M4_E16_MASK, VFSGNJX_VV, 0x2, 0x10 }, // 2743 { PseudoVFSGNJX_VV_M4_E32, VFSGNJX_VV, 0x2, 0x20 }, // 2744 { PseudoVFSGNJX_VV_M4_E32_MASK, VFSGNJX_VV, 0x2, 0x20 }, // 2745 { PseudoVFSGNJX_VV_M4_E64, VFSGNJX_VV, 0x2, 0x40 }, // 2746 { PseudoVFSGNJX_VV_M4_E64_MASK, VFSGNJX_VV, 0x2, 0x40 }, // 2747 { PseudoVFSGNJX_VV_M8_E16, VFSGNJX_VV, 0x3, 0x10 }, // 2748 { PseudoVFSGNJX_VV_M8_E16_MASK, VFSGNJX_VV, 0x3, 0x10 }, // 2749 { PseudoVFSGNJX_VV_M8_E32, VFSGNJX_VV, 0x3, 0x20 }, // 2750 { PseudoVFSGNJX_VV_M8_E32_MASK, VFSGNJX_VV, 0x3, 0x20 }, // 2751 { PseudoVFSGNJX_VV_M8_E64, VFSGNJX_VV, 0x3, 0x40 }, // 2752 { PseudoVFSGNJX_VV_M8_E64_MASK, VFSGNJX_VV, 0x3, 0x40 }, // 2753 { PseudoVFSGNJX_VV_MF4_E16, VFSGNJX_VV, 0x6, 0x10 }, // 2754 { PseudoVFSGNJX_VV_MF4_E16_MASK, VFSGNJX_VV, 0x6, 0x10 }, // 2755 { PseudoVFSGNJX_VV_MF2_E16, VFSGNJX_VV, 0x7, 0x10 }, // 2756 { PseudoVFSGNJX_VV_MF2_E16_MASK, VFSGNJX_VV, 0x7, 0x10 }, // 2757 { PseudoVFSGNJX_VV_MF2_E32, VFSGNJX_VV, 0x7, 0x20 }, // 2758 { PseudoVFSGNJX_VV_MF2_E32_MASK, VFSGNJX_VV, 0x7, 0x20 }, // 2759 { PseudoVFSGNJ_VFPR16_M1_E16, VFSGNJ_VF, 0x0, 0x10 }, // 2760 { PseudoVFSGNJ_VFPR16_M1_E16_MASK, VFSGNJ_VF, 0x0, 0x10 }, // 2761 { PseudoVFSGNJ_VFPR32_M1_E32, VFSGNJ_VF, 0x0, 0x20 }, // 2762 { PseudoVFSGNJ_VFPR32_M1_E32_MASK, VFSGNJ_VF, 0x0, 0x20 }, // 2763 { PseudoVFSGNJ_VFPR64_M1_E64, VFSGNJ_VF, 0x0, 0x40 }, // 2764 { PseudoVFSGNJ_VFPR64_M1_E64_MASK, VFSGNJ_VF, 0x0, 0x40 }, // 2765 { PseudoVFSGNJ_VFPR16_M2_E16, VFSGNJ_VF, 0x1, 0x10 }, // 2766 { PseudoVFSGNJ_VFPR16_M2_E16_MASK, VFSGNJ_VF, 0x1, 0x10 }, // 2767 { PseudoVFSGNJ_VFPR32_M2_E32, VFSGNJ_VF, 0x1, 0x20 }, // 2768 { PseudoVFSGNJ_VFPR32_M2_E32_MASK, VFSGNJ_VF, 0x1, 0x20 }, // 2769 { PseudoVFSGNJ_VFPR64_M2_E64, VFSGNJ_VF, 0x1, 0x40 }, // 2770 { PseudoVFSGNJ_VFPR64_M2_E64_MASK, VFSGNJ_VF, 0x1, 0x40 }, // 2771 { PseudoVFSGNJ_VFPR16_M4_E16, VFSGNJ_VF, 0x2, 0x10 }, // 2772 { PseudoVFSGNJ_VFPR16_M4_E16_MASK, VFSGNJ_VF, 0x2, 0x10 }, // 2773 { PseudoVFSGNJ_VFPR32_M4_E32, VFSGNJ_VF, 0x2, 0x20 }, // 2774 { PseudoVFSGNJ_VFPR32_M4_E32_MASK, VFSGNJ_VF, 0x2, 0x20 }, // 2775 { PseudoVFSGNJ_VFPR64_M4_E64, VFSGNJ_VF, 0x2, 0x40 }, // 2776 { PseudoVFSGNJ_VFPR64_M4_E64_MASK, VFSGNJ_VF, 0x2, 0x40 }, // 2777 { PseudoVFSGNJ_VFPR16_M8_E16, VFSGNJ_VF, 0x3, 0x10 }, // 2778 { PseudoVFSGNJ_VFPR16_M8_E16_MASK, VFSGNJ_VF, 0x3, 0x10 }, // 2779 { PseudoVFSGNJ_VFPR32_M8_E32, VFSGNJ_VF, 0x3, 0x20 }, // 2780 { PseudoVFSGNJ_VFPR32_M8_E32_MASK, VFSGNJ_VF, 0x3, 0x20 }, // 2781 { PseudoVFSGNJ_VFPR64_M8_E64, VFSGNJ_VF, 0x3, 0x40 }, // 2782 { PseudoVFSGNJ_VFPR64_M8_E64_MASK, VFSGNJ_VF, 0x3, 0x40 }, // 2783 { PseudoVFSGNJ_VFPR16_MF4_E16, VFSGNJ_VF, 0x6, 0x10 }, // 2784 { PseudoVFSGNJ_VFPR16_MF4_E16_MASK, VFSGNJ_VF, 0x6, 0x10 }, // 2785 { PseudoVFSGNJ_VFPR16_MF2_E16, VFSGNJ_VF, 0x7, 0x10 }, // 2786 { PseudoVFSGNJ_VFPR16_MF2_E16_MASK, VFSGNJ_VF, 0x7, 0x10 }, // 2787 { PseudoVFSGNJ_VFPR32_MF2_E32, VFSGNJ_VF, 0x7, 0x20 }, // 2788 { PseudoVFSGNJ_VFPR32_MF2_E32_MASK, VFSGNJ_VF, 0x7, 0x20 }, // 2789 { PseudoVFSGNJ_VV_M1_E16, VFSGNJ_VV, 0x0, 0x10 }, // 2790 { PseudoVFSGNJ_VV_M1_E16_MASK, VFSGNJ_VV, 0x0, 0x10 }, // 2791 { PseudoVFSGNJ_VV_M1_E32, VFSGNJ_VV, 0x0, 0x20 }, // 2792 { PseudoVFSGNJ_VV_M1_E32_MASK, VFSGNJ_VV, 0x0, 0x20 }, // 2793 { PseudoVFSGNJ_VV_M1_E64, VFSGNJ_VV, 0x0, 0x40 }, // 2794 { PseudoVFSGNJ_VV_M1_E64_MASK, VFSGNJ_VV, 0x0, 0x40 }, // 2795 { PseudoVFSGNJ_VV_M2_E16, VFSGNJ_VV, 0x1, 0x10 }, // 2796 { PseudoVFSGNJ_VV_M2_E16_MASK, VFSGNJ_VV, 0x1, 0x10 }, // 2797 { PseudoVFSGNJ_VV_M2_E32, VFSGNJ_VV, 0x1, 0x20 }, // 2798 { PseudoVFSGNJ_VV_M2_E32_MASK, VFSGNJ_VV, 0x1, 0x20 }, // 2799 { PseudoVFSGNJ_VV_M2_E64, VFSGNJ_VV, 0x1, 0x40 }, // 2800 { PseudoVFSGNJ_VV_M2_E64_MASK, VFSGNJ_VV, 0x1, 0x40 }, // 2801 { PseudoVFSGNJ_VV_M4_E16, VFSGNJ_VV, 0x2, 0x10 }, // 2802 { PseudoVFSGNJ_VV_M4_E16_MASK, VFSGNJ_VV, 0x2, 0x10 }, // 2803 { PseudoVFSGNJ_VV_M4_E32, VFSGNJ_VV, 0x2, 0x20 }, // 2804 { PseudoVFSGNJ_VV_M4_E32_MASK, VFSGNJ_VV, 0x2, 0x20 }, // 2805 { PseudoVFSGNJ_VV_M4_E64, VFSGNJ_VV, 0x2, 0x40 }, // 2806 { PseudoVFSGNJ_VV_M4_E64_MASK, VFSGNJ_VV, 0x2, 0x40 }, // 2807 { PseudoVFSGNJ_VV_M8_E16, VFSGNJ_VV, 0x3, 0x10 }, // 2808 { PseudoVFSGNJ_VV_M8_E16_MASK, VFSGNJ_VV, 0x3, 0x10 }, // 2809 { PseudoVFSGNJ_VV_M8_E32, VFSGNJ_VV, 0x3, 0x20 }, // 2810 { PseudoVFSGNJ_VV_M8_E32_MASK, VFSGNJ_VV, 0x3, 0x20 }, // 2811 { PseudoVFSGNJ_VV_M8_E64, VFSGNJ_VV, 0x3, 0x40 }, // 2812 { PseudoVFSGNJ_VV_M8_E64_MASK, VFSGNJ_VV, 0x3, 0x40 }, // 2813 { PseudoVFSGNJ_VV_MF4_E16, VFSGNJ_VV, 0x6, 0x10 }, // 2814 { PseudoVFSGNJ_VV_MF4_E16_MASK, VFSGNJ_VV, 0x6, 0x10 }, // 2815 { PseudoVFSGNJ_VV_MF2_E16, VFSGNJ_VV, 0x7, 0x10 }, // 2816 { PseudoVFSGNJ_VV_MF2_E16_MASK, VFSGNJ_VV, 0x7, 0x10 }, // 2817 { PseudoVFSGNJ_VV_MF2_E32, VFSGNJ_VV, 0x7, 0x20 }, // 2818 { PseudoVFSGNJ_VV_MF2_E32_MASK, VFSGNJ_VV, 0x7, 0x20 }, // 2819 { PseudoVFSLIDE1DOWN_VFPR16_M1, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2820 { PseudoVFSLIDE1DOWN_VFPR16_M1_MASK, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2821 { PseudoVFSLIDE1DOWN_VFPR32_M1, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2822 { PseudoVFSLIDE1DOWN_VFPR32_M1_MASK, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2823 { PseudoVFSLIDE1DOWN_VFPR64_M1, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2824 { PseudoVFSLIDE1DOWN_VFPR64_M1_MASK, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2825 { PseudoVFSLIDE1DOWN_VFPR16_M2, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2826 { PseudoVFSLIDE1DOWN_VFPR16_M2_MASK, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2827 { PseudoVFSLIDE1DOWN_VFPR32_M2, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2828 { PseudoVFSLIDE1DOWN_VFPR32_M2_MASK, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2829 { PseudoVFSLIDE1DOWN_VFPR64_M2, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2830 { PseudoVFSLIDE1DOWN_VFPR64_M2_MASK, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2831 { PseudoVFSLIDE1DOWN_VFPR16_M4, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2832 { PseudoVFSLIDE1DOWN_VFPR16_M4_MASK, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2833 { PseudoVFSLIDE1DOWN_VFPR32_M4, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2834 { PseudoVFSLIDE1DOWN_VFPR32_M4_MASK, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2835 { PseudoVFSLIDE1DOWN_VFPR64_M4, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2836 { PseudoVFSLIDE1DOWN_VFPR64_M4_MASK, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2837 { PseudoVFSLIDE1DOWN_VFPR16_M8, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2838 { PseudoVFSLIDE1DOWN_VFPR16_M8_MASK, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2839 { PseudoVFSLIDE1DOWN_VFPR32_M8, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2840 { PseudoVFSLIDE1DOWN_VFPR32_M8_MASK, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2841 { PseudoVFSLIDE1DOWN_VFPR64_M8, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2842 { PseudoVFSLIDE1DOWN_VFPR64_M8_MASK, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2843 { PseudoVFSLIDE1DOWN_VFPR16_MF4, VFSLIDE1DOWN_VF, 0x6, 0x0 }, // 2844 { PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK, VFSLIDE1DOWN_VF, 0x6, 0x0 }, // 2845 { PseudoVFSLIDE1DOWN_VFPR16_MF2, VFSLIDE1DOWN_VF, 0x7, 0x0 }, // 2846 { PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK, VFSLIDE1DOWN_VF, 0x7, 0x0 }, // 2847 { PseudoVFSLIDE1DOWN_VFPR32_MF2, VFSLIDE1DOWN_VF, 0x7, 0x0 }, // 2848 { PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK, VFSLIDE1DOWN_VF, 0x7, 0x0 }, // 2849 { PseudoVFSLIDE1UP_VFPR16_M1, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2850 { PseudoVFSLIDE1UP_VFPR16_M1_MASK, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2851 { PseudoVFSLIDE1UP_VFPR32_M1, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2852 { PseudoVFSLIDE1UP_VFPR32_M1_MASK, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2853 { PseudoVFSLIDE1UP_VFPR64_M1, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2854 { PseudoVFSLIDE1UP_VFPR64_M1_MASK, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2855 { PseudoVFSLIDE1UP_VFPR16_M2, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2856 { PseudoVFSLIDE1UP_VFPR16_M2_MASK, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2857 { PseudoVFSLIDE1UP_VFPR32_M2, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2858 { PseudoVFSLIDE1UP_VFPR32_M2_MASK, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2859 { PseudoVFSLIDE1UP_VFPR64_M2, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2860 { PseudoVFSLIDE1UP_VFPR64_M2_MASK, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2861 { PseudoVFSLIDE1UP_VFPR16_M4, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2862 { PseudoVFSLIDE1UP_VFPR16_M4_MASK, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2863 { PseudoVFSLIDE1UP_VFPR32_M4, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2864 { PseudoVFSLIDE1UP_VFPR32_M4_MASK, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2865 { PseudoVFSLIDE1UP_VFPR64_M4, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2866 { PseudoVFSLIDE1UP_VFPR64_M4_MASK, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2867 { PseudoVFSLIDE1UP_VFPR16_M8, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2868 { PseudoVFSLIDE1UP_VFPR16_M8_MASK, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2869 { PseudoVFSLIDE1UP_VFPR32_M8, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2870 { PseudoVFSLIDE1UP_VFPR32_M8_MASK, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2871 { PseudoVFSLIDE1UP_VFPR64_M8, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2872 { PseudoVFSLIDE1UP_VFPR64_M8_MASK, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2873 { PseudoVFSLIDE1UP_VFPR16_MF4, VFSLIDE1UP_VF, 0x6, 0x0 }, // 2874 { PseudoVFSLIDE1UP_VFPR16_MF4_MASK, VFSLIDE1UP_VF, 0x6, 0x0 }, // 2875 { PseudoVFSLIDE1UP_VFPR16_MF2, VFSLIDE1UP_VF, 0x7, 0x0 }, // 2876 { PseudoVFSLIDE1UP_VFPR16_MF2_MASK, VFSLIDE1UP_VF, 0x7, 0x0 }, // 2877 { PseudoVFSLIDE1UP_VFPR32_MF2, VFSLIDE1UP_VF, 0x7, 0x0 }, // 2878 { PseudoVFSLIDE1UP_VFPR32_MF2_MASK, VFSLIDE1UP_VF, 0x7, 0x0 }, // 2879 { PseudoVFSQRT_V_M1_E16, VFSQRT_V, 0x0, 0x10 }, // 2880 { PseudoVFSQRT_V_M1_E16_MASK, VFSQRT_V, 0x0, 0x10 }, // 2881 { PseudoVFSQRT_V_M1_E32, VFSQRT_V, 0x0, 0x20 }, // 2882 { PseudoVFSQRT_V_M1_E32_MASK, VFSQRT_V, 0x0, 0x20 }, // 2883 { PseudoVFSQRT_V_M1_E64, VFSQRT_V, 0x0, 0x40 }, // 2884 { PseudoVFSQRT_V_M1_E64_MASK, VFSQRT_V, 0x0, 0x40 }, // 2885 { PseudoVFSQRT_V_M2_E16, VFSQRT_V, 0x1, 0x10 }, // 2886 { PseudoVFSQRT_V_M2_E16_MASK, VFSQRT_V, 0x1, 0x10 }, // 2887 { PseudoVFSQRT_V_M2_E32, VFSQRT_V, 0x1, 0x20 }, // 2888 { PseudoVFSQRT_V_M2_E32_MASK, VFSQRT_V, 0x1, 0x20 }, // 2889 { PseudoVFSQRT_V_M2_E64, VFSQRT_V, 0x1, 0x40 }, // 2890 { PseudoVFSQRT_V_M2_E64_MASK, VFSQRT_V, 0x1, 0x40 }, // 2891 { PseudoVFSQRT_V_M4_E16, VFSQRT_V, 0x2, 0x10 }, // 2892 { PseudoVFSQRT_V_M4_E16_MASK, VFSQRT_V, 0x2, 0x10 }, // 2893 { PseudoVFSQRT_V_M4_E32, VFSQRT_V, 0x2, 0x20 }, // 2894 { PseudoVFSQRT_V_M4_E32_MASK, VFSQRT_V, 0x2, 0x20 }, // 2895 { PseudoVFSQRT_V_M4_E64, VFSQRT_V, 0x2, 0x40 }, // 2896 { PseudoVFSQRT_V_M4_E64_MASK, VFSQRT_V, 0x2, 0x40 }, // 2897 { PseudoVFSQRT_V_M8_E16, VFSQRT_V, 0x3, 0x10 }, // 2898 { PseudoVFSQRT_V_M8_E16_MASK, VFSQRT_V, 0x3, 0x10 }, // 2899 { PseudoVFSQRT_V_M8_E32, VFSQRT_V, 0x3, 0x20 }, // 2900 { PseudoVFSQRT_V_M8_E32_MASK, VFSQRT_V, 0x3, 0x20 }, // 2901 { PseudoVFSQRT_V_M8_E64, VFSQRT_V, 0x3, 0x40 }, // 2902 { PseudoVFSQRT_V_M8_E64_MASK, VFSQRT_V, 0x3, 0x40 }, // 2903 { PseudoVFSQRT_V_MF4_E16, VFSQRT_V, 0x6, 0x10 }, // 2904 { PseudoVFSQRT_V_MF4_E16_MASK, VFSQRT_V, 0x6, 0x10 }, // 2905 { PseudoVFSQRT_V_MF2_E16, VFSQRT_V, 0x7, 0x10 }, // 2906 { PseudoVFSQRT_V_MF2_E16_MASK, VFSQRT_V, 0x7, 0x10 }, // 2907 { PseudoVFSQRT_V_MF2_E32, VFSQRT_V, 0x7, 0x20 }, // 2908 { PseudoVFSQRT_V_MF2_E32_MASK, VFSQRT_V, 0x7, 0x20 }, // 2909 { PseudoVFSUB_VFPR16_M1_E16, VFSUB_VF, 0x0, 0x10 }, // 2910 { PseudoVFSUB_VFPR16_M1_E16_MASK, VFSUB_VF, 0x0, 0x10 }, // 2911 { PseudoVFSUB_VFPR32_M1_E32, VFSUB_VF, 0x0, 0x20 }, // 2912 { PseudoVFSUB_VFPR32_M1_E32_MASK, VFSUB_VF, 0x0, 0x20 }, // 2913 { PseudoVFSUB_VFPR64_M1_E64, VFSUB_VF, 0x0, 0x40 }, // 2914 { PseudoVFSUB_VFPR64_M1_E64_MASK, VFSUB_VF, 0x0, 0x40 }, // 2915 { PseudoVFSUB_VFPR16_M2_E16, VFSUB_VF, 0x1, 0x10 }, // 2916 { PseudoVFSUB_VFPR16_M2_E16_MASK, VFSUB_VF, 0x1, 0x10 }, // 2917 { PseudoVFSUB_VFPR32_M2_E32, VFSUB_VF, 0x1, 0x20 }, // 2918 { PseudoVFSUB_VFPR32_M2_E32_MASK, VFSUB_VF, 0x1, 0x20 }, // 2919 { PseudoVFSUB_VFPR64_M2_E64, VFSUB_VF, 0x1, 0x40 }, // 2920 { PseudoVFSUB_VFPR64_M2_E64_MASK, VFSUB_VF, 0x1, 0x40 }, // 2921 { PseudoVFSUB_VFPR16_M4_E16, VFSUB_VF, 0x2, 0x10 }, // 2922 { PseudoVFSUB_VFPR16_M4_E16_MASK, VFSUB_VF, 0x2, 0x10 }, // 2923 { PseudoVFSUB_VFPR32_M4_E32, VFSUB_VF, 0x2, 0x20 }, // 2924 { PseudoVFSUB_VFPR32_M4_E32_MASK, VFSUB_VF, 0x2, 0x20 }, // 2925 { PseudoVFSUB_VFPR64_M4_E64, VFSUB_VF, 0x2, 0x40 }, // 2926 { PseudoVFSUB_VFPR64_M4_E64_MASK, VFSUB_VF, 0x2, 0x40 }, // 2927 { PseudoVFSUB_VFPR16_M8_E16, VFSUB_VF, 0x3, 0x10 }, // 2928 { PseudoVFSUB_VFPR16_M8_E16_MASK, VFSUB_VF, 0x3, 0x10 }, // 2929 { PseudoVFSUB_VFPR32_M8_E32, VFSUB_VF, 0x3, 0x20 }, // 2930 { PseudoVFSUB_VFPR32_M8_E32_MASK, VFSUB_VF, 0x3, 0x20 }, // 2931 { PseudoVFSUB_VFPR64_M8_E64, VFSUB_VF, 0x3, 0x40 }, // 2932 { PseudoVFSUB_VFPR64_M8_E64_MASK, VFSUB_VF, 0x3, 0x40 }, // 2933 { PseudoVFSUB_VFPR16_MF4_E16, VFSUB_VF, 0x6, 0x10 }, // 2934 { PseudoVFSUB_VFPR16_MF4_E16_MASK, VFSUB_VF, 0x6, 0x10 }, // 2935 { PseudoVFSUB_VFPR16_MF2_E16, VFSUB_VF, 0x7, 0x10 }, // 2936 { PseudoVFSUB_VFPR16_MF2_E16_MASK, VFSUB_VF, 0x7, 0x10 }, // 2937 { PseudoVFSUB_VFPR32_MF2_E32, VFSUB_VF, 0x7, 0x20 }, // 2938 { PseudoVFSUB_VFPR32_MF2_E32_MASK, VFSUB_VF, 0x7, 0x20 }, // 2939 { PseudoVFSUB_VV_M1_E16, VFSUB_VV, 0x0, 0x10 }, // 2940 { PseudoVFSUB_VV_M1_E16_MASK, VFSUB_VV, 0x0, 0x10 }, // 2941 { PseudoVFSUB_VV_M1_E32, VFSUB_VV, 0x0, 0x20 }, // 2942 { PseudoVFSUB_VV_M1_E32_MASK, VFSUB_VV, 0x0, 0x20 }, // 2943 { PseudoVFSUB_VV_M1_E64, VFSUB_VV, 0x0, 0x40 }, // 2944 { PseudoVFSUB_VV_M1_E64_MASK, VFSUB_VV, 0x0, 0x40 }, // 2945 { PseudoVFSUB_VV_M2_E16, VFSUB_VV, 0x1, 0x10 }, // 2946 { PseudoVFSUB_VV_M2_E16_MASK, VFSUB_VV, 0x1, 0x10 }, // 2947 { PseudoVFSUB_VV_M2_E32, VFSUB_VV, 0x1, 0x20 }, // 2948 { PseudoVFSUB_VV_M2_E32_MASK, VFSUB_VV, 0x1, 0x20 }, // 2949 { PseudoVFSUB_VV_M2_E64, VFSUB_VV, 0x1, 0x40 }, // 2950 { PseudoVFSUB_VV_M2_E64_MASK, VFSUB_VV, 0x1, 0x40 }, // 2951 { PseudoVFSUB_VV_M4_E16, VFSUB_VV, 0x2, 0x10 }, // 2952 { PseudoVFSUB_VV_M4_E16_MASK, VFSUB_VV, 0x2, 0x10 }, // 2953 { PseudoVFSUB_VV_M4_E32, VFSUB_VV, 0x2, 0x20 }, // 2954 { PseudoVFSUB_VV_M4_E32_MASK, VFSUB_VV, 0x2, 0x20 }, // 2955 { PseudoVFSUB_VV_M4_E64, VFSUB_VV, 0x2, 0x40 }, // 2956 { PseudoVFSUB_VV_M4_E64_MASK, VFSUB_VV, 0x2, 0x40 }, // 2957 { PseudoVFSUB_VV_M8_E16, VFSUB_VV, 0x3, 0x10 }, // 2958 { PseudoVFSUB_VV_M8_E16_MASK, VFSUB_VV, 0x3, 0x10 }, // 2959 { PseudoVFSUB_VV_M8_E32, VFSUB_VV, 0x3, 0x20 }, // 2960 { PseudoVFSUB_VV_M8_E32_MASK, VFSUB_VV, 0x3, 0x20 }, // 2961 { PseudoVFSUB_VV_M8_E64, VFSUB_VV, 0x3, 0x40 }, // 2962 { PseudoVFSUB_VV_M8_E64_MASK, VFSUB_VV, 0x3, 0x40 }, // 2963 { PseudoVFSUB_VV_MF4_E16, VFSUB_VV, 0x6, 0x10 }, // 2964 { PseudoVFSUB_VV_MF4_E16_MASK, VFSUB_VV, 0x6, 0x10 }, // 2965 { PseudoVFSUB_VV_MF2_E16, VFSUB_VV, 0x7, 0x10 }, // 2966 { PseudoVFSUB_VV_MF2_E16_MASK, VFSUB_VV, 0x7, 0x10 }, // 2967 { PseudoVFSUB_VV_MF2_E32, VFSUB_VV, 0x7, 0x20 }, // 2968 { PseudoVFSUB_VV_MF2_E32_MASK, VFSUB_VV, 0x7, 0x20 }, // 2969 { PseudoVFWADD_VFPR16_M1_E16, VFWADD_VF, 0x0, 0x10 }, // 2970 { PseudoVFWADD_VFPR16_M1_E16_MASK, VFWADD_VF, 0x0, 0x10 }, // 2971 { PseudoVFWADD_VFPR32_M1_E32, VFWADD_VF, 0x0, 0x20 }, // 2972 { PseudoVFWADD_VFPR32_M1_E32_MASK, VFWADD_VF, 0x0, 0x20 }, // 2973 { PseudoVFWADD_VFPR16_M2_E16, VFWADD_VF, 0x1, 0x10 }, // 2974 { PseudoVFWADD_VFPR16_M2_E16_MASK, VFWADD_VF, 0x1, 0x10 }, // 2975 { PseudoVFWADD_VFPR32_M2_E32, VFWADD_VF, 0x1, 0x20 }, // 2976 { PseudoVFWADD_VFPR32_M2_E32_MASK, VFWADD_VF, 0x1, 0x20 }, // 2977 { PseudoVFWADD_VFPR16_M4_E16, VFWADD_VF, 0x2, 0x10 }, // 2978 { PseudoVFWADD_VFPR16_M4_E16_MASK, VFWADD_VF, 0x2, 0x10 }, // 2979 { PseudoVFWADD_VFPR32_M4_E32, VFWADD_VF, 0x2, 0x20 }, // 2980 { PseudoVFWADD_VFPR32_M4_E32_MASK, VFWADD_VF, 0x2, 0x20 }, // 2981 { PseudoVFWADD_VFPR16_MF4_E16, VFWADD_VF, 0x6, 0x10 }, // 2982 { PseudoVFWADD_VFPR16_MF4_E16_MASK, VFWADD_VF, 0x6, 0x10 }, // 2983 { PseudoVFWADD_VFPR16_MF2_E16, VFWADD_VF, 0x7, 0x10 }, // 2984 { PseudoVFWADD_VFPR16_MF2_E16_MASK, VFWADD_VF, 0x7, 0x10 }, // 2985 { PseudoVFWADD_VFPR32_MF2_E32, VFWADD_VF, 0x7, 0x20 }, // 2986 { PseudoVFWADD_VFPR32_MF2_E32_MASK, VFWADD_VF, 0x7, 0x20 }, // 2987 { PseudoVFWADD_VV_M1_E16, VFWADD_VV, 0x0, 0x10 }, // 2988 { PseudoVFWADD_VV_M1_E16_MASK, VFWADD_VV, 0x0, 0x10 }, // 2989 { PseudoVFWADD_VV_M1_E32, VFWADD_VV, 0x0, 0x20 }, // 2990 { PseudoVFWADD_VV_M1_E32_MASK, VFWADD_VV, 0x0, 0x20 }, // 2991 { PseudoVFWADD_VV_M2_E16, VFWADD_VV, 0x1, 0x10 }, // 2992 { PseudoVFWADD_VV_M2_E16_MASK, VFWADD_VV, 0x1, 0x10 }, // 2993 { PseudoVFWADD_VV_M2_E32, VFWADD_VV, 0x1, 0x20 }, // 2994 { PseudoVFWADD_VV_M2_E32_MASK, VFWADD_VV, 0x1, 0x20 }, // 2995 { PseudoVFWADD_VV_M4_E16, VFWADD_VV, 0x2, 0x10 }, // 2996 { PseudoVFWADD_VV_M4_E16_MASK, VFWADD_VV, 0x2, 0x10 }, // 2997 { PseudoVFWADD_VV_M4_E32, VFWADD_VV, 0x2, 0x20 }, // 2998 { PseudoVFWADD_VV_M4_E32_MASK, VFWADD_VV, 0x2, 0x20 }, // 2999 { PseudoVFWADD_VV_MF4_E16, VFWADD_VV, 0x6, 0x10 }, // 3000 { PseudoVFWADD_VV_MF4_E16_MASK, VFWADD_VV, 0x6, 0x10 }, // 3001 { PseudoVFWADD_VV_MF2_E16, VFWADD_VV, 0x7, 0x10 }, // 3002 { PseudoVFWADD_VV_MF2_E16_MASK, VFWADD_VV, 0x7, 0x10 }, // 3003 { PseudoVFWADD_VV_MF2_E32, VFWADD_VV, 0x7, 0x20 }, // 3004 { PseudoVFWADD_VV_MF2_E32_MASK, VFWADD_VV, 0x7, 0x20 }, // 3005 { PseudoVFWADD_WFPR16_M1_E16, VFWADD_WF, 0x0, 0x10 }, // 3006 { PseudoVFWADD_WFPR16_M1_E16_MASK, VFWADD_WF, 0x0, 0x10 }, // 3007 { PseudoVFWADD_WFPR32_M1_E32, VFWADD_WF, 0x0, 0x20 }, // 3008 { PseudoVFWADD_WFPR32_M1_E32_MASK, VFWADD_WF, 0x0, 0x20 }, // 3009 { PseudoVFWADD_WFPR16_M2_E16, VFWADD_WF, 0x1, 0x10 }, // 3010 { PseudoVFWADD_WFPR16_M2_E16_MASK, VFWADD_WF, 0x1, 0x10 }, // 3011 { PseudoVFWADD_WFPR32_M2_E32, VFWADD_WF, 0x1, 0x20 }, // 3012 { PseudoVFWADD_WFPR32_M2_E32_MASK, VFWADD_WF, 0x1, 0x20 }, // 3013 { PseudoVFWADD_WFPR16_M4_E16, VFWADD_WF, 0x2, 0x10 }, // 3014 { PseudoVFWADD_WFPR16_M4_E16_MASK, VFWADD_WF, 0x2, 0x10 }, // 3015 { PseudoVFWADD_WFPR32_M4_E32, VFWADD_WF, 0x2, 0x20 }, // 3016 { PseudoVFWADD_WFPR32_M4_E32_MASK, VFWADD_WF, 0x2, 0x20 }, // 3017 { PseudoVFWADD_WFPR16_MF4_E16, VFWADD_WF, 0x6, 0x10 }, // 3018 { PseudoVFWADD_WFPR16_MF4_E16_MASK, VFWADD_WF, 0x6, 0x10 }, // 3019 { PseudoVFWADD_WFPR16_MF2_E16, VFWADD_WF, 0x7, 0x10 }, // 3020 { PseudoVFWADD_WFPR16_MF2_E16_MASK, VFWADD_WF, 0x7, 0x10 }, // 3021 { PseudoVFWADD_WFPR32_MF2_E32, VFWADD_WF, 0x7, 0x20 }, // 3022 { PseudoVFWADD_WFPR32_MF2_E32_MASK, VFWADD_WF, 0x7, 0x20 }, // 3023 { PseudoVFWADD_WV_M1_E16_MASK_TIED, VFWADD_WV, 0x0, 0x0 }, // 3024 { PseudoVFWADD_WV_M1_E16_TIED, VFWADD_WV, 0x0, 0x0 }, // 3025 { PseudoVFWADD_WV_M1_E32_MASK_TIED, VFWADD_WV, 0x0, 0x0 }, // 3026 { PseudoVFWADD_WV_M1_E32_TIED, VFWADD_WV, 0x0, 0x0 }, // 3027 { PseudoVFWADD_WV_M1_E16, VFWADD_WV, 0x0, 0x10 }, // 3028 { PseudoVFWADD_WV_M1_E16_MASK, VFWADD_WV, 0x0, 0x10 }, // 3029 { PseudoVFWADD_WV_M1_E32, VFWADD_WV, 0x0, 0x20 }, // 3030 { PseudoVFWADD_WV_M1_E32_MASK, VFWADD_WV, 0x0, 0x20 }, // 3031 { PseudoVFWADD_WV_M2_E16_MASK_TIED, VFWADD_WV, 0x1, 0x0 }, // 3032 { PseudoVFWADD_WV_M2_E16_TIED, VFWADD_WV, 0x1, 0x0 }, // 3033 { PseudoVFWADD_WV_M2_E32_MASK_TIED, VFWADD_WV, 0x1, 0x0 }, // 3034 { PseudoVFWADD_WV_M2_E32_TIED, VFWADD_WV, 0x1, 0x0 }, // 3035 { PseudoVFWADD_WV_M2_E16, VFWADD_WV, 0x1, 0x10 }, // 3036 { PseudoVFWADD_WV_M2_E16_MASK, VFWADD_WV, 0x1, 0x10 }, // 3037 { PseudoVFWADD_WV_M2_E32, VFWADD_WV, 0x1, 0x20 }, // 3038 { PseudoVFWADD_WV_M2_E32_MASK, VFWADD_WV, 0x1, 0x20 }, // 3039 { PseudoVFWADD_WV_M4_E16_MASK_TIED, VFWADD_WV, 0x2, 0x0 }, // 3040 { PseudoVFWADD_WV_M4_E16_TIED, VFWADD_WV, 0x2, 0x0 }, // 3041 { PseudoVFWADD_WV_M4_E32_MASK_TIED, VFWADD_WV, 0x2, 0x0 }, // 3042 { PseudoVFWADD_WV_M4_E32_TIED, VFWADD_WV, 0x2, 0x0 }, // 3043 { PseudoVFWADD_WV_M4_E16, VFWADD_WV, 0x2, 0x10 }, // 3044 { PseudoVFWADD_WV_M4_E16_MASK, VFWADD_WV, 0x2, 0x10 }, // 3045 { PseudoVFWADD_WV_M4_E32, VFWADD_WV, 0x2, 0x20 }, // 3046 { PseudoVFWADD_WV_M4_E32_MASK, VFWADD_WV, 0x2, 0x20 }, // 3047 { PseudoVFWADD_WV_MF4_E16_MASK_TIED, VFWADD_WV, 0x6, 0x0 }, // 3048 { PseudoVFWADD_WV_MF4_E16_TIED, VFWADD_WV, 0x6, 0x0 }, // 3049 { PseudoVFWADD_WV_MF4_E16, VFWADD_WV, 0x6, 0x10 }, // 3050 { PseudoVFWADD_WV_MF4_E16_MASK, VFWADD_WV, 0x6, 0x10 }, // 3051 { PseudoVFWADD_WV_MF2_E16_MASK_TIED, VFWADD_WV, 0x7, 0x0 }, // 3052 { PseudoVFWADD_WV_MF2_E16_TIED, VFWADD_WV, 0x7, 0x0 }, // 3053 { PseudoVFWADD_WV_MF2_E32_MASK_TIED, VFWADD_WV, 0x7, 0x0 }, // 3054 { PseudoVFWADD_WV_MF2_E32_TIED, VFWADD_WV, 0x7, 0x0 }, // 3055 { PseudoVFWADD_WV_MF2_E16, VFWADD_WV, 0x7, 0x10 }, // 3056 { PseudoVFWADD_WV_MF2_E16_MASK, VFWADD_WV, 0x7, 0x10 }, // 3057 { PseudoVFWADD_WV_MF2_E32, VFWADD_WV, 0x7, 0x20 }, // 3058 { PseudoVFWADD_WV_MF2_E32_MASK, VFWADD_WV, 0x7, 0x20 }, // 3059 { PseudoVFWCVTBF16_F_F_V_M1_E16, VFWCVTBF16_F_F_V, 0x0, 0x10 }, // 3060 { PseudoVFWCVTBF16_F_F_V_M1_E16_MASK, VFWCVTBF16_F_F_V, 0x0, 0x10 }, // 3061 { PseudoVFWCVTBF16_F_F_V_M1_E32, VFWCVTBF16_F_F_V, 0x0, 0x20 }, // 3062 { PseudoVFWCVTBF16_F_F_V_M1_E32_MASK, VFWCVTBF16_F_F_V, 0x0, 0x20 }, // 3063 { PseudoVFWCVTBF16_F_F_V_M2_E16, VFWCVTBF16_F_F_V, 0x1, 0x10 }, // 3064 { PseudoVFWCVTBF16_F_F_V_M2_E16_MASK, VFWCVTBF16_F_F_V, 0x1, 0x10 }, // 3065 { PseudoVFWCVTBF16_F_F_V_M2_E32, VFWCVTBF16_F_F_V, 0x1, 0x20 }, // 3066 { PseudoVFWCVTBF16_F_F_V_M2_E32_MASK, VFWCVTBF16_F_F_V, 0x1, 0x20 }, // 3067 { PseudoVFWCVTBF16_F_F_V_M4_E16, VFWCVTBF16_F_F_V, 0x2, 0x10 }, // 3068 { PseudoVFWCVTBF16_F_F_V_M4_E16_MASK, VFWCVTBF16_F_F_V, 0x2, 0x10 }, // 3069 { PseudoVFWCVTBF16_F_F_V_M4_E32, VFWCVTBF16_F_F_V, 0x2, 0x20 }, // 3070 { PseudoVFWCVTBF16_F_F_V_M4_E32_MASK, VFWCVTBF16_F_F_V, 0x2, 0x20 }, // 3071 { PseudoVFWCVTBF16_F_F_V_MF4_E16, VFWCVTBF16_F_F_V, 0x6, 0x10 }, // 3072 { PseudoVFWCVTBF16_F_F_V_MF4_E16_MASK, VFWCVTBF16_F_F_V, 0x6, 0x10 }, // 3073 { PseudoVFWCVTBF16_F_F_V_MF2_E16, VFWCVTBF16_F_F_V, 0x7, 0x10 }, // 3074 { PseudoVFWCVTBF16_F_F_V_MF2_E16_MASK, VFWCVTBF16_F_F_V, 0x7, 0x10 }, // 3075 { PseudoVFWCVTBF16_F_F_V_MF2_E32, VFWCVTBF16_F_F_V, 0x7, 0x20 }, // 3076 { PseudoVFWCVTBF16_F_F_V_MF2_E32_MASK, VFWCVTBF16_F_F_V, 0x7, 0x20 }, // 3077 { PseudoVFWCVT_F_F_V_M1_E16, VFWCVT_F_F_V, 0x0, 0x10 }, // 3078 { PseudoVFWCVT_F_F_V_M1_E16_MASK, VFWCVT_F_F_V, 0x0, 0x10 }, // 3079 { PseudoVFWCVT_F_F_V_M1_E32, VFWCVT_F_F_V, 0x0, 0x20 }, // 3080 { PseudoVFWCVT_F_F_V_M1_E32_MASK, VFWCVT_F_F_V, 0x0, 0x20 }, // 3081 { PseudoVFWCVT_F_F_V_M2_E16, VFWCVT_F_F_V, 0x1, 0x10 }, // 3082 { PseudoVFWCVT_F_F_V_M2_E16_MASK, VFWCVT_F_F_V, 0x1, 0x10 }, // 3083 { PseudoVFWCVT_F_F_V_M2_E32, VFWCVT_F_F_V, 0x1, 0x20 }, // 3084 { PseudoVFWCVT_F_F_V_M2_E32_MASK, VFWCVT_F_F_V, 0x1, 0x20 }, // 3085 { PseudoVFWCVT_F_F_V_M4_E16, VFWCVT_F_F_V, 0x2, 0x10 }, // 3086 { PseudoVFWCVT_F_F_V_M4_E16_MASK, VFWCVT_F_F_V, 0x2, 0x10 }, // 3087 { PseudoVFWCVT_F_F_V_M4_E32, VFWCVT_F_F_V, 0x2, 0x20 }, // 3088 { PseudoVFWCVT_F_F_V_M4_E32_MASK, VFWCVT_F_F_V, 0x2, 0x20 }, // 3089 { PseudoVFWCVT_F_F_V_MF4_E16, VFWCVT_F_F_V, 0x6, 0x10 }, // 3090 { PseudoVFWCVT_F_F_V_MF4_E16_MASK, VFWCVT_F_F_V, 0x6, 0x10 }, // 3091 { PseudoVFWCVT_F_F_V_MF2_E16, VFWCVT_F_F_V, 0x7, 0x10 }, // 3092 { PseudoVFWCVT_F_F_V_MF2_E16_MASK, VFWCVT_F_F_V, 0x7, 0x10 }, // 3093 { PseudoVFWCVT_F_F_V_MF2_E32, VFWCVT_F_F_V, 0x7, 0x20 }, // 3094 { PseudoVFWCVT_F_F_V_MF2_E32_MASK, VFWCVT_F_F_V, 0x7, 0x20 }, // 3095 { PseudoVFWCVT_F_XU_V_M1_E8, VFWCVT_F_XU_V, 0x0, 0x8 }, // 3096 { PseudoVFWCVT_F_XU_V_M1_E8_MASK, VFWCVT_F_XU_V, 0x0, 0x8 }, // 3097 { PseudoVFWCVT_F_XU_V_M1_E16, VFWCVT_F_XU_V, 0x0, 0x10 }, // 3098 { PseudoVFWCVT_F_XU_V_M1_E16_MASK, VFWCVT_F_XU_V, 0x0, 0x10 }, // 3099 { PseudoVFWCVT_F_XU_V_M1_E32, VFWCVT_F_XU_V, 0x0, 0x20 }, // 3100 { PseudoVFWCVT_F_XU_V_M1_E32_MASK, VFWCVT_F_XU_V, 0x0, 0x20 }, // 3101 { PseudoVFWCVT_F_XU_V_M2_E8, VFWCVT_F_XU_V, 0x1, 0x8 }, // 3102 { PseudoVFWCVT_F_XU_V_M2_E8_MASK, VFWCVT_F_XU_V, 0x1, 0x8 }, // 3103 { PseudoVFWCVT_F_XU_V_M2_E16, VFWCVT_F_XU_V, 0x1, 0x10 }, // 3104 { PseudoVFWCVT_F_XU_V_M2_E16_MASK, VFWCVT_F_XU_V, 0x1, 0x10 }, // 3105 { PseudoVFWCVT_F_XU_V_M2_E32, VFWCVT_F_XU_V, 0x1, 0x20 }, // 3106 { PseudoVFWCVT_F_XU_V_M2_E32_MASK, VFWCVT_F_XU_V, 0x1, 0x20 }, // 3107 { PseudoVFWCVT_F_XU_V_M4_E8, VFWCVT_F_XU_V, 0x2, 0x8 }, // 3108 { PseudoVFWCVT_F_XU_V_M4_E8_MASK, VFWCVT_F_XU_V, 0x2, 0x8 }, // 3109 { PseudoVFWCVT_F_XU_V_M4_E16, VFWCVT_F_XU_V, 0x2, 0x10 }, // 3110 { PseudoVFWCVT_F_XU_V_M4_E16_MASK, VFWCVT_F_XU_V, 0x2, 0x10 }, // 3111 { PseudoVFWCVT_F_XU_V_M4_E32, VFWCVT_F_XU_V, 0x2, 0x20 }, // 3112 { PseudoVFWCVT_F_XU_V_M4_E32_MASK, VFWCVT_F_XU_V, 0x2, 0x20 }, // 3113 { PseudoVFWCVT_F_XU_V_MF8_E8, VFWCVT_F_XU_V, 0x5, 0x8 }, // 3114 { PseudoVFWCVT_F_XU_V_MF8_E8_MASK, VFWCVT_F_XU_V, 0x5, 0x8 }, // 3115 { PseudoVFWCVT_F_XU_V_MF4_E8, VFWCVT_F_XU_V, 0x6, 0x8 }, // 3116 { PseudoVFWCVT_F_XU_V_MF4_E8_MASK, VFWCVT_F_XU_V, 0x6, 0x8 }, // 3117 { PseudoVFWCVT_F_XU_V_MF4_E16, VFWCVT_F_XU_V, 0x6, 0x10 }, // 3118 { PseudoVFWCVT_F_XU_V_MF4_E16_MASK, VFWCVT_F_XU_V, 0x6, 0x10 }, // 3119 { PseudoVFWCVT_F_XU_V_MF2_E8, VFWCVT_F_XU_V, 0x7, 0x8 }, // 3120 { PseudoVFWCVT_F_XU_V_MF2_E8_MASK, VFWCVT_F_XU_V, 0x7, 0x8 }, // 3121 { PseudoVFWCVT_F_XU_V_MF2_E16, VFWCVT_F_XU_V, 0x7, 0x10 }, // 3122 { PseudoVFWCVT_F_XU_V_MF2_E16_MASK, VFWCVT_F_XU_V, 0x7, 0x10 }, // 3123 { PseudoVFWCVT_F_XU_V_MF2_E32, VFWCVT_F_XU_V, 0x7, 0x20 }, // 3124 { PseudoVFWCVT_F_XU_V_MF2_E32_MASK, VFWCVT_F_XU_V, 0x7, 0x20 }, // 3125 { PseudoVFWCVT_F_X_V_M1_E8, VFWCVT_F_X_V, 0x0, 0x8 }, // 3126 { PseudoVFWCVT_F_X_V_M1_E8_MASK, VFWCVT_F_X_V, 0x0, 0x8 }, // 3127 { PseudoVFWCVT_F_X_V_M1_E16, VFWCVT_F_X_V, 0x0, 0x10 }, // 3128 { PseudoVFWCVT_F_X_V_M1_E16_MASK, VFWCVT_F_X_V, 0x0, 0x10 }, // 3129 { PseudoVFWCVT_F_X_V_M1_E32, VFWCVT_F_X_V, 0x0, 0x20 }, // 3130 { PseudoVFWCVT_F_X_V_M1_E32_MASK, VFWCVT_F_X_V, 0x0, 0x20 }, // 3131 { PseudoVFWCVT_F_X_V_M2_E8, VFWCVT_F_X_V, 0x1, 0x8 }, // 3132 { PseudoVFWCVT_F_X_V_M2_E8_MASK, VFWCVT_F_X_V, 0x1, 0x8 }, // 3133 { PseudoVFWCVT_F_X_V_M2_E16, VFWCVT_F_X_V, 0x1, 0x10 }, // 3134 { PseudoVFWCVT_F_X_V_M2_E16_MASK, VFWCVT_F_X_V, 0x1, 0x10 }, // 3135 { PseudoVFWCVT_F_X_V_M2_E32, VFWCVT_F_X_V, 0x1, 0x20 }, // 3136 { PseudoVFWCVT_F_X_V_M2_E32_MASK, VFWCVT_F_X_V, 0x1, 0x20 }, // 3137 { PseudoVFWCVT_F_X_V_M4_E8, VFWCVT_F_X_V, 0x2, 0x8 }, // 3138 { PseudoVFWCVT_F_X_V_M4_E8_MASK, VFWCVT_F_X_V, 0x2, 0x8 }, // 3139 { PseudoVFWCVT_F_X_V_M4_E16, VFWCVT_F_X_V, 0x2, 0x10 }, // 3140 { PseudoVFWCVT_F_X_V_M4_E16_MASK, VFWCVT_F_X_V, 0x2, 0x10 }, // 3141 { PseudoVFWCVT_F_X_V_M4_E32, VFWCVT_F_X_V, 0x2, 0x20 }, // 3142 { PseudoVFWCVT_F_X_V_M4_E32_MASK, VFWCVT_F_X_V, 0x2, 0x20 }, // 3143 { PseudoVFWCVT_F_X_V_MF8_E8, VFWCVT_F_X_V, 0x5, 0x8 }, // 3144 { PseudoVFWCVT_F_X_V_MF8_E8_MASK, VFWCVT_F_X_V, 0x5, 0x8 }, // 3145 { PseudoVFWCVT_F_X_V_MF4_E8, VFWCVT_F_X_V, 0x6, 0x8 }, // 3146 { PseudoVFWCVT_F_X_V_MF4_E8_MASK, VFWCVT_F_X_V, 0x6, 0x8 }, // 3147 { PseudoVFWCVT_F_X_V_MF4_E16, VFWCVT_F_X_V, 0x6, 0x10 }, // 3148 { PseudoVFWCVT_F_X_V_MF4_E16_MASK, VFWCVT_F_X_V, 0x6, 0x10 }, // 3149 { PseudoVFWCVT_F_X_V_MF2_E8, VFWCVT_F_X_V, 0x7, 0x8 }, // 3150 { PseudoVFWCVT_F_X_V_MF2_E8_MASK, VFWCVT_F_X_V, 0x7, 0x8 }, // 3151 { PseudoVFWCVT_F_X_V_MF2_E16, VFWCVT_F_X_V, 0x7, 0x10 }, // 3152 { PseudoVFWCVT_F_X_V_MF2_E16_MASK, VFWCVT_F_X_V, 0x7, 0x10 }, // 3153 { PseudoVFWCVT_F_X_V_MF2_E32, VFWCVT_F_X_V, 0x7, 0x20 }, // 3154 { PseudoVFWCVT_F_X_V_MF2_E32_MASK, VFWCVT_F_X_V, 0x7, 0x20 }, // 3155 { PseudoVFWCVT_RTZ_XU_F_V_M1, VFWCVT_RTZ_XU_F_V, 0x0, 0x0 }, // 3156 { PseudoVFWCVT_RTZ_XU_F_V_M1_MASK, VFWCVT_RTZ_XU_F_V, 0x0, 0x0 }, // 3157 { PseudoVFWCVT_RTZ_XU_F_V_M2, VFWCVT_RTZ_XU_F_V, 0x1, 0x0 }, // 3158 { PseudoVFWCVT_RTZ_XU_F_V_M2_MASK, VFWCVT_RTZ_XU_F_V, 0x1, 0x0 }, // 3159 { PseudoVFWCVT_RTZ_XU_F_V_M4, VFWCVT_RTZ_XU_F_V, 0x2, 0x0 }, // 3160 { PseudoVFWCVT_RTZ_XU_F_V_M4_MASK, VFWCVT_RTZ_XU_F_V, 0x2, 0x0 }, // 3161 { PseudoVFWCVT_RTZ_XU_F_V_MF4, VFWCVT_RTZ_XU_F_V, 0x6, 0x0 }, // 3162 { PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK, VFWCVT_RTZ_XU_F_V, 0x6, 0x0 }, // 3163 { PseudoVFWCVT_RTZ_XU_F_V_MF2, VFWCVT_RTZ_XU_F_V, 0x7, 0x0 }, // 3164 { PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK, VFWCVT_RTZ_XU_F_V, 0x7, 0x0 }, // 3165 { PseudoVFWCVT_RTZ_X_F_V_M1, VFWCVT_RTZ_X_F_V, 0x0, 0x0 }, // 3166 { PseudoVFWCVT_RTZ_X_F_V_M1_MASK, VFWCVT_RTZ_X_F_V, 0x0, 0x0 }, // 3167 { PseudoVFWCVT_RTZ_X_F_V_M2, VFWCVT_RTZ_X_F_V, 0x1, 0x0 }, // 3168 { PseudoVFWCVT_RTZ_X_F_V_M2_MASK, VFWCVT_RTZ_X_F_V, 0x1, 0x0 }, // 3169 { PseudoVFWCVT_RTZ_X_F_V_M4, VFWCVT_RTZ_X_F_V, 0x2, 0x0 }, // 3170 { PseudoVFWCVT_RTZ_X_F_V_M4_MASK, VFWCVT_RTZ_X_F_V, 0x2, 0x0 }, // 3171 { PseudoVFWCVT_RTZ_X_F_V_MF4, VFWCVT_RTZ_X_F_V, 0x6, 0x0 }, // 3172 { PseudoVFWCVT_RTZ_X_F_V_MF4_MASK, VFWCVT_RTZ_X_F_V, 0x6, 0x0 }, // 3173 { PseudoVFWCVT_RTZ_X_F_V_MF2, VFWCVT_RTZ_X_F_V, 0x7, 0x0 }, // 3174 { PseudoVFWCVT_RTZ_X_F_V_MF2_MASK, VFWCVT_RTZ_X_F_V, 0x7, 0x0 }, // 3175 { PseudoVFWCVT_RM_XU_F_V_M1, VFWCVT_XU_F_V, 0x0, 0x0 }, // 3176 { PseudoVFWCVT_RM_XU_F_V_M1_MASK, VFWCVT_XU_F_V, 0x0, 0x0 }, // 3177 { PseudoVFWCVT_XU_F_V_M1, VFWCVT_XU_F_V, 0x0, 0x0 }, // 3178 { PseudoVFWCVT_XU_F_V_M1_MASK, VFWCVT_XU_F_V, 0x0, 0x0 }, // 3179 { PseudoVFWCVT_RM_XU_F_V_M2, VFWCVT_XU_F_V, 0x1, 0x0 }, // 3180 { PseudoVFWCVT_RM_XU_F_V_M2_MASK, VFWCVT_XU_F_V, 0x1, 0x0 }, // 3181 { PseudoVFWCVT_XU_F_V_M2, VFWCVT_XU_F_V, 0x1, 0x0 }, // 3182 { PseudoVFWCVT_XU_F_V_M2_MASK, VFWCVT_XU_F_V, 0x1, 0x0 }, // 3183 { PseudoVFWCVT_RM_XU_F_V_M4, VFWCVT_XU_F_V, 0x2, 0x0 }, // 3184 { PseudoVFWCVT_RM_XU_F_V_M4_MASK, VFWCVT_XU_F_V, 0x2, 0x0 }, // 3185 { PseudoVFWCVT_XU_F_V_M4, VFWCVT_XU_F_V, 0x2, 0x0 }, // 3186 { PseudoVFWCVT_XU_F_V_M4_MASK, VFWCVT_XU_F_V, 0x2, 0x0 }, // 3187 { PseudoVFWCVT_RM_XU_F_V_MF4, VFWCVT_XU_F_V, 0x6, 0x0 }, // 3188 { PseudoVFWCVT_RM_XU_F_V_MF4_MASK, VFWCVT_XU_F_V, 0x6, 0x0 }, // 3189 { PseudoVFWCVT_XU_F_V_MF4, VFWCVT_XU_F_V, 0x6, 0x0 }, // 3190 { PseudoVFWCVT_XU_F_V_MF4_MASK, VFWCVT_XU_F_V, 0x6, 0x0 }, // 3191 { PseudoVFWCVT_RM_XU_F_V_MF2, VFWCVT_XU_F_V, 0x7, 0x0 }, // 3192 { PseudoVFWCVT_RM_XU_F_V_MF2_MASK, VFWCVT_XU_F_V, 0x7, 0x0 }, // 3193 { PseudoVFWCVT_XU_F_V_MF2, VFWCVT_XU_F_V, 0x7, 0x0 }, // 3194 { PseudoVFWCVT_XU_F_V_MF2_MASK, VFWCVT_XU_F_V, 0x7, 0x0 }, // 3195 { PseudoVFWCVT_RM_X_F_V_M1, VFWCVT_X_F_V, 0x0, 0x0 }, // 3196 { PseudoVFWCVT_RM_X_F_V_M1_MASK, VFWCVT_X_F_V, 0x0, 0x0 }, // 3197 { PseudoVFWCVT_X_F_V_M1, VFWCVT_X_F_V, 0x0, 0x0 }, // 3198 { PseudoVFWCVT_X_F_V_M1_MASK, VFWCVT_X_F_V, 0x0, 0x0 }, // 3199 { PseudoVFWCVT_RM_X_F_V_M2, VFWCVT_X_F_V, 0x1, 0x0 }, // 3200 { PseudoVFWCVT_RM_X_F_V_M2_MASK, VFWCVT_X_F_V, 0x1, 0x0 }, // 3201 { PseudoVFWCVT_X_F_V_M2, VFWCVT_X_F_V, 0x1, 0x0 }, // 3202 { PseudoVFWCVT_X_F_V_M2_MASK, VFWCVT_X_F_V, 0x1, 0x0 }, // 3203 { PseudoVFWCVT_RM_X_F_V_M4, VFWCVT_X_F_V, 0x2, 0x0 }, // 3204 { PseudoVFWCVT_RM_X_F_V_M4_MASK, VFWCVT_X_F_V, 0x2, 0x0 }, // 3205 { PseudoVFWCVT_X_F_V_M4, VFWCVT_X_F_V, 0x2, 0x0 }, // 3206 { PseudoVFWCVT_X_F_V_M4_MASK, VFWCVT_X_F_V, 0x2, 0x0 }, // 3207 { PseudoVFWCVT_RM_X_F_V_MF4, VFWCVT_X_F_V, 0x6, 0x0 }, // 3208 { PseudoVFWCVT_RM_X_F_V_MF4_MASK, VFWCVT_X_F_V, 0x6, 0x0 }, // 3209 { PseudoVFWCVT_X_F_V_MF4, VFWCVT_X_F_V, 0x6, 0x0 }, // 3210 { PseudoVFWCVT_X_F_V_MF4_MASK, VFWCVT_X_F_V, 0x6, 0x0 }, // 3211 { PseudoVFWCVT_RM_X_F_V_MF2, VFWCVT_X_F_V, 0x7, 0x0 }, // 3212 { PseudoVFWCVT_RM_X_F_V_MF2_MASK, VFWCVT_X_F_V, 0x7, 0x0 }, // 3213 { PseudoVFWCVT_X_F_V_MF2, VFWCVT_X_F_V, 0x7, 0x0 }, // 3214 { PseudoVFWCVT_X_F_V_MF2_MASK, VFWCVT_X_F_V, 0x7, 0x0 }, // 3215 { PseudoVFWMACCBF16_VFPR16_M1_E16, VFWMACCBF16_VF, 0x0, 0x0 }, // 3216 { PseudoVFWMACCBF16_VFPR16_M1_E16_MASK, VFWMACCBF16_VF, 0x0, 0x0 }, // 3217 { PseudoVFWMACCBF16_VFPR16_M2_E16, VFWMACCBF16_VF, 0x1, 0x0 }, // 3218 { PseudoVFWMACCBF16_VFPR16_M2_E16_MASK, VFWMACCBF16_VF, 0x1, 0x0 }, // 3219 { PseudoVFWMACCBF16_VFPR16_M4_E16, VFWMACCBF16_VF, 0x2, 0x0 }, // 3220 { PseudoVFWMACCBF16_VFPR16_M4_E16_MASK, VFWMACCBF16_VF, 0x2, 0x0 }, // 3221 { PseudoVFWMACCBF16_VFPR16_MF4_E16, VFWMACCBF16_VF, 0x6, 0x0 }, // 3222 { PseudoVFWMACCBF16_VFPR16_MF4_E16_MASK, VFWMACCBF16_VF, 0x6, 0x0 }, // 3223 { PseudoVFWMACCBF16_VFPR16_MF2_E16, VFWMACCBF16_VF, 0x7, 0x0 }, // 3224 { PseudoVFWMACCBF16_VFPR16_MF2_E16_MASK, VFWMACCBF16_VF, 0x7, 0x0 }, // 3225 { PseudoVFWMACCBF16_VV_M1_E16, VFWMACCBF16_VV, 0x0, 0x0 }, // 3226 { PseudoVFWMACCBF16_VV_M1_E16_MASK, VFWMACCBF16_VV, 0x0, 0x0 }, // 3227 { PseudoVFWMACCBF16_VV_M1_E32, VFWMACCBF16_VV, 0x0, 0x0 }, // 3228 { PseudoVFWMACCBF16_VV_M1_E32_MASK, VFWMACCBF16_VV, 0x0, 0x0 }, // 3229 { PseudoVFWMACCBF16_VV_M2_E16, VFWMACCBF16_VV, 0x1, 0x0 }, // 3230 { PseudoVFWMACCBF16_VV_M2_E16_MASK, VFWMACCBF16_VV, 0x1, 0x0 }, // 3231 { PseudoVFWMACCBF16_VV_M2_E32, VFWMACCBF16_VV, 0x1, 0x0 }, // 3232 { PseudoVFWMACCBF16_VV_M2_E32_MASK, VFWMACCBF16_VV, 0x1, 0x0 }, // 3233 { PseudoVFWMACCBF16_VV_M4_E16, VFWMACCBF16_VV, 0x2, 0x0 }, // 3234 { PseudoVFWMACCBF16_VV_M4_E16_MASK, VFWMACCBF16_VV, 0x2, 0x0 }, // 3235 { PseudoVFWMACCBF16_VV_M4_E32, VFWMACCBF16_VV, 0x2, 0x0 }, // 3236 { PseudoVFWMACCBF16_VV_M4_E32_MASK, VFWMACCBF16_VV, 0x2, 0x0 }, // 3237 { PseudoVFWMACCBF16_VV_MF4_E16, VFWMACCBF16_VV, 0x6, 0x0 }, // 3238 { PseudoVFWMACCBF16_VV_MF4_E16_MASK, VFWMACCBF16_VV, 0x6, 0x0 }, // 3239 { PseudoVFWMACCBF16_VV_MF2_E16, VFWMACCBF16_VV, 0x7, 0x0 }, // 3240 { PseudoVFWMACCBF16_VV_MF2_E16_MASK, VFWMACCBF16_VV, 0x7, 0x0 }, // 3241 { PseudoVFWMACCBF16_VV_MF2_E32, VFWMACCBF16_VV, 0x7, 0x0 }, // 3242 { PseudoVFWMACCBF16_VV_MF2_E32_MASK, VFWMACCBF16_VV, 0x7, 0x0 }, // 3243 { PseudoVFWMACC_4x4x4_M1, VFWMACC_4x4x4, 0x0, 0x0 }, // 3244 { PseudoVFWMACC_4x4x4_M2, VFWMACC_4x4x4, 0x1, 0x0 }, // 3245 { PseudoVFWMACC_4x4x4_M4, VFWMACC_4x4x4, 0x2, 0x0 }, // 3246 { PseudoVFWMACC_4x4x4_M8, VFWMACC_4x4x4, 0x3, 0x0 }, // 3247 { PseudoVFWMACC_4x4x4_MF4, VFWMACC_4x4x4, 0x6, 0x0 }, // 3248 { PseudoVFWMACC_4x4x4_MF2, VFWMACC_4x4x4, 0x7, 0x0 }, // 3249 { PseudoVFWMACC_VFPR16_M1_E16, VFWMACC_VF, 0x0, 0x0 }, // 3250 { PseudoVFWMACC_VFPR16_M1_E16_MASK, VFWMACC_VF, 0x0, 0x0 }, // 3251 { PseudoVFWMACC_VFPR32_M1_E32, VFWMACC_VF, 0x0, 0x0 }, // 3252 { PseudoVFWMACC_VFPR32_M1_E32_MASK, VFWMACC_VF, 0x0, 0x0 }, // 3253 { PseudoVFWMACC_VFPR16_M2_E16, VFWMACC_VF, 0x1, 0x0 }, // 3254 { PseudoVFWMACC_VFPR16_M2_E16_MASK, VFWMACC_VF, 0x1, 0x0 }, // 3255 { PseudoVFWMACC_VFPR32_M2_E32, VFWMACC_VF, 0x1, 0x0 }, // 3256 { PseudoVFWMACC_VFPR32_M2_E32_MASK, VFWMACC_VF, 0x1, 0x0 }, // 3257 { PseudoVFWMACC_VFPR16_M4_E16, VFWMACC_VF, 0x2, 0x0 }, // 3258 { PseudoVFWMACC_VFPR16_M4_E16_MASK, VFWMACC_VF, 0x2, 0x0 }, // 3259 { PseudoVFWMACC_VFPR32_M4_E32, VFWMACC_VF, 0x2, 0x0 }, // 3260 { PseudoVFWMACC_VFPR32_M4_E32_MASK, VFWMACC_VF, 0x2, 0x0 }, // 3261 { PseudoVFWMACC_VFPR16_MF4_E16, VFWMACC_VF, 0x6, 0x0 }, // 3262 { PseudoVFWMACC_VFPR16_MF4_E16_MASK, VFWMACC_VF, 0x6, 0x0 }, // 3263 { PseudoVFWMACC_VFPR16_MF2_E16, VFWMACC_VF, 0x7, 0x0 }, // 3264 { PseudoVFWMACC_VFPR16_MF2_E16_MASK, VFWMACC_VF, 0x7, 0x0 }, // 3265 { PseudoVFWMACC_VFPR32_MF2_E32, VFWMACC_VF, 0x7, 0x0 }, // 3266 { PseudoVFWMACC_VFPR32_MF2_E32_MASK, VFWMACC_VF, 0x7, 0x0 }, // 3267 { PseudoVFWMACC_VV_M1_E16, VFWMACC_VV, 0x0, 0x0 }, // 3268 { PseudoVFWMACC_VV_M1_E16_MASK, VFWMACC_VV, 0x0, 0x0 }, // 3269 { PseudoVFWMACC_VV_M1_E32, VFWMACC_VV, 0x0, 0x0 }, // 3270 { PseudoVFWMACC_VV_M1_E32_MASK, VFWMACC_VV, 0x0, 0x0 }, // 3271 { PseudoVFWMACC_VV_M2_E16, VFWMACC_VV, 0x1, 0x0 }, // 3272 { PseudoVFWMACC_VV_M2_E16_MASK, VFWMACC_VV, 0x1, 0x0 }, // 3273 { PseudoVFWMACC_VV_M2_E32, VFWMACC_VV, 0x1, 0x0 }, // 3274 { PseudoVFWMACC_VV_M2_E32_MASK, VFWMACC_VV, 0x1, 0x0 }, // 3275 { PseudoVFWMACC_VV_M4_E16, VFWMACC_VV, 0x2, 0x0 }, // 3276 { PseudoVFWMACC_VV_M4_E16_MASK, VFWMACC_VV, 0x2, 0x0 }, // 3277 { PseudoVFWMACC_VV_M4_E32, VFWMACC_VV, 0x2, 0x0 }, // 3278 { PseudoVFWMACC_VV_M4_E32_MASK, VFWMACC_VV, 0x2, 0x0 }, // 3279 { PseudoVFWMACC_VV_MF4_E16, VFWMACC_VV, 0x6, 0x0 }, // 3280 { PseudoVFWMACC_VV_MF4_E16_MASK, VFWMACC_VV, 0x6, 0x0 }, // 3281 { PseudoVFWMACC_VV_MF2_E16, VFWMACC_VV, 0x7, 0x0 }, // 3282 { PseudoVFWMACC_VV_MF2_E16_MASK, VFWMACC_VV, 0x7, 0x0 }, // 3283 { PseudoVFWMACC_VV_MF2_E32, VFWMACC_VV, 0x7, 0x0 }, // 3284 { PseudoVFWMACC_VV_MF2_E32_MASK, VFWMACC_VV, 0x7, 0x0 }, // 3285 { PseudoVFWMSAC_VFPR16_M1_E16, VFWMSAC_VF, 0x0, 0x0 }, // 3286 { PseudoVFWMSAC_VFPR16_M1_E16_MASK, VFWMSAC_VF, 0x0, 0x0 }, // 3287 { PseudoVFWMSAC_VFPR32_M1_E32, VFWMSAC_VF, 0x0, 0x0 }, // 3288 { PseudoVFWMSAC_VFPR32_M1_E32_MASK, VFWMSAC_VF, 0x0, 0x0 }, // 3289 { PseudoVFWMSAC_VFPR16_M2_E16, VFWMSAC_VF, 0x1, 0x0 }, // 3290 { PseudoVFWMSAC_VFPR16_M2_E16_MASK, VFWMSAC_VF, 0x1, 0x0 }, // 3291 { PseudoVFWMSAC_VFPR32_M2_E32, VFWMSAC_VF, 0x1, 0x0 }, // 3292 { PseudoVFWMSAC_VFPR32_M2_E32_MASK, VFWMSAC_VF, 0x1, 0x0 }, // 3293 { PseudoVFWMSAC_VFPR16_M4_E16, VFWMSAC_VF, 0x2, 0x0 }, // 3294 { PseudoVFWMSAC_VFPR16_M4_E16_MASK, VFWMSAC_VF, 0x2, 0x0 }, // 3295 { PseudoVFWMSAC_VFPR32_M4_E32, VFWMSAC_VF, 0x2, 0x0 }, // 3296 { PseudoVFWMSAC_VFPR32_M4_E32_MASK, VFWMSAC_VF, 0x2, 0x0 }, // 3297 { PseudoVFWMSAC_VFPR16_MF4_E16, VFWMSAC_VF, 0x6, 0x0 }, // 3298 { PseudoVFWMSAC_VFPR16_MF4_E16_MASK, VFWMSAC_VF, 0x6, 0x0 }, // 3299 { PseudoVFWMSAC_VFPR16_MF2_E16, VFWMSAC_VF, 0x7, 0x0 }, // 3300 { PseudoVFWMSAC_VFPR16_MF2_E16_MASK, VFWMSAC_VF, 0x7, 0x0 }, // 3301 { PseudoVFWMSAC_VFPR32_MF2_E32, VFWMSAC_VF, 0x7, 0x0 }, // 3302 { PseudoVFWMSAC_VFPR32_MF2_E32_MASK, VFWMSAC_VF, 0x7, 0x0 }, // 3303 { PseudoVFWMSAC_VV_M1_E16, VFWMSAC_VV, 0x0, 0x0 }, // 3304 { PseudoVFWMSAC_VV_M1_E16_MASK, VFWMSAC_VV, 0x0, 0x0 }, // 3305 { PseudoVFWMSAC_VV_M1_E32, VFWMSAC_VV, 0x0, 0x0 }, // 3306 { PseudoVFWMSAC_VV_M1_E32_MASK, VFWMSAC_VV, 0x0, 0x0 }, // 3307 { PseudoVFWMSAC_VV_M2_E16, VFWMSAC_VV, 0x1, 0x0 }, // 3308 { PseudoVFWMSAC_VV_M2_E16_MASK, VFWMSAC_VV, 0x1, 0x0 }, // 3309 { PseudoVFWMSAC_VV_M2_E32, VFWMSAC_VV, 0x1, 0x0 }, // 3310 { PseudoVFWMSAC_VV_M2_E32_MASK, VFWMSAC_VV, 0x1, 0x0 }, // 3311 { PseudoVFWMSAC_VV_M4_E16, VFWMSAC_VV, 0x2, 0x0 }, // 3312 { PseudoVFWMSAC_VV_M4_E16_MASK, VFWMSAC_VV, 0x2, 0x0 }, // 3313 { PseudoVFWMSAC_VV_M4_E32, VFWMSAC_VV, 0x2, 0x0 }, // 3314 { PseudoVFWMSAC_VV_M4_E32_MASK, VFWMSAC_VV, 0x2, 0x0 }, // 3315 { PseudoVFWMSAC_VV_MF4_E16, VFWMSAC_VV, 0x6, 0x0 }, // 3316 { PseudoVFWMSAC_VV_MF4_E16_MASK, VFWMSAC_VV, 0x6, 0x0 }, // 3317 { PseudoVFWMSAC_VV_MF2_E16, VFWMSAC_VV, 0x7, 0x0 }, // 3318 { PseudoVFWMSAC_VV_MF2_E16_MASK, VFWMSAC_VV, 0x7, 0x0 }, // 3319 { PseudoVFWMSAC_VV_MF2_E32, VFWMSAC_VV, 0x7, 0x0 }, // 3320 { PseudoVFWMSAC_VV_MF2_E32_MASK, VFWMSAC_VV, 0x7, 0x0 }, // 3321 { PseudoVFWMUL_VFPR16_M1_E16, VFWMUL_VF, 0x0, 0x10 }, // 3322 { PseudoVFWMUL_VFPR16_M1_E16_MASK, VFWMUL_VF, 0x0, 0x10 }, // 3323 { PseudoVFWMUL_VFPR32_M1_E32, VFWMUL_VF, 0x0, 0x20 }, // 3324 { PseudoVFWMUL_VFPR32_M1_E32_MASK, VFWMUL_VF, 0x0, 0x20 }, // 3325 { PseudoVFWMUL_VFPR16_M2_E16, VFWMUL_VF, 0x1, 0x10 }, // 3326 { PseudoVFWMUL_VFPR16_M2_E16_MASK, VFWMUL_VF, 0x1, 0x10 }, // 3327 { PseudoVFWMUL_VFPR32_M2_E32, VFWMUL_VF, 0x1, 0x20 }, // 3328 { PseudoVFWMUL_VFPR32_M2_E32_MASK, VFWMUL_VF, 0x1, 0x20 }, // 3329 { PseudoVFWMUL_VFPR16_M4_E16, VFWMUL_VF, 0x2, 0x10 }, // 3330 { PseudoVFWMUL_VFPR16_M4_E16_MASK, VFWMUL_VF, 0x2, 0x10 }, // 3331 { PseudoVFWMUL_VFPR32_M4_E32, VFWMUL_VF, 0x2, 0x20 }, // 3332 { PseudoVFWMUL_VFPR32_M4_E32_MASK, VFWMUL_VF, 0x2, 0x20 }, // 3333 { PseudoVFWMUL_VFPR16_MF4_E16, VFWMUL_VF, 0x6, 0x10 }, // 3334 { PseudoVFWMUL_VFPR16_MF4_E16_MASK, VFWMUL_VF, 0x6, 0x10 }, // 3335 { PseudoVFWMUL_VFPR16_MF2_E16, VFWMUL_VF, 0x7, 0x10 }, // 3336 { PseudoVFWMUL_VFPR16_MF2_E16_MASK, VFWMUL_VF, 0x7, 0x10 }, // 3337 { PseudoVFWMUL_VFPR32_MF2_E32, VFWMUL_VF, 0x7, 0x20 }, // 3338 { PseudoVFWMUL_VFPR32_MF2_E32_MASK, VFWMUL_VF, 0x7, 0x20 }, // 3339 { PseudoVFWMUL_VV_M1_E16, VFWMUL_VV, 0x0, 0x10 }, // 3340 { PseudoVFWMUL_VV_M1_E16_MASK, VFWMUL_VV, 0x0, 0x10 }, // 3341 { PseudoVFWMUL_VV_M1_E32, VFWMUL_VV, 0x0, 0x20 }, // 3342 { PseudoVFWMUL_VV_M1_E32_MASK, VFWMUL_VV, 0x0, 0x20 }, // 3343 { PseudoVFWMUL_VV_M2_E16, VFWMUL_VV, 0x1, 0x10 }, // 3344 { PseudoVFWMUL_VV_M2_E16_MASK, VFWMUL_VV, 0x1, 0x10 }, // 3345 { PseudoVFWMUL_VV_M2_E32, VFWMUL_VV, 0x1, 0x20 }, // 3346 { PseudoVFWMUL_VV_M2_E32_MASK, VFWMUL_VV, 0x1, 0x20 }, // 3347 { PseudoVFWMUL_VV_M4_E16, VFWMUL_VV, 0x2, 0x10 }, // 3348 { PseudoVFWMUL_VV_M4_E16_MASK, VFWMUL_VV, 0x2, 0x10 }, // 3349 { PseudoVFWMUL_VV_M4_E32, VFWMUL_VV, 0x2, 0x20 }, // 3350 { PseudoVFWMUL_VV_M4_E32_MASK, VFWMUL_VV, 0x2, 0x20 }, // 3351 { PseudoVFWMUL_VV_MF4_E16, VFWMUL_VV, 0x6, 0x10 }, // 3352 { PseudoVFWMUL_VV_MF4_E16_MASK, VFWMUL_VV, 0x6, 0x10 }, // 3353 { PseudoVFWMUL_VV_MF2_E16, VFWMUL_VV, 0x7, 0x10 }, // 3354 { PseudoVFWMUL_VV_MF2_E16_MASK, VFWMUL_VV, 0x7, 0x10 }, // 3355 { PseudoVFWMUL_VV_MF2_E32, VFWMUL_VV, 0x7, 0x20 }, // 3356 { PseudoVFWMUL_VV_MF2_E32_MASK, VFWMUL_VV, 0x7, 0x20 }, // 3357 { PseudoVFWNMACC_VFPR16_M1_E16, VFWNMACC_VF, 0x0, 0x0 }, // 3358 { PseudoVFWNMACC_VFPR16_M1_E16_MASK, VFWNMACC_VF, 0x0, 0x0 }, // 3359 { PseudoVFWNMACC_VFPR32_M1_E32, VFWNMACC_VF, 0x0, 0x0 }, // 3360 { PseudoVFWNMACC_VFPR32_M1_E32_MASK, VFWNMACC_VF, 0x0, 0x0 }, // 3361 { PseudoVFWNMACC_VFPR16_M2_E16, VFWNMACC_VF, 0x1, 0x0 }, // 3362 { PseudoVFWNMACC_VFPR16_M2_E16_MASK, VFWNMACC_VF, 0x1, 0x0 }, // 3363 { PseudoVFWNMACC_VFPR32_M2_E32, VFWNMACC_VF, 0x1, 0x0 }, // 3364 { PseudoVFWNMACC_VFPR32_M2_E32_MASK, VFWNMACC_VF, 0x1, 0x0 }, // 3365 { PseudoVFWNMACC_VFPR16_M4_E16, VFWNMACC_VF, 0x2, 0x0 }, // 3366 { PseudoVFWNMACC_VFPR16_M4_E16_MASK, VFWNMACC_VF, 0x2, 0x0 }, // 3367 { PseudoVFWNMACC_VFPR32_M4_E32, VFWNMACC_VF, 0x2, 0x0 }, // 3368 { PseudoVFWNMACC_VFPR32_M4_E32_MASK, VFWNMACC_VF, 0x2, 0x0 }, // 3369 { PseudoVFWNMACC_VFPR16_MF4_E16, VFWNMACC_VF, 0x6, 0x0 }, // 3370 { PseudoVFWNMACC_VFPR16_MF4_E16_MASK, VFWNMACC_VF, 0x6, 0x0 }, // 3371 { PseudoVFWNMACC_VFPR16_MF2_E16, VFWNMACC_VF, 0x7, 0x0 }, // 3372 { PseudoVFWNMACC_VFPR16_MF2_E16_MASK, VFWNMACC_VF, 0x7, 0x0 }, // 3373 { PseudoVFWNMACC_VFPR32_MF2_E32, VFWNMACC_VF, 0x7, 0x0 }, // 3374 { PseudoVFWNMACC_VFPR32_MF2_E32_MASK, VFWNMACC_VF, 0x7, 0x0 }, // 3375 { PseudoVFWNMACC_VV_M1_E16, VFWNMACC_VV, 0x0, 0x0 }, // 3376 { PseudoVFWNMACC_VV_M1_E16_MASK, VFWNMACC_VV, 0x0, 0x0 }, // 3377 { PseudoVFWNMACC_VV_M1_E32, VFWNMACC_VV, 0x0, 0x0 }, // 3378 { PseudoVFWNMACC_VV_M1_E32_MASK, VFWNMACC_VV, 0x0, 0x0 }, // 3379 { PseudoVFWNMACC_VV_M2_E16, VFWNMACC_VV, 0x1, 0x0 }, // 3380 { PseudoVFWNMACC_VV_M2_E16_MASK, VFWNMACC_VV, 0x1, 0x0 }, // 3381 { PseudoVFWNMACC_VV_M2_E32, VFWNMACC_VV, 0x1, 0x0 }, // 3382 { PseudoVFWNMACC_VV_M2_E32_MASK, VFWNMACC_VV, 0x1, 0x0 }, // 3383 { PseudoVFWNMACC_VV_M4_E16, VFWNMACC_VV, 0x2, 0x0 }, // 3384 { PseudoVFWNMACC_VV_M4_E16_MASK, VFWNMACC_VV, 0x2, 0x0 }, // 3385 { PseudoVFWNMACC_VV_M4_E32, VFWNMACC_VV, 0x2, 0x0 }, // 3386 { PseudoVFWNMACC_VV_M4_E32_MASK, VFWNMACC_VV, 0x2, 0x0 }, // 3387 { PseudoVFWNMACC_VV_MF4_E16, VFWNMACC_VV, 0x6, 0x0 }, // 3388 { PseudoVFWNMACC_VV_MF4_E16_MASK, VFWNMACC_VV, 0x6, 0x0 }, // 3389 { PseudoVFWNMACC_VV_MF2_E16, VFWNMACC_VV, 0x7, 0x0 }, // 3390 { PseudoVFWNMACC_VV_MF2_E16_MASK, VFWNMACC_VV, 0x7, 0x0 }, // 3391 { PseudoVFWNMACC_VV_MF2_E32, VFWNMACC_VV, 0x7, 0x0 }, // 3392 { PseudoVFWNMACC_VV_MF2_E32_MASK, VFWNMACC_VV, 0x7, 0x0 }, // 3393 { PseudoVFWNMSAC_VFPR16_M1_E16, VFWNMSAC_VF, 0x0, 0x0 }, // 3394 { PseudoVFWNMSAC_VFPR16_M1_E16_MASK, VFWNMSAC_VF, 0x0, 0x0 }, // 3395 { PseudoVFWNMSAC_VFPR32_M1_E32, VFWNMSAC_VF, 0x0, 0x0 }, // 3396 { PseudoVFWNMSAC_VFPR32_M1_E32_MASK, VFWNMSAC_VF, 0x0, 0x0 }, // 3397 { PseudoVFWNMSAC_VFPR16_M2_E16, VFWNMSAC_VF, 0x1, 0x0 }, // 3398 { PseudoVFWNMSAC_VFPR16_M2_E16_MASK, VFWNMSAC_VF, 0x1, 0x0 }, // 3399 { PseudoVFWNMSAC_VFPR32_M2_E32, VFWNMSAC_VF, 0x1, 0x0 }, // 3400 { PseudoVFWNMSAC_VFPR32_M2_E32_MASK, VFWNMSAC_VF, 0x1, 0x0 }, // 3401 { PseudoVFWNMSAC_VFPR16_M4_E16, VFWNMSAC_VF, 0x2, 0x0 }, // 3402 { PseudoVFWNMSAC_VFPR16_M4_E16_MASK, VFWNMSAC_VF, 0x2, 0x0 }, // 3403 { PseudoVFWNMSAC_VFPR32_M4_E32, VFWNMSAC_VF, 0x2, 0x0 }, // 3404 { PseudoVFWNMSAC_VFPR32_M4_E32_MASK, VFWNMSAC_VF, 0x2, 0x0 }, // 3405 { PseudoVFWNMSAC_VFPR16_MF4_E16, VFWNMSAC_VF, 0x6, 0x0 }, // 3406 { PseudoVFWNMSAC_VFPR16_MF4_E16_MASK, VFWNMSAC_VF, 0x6, 0x0 }, // 3407 { PseudoVFWNMSAC_VFPR16_MF2_E16, VFWNMSAC_VF, 0x7, 0x0 }, // 3408 { PseudoVFWNMSAC_VFPR16_MF2_E16_MASK, VFWNMSAC_VF, 0x7, 0x0 }, // 3409 { PseudoVFWNMSAC_VFPR32_MF2_E32, VFWNMSAC_VF, 0x7, 0x0 }, // 3410 { PseudoVFWNMSAC_VFPR32_MF2_E32_MASK, VFWNMSAC_VF, 0x7, 0x0 }, // 3411 { PseudoVFWNMSAC_VV_M1_E16, VFWNMSAC_VV, 0x0, 0x0 }, // 3412 { PseudoVFWNMSAC_VV_M1_E16_MASK, VFWNMSAC_VV, 0x0, 0x0 }, // 3413 { PseudoVFWNMSAC_VV_M1_E32, VFWNMSAC_VV, 0x0, 0x0 }, // 3414 { PseudoVFWNMSAC_VV_M1_E32_MASK, VFWNMSAC_VV, 0x0, 0x0 }, // 3415 { PseudoVFWNMSAC_VV_M2_E16, VFWNMSAC_VV, 0x1, 0x0 }, // 3416 { PseudoVFWNMSAC_VV_M2_E16_MASK, VFWNMSAC_VV, 0x1, 0x0 }, // 3417 { PseudoVFWNMSAC_VV_M2_E32, VFWNMSAC_VV, 0x1, 0x0 }, // 3418 { PseudoVFWNMSAC_VV_M2_E32_MASK, VFWNMSAC_VV, 0x1, 0x0 }, // 3419 { PseudoVFWNMSAC_VV_M4_E16, VFWNMSAC_VV, 0x2, 0x0 }, // 3420 { PseudoVFWNMSAC_VV_M4_E16_MASK, VFWNMSAC_VV, 0x2, 0x0 }, // 3421 { PseudoVFWNMSAC_VV_M4_E32, VFWNMSAC_VV, 0x2, 0x0 }, // 3422 { PseudoVFWNMSAC_VV_M4_E32_MASK, VFWNMSAC_VV, 0x2, 0x0 }, // 3423 { PseudoVFWNMSAC_VV_MF4_E16, VFWNMSAC_VV, 0x6, 0x0 }, // 3424 { PseudoVFWNMSAC_VV_MF4_E16_MASK, VFWNMSAC_VV, 0x6, 0x0 }, // 3425 { PseudoVFWNMSAC_VV_MF2_E16, VFWNMSAC_VV, 0x7, 0x0 }, // 3426 { PseudoVFWNMSAC_VV_MF2_E16_MASK, VFWNMSAC_VV, 0x7, 0x0 }, // 3427 { PseudoVFWNMSAC_VV_MF2_E32, VFWNMSAC_VV, 0x7, 0x0 }, // 3428 { PseudoVFWNMSAC_VV_MF2_E32_MASK, VFWNMSAC_VV, 0x7, 0x0 }, // 3429 { PseudoVFWREDOSUM_VS_M1_E16, VFWREDOSUM_VS, 0x0, 0x10 }, // 3430 { PseudoVFWREDOSUM_VS_M1_E16_MASK, VFWREDOSUM_VS, 0x0, 0x10 }, // 3431 { PseudoVFWREDOSUM_VS_M1_E32, VFWREDOSUM_VS, 0x0, 0x20 }, // 3432 { PseudoVFWREDOSUM_VS_M1_E32_MASK, VFWREDOSUM_VS, 0x0, 0x20 }, // 3433 { PseudoVFWREDOSUM_VS_M2_E16, VFWREDOSUM_VS, 0x1, 0x10 }, // 3434 { PseudoVFWREDOSUM_VS_M2_E16_MASK, VFWREDOSUM_VS, 0x1, 0x10 }, // 3435 { PseudoVFWREDOSUM_VS_M2_E32, VFWREDOSUM_VS, 0x1, 0x20 }, // 3436 { PseudoVFWREDOSUM_VS_M2_E32_MASK, VFWREDOSUM_VS, 0x1, 0x20 }, // 3437 { PseudoVFWREDOSUM_VS_M4_E16, VFWREDOSUM_VS, 0x2, 0x10 }, // 3438 { PseudoVFWREDOSUM_VS_M4_E16_MASK, VFWREDOSUM_VS, 0x2, 0x10 }, // 3439 { PseudoVFWREDOSUM_VS_M4_E32, VFWREDOSUM_VS, 0x2, 0x20 }, // 3440 { PseudoVFWREDOSUM_VS_M4_E32_MASK, VFWREDOSUM_VS, 0x2, 0x20 }, // 3441 { PseudoVFWREDOSUM_VS_M8_E16, VFWREDOSUM_VS, 0x3, 0x10 }, // 3442 { PseudoVFWREDOSUM_VS_M8_E16_MASK, VFWREDOSUM_VS, 0x3, 0x10 }, // 3443 { PseudoVFWREDOSUM_VS_M8_E32, VFWREDOSUM_VS, 0x3, 0x20 }, // 3444 { PseudoVFWREDOSUM_VS_M8_E32_MASK, VFWREDOSUM_VS, 0x3, 0x20 }, // 3445 { PseudoVFWREDOSUM_VS_MF4_E16, VFWREDOSUM_VS, 0x6, 0x10 }, // 3446 { PseudoVFWREDOSUM_VS_MF4_E16_MASK, VFWREDOSUM_VS, 0x6, 0x10 }, // 3447 { PseudoVFWREDOSUM_VS_MF2_E16, VFWREDOSUM_VS, 0x7, 0x10 }, // 3448 { PseudoVFWREDOSUM_VS_MF2_E16_MASK, VFWREDOSUM_VS, 0x7, 0x10 }, // 3449 { PseudoVFWREDOSUM_VS_MF2_E32, VFWREDOSUM_VS, 0x7, 0x20 }, // 3450 { PseudoVFWREDOSUM_VS_MF2_E32_MASK, VFWREDOSUM_VS, 0x7, 0x20 }, // 3451 { PseudoVFWREDUSUM_VS_M1_E16, VFWREDUSUM_VS, 0x0, 0x10 }, // 3452 { PseudoVFWREDUSUM_VS_M1_E16_MASK, VFWREDUSUM_VS, 0x0, 0x10 }, // 3453 { PseudoVFWREDUSUM_VS_M1_E32, VFWREDUSUM_VS, 0x0, 0x20 }, // 3454 { PseudoVFWREDUSUM_VS_M1_E32_MASK, VFWREDUSUM_VS, 0x0, 0x20 }, // 3455 { PseudoVFWREDUSUM_VS_M2_E16, VFWREDUSUM_VS, 0x1, 0x10 }, // 3456 { PseudoVFWREDUSUM_VS_M2_E16_MASK, VFWREDUSUM_VS, 0x1, 0x10 }, // 3457 { PseudoVFWREDUSUM_VS_M2_E32, VFWREDUSUM_VS, 0x1, 0x20 }, // 3458 { PseudoVFWREDUSUM_VS_M2_E32_MASK, VFWREDUSUM_VS, 0x1, 0x20 }, // 3459 { PseudoVFWREDUSUM_VS_M4_E16, VFWREDUSUM_VS, 0x2, 0x10 }, // 3460 { PseudoVFWREDUSUM_VS_M4_E16_MASK, VFWREDUSUM_VS, 0x2, 0x10 }, // 3461 { PseudoVFWREDUSUM_VS_M4_E32, VFWREDUSUM_VS, 0x2, 0x20 }, // 3462 { PseudoVFWREDUSUM_VS_M4_E32_MASK, VFWREDUSUM_VS, 0x2, 0x20 }, // 3463 { PseudoVFWREDUSUM_VS_M8_E16, VFWREDUSUM_VS, 0x3, 0x10 }, // 3464 { PseudoVFWREDUSUM_VS_M8_E16_MASK, VFWREDUSUM_VS, 0x3, 0x10 }, // 3465 { PseudoVFWREDUSUM_VS_M8_E32, VFWREDUSUM_VS, 0x3, 0x20 }, // 3466 { PseudoVFWREDUSUM_VS_M8_E32_MASK, VFWREDUSUM_VS, 0x3, 0x20 }, // 3467 { PseudoVFWREDUSUM_VS_MF4_E16, VFWREDUSUM_VS, 0x6, 0x10 }, // 3468 { PseudoVFWREDUSUM_VS_MF4_E16_MASK, VFWREDUSUM_VS, 0x6, 0x10 }, // 3469 { PseudoVFWREDUSUM_VS_MF2_E16, VFWREDUSUM_VS, 0x7, 0x10 }, // 3470 { PseudoVFWREDUSUM_VS_MF2_E16_MASK, VFWREDUSUM_VS, 0x7, 0x10 }, // 3471 { PseudoVFWREDUSUM_VS_MF2_E32, VFWREDUSUM_VS, 0x7, 0x20 }, // 3472 { PseudoVFWREDUSUM_VS_MF2_E32_MASK, VFWREDUSUM_VS, 0x7, 0x20 }, // 3473 { PseudoVFWSUB_VFPR16_M1_E16, VFWSUB_VF, 0x0, 0x10 }, // 3474 { PseudoVFWSUB_VFPR16_M1_E16_MASK, VFWSUB_VF, 0x0, 0x10 }, // 3475 { PseudoVFWSUB_VFPR32_M1_E32, VFWSUB_VF, 0x0, 0x20 }, // 3476 { PseudoVFWSUB_VFPR32_M1_E32_MASK, VFWSUB_VF, 0x0, 0x20 }, // 3477 { PseudoVFWSUB_VFPR16_M2_E16, VFWSUB_VF, 0x1, 0x10 }, // 3478 { PseudoVFWSUB_VFPR16_M2_E16_MASK, VFWSUB_VF, 0x1, 0x10 }, // 3479 { PseudoVFWSUB_VFPR32_M2_E32, VFWSUB_VF, 0x1, 0x20 }, // 3480 { PseudoVFWSUB_VFPR32_M2_E32_MASK, VFWSUB_VF, 0x1, 0x20 }, // 3481 { PseudoVFWSUB_VFPR16_M4_E16, VFWSUB_VF, 0x2, 0x10 }, // 3482 { PseudoVFWSUB_VFPR16_M4_E16_MASK, VFWSUB_VF, 0x2, 0x10 }, // 3483 { PseudoVFWSUB_VFPR32_M4_E32, VFWSUB_VF, 0x2, 0x20 }, // 3484 { PseudoVFWSUB_VFPR32_M4_E32_MASK, VFWSUB_VF, 0x2, 0x20 }, // 3485 { PseudoVFWSUB_VFPR16_MF4_E16, VFWSUB_VF, 0x6, 0x10 }, // 3486 { PseudoVFWSUB_VFPR16_MF4_E16_MASK, VFWSUB_VF, 0x6, 0x10 }, // 3487 { PseudoVFWSUB_VFPR16_MF2_E16, VFWSUB_VF, 0x7, 0x10 }, // 3488 { PseudoVFWSUB_VFPR16_MF2_E16_MASK, VFWSUB_VF, 0x7, 0x10 }, // 3489 { PseudoVFWSUB_VFPR32_MF2_E32, VFWSUB_VF, 0x7, 0x20 }, // 3490 { PseudoVFWSUB_VFPR32_MF2_E32_MASK, VFWSUB_VF, 0x7, 0x20 }, // 3491 { PseudoVFWSUB_VV_M1_E16, VFWSUB_VV, 0x0, 0x10 }, // 3492 { PseudoVFWSUB_VV_M1_E16_MASK, VFWSUB_VV, 0x0, 0x10 }, // 3493 { PseudoVFWSUB_VV_M1_E32, VFWSUB_VV, 0x0, 0x20 }, // 3494 { PseudoVFWSUB_VV_M1_E32_MASK, VFWSUB_VV, 0x0, 0x20 }, // 3495 { PseudoVFWSUB_VV_M2_E16, VFWSUB_VV, 0x1, 0x10 }, // 3496 { PseudoVFWSUB_VV_M2_E16_MASK, VFWSUB_VV, 0x1, 0x10 }, // 3497 { PseudoVFWSUB_VV_M2_E32, VFWSUB_VV, 0x1, 0x20 }, // 3498 { PseudoVFWSUB_VV_M2_E32_MASK, VFWSUB_VV, 0x1, 0x20 }, // 3499 { PseudoVFWSUB_VV_M4_E16, VFWSUB_VV, 0x2, 0x10 }, // 3500 { PseudoVFWSUB_VV_M4_E16_MASK, VFWSUB_VV, 0x2, 0x10 }, // 3501 { PseudoVFWSUB_VV_M4_E32, VFWSUB_VV, 0x2, 0x20 }, // 3502 { PseudoVFWSUB_VV_M4_E32_MASK, VFWSUB_VV, 0x2, 0x20 }, // 3503 { PseudoVFWSUB_VV_MF4_E16, VFWSUB_VV, 0x6, 0x10 }, // 3504 { PseudoVFWSUB_VV_MF4_E16_MASK, VFWSUB_VV, 0x6, 0x10 }, // 3505 { PseudoVFWSUB_VV_MF2_E16, VFWSUB_VV, 0x7, 0x10 }, // 3506 { PseudoVFWSUB_VV_MF2_E16_MASK, VFWSUB_VV, 0x7, 0x10 }, // 3507 { PseudoVFWSUB_VV_MF2_E32, VFWSUB_VV, 0x7, 0x20 }, // 3508 { PseudoVFWSUB_VV_MF2_E32_MASK, VFWSUB_VV, 0x7, 0x20 }, // 3509 { PseudoVFWSUB_WFPR16_M1_E16, VFWSUB_WF, 0x0, 0x10 }, // 3510 { PseudoVFWSUB_WFPR16_M1_E16_MASK, VFWSUB_WF, 0x0, 0x10 }, // 3511 { PseudoVFWSUB_WFPR32_M1_E32, VFWSUB_WF, 0x0, 0x20 }, // 3512 { PseudoVFWSUB_WFPR32_M1_E32_MASK, VFWSUB_WF, 0x0, 0x20 }, // 3513 { PseudoVFWSUB_WFPR16_M2_E16, VFWSUB_WF, 0x1, 0x10 }, // 3514 { PseudoVFWSUB_WFPR16_M2_E16_MASK, VFWSUB_WF, 0x1, 0x10 }, // 3515 { PseudoVFWSUB_WFPR32_M2_E32, VFWSUB_WF, 0x1, 0x20 }, // 3516 { PseudoVFWSUB_WFPR32_M2_E32_MASK, VFWSUB_WF, 0x1, 0x20 }, // 3517 { PseudoVFWSUB_WFPR16_M4_E16, VFWSUB_WF, 0x2, 0x10 }, // 3518 { PseudoVFWSUB_WFPR16_M4_E16_MASK, VFWSUB_WF, 0x2, 0x10 }, // 3519 { PseudoVFWSUB_WFPR32_M4_E32, VFWSUB_WF, 0x2, 0x20 }, // 3520 { PseudoVFWSUB_WFPR32_M4_E32_MASK, VFWSUB_WF, 0x2, 0x20 }, // 3521 { PseudoVFWSUB_WFPR16_MF4_E16, VFWSUB_WF, 0x6, 0x10 }, // 3522 { PseudoVFWSUB_WFPR16_MF4_E16_MASK, VFWSUB_WF, 0x6, 0x10 }, // 3523 { PseudoVFWSUB_WFPR16_MF2_E16, VFWSUB_WF, 0x7, 0x10 }, // 3524 { PseudoVFWSUB_WFPR16_MF2_E16_MASK, VFWSUB_WF, 0x7, 0x10 }, // 3525 { PseudoVFWSUB_WFPR32_MF2_E32, VFWSUB_WF, 0x7, 0x20 }, // 3526 { PseudoVFWSUB_WFPR32_MF2_E32_MASK, VFWSUB_WF, 0x7, 0x20 }, // 3527 { PseudoVFWSUB_WV_M1_E16_MASK_TIED, VFWSUB_WV, 0x0, 0x0 }, // 3528 { PseudoVFWSUB_WV_M1_E16_TIED, VFWSUB_WV, 0x0, 0x0 }, // 3529 { PseudoVFWSUB_WV_M1_E32_MASK_TIED, VFWSUB_WV, 0x0, 0x0 }, // 3530 { PseudoVFWSUB_WV_M1_E32_TIED, VFWSUB_WV, 0x0, 0x0 }, // 3531 { PseudoVFWSUB_WV_M1_E16, VFWSUB_WV, 0x0, 0x10 }, // 3532 { PseudoVFWSUB_WV_M1_E16_MASK, VFWSUB_WV, 0x0, 0x10 }, // 3533 { PseudoVFWSUB_WV_M1_E32, VFWSUB_WV, 0x0, 0x20 }, // 3534 { PseudoVFWSUB_WV_M1_E32_MASK, VFWSUB_WV, 0x0, 0x20 }, // 3535 { PseudoVFWSUB_WV_M2_E16_MASK_TIED, VFWSUB_WV, 0x1, 0x0 }, // 3536 { PseudoVFWSUB_WV_M2_E16_TIED, VFWSUB_WV, 0x1, 0x0 }, // 3537 { PseudoVFWSUB_WV_M2_E32_MASK_TIED, VFWSUB_WV, 0x1, 0x0 }, // 3538 { PseudoVFWSUB_WV_M2_E32_TIED, VFWSUB_WV, 0x1, 0x0 }, // 3539 { PseudoVFWSUB_WV_M2_E16, VFWSUB_WV, 0x1, 0x10 }, // 3540 { PseudoVFWSUB_WV_M2_E16_MASK, VFWSUB_WV, 0x1, 0x10 }, // 3541 { PseudoVFWSUB_WV_M2_E32, VFWSUB_WV, 0x1, 0x20 }, // 3542 { PseudoVFWSUB_WV_M2_E32_MASK, VFWSUB_WV, 0x1, 0x20 }, // 3543 { PseudoVFWSUB_WV_M4_E16_MASK_TIED, VFWSUB_WV, 0x2, 0x0 }, // 3544 { PseudoVFWSUB_WV_M4_E16_TIED, VFWSUB_WV, 0x2, 0x0 }, // 3545 { PseudoVFWSUB_WV_M4_E32_MASK_TIED, VFWSUB_WV, 0x2, 0x0 }, // 3546 { PseudoVFWSUB_WV_M4_E32_TIED, VFWSUB_WV, 0x2, 0x0 }, // 3547 { PseudoVFWSUB_WV_M4_E16, VFWSUB_WV, 0x2, 0x10 }, // 3548 { PseudoVFWSUB_WV_M4_E16_MASK, VFWSUB_WV, 0x2, 0x10 }, // 3549 { PseudoVFWSUB_WV_M4_E32, VFWSUB_WV, 0x2, 0x20 }, // 3550 { PseudoVFWSUB_WV_M4_E32_MASK, VFWSUB_WV, 0x2, 0x20 }, // 3551 { PseudoVFWSUB_WV_MF4_E16_MASK_TIED, VFWSUB_WV, 0x6, 0x0 }, // 3552 { PseudoVFWSUB_WV_MF4_E16_TIED, VFWSUB_WV, 0x6, 0x0 }, // 3553 { PseudoVFWSUB_WV_MF4_E16, VFWSUB_WV, 0x6, 0x10 }, // 3554 { PseudoVFWSUB_WV_MF4_E16_MASK, VFWSUB_WV, 0x6, 0x10 }, // 3555 { PseudoVFWSUB_WV_MF2_E16_MASK_TIED, VFWSUB_WV, 0x7, 0x0 }, // 3556 { PseudoVFWSUB_WV_MF2_E16_TIED, VFWSUB_WV, 0x7, 0x0 }, // 3557 { PseudoVFWSUB_WV_MF2_E32_MASK_TIED, VFWSUB_WV, 0x7, 0x0 }, // 3558 { PseudoVFWSUB_WV_MF2_E32_TIED, VFWSUB_WV, 0x7, 0x0 }, // 3559 { PseudoVFWSUB_WV_MF2_E16, VFWSUB_WV, 0x7, 0x10 }, // 3560 { PseudoVFWSUB_WV_MF2_E16_MASK, VFWSUB_WV, 0x7, 0x10 }, // 3561 { PseudoVFWSUB_WV_MF2_E32, VFWSUB_WV, 0x7, 0x20 }, // 3562 { PseudoVFWSUB_WV_MF2_E32_MASK, VFWSUB_WV, 0x7, 0x20 }, // 3563 { PseudoVGHSH_VV_M1, VGHSH_VV, 0x0, 0x0 }, // 3564 { PseudoVGHSH_VV_M2, VGHSH_VV, 0x1, 0x0 }, // 3565 { PseudoVGHSH_VV_M4, VGHSH_VV, 0x2, 0x0 }, // 3566 { PseudoVGHSH_VV_M8, VGHSH_VV, 0x3, 0x0 }, // 3567 { PseudoVGHSH_VV_MF2, VGHSH_VV, 0x7, 0x0 }, // 3568 { PseudoVGMUL_VV_M1, VGMUL_VV, 0x0, 0x0 }, // 3569 { PseudoVGMUL_VV_M2, VGMUL_VV, 0x1, 0x0 }, // 3570 { PseudoVGMUL_VV_M4, VGMUL_VV, 0x2, 0x0 }, // 3571 { PseudoVGMUL_VV_M8, VGMUL_VV, 0x3, 0x0 }, // 3572 { PseudoVGMUL_VV_MF2, VGMUL_VV, 0x7, 0x0 }, // 3573 { PseudoVID_V_M1, VID_V, 0x0, 0x0 }, // 3574 { PseudoVID_V_M1_MASK, VID_V, 0x0, 0x0 }, // 3575 { PseudoVID_V_M2, VID_V, 0x1, 0x0 }, // 3576 { PseudoVID_V_M2_MASK, VID_V, 0x1, 0x0 }, // 3577 { PseudoVID_V_M4, VID_V, 0x2, 0x0 }, // 3578 { PseudoVID_V_M4_MASK, VID_V, 0x2, 0x0 }, // 3579 { PseudoVID_V_M8, VID_V, 0x3, 0x0 }, // 3580 { PseudoVID_V_M8_MASK, VID_V, 0x3, 0x0 }, // 3581 { PseudoVID_V_MF8, VID_V, 0x5, 0x0 }, // 3582 { PseudoVID_V_MF8_MASK, VID_V, 0x5, 0x0 }, // 3583 { PseudoVID_V_MF4, VID_V, 0x6, 0x0 }, // 3584 { PseudoVID_V_MF4_MASK, VID_V, 0x6, 0x0 }, // 3585 { PseudoVID_V_MF2, VID_V, 0x7, 0x0 }, // 3586 { PseudoVID_V_MF2_MASK, VID_V, 0x7, 0x0 }, // 3587 { PseudoVIOTA_M_M1, VIOTA_M, 0x0, 0x0 }, // 3588 { PseudoVIOTA_M_M1_MASK, VIOTA_M, 0x0, 0x0 }, // 3589 { PseudoVIOTA_M_M2, VIOTA_M, 0x1, 0x0 }, // 3590 { PseudoVIOTA_M_M2_MASK, VIOTA_M, 0x1, 0x0 }, // 3591 { PseudoVIOTA_M_M4, VIOTA_M, 0x2, 0x0 }, // 3592 { PseudoVIOTA_M_M4_MASK, VIOTA_M, 0x2, 0x0 }, // 3593 { PseudoVIOTA_M_M8, VIOTA_M, 0x3, 0x0 }, // 3594 { PseudoVIOTA_M_M8_MASK, VIOTA_M, 0x3, 0x0 }, // 3595 { PseudoVIOTA_M_MF8, VIOTA_M, 0x5, 0x0 }, // 3596 { PseudoVIOTA_M_MF8_MASK, VIOTA_M, 0x5, 0x0 }, // 3597 { PseudoVIOTA_M_MF4, VIOTA_M, 0x6, 0x0 }, // 3598 { PseudoVIOTA_M_MF4_MASK, VIOTA_M, 0x6, 0x0 }, // 3599 { PseudoVIOTA_M_MF2, VIOTA_M, 0x7, 0x0 }, // 3600 { PseudoVIOTA_M_MF2_MASK, VIOTA_M, 0x7, 0x0 }, // 3601 { PseudoVLE16FF_V_M1, VLE16FF_V, 0x0, 0x10 }, // 3602 { PseudoVLE16FF_V_M1_MASK, VLE16FF_V, 0x0, 0x10 }, // 3603 { PseudoVLE16FF_V_M2, VLE16FF_V, 0x1, 0x10 }, // 3604 { PseudoVLE16FF_V_M2_MASK, VLE16FF_V, 0x1, 0x10 }, // 3605 { PseudoVLE16FF_V_M4, VLE16FF_V, 0x2, 0x10 }, // 3606 { PseudoVLE16FF_V_M4_MASK, VLE16FF_V, 0x2, 0x10 }, // 3607 { PseudoVLE16FF_V_M8, VLE16FF_V, 0x3, 0x10 }, // 3608 { PseudoVLE16FF_V_M8_MASK, VLE16FF_V, 0x3, 0x10 }, // 3609 { PseudoVLE16FF_V_MF4, VLE16FF_V, 0x6, 0x10 }, // 3610 { PseudoVLE16FF_V_MF4_MASK, VLE16FF_V, 0x6, 0x10 }, // 3611 { PseudoVLE16FF_V_MF2, VLE16FF_V, 0x7, 0x10 }, // 3612 { PseudoVLE16FF_V_MF2_MASK, VLE16FF_V, 0x7, 0x10 }, // 3613 { PseudoVLE16_V_M1, VLE16_V, 0x0, 0x10 }, // 3614 { PseudoVLE16_V_M1_MASK, VLE16_V, 0x0, 0x10 }, // 3615 { PseudoVLE16_V_M2, VLE16_V, 0x1, 0x10 }, // 3616 { PseudoVLE16_V_M2_MASK, VLE16_V, 0x1, 0x10 }, // 3617 { PseudoVLE16_V_M4, VLE16_V, 0x2, 0x10 }, // 3618 { PseudoVLE16_V_M4_MASK, VLE16_V, 0x2, 0x10 }, // 3619 { PseudoVLE16_V_M8, VLE16_V, 0x3, 0x10 }, // 3620 { PseudoVLE16_V_M8_MASK, VLE16_V, 0x3, 0x10 }, // 3621 { PseudoVLE16_V_MF4, VLE16_V, 0x6, 0x10 }, // 3622 { PseudoVLE16_V_MF4_MASK, VLE16_V, 0x6, 0x10 }, // 3623 { PseudoVLE16_V_MF2, VLE16_V, 0x7, 0x10 }, // 3624 { PseudoVLE16_V_MF2_MASK, VLE16_V, 0x7, 0x10 }, // 3625 { PseudoVLE32FF_V_M1, VLE32FF_V, 0x0, 0x20 }, // 3626 { PseudoVLE32FF_V_M1_MASK, VLE32FF_V, 0x0, 0x20 }, // 3627 { PseudoVLE32FF_V_M2, VLE32FF_V, 0x1, 0x20 }, // 3628 { PseudoVLE32FF_V_M2_MASK, VLE32FF_V, 0x1, 0x20 }, // 3629 { PseudoVLE32FF_V_M4, VLE32FF_V, 0x2, 0x20 }, // 3630 { PseudoVLE32FF_V_M4_MASK, VLE32FF_V, 0x2, 0x20 }, // 3631 { PseudoVLE32FF_V_M8, VLE32FF_V, 0x3, 0x20 }, // 3632 { PseudoVLE32FF_V_M8_MASK, VLE32FF_V, 0x3, 0x20 }, // 3633 { PseudoVLE32FF_V_MF2, VLE32FF_V, 0x7, 0x20 }, // 3634 { PseudoVLE32FF_V_MF2_MASK, VLE32FF_V, 0x7, 0x20 }, // 3635 { PseudoVLE32_V_M1, VLE32_V, 0x0, 0x20 }, // 3636 { PseudoVLE32_V_M1_MASK, VLE32_V, 0x0, 0x20 }, // 3637 { PseudoVLE32_V_M2, VLE32_V, 0x1, 0x20 }, // 3638 { PseudoVLE32_V_M2_MASK, VLE32_V, 0x1, 0x20 }, // 3639 { PseudoVLE32_V_M4, VLE32_V, 0x2, 0x20 }, // 3640 { PseudoVLE32_V_M4_MASK, VLE32_V, 0x2, 0x20 }, // 3641 { PseudoVLE32_V_M8, VLE32_V, 0x3, 0x20 }, // 3642 { PseudoVLE32_V_M8_MASK, VLE32_V, 0x3, 0x20 }, // 3643 { PseudoVLE32_V_MF2, VLE32_V, 0x7, 0x20 }, // 3644 { PseudoVLE32_V_MF2_MASK, VLE32_V, 0x7, 0x20 }, // 3645 { PseudoVLE64FF_V_M1, VLE64FF_V, 0x0, 0x40 }, // 3646 { PseudoVLE64FF_V_M1_MASK, VLE64FF_V, 0x0, 0x40 }, // 3647 { PseudoVLE64FF_V_M2, VLE64FF_V, 0x1, 0x40 }, // 3648 { PseudoVLE64FF_V_M2_MASK, VLE64FF_V, 0x1, 0x40 }, // 3649 { PseudoVLE64FF_V_M4, VLE64FF_V, 0x2, 0x40 }, // 3650 { PseudoVLE64FF_V_M4_MASK, VLE64FF_V, 0x2, 0x40 }, // 3651 { PseudoVLE64FF_V_M8, VLE64FF_V, 0x3, 0x40 }, // 3652 { PseudoVLE64FF_V_M8_MASK, VLE64FF_V, 0x3, 0x40 }, // 3653 { PseudoVLE64_V_M1, VLE64_V, 0x0, 0x40 }, // 3654 { PseudoVLE64_V_M1_MASK, VLE64_V, 0x0, 0x40 }, // 3655 { PseudoVLE64_V_M2, VLE64_V, 0x1, 0x40 }, // 3656 { PseudoVLE64_V_M2_MASK, VLE64_V, 0x1, 0x40 }, // 3657 { PseudoVLE64_V_M4, VLE64_V, 0x2, 0x40 }, // 3658 { PseudoVLE64_V_M4_MASK, VLE64_V, 0x2, 0x40 }, // 3659 { PseudoVLE64_V_M8, VLE64_V, 0x3, 0x40 }, // 3660 { PseudoVLE64_V_M8_MASK, VLE64_V, 0x3, 0x40 }, // 3661 { PseudoVLE8FF_V_M1, VLE8FF_V, 0x0, 0x8 }, // 3662 { PseudoVLE8FF_V_M1_MASK, VLE8FF_V, 0x0, 0x8 }, // 3663 { PseudoVLE8FF_V_M2, VLE8FF_V, 0x1, 0x8 }, // 3664 { PseudoVLE8FF_V_M2_MASK, VLE8FF_V, 0x1, 0x8 }, // 3665 { PseudoVLE8FF_V_M4, VLE8FF_V, 0x2, 0x8 }, // 3666 { PseudoVLE8FF_V_M4_MASK, VLE8FF_V, 0x2, 0x8 }, // 3667 { PseudoVLE8FF_V_M8, VLE8FF_V, 0x3, 0x8 }, // 3668 { PseudoVLE8FF_V_M8_MASK, VLE8FF_V, 0x3, 0x8 }, // 3669 { PseudoVLE8FF_V_MF8, VLE8FF_V, 0x5, 0x8 }, // 3670 { PseudoVLE8FF_V_MF8_MASK, VLE8FF_V, 0x5, 0x8 }, // 3671 { PseudoVLE8FF_V_MF4, VLE8FF_V, 0x6, 0x8 }, // 3672 { PseudoVLE8FF_V_MF4_MASK, VLE8FF_V, 0x6, 0x8 }, // 3673 { PseudoVLE8FF_V_MF2, VLE8FF_V, 0x7, 0x8 }, // 3674 { PseudoVLE8FF_V_MF2_MASK, VLE8FF_V, 0x7, 0x8 }, // 3675 { PseudoVLE8_V_M1, VLE8_V, 0x0, 0x8 }, // 3676 { PseudoVLE8_V_M1_MASK, VLE8_V, 0x0, 0x8 }, // 3677 { PseudoVLE8_V_M2, VLE8_V, 0x1, 0x8 }, // 3678 { PseudoVLE8_V_M2_MASK, VLE8_V, 0x1, 0x8 }, // 3679 { PseudoVLE8_V_M4, VLE8_V, 0x2, 0x8 }, // 3680 { PseudoVLE8_V_M4_MASK, VLE8_V, 0x2, 0x8 }, // 3681 { PseudoVLE8_V_M8, VLE8_V, 0x3, 0x8 }, // 3682 { PseudoVLE8_V_M8_MASK, VLE8_V, 0x3, 0x8 }, // 3683 { PseudoVLE8_V_MF8, VLE8_V, 0x5, 0x8 }, // 3684 { PseudoVLE8_V_MF8_MASK, VLE8_V, 0x5, 0x8 }, // 3685 { PseudoVLE8_V_MF4, VLE8_V, 0x6, 0x8 }, // 3686 { PseudoVLE8_V_MF4_MASK, VLE8_V, 0x6, 0x8 }, // 3687 { PseudoVLE8_V_MF2, VLE8_V, 0x7, 0x8 }, // 3688 { PseudoVLE8_V_MF2_MASK, VLE8_V, 0x7, 0x8 }, // 3689 { PseudoVLM_V_B8, VLM_V, 0x0, 0x0 }, // 3690 { PseudoVLM_V_B16, VLM_V, 0x1, 0x0 }, // 3691 { PseudoVLM_V_B32, VLM_V, 0x2, 0x0 }, // 3692 { PseudoVLM_V_B64, VLM_V, 0x3, 0x0 }, // 3693 { PseudoVLM_V_B1, VLM_V, 0x5, 0x0 }, // 3694 { PseudoVLM_V_B2, VLM_V, 0x6, 0x0 }, // 3695 { PseudoVLM_V_B4, VLM_V, 0x7, 0x0 }, // 3696 { PseudoVLOXEI16_V_M1_M1, VLOXEI16_V, 0x0, 0x0 }, // 3697 { PseudoVLOXEI16_V_M1_M1_MASK, VLOXEI16_V, 0x0, 0x0 }, // 3698 { PseudoVLOXEI16_V_M2_M1, VLOXEI16_V, 0x0, 0x0 }, // 3699 { PseudoVLOXEI16_V_M2_M1_MASK, VLOXEI16_V, 0x0, 0x0 }, // 3700 { PseudoVLOXEI16_V_MF2_M1, VLOXEI16_V, 0x0, 0x0 }, // 3701 { PseudoVLOXEI16_V_MF2_M1_MASK, VLOXEI16_V, 0x0, 0x0 }, // 3702 { PseudoVLOXEI16_V_MF4_M1, VLOXEI16_V, 0x0, 0x0 }, // 3703 { PseudoVLOXEI16_V_MF4_M1_MASK, VLOXEI16_V, 0x0, 0x0 }, // 3704 { PseudoVLOXEI16_V_M1_M2, VLOXEI16_V, 0x1, 0x0 }, // 3705 { PseudoVLOXEI16_V_M1_M2_MASK, VLOXEI16_V, 0x1, 0x0 }, // 3706 { PseudoVLOXEI16_V_M2_M2, VLOXEI16_V, 0x1, 0x0 }, // 3707 { PseudoVLOXEI16_V_M2_M2_MASK, VLOXEI16_V, 0x1, 0x0 }, // 3708 { PseudoVLOXEI16_V_M4_M2, VLOXEI16_V, 0x1, 0x0 }, // 3709 { PseudoVLOXEI16_V_M4_M2_MASK, VLOXEI16_V, 0x1, 0x0 }, // 3710 { PseudoVLOXEI16_V_MF2_M2, VLOXEI16_V, 0x1, 0x0 }, // 3711 { PseudoVLOXEI16_V_MF2_M2_MASK, VLOXEI16_V, 0x1, 0x0 }, // 3712 { PseudoVLOXEI16_V_M1_M4, VLOXEI16_V, 0x2, 0x0 }, // 3713 { PseudoVLOXEI16_V_M1_M4_MASK, VLOXEI16_V, 0x2, 0x0 }, // 3714 { PseudoVLOXEI16_V_M2_M4, VLOXEI16_V, 0x2, 0x0 }, // 3715 { PseudoVLOXEI16_V_M2_M4_MASK, VLOXEI16_V, 0x2, 0x0 }, // 3716 { PseudoVLOXEI16_V_M4_M4, VLOXEI16_V, 0x2, 0x0 }, // 3717 { PseudoVLOXEI16_V_M4_M4_MASK, VLOXEI16_V, 0x2, 0x0 }, // 3718 { PseudoVLOXEI16_V_M8_M4, VLOXEI16_V, 0x2, 0x0 }, // 3719 { PseudoVLOXEI16_V_M8_M4_MASK, VLOXEI16_V, 0x2, 0x0 }, // 3720 { PseudoVLOXEI16_V_M2_M8, VLOXEI16_V, 0x3, 0x0 }, // 3721 { PseudoVLOXEI16_V_M2_M8_MASK, VLOXEI16_V, 0x3, 0x0 }, // 3722 { PseudoVLOXEI16_V_M4_M8, VLOXEI16_V, 0x3, 0x0 }, // 3723 { PseudoVLOXEI16_V_M4_M8_MASK, VLOXEI16_V, 0x3, 0x0 }, // 3724 { PseudoVLOXEI16_V_M8_M8, VLOXEI16_V, 0x3, 0x0 }, // 3725 { PseudoVLOXEI16_V_M8_M8_MASK, VLOXEI16_V, 0x3, 0x0 }, // 3726 { PseudoVLOXEI16_V_MF4_MF8, VLOXEI16_V, 0x5, 0x0 }, // 3727 { PseudoVLOXEI16_V_MF4_MF8_MASK, VLOXEI16_V, 0x5, 0x0 }, // 3728 { PseudoVLOXEI16_V_MF2_MF4, VLOXEI16_V, 0x6, 0x0 }, // 3729 { PseudoVLOXEI16_V_MF2_MF4_MASK, VLOXEI16_V, 0x6, 0x0 }, // 3730 { PseudoVLOXEI16_V_MF4_MF4, VLOXEI16_V, 0x6, 0x0 }, // 3731 { PseudoVLOXEI16_V_MF4_MF4_MASK, VLOXEI16_V, 0x6, 0x0 }, // 3732 { PseudoVLOXEI16_V_M1_MF2, VLOXEI16_V, 0x7, 0x0 }, // 3733 { PseudoVLOXEI16_V_M1_MF2_MASK, VLOXEI16_V, 0x7, 0x0 }, // 3734 { PseudoVLOXEI16_V_MF2_MF2, VLOXEI16_V, 0x7, 0x0 }, // 3735 { PseudoVLOXEI16_V_MF2_MF2_MASK, VLOXEI16_V, 0x7, 0x0 }, // 3736 { PseudoVLOXEI16_V_MF4_MF2, VLOXEI16_V, 0x7, 0x0 }, // 3737 { PseudoVLOXEI16_V_MF4_MF2_MASK, VLOXEI16_V, 0x7, 0x0 }, // 3738 { PseudoVLOXEI32_V_M1_M1, VLOXEI32_V, 0x0, 0x0 }, // 3739 { PseudoVLOXEI32_V_M1_M1_MASK, VLOXEI32_V, 0x0, 0x0 }, // 3740 { PseudoVLOXEI32_V_M2_M1, VLOXEI32_V, 0x0, 0x0 }, // 3741 { PseudoVLOXEI32_V_M2_M1_MASK, VLOXEI32_V, 0x0, 0x0 }, // 3742 { PseudoVLOXEI32_V_M4_M1, VLOXEI32_V, 0x0, 0x0 }, // 3743 { PseudoVLOXEI32_V_M4_M1_MASK, VLOXEI32_V, 0x0, 0x0 }, // 3744 { PseudoVLOXEI32_V_MF2_M1, VLOXEI32_V, 0x0, 0x0 }, // 3745 { PseudoVLOXEI32_V_MF2_M1_MASK, VLOXEI32_V, 0x0, 0x0 }, // 3746 { PseudoVLOXEI32_V_M1_M2, VLOXEI32_V, 0x1, 0x0 }, // 3747 { PseudoVLOXEI32_V_M1_M2_MASK, VLOXEI32_V, 0x1, 0x0 }, // 3748 { PseudoVLOXEI32_V_M2_M2, VLOXEI32_V, 0x1, 0x0 }, // 3749 { PseudoVLOXEI32_V_M2_M2_MASK, VLOXEI32_V, 0x1, 0x0 }, // 3750 { PseudoVLOXEI32_V_M4_M2, VLOXEI32_V, 0x1, 0x0 }, // 3751 { PseudoVLOXEI32_V_M4_M2_MASK, VLOXEI32_V, 0x1, 0x0 }, // 3752 { PseudoVLOXEI32_V_M8_M2, VLOXEI32_V, 0x1, 0x0 }, // 3753 { PseudoVLOXEI32_V_M8_M2_MASK, VLOXEI32_V, 0x1, 0x0 }, // 3754 { PseudoVLOXEI32_V_M2_M4, VLOXEI32_V, 0x2, 0x0 }, // 3755 { PseudoVLOXEI32_V_M2_M4_MASK, VLOXEI32_V, 0x2, 0x0 }, // 3756 { PseudoVLOXEI32_V_M4_M4, VLOXEI32_V, 0x2, 0x0 }, // 3757 { PseudoVLOXEI32_V_M4_M4_MASK, VLOXEI32_V, 0x2, 0x0 }, // 3758 { PseudoVLOXEI32_V_M8_M4, VLOXEI32_V, 0x2, 0x0 }, // 3759 { PseudoVLOXEI32_V_M8_M4_MASK, VLOXEI32_V, 0x2, 0x0 }, // 3760 { PseudoVLOXEI32_V_M4_M8, VLOXEI32_V, 0x3, 0x0 }, // 3761 { PseudoVLOXEI32_V_M4_M8_MASK, VLOXEI32_V, 0x3, 0x0 }, // 3762 { PseudoVLOXEI32_V_M8_M8, VLOXEI32_V, 0x3, 0x0 }, // 3763 { PseudoVLOXEI32_V_M8_M8_MASK, VLOXEI32_V, 0x3, 0x0 }, // 3764 { PseudoVLOXEI32_V_MF2_MF8, VLOXEI32_V, 0x5, 0x0 }, // 3765 { PseudoVLOXEI32_V_MF2_MF8_MASK, VLOXEI32_V, 0x5, 0x0 }, // 3766 { PseudoVLOXEI32_V_M1_MF4, VLOXEI32_V, 0x6, 0x0 }, // 3767 { PseudoVLOXEI32_V_M1_MF4_MASK, VLOXEI32_V, 0x6, 0x0 }, // 3768 { PseudoVLOXEI32_V_MF2_MF4, VLOXEI32_V, 0x6, 0x0 }, // 3769 { PseudoVLOXEI32_V_MF2_MF4_MASK, VLOXEI32_V, 0x6, 0x0 }, // 3770 { PseudoVLOXEI32_V_M1_MF2, VLOXEI32_V, 0x7, 0x0 }, // 3771 { PseudoVLOXEI32_V_M1_MF2_MASK, VLOXEI32_V, 0x7, 0x0 }, // 3772 { PseudoVLOXEI32_V_M2_MF2, VLOXEI32_V, 0x7, 0x0 }, // 3773 { PseudoVLOXEI32_V_M2_MF2_MASK, VLOXEI32_V, 0x7, 0x0 }, // 3774 { PseudoVLOXEI32_V_MF2_MF2, VLOXEI32_V, 0x7, 0x0 }, // 3775 { PseudoVLOXEI32_V_MF2_MF2_MASK, VLOXEI32_V, 0x7, 0x0 }, // 3776 { PseudoVLOXEI64_V_M1_M1, VLOXEI64_V, 0x0, 0x0 }, // 3777 { PseudoVLOXEI64_V_M1_M1_MASK, VLOXEI64_V, 0x0, 0x0 }, // 3778 { PseudoVLOXEI64_V_M2_M1, VLOXEI64_V, 0x0, 0x0 }, // 3779 { PseudoVLOXEI64_V_M2_M1_MASK, VLOXEI64_V, 0x0, 0x0 }, // 3780 { PseudoVLOXEI64_V_M4_M1, VLOXEI64_V, 0x0, 0x0 }, // 3781 { PseudoVLOXEI64_V_M4_M1_MASK, VLOXEI64_V, 0x0, 0x0 }, // 3782 { PseudoVLOXEI64_V_M8_M1, VLOXEI64_V, 0x0, 0x0 }, // 3783 { PseudoVLOXEI64_V_M8_M1_MASK, VLOXEI64_V, 0x0, 0x0 }, // 3784 { PseudoVLOXEI64_V_M2_M2, VLOXEI64_V, 0x1, 0x0 }, // 3785 { PseudoVLOXEI64_V_M2_M2_MASK, VLOXEI64_V, 0x1, 0x0 }, // 3786 { PseudoVLOXEI64_V_M4_M2, VLOXEI64_V, 0x1, 0x0 }, // 3787 { PseudoVLOXEI64_V_M4_M2_MASK, VLOXEI64_V, 0x1, 0x0 }, // 3788 { PseudoVLOXEI64_V_M8_M2, VLOXEI64_V, 0x1, 0x0 }, // 3789 { PseudoVLOXEI64_V_M8_M2_MASK, VLOXEI64_V, 0x1, 0x0 }, // 3790 { PseudoVLOXEI64_V_M4_M4, VLOXEI64_V, 0x2, 0x0 }, // 3791 { PseudoVLOXEI64_V_M4_M4_MASK, VLOXEI64_V, 0x2, 0x0 }, // 3792 { PseudoVLOXEI64_V_M8_M4, VLOXEI64_V, 0x2, 0x0 }, // 3793 { PseudoVLOXEI64_V_M8_M4_MASK, VLOXEI64_V, 0x2, 0x0 }, // 3794 { PseudoVLOXEI64_V_M8_M8, VLOXEI64_V, 0x3, 0x0 }, // 3795 { PseudoVLOXEI64_V_M8_M8_MASK, VLOXEI64_V, 0x3, 0x0 }, // 3796 { PseudoVLOXEI64_V_M1_MF8, VLOXEI64_V, 0x5, 0x0 }, // 3797 { PseudoVLOXEI64_V_M1_MF8_MASK, VLOXEI64_V, 0x5, 0x0 }, // 3798 { PseudoVLOXEI64_V_M1_MF4, VLOXEI64_V, 0x6, 0x0 }, // 3799 { PseudoVLOXEI64_V_M1_MF4_MASK, VLOXEI64_V, 0x6, 0x0 }, // 3800 { PseudoVLOXEI64_V_M2_MF4, VLOXEI64_V, 0x6, 0x0 }, // 3801 { PseudoVLOXEI64_V_M2_MF4_MASK, VLOXEI64_V, 0x6, 0x0 }, // 3802 { PseudoVLOXEI64_V_M1_MF2, VLOXEI64_V, 0x7, 0x0 }, // 3803 { PseudoVLOXEI64_V_M1_MF2_MASK, VLOXEI64_V, 0x7, 0x0 }, // 3804 { PseudoVLOXEI64_V_M2_MF2, VLOXEI64_V, 0x7, 0x0 }, // 3805 { PseudoVLOXEI64_V_M2_MF2_MASK, VLOXEI64_V, 0x7, 0x0 }, // 3806 { PseudoVLOXEI64_V_M4_MF2, VLOXEI64_V, 0x7, 0x0 }, // 3807 { PseudoVLOXEI64_V_M4_MF2_MASK, VLOXEI64_V, 0x7, 0x0 }, // 3808 { PseudoVLOXEI8_V_M1_M1, VLOXEI8_V, 0x0, 0x0 }, // 3809 { PseudoVLOXEI8_V_M1_M1_MASK, VLOXEI8_V, 0x0, 0x0 }, // 3810 { PseudoVLOXEI8_V_MF2_M1, VLOXEI8_V, 0x0, 0x0 }, // 3811 { PseudoVLOXEI8_V_MF2_M1_MASK, VLOXEI8_V, 0x0, 0x0 }, // 3812 { PseudoVLOXEI8_V_MF4_M1, VLOXEI8_V, 0x0, 0x0 }, // 3813 { PseudoVLOXEI8_V_MF4_M1_MASK, VLOXEI8_V, 0x0, 0x0 }, // 3814 { PseudoVLOXEI8_V_MF8_M1, VLOXEI8_V, 0x0, 0x0 }, // 3815 { PseudoVLOXEI8_V_MF8_M1_MASK, VLOXEI8_V, 0x0, 0x0 }, // 3816 { PseudoVLOXEI8_V_M1_M2, VLOXEI8_V, 0x1, 0x0 }, // 3817 { PseudoVLOXEI8_V_M1_M2_MASK, VLOXEI8_V, 0x1, 0x0 }, // 3818 { PseudoVLOXEI8_V_M2_M2, VLOXEI8_V, 0x1, 0x0 }, // 3819 { PseudoVLOXEI8_V_M2_M2_MASK, VLOXEI8_V, 0x1, 0x0 }, // 3820 { PseudoVLOXEI8_V_MF2_M2, VLOXEI8_V, 0x1, 0x0 }, // 3821 { PseudoVLOXEI8_V_MF2_M2_MASK, VLOXEI8_V, 0x1, 0x0 }, // 3822 { PseudoVLOXEI8_V_MF4_M2, VLOXEI8_V, 0x1, 0x0 }, // 3823 { PseudoVLOXEI8_V_MF4_M2_MASK, VLOXEI8_V, 0x1, 0x0 }, // 3824 { PseudoVLOXEI8_V_M1_M4, VLOXEI8_V, 0x2, 0x0 }, // 3825 { PseudoVLOXEI8_V_M1_M4_MASK, VLOXEI8_V, 0x2, 0x0 }, // 3826 { PseudoVLOXEI8_V_M2_M4, VLOXEI8_V, 0x2, 0x0 }, // 3827 { PseudoVLOXEI8_V_M2_M4_MASK, VLOXEI8_V, 0x2, 0x0 }, // 3828 { PseudoVLOXEI8_V_M4_M4, VLOXEI8_V, 0x2, 0x0 }, // 3829 { PseudoVLOXEI8_V_M4_M4_MASK, VLOXEI8_V, 0x2, 0x0 }, // 3830 { PseudoVLOXEI8_V_MF2_M4, VLOXEI8_V, 0x2, 0x0 }, // 3831 { PseudoVLOXEI8_V_MF2_M4_MASK, VLOXEI8_V, 0x2, 0x0 }, // 3832 { PseudoVLOXEI8_V_M1_M8, VLOXEI8_V, 0x3, 0x0 }, // 3833 { PseudoVLOXEI8_V_M1_M8_MASK, VLOXEI8_V, 0x3, 0x0 }, // 3834 { PseudoVLOXEI8_V_M2_M8, VLOXEI8_V, 0x3, 0x0 }, // 3835 { PseudoVLOXEI8_V_M2_M8_MASK, VLOXEI8_V, 0x3, 0x0 }, // 3836 { PseudoVLOXEI8_V_M4_M8, VLOXEI8_V, 0x3, 0x0 }, // 3837 { PseudoVLOXEI8_V_M4_M8_MASK, VLOXEI8_V, 0x3, 0x0 }, // 3838 { PseudoVLOXEI8_V_M8_M8, VLOXEI8_V, 0x3, 0x0 }, // 3839 { PseudoVLOXEI8_V_M8_M8_MASK, VLOXEI8_V, 0x3, 0x0 }, // 3840 { PseudoVLOXEI8_V_MF8_MF8, VLOXEI8_V, 0x5, 0x0 }, // 3841 { PseudoVLOXEI8_V_MF8_MF8_MASK, VLOXEI8_V, 0x5, 0x0 }, // 3842 { PseudoVLOXEI8_V_MF4_MF4, VLOXEI8_V, 0x6, 0x0 }, // 3843 { PseudoVLOXEI8_V_MF4_MF4_MASK, VLOXEI8_V, 0x6, 0x0 }, // 3844 { PseudoVLOXEI8_V_MF8_MF4, VLOXEI8_V, 0x6, 0x0 }, // 3845 { PseudoVLOXEI8_V_MF8_MF4_MASK, VLOXEI8_V, 0x6, 0x0 }, // 3846 { PseudoVLOXEI8_V_MF2_MF2, VLOXEI8_V, 0x7, 0x0 }, // 3847 { PseudoVLOXEI8_V_MF2_MF2_MASK, VLOXEI8_V, 0x7, 0x0 }, // 3848 { PseudoVLOXEI8_V_MF4_MF2, VLOXEI8_V, 0x7, 0x0 }, // 3849 { PseudoVLOXEI8_V_MF4_MF2_MASK, VLOXEI8_V, 0x7, 0x0 }, // 3850 { PseudoVLOXEI8_V_MF8_MF2, VLOXEI8_V, 0x7, 0x0 }, // 3851 { PseudoVLOXEI8_V_MF8_MF2_MASK, VLOXEI8_V, 0x7, 0x0 }, // 3852 { PseudoVLOXSEG2EI16_V_M1_M1, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3853 { PseudoVLOXSEG2EI16_V_M1_M1_MASK, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3854 { PseudoVLOXSEG2EI16_V_M2_M1, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3855 { PseudoVLOXSEG2EI16_V_M2_M1_MASK, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3856 { PseudoVLOXSEG2EI16_V_MF2_M1, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3857 { PseudoVLOXSEG2EI16_V_MF2_M1_MASK, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3858 { PseudoVLOXSEG2EI16_V_MF4_M1, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3859 { PseudoVLOXSEG2EI16_V_MF4_M1_MASK, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3860 { PseudoVLOXSEG2EI16_V_M1_M2, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3861 { PseudoVLOXSEG2EI16_V_M1_M2_MASK, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3862 { PseudoVLOXSEG2EI16_V_M2_M2, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3863 { PseudoVLOXSEG2EI16_V_M2_M2_MASK, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3864 { PseudoVLOXSEG2EI16_V_M4_M2, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3865 { PseudoVLOXSEG2EI16_V_M4_M2_MASK, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3866 { PseudoVLOXSEG2EI16_V_MF2_M2, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3867 { PseudoVLOXSEG2EI16_V_MF2_M2_MASK, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3868 { PseudoVLOXSEG2EI16_V_M1_M4, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3869 { PseudoVLOXSEG2EI16_V_M1_M4_MASK, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3870 { PseudoVLOXSEG2EI16_V_M2_M4, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3871 { PseudoVLOXSEG2EI16_V_M2_M4_MASK, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3872 { PseudoVLOXSEG2EI16_V_M4_M4, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3873 { PseudoVLOXSEG2EI16_V_M4_M4_MASK, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3874 { PseudoVLOXSEG2EI16_V_M8_M4, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3875 { PseudoVLOXSEG2EI16_V_M8_M4_MASK, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3876 { PseudoVLOXSEG2EI16_V_MF4_MF8, VLOXSEG2EI16_V, 0x5, 0x0 }, // 3877 { PseudoVLOXSEG2EI16_V_MF4_MF8_MASK, VLOXSEG2EI16_V, 0x5, 0x0 }, // 3878 { PseudoVLOXSEG2EI16_V_MF2_MF4, VLOXSEG2EI16_V, 0x6, 0x0 }, // 3879 { PseudoVLOXSEG2EI16_V_MF2_MF4_MASK, VLOXSEG2EI16_V, 0x6, 0x0 }, // 3880 { PseudoVLOXSEG2EI16_V_MF4_MF4, VLOXSEG2EI16_V, 0x6, 0x0 }, // 3881 { PseudoVLOXSEG2EI16_V_MF4_MF4_MASK, VLOXSEG2EI16_V, 0x6, 0x0 }, // 3882 { PseudoVLOXSEG2EI16_V_M1_MF2, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3883 { PseudoVLOXSEG2EI16_V_M1_MF2_MASK, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3884 { PseudoVLOXSEG2EI16_V_MF2_MF2, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3885 { PseudoVLOXSEG2EI16_V_MF2_MF2_MASK, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3886 { PseudoVLOXSEG2EI16_V_MF4_MF2, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3887 { PseudoVLOXSEG2EI16_V_MF4_MF2_MASK, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3888 { PseudoVLOXSEG2EI32_V_M1_M1, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3889 { PseudoVLOXSEG2EI32_V_M1_M1_MASK, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3890 { PseudoVLOXSEG2EI32_V_M2_M1, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3891 { PseudoVLOXSEG2EI32_V_M2_M1_MASK, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3892 { PseudoVLOXSEG2EI32_V_M4_M1, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3893 { PseudoVLOXSEG2EI32_V_M4_M1_MASK, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3894 { PseudoVLOXSEG2EI32_V_MF2_M1, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3895 { PseudoVLOXSEG2EI32_V_MF2_M1_MASK, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3896 { PseudoVLOXSEG2EI32_V_M1_M2, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3897 { PseudoVLOXSEG2EI32_V_M1_M2_MASK, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3898 { PseudoVLOXSEG2EI32_V_M2_M2, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3899 { PseudoVLOXSEG2EI32_V_M2_M2_MASK, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3900 { PseudoVLOXSEG2EI32_V_M4_M2, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3901 { PseudoVLOXSEG2EI32_V_M4_M2_MASK, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3902 { PseudoVLOXSEG2EI32_V_M8_M2, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3903 { PseudoVLOXSEG2EI32_V_M8_M2_MASK, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3904 { PseudoVLOXSEG2EI32_V_M2_M4, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3905 { PseudoVLOXSEG2EI32_V_M2_M4_MASK, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3906 { PseudoVLOXSEG2EI32_V_M4_M4, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3907 { PseudoVLOXSEG2EI32_V_M4_M4_MASK, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3908 { PseudoVLOXSEG2EI32_V_M8_M4, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3909 { PseudoVLOXSEG2EI32_V_M8_M4_MASK, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3910 { PseudoVLOXSEG2EI32_V_MF2_MF8, VLOXSEG2EI32_V, 0x5, 0x0 }, // 3911 { PseudoVLOXSEG2EI32_V_MF2_MF8_MASK, VLOXSEG2EI32_V, 0x5, 0x0 }, // 3912 { PseudoVLOXSEG2EI32_V_M1_MF4, VLOXSEG2EI32_V, 0x6, 0x0 }, // 3913 { PseudoVLOXSEG2EI32_V_M1_MF4_MASK, VLOXSEG2EI32_V, 0x6, 0x0 }, // 3914 { PseudoVLOXSEG2EI32_V_MF2_MF4, VLOXSEG2EI32_V, 0x6, 0x0 }, // 3915 { PseudoVLOXSEG2EI32_V_MF2_MF4_MASK, VLOXSEG2EI32_V, 0x6, 0x0 }, // 3916 { PseudoVLOXSEG2EI32_V_M1_MF2, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3917 { PseudoVLOXSEG2EI32_V_M1_MF2_MASK, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3918 { PseudoVLOXSEG2EI32_V_M2_MF2, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3919 { PseudoVLOXSEG2EI32_V_M2_MF2_MASK, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3920 { PseudoVLOXSEG2EI32_V_MF2_MF2, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3921 { PseudoVLOXSEG2EI32_V_MF2_MF2_MASK, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3922 { PseudoVLOXSEG2EI64_V_M1_M1, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3923 { PseudoVLOXSEG2EI64_V_M1_M1_MASK, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3924 { PseudoVLOXSEG2EI64_V_M2_M1, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3925 { PseudoVLOXSEG2EI64_V_M2_M1_MASK, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3926 { PseudoVLOXSEG2EI64_V_M4_M1, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3927 { PseudoVLOXSEG2EI64_V_M4_M1_MASK, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3928 { PseudoVLOXSEG2EI64_V_M8_M1, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3929 { PseudoVLOXSEG2EI64_V_M8_M1_MASK, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3930 { PseudoVLOXSEG2EI64_V_M2_M2, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3931 { PseudoVLOXSEG2EI64_V_M2_M2_MASK, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3932 { PseudoVLOXSEG2EI64_V_M4_M2, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3933 { PseudoVLOXSEG2EI64_V_M4_M2_MASK, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3934 { PseudoVLOXSEG2EI64_V_M8_M2, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3935 { PseudoVLOXSEG2EI64_V_M8_M2_MASK, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3936 { PseudoVLOXSEG2EI64_V_M4_M4, VLOXSEG2EI64_V, 0x2, 0x0 }, // 3937 { PseudoVLOXSEG2EI64_V_M4_M4_MASK, VLOXSEG2EI64_V, 0x2, 0x0 }, // 3938 { PseudoVLOXSEG2EI64_V_M8_M4, VLOXSEG2EI64_V, 0x2, 0x0 }, // 3939 { PseudoVLOXSEG2EI64_V_M8_M4_MASK, VLOXSEG2EI64_V, 0x2, 0x0 }, // 3940 { PseudoVLOXSEG2EI64_V_M1_MF8, VLOXSEG2EI64_V, 0x5, 0x0 }, // 3941 { PseudoVLOXSEG2EI64_V_M1_MF8_MASK, VLOXSEG2EI64_V, 0x5, 0x0 }, // 3942 { PseudoVLOXSEG2EI64_V_M1_MF4, VLOXSEG2EI64_V, 0x6, 0x0 }, // 3943 { PseudoVLOXSEG2EI64_V_M1_MF4_MASK, VLOXSEG2EI64_V, 0x6, 0x0 }, // 3944 { PseudoVLOXSEG2EI64_V_M2_MF4, VLOXSEG2EI64_V, 0x6, 0x0 }, // 3945 { PseudoVLOXSEG2EI64_V_M2_MF4_MASK, VLOXSEG2EI64_V, 0x6, 0x0 }, // 3946 { PseudoVLOXSEG2EI64_V_M1_MF2, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3947 { PseudoVLOXSEG2EI64_V_M1_MF2_MASK, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3948 { PseudoVLOXSEG2EI64_V_M2_MF2, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3949 { PseudoVLOXSEG2EI64_V_M2_MF2_MASK, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3950 { PseudoVLOXSEG2EI64_V_M4_MF2, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3951 { PseudoVLOXSEG2EI64_V_M4_MF2_MASK, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3952 { PseudoVLOXSEG2EI8_V_M1_M1, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3953 { PseudoVLOXSEG2EI8_V_M1_M1_MASK, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3954 { PseudoVLOXSEG2EI8_V_MF2_M1, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3955 { PseudoVLOXSEG2EI8_V_MF2_M1_MASK, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3956 { PseudoVLOXSEG2EI8_V_MF4_M1, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3957 { PseudoVLOXSEG2EI8_V_MF4_M1_MASK, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3958 { PseudoVLOXSEG2EI8_V_MF8_M1, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3959 { PseudoVLOXSEG2EI8_V_MF8_M1_MASK, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3960 { PseudoVLOXSEG2EI8_V_M1_M2, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3961 { PseudoVLOXSEG2EI8_V_M1_M2_MASK, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3962 { PseudoVLOXSEG2EI8_V_M2_M2, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3963 { PseudoVLOXSEG2EI8_V_M2_M2_MASK, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3964 { PseudoVLOXSEG2EI8_V_MF2_M2, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3965 { PseudoVLOXSEG2EI8_V_MF2_M2_MASK, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3966 { PseudoVLOXSEG2EI8_V_MF4_M2, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3967 { PseudoVLOXSEG2EI8_V_MF4_M2_MASK, VLOXSEG2EI8_V, 0x1, 0x0 }<TRUNCATED>#endif#ifdef GET_RISCVVLETable_DECL#endif#ifdef GET_RISCVVLETable_IMPL#endif#ifdef GET_RISCVVLSEGTable_DECL#endif#ifdef GET_RISCVVLSEGTable_IMPL#endif#ifdef GET_RISCVVLXSEGTable_DECL#endif#ifdef GET_RISCVVLXSEGTable_IMPL#endif#ifdef GET_RISCVVLXTable_DECL#endif#ifdef GET_RISCVVLXTable_IMPL#endif#ifdef GET_RISCVVPseudosTable_DECL#endif#ifdef GET_RISCVVPseudosTable_IMPL#endif#ifdef GET_RISCVVSETable_DECL#endif#ifdef GET_RISCVVSETable_IMPL#endif#ifdef GET_RISCVVSSEGTable_DECL#endif#ifdef GET_RISCVVSSEGTable_IMPL#endif#ifdef GET_RISCVVSXSEGTable_DECL#endif#ifdef GET_RISCVVSXSEGTable_IMPL#endif#ifdef GET_RISCVVSXTable_DECL#endif#ifdef GET_RISCVVSXTable_IMPL#endif#ifdef GET_SysRegsList_DECL#endif#ifdef GET_SysRegsList_IMPL#endif#undef GET_RISCVMaskedPseudosTable_DECL#undef GET_RISCVMaskedPseudosTable_IMPL#undef GET_RISCVOpcodesList_DECL#undef GET_RISCVOpcodesList_IMPL#undef GET_RISCVTuneInfoTable_DECL#undef GET_RISCVTuneInfoTable_IMPL#undef GET_RISCVVIntrinsicsTable_DECL#undef GET_RISCVVIntrinsicsTable_IMPL#undef GET_RISCVVInversePseudosTable_DECL#undef GET_RISCVVInversePseudosTable_IMPL#undef GET_RISCVVLETable_DECL#undef GET_RISCVVLETable_IMPL#undef GET_RISCVVLSEGTable_DECL#undef GET_RISCVVLSEGTable_IMPL#undef GET_RISCVVLXSEGTable_DECL#undef GET_RISCVVLXSEGTable_IMPL#undef GET_RISCVVLXTable_DECL#undef GET_RISCVVLXTable_IMPL#undef GET_RISCVVPseudosTable_DECL#undef GET_RISCVVPseudosTable_IMPL#undef GET_RISCVVSETable_DECL#undef GET_RISCVVSETable_IMPL#undef GET_RISCVVSSEGTable_DECL#undef GET_RISCVVSSEGTable_IMPL#undef GET_RISCVVSXSEGTable_DECL#undef GET_RISCVVSXSEGTable_IMPL#undef GET_RISCVVSXTable_DECL#undef GET_RISCVVSXTable_IMPL#undef GET_SysRegsList_DECL#undef GET_SysRegsList_IMPL
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