llvm/lib/Target/Sparc/SparcGenInstrInfo.inc

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Instruction Enum Values and Descriptors                             *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
namespace llvm {

namespace SP {
  enum { … };

} // end namespace SP
} // end namespace llvm
#endif // GET_INSTRINFO_ENUM

#ifdef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_SCHED_ENUM
namespace llvm {

namespace SP {
namespace Sched {
  enum {
    NoInstrModel	= 0,
    IIC_iu_instr	= 1,
    IIC_fpu_normal_instr	= 2,
    IIC_jmp_or_call	= 3,
    IIC_fpu_abs	= 4,
    IIC_fpu_fast_instr	= 5,
    IIC_fpu_divd	= 6,
    IIC_fpu_divs	= 7,
    IIC_fpu_muld	= 8,
    IIC_fpu_muls	= 9,
    IIC_fpu_negs	= 10,
    IIC_fpu_sqrtd	= 11,
    IIC_fpu_sqrts	= 12,
    IIC_fpu_stod	= 13,
    IIC_ldd	= 14,
    IIC_iu_or_fpu_instr	= 15,
    IIC_iu_div	= 16,
    IIC_smac_umac	= 17,
    IIC_iu_smul	= 18,
    IIC_st	= 19,
    IIC_std	= 20,
    IIC_iu_umul	= 21,
    SCHED_LIST_END = 22
  };
} // end namespace Sched
} // end namespace SP
} // end namespace llvm
#endif // GET_INSTRINFO_SCHED_ENUM

#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
namespace llvm {

struct SparcInstrTable {
  MCInstrDesc Insts[816];
  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
  MCOperandInfo OperandInfo[544];
  static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
  MCPhysReg ImplicitOps[32];
};

} // end namespace llvm
#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)

#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC
namespace llvm {

static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
static constexpr unsigned SparcImpOpBase = sizeof SparcInstrTable::OperandInfo / (sizeof(MCPhysReg));

extern const SparcInstrTable SparcDescs = {
  {
    { 815,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	176,	0, 0x0ULL },  // Inst #815 = XORrr
    { 814,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	173,	0, 0x0ULL },  // Inst #814 = XORri
    { 813,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	176,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #813 = XORCCrr
    { 812,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #812 = XORCCri
    { 811,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	176,	0, 0x0ULL },  // Inst #811 = XNORrr
    { 810,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #810 = XNORri
    { 809,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	176,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #809 = XNORCCrr
    { 808,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #808 = XNORCCri
    { 807,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #807 = XMULXHI
    { 806,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #806 = XMULX
    { 805,	2,	0,	4,	1,	0,	1,	SparcImpOpBase + 18,	375,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #805 = WRWIMrr
    { 804,	2,	0,	4,	1,	0,	1,	SparcImpOpBase + 18,	168,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #804 = WRWIMri
    { 803,	2,	0,	4,	1,	0,	1,	SparcImpOpBase + 17,	375,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #803 = WRTBRrr
    { 802,	2,	0,	4,	1,	0,	1,	SparcImpOpBase + 17,	168,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #802 = WRTBRri
    { 801,	2,	0,	4,	1,	0,	1,	SparcImpOpBase + 15,	375,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #801 = WRPSRrr
    { 800,	2,	0,	4,	1,	0,	1,	SparcImpOpBase + 15,	168,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #800 = WRPSRri
    { 799,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	541,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #799 = WRPRrr
    { 798,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	538,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #798 = WRPRri
    { 797,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	535,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #797 = WRASRrr
    { 796,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	532,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #796 = WRASRri
    { 795,	5,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	527,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #795 = V9MOVFCCrr
    { 794,	5,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	522,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #794 = V9MOVFCCri
    { 793,	5,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	517,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #793 = V9FMOVS_FCC
    { 792,	5,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	512,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #792 = V9FMOVQ_FCC
    { 791,	5,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	507,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #791 = V9FMOVD_FCC
    { 790,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	504,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #790 = V9FCMPS
    { 789,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	501,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #789 = V9FCMPQ
    { 788,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	504,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #788 = V9FCMPES
    { 787,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	501,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #787 = V9FCMPEQ
    { 786,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	238,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #786 = V9FCMPED
    { 785,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	238,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #785 = V9FCMPD
    { 784,	1,	0,	4,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #784 = UNIMP
    { 783,	3,	1,	4,	21,	0,	1,	SparcImpOpBase + 30,	176,	0, 0x0ULL },  // Inst #783 = UMULrr
    { 782,	3,	1,	4,	21,	0,	1,	SparcImpOpBase + 30,	173,	0, 0x0ULL },  // Inst #782 = UMULri
    { 781,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #781 = UMULXHI
    { 780,	3,	1,	4,	21,	0,	2,	SparcImpOpBase + 28,	176,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #780 = UMULCCrr
    { 779,	3,	1,	4,	21,	0,	2,	SparcImpOpBase + 28,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #779 = UMULCCri
    { 778,	4,	1,	4,	17,	2,	2,	SparcImpOpBase + 24,	405,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #778 = UMACrr
    { 777,	4,	1,	4,	17,	2,	2,	SparcImpOpBase + 24,	401,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #777 = UMACri
    { 776,	3,	1,	4,	16,	1,	1,	SparcImpOpBase + 22,	176,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #776 = UDIVrr
    { 775,	3,	1,	4,	16,	1,	1,	SparcImpOpBase + 22,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #775 = UDIVri
    { 774,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #774 = UDIVXrr
    { 773,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #773 = UDIVXri
    { 772,	3,	1,	4,	16,	1,	2,	SparcImpOpBase + 19,	176,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #772 = UDIVCCrr
    { 771,	3,	1,	4,	16,	1,	2,	SparcImpOpBase + 19,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #771 = UDIVCCri
    { 770,	3,	0,	4,	0,	1,	0,	SparcImpOpBase + 4,	398,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #770 = TXCCrr
    { 769,	3,	0,	4,	0,	1,	0,	SparcImpOpBase + 4,	494,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #769 = TXCCri
    { 768,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	176,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #768 = TSUBCCrr
    { 767,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #767 = TSUBCCri
    { 766,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	176,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #766 = TSUBCCTVrr
    { 765,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #765 = TSUBCCTVri
    { 764,	3,	0,	4,	0,	1,	0,	SparcImpOpBase + 4,	398,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #764 = TRAPrr
    { 763,	3,	0,	4,	0,	1,	0,	SparcImpOpBase + 4,	494,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #763 = TRAPri
    { 762,	4,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	283,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #762 = TLS_LDrr
    { 761,	4,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	283,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #761 = TLS_LDXrr
    { 760,	2,	0,	4,	3,	1,	0,	SparcImpOpBase + 7,	13,	0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #760 = TLS_CALL
    { 759,	4,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	497,	0, 0x0ULL },  // Inst #759 = TLS_ADDrr
    { 758,	3,	0,	4,	0,	1,	0,	SparcImpOpBase + 4,	398,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #758 = TICCrr
    { 757,	3,	0,	4,	0,	1,	0,	SparcImpOpBase + 4,	494,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #757 = TICCri
    { 756,	2,	0,	4,	1,	0,	0,	SparcImpOpBase + 0,	35,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #756 = TAIL_CALLri
    { 755,	1,	0,	4,	0,	0,	0,	SparcImpOpBase + 0,	0,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #755 = TAIL_CALL
    { 754,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	176,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #754 = TADDCCrr
    { 753,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #753 = TADDCCri
    { 752,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	176,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #752 = TADDCCTVrr
    { 751,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #751 = TADDCCTVri
    { 750,	0,	0,	4,	1,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #750 = TA5
    { 749,	0,	0,	4,	1,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #749 = TA3
    { 748,	0,	0,	4,	1,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #748 = TA1
    { 747,	4,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	490,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #747 = SWAPrr
    { 746,	4,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	481,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #746 = SWAPri
    { 745,	5,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	485,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #745 = SWAPArr
    { 744,	4,	1,	4,	1,	1,	0,	SparcImpOpBase + 8,	481,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #744 = SWAPAri
    { 743,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	176,	0, 0x0ULL },  // Inst #743 = SUBrr
    { 742,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	173,	0, 0x0ULL },  // Inst #742 = SUBri
    { 741,	3,	1,	4,	1,	1,	1,	SparcImpOpBase + 5,	176,	0, 0x0ULL },  // Inst #741 = SUBErr
    { 740,	3,	1,	4,	1,	1,	1,	SparcImpOpBase + 5,	173,	0, 0x0ULL },  // Inst #740 = SUBEri
    { 739,	3,	1,	4,	1,	1,	0,	SparcImpOpBase + 4,	176,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #739 = SUBCrr
    { 738,	3,	1,	4,	1,	1,	0,	SparcImpOpBase + 4,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #738 = SUBCri
    { 737,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	176,	0|(1ULL<<MCID::HasPostISelHook), 0x0ULL },  // Inst #737 = SUBCCrr
    { 736,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	173,	0|(1ULL<<MCID::HasPostISelHook), 0x0ULL },  // Inst #736 = SUBCCri
    { 735,	3,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	416,	0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #735 = STrr
    { 734,	3,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	409,	0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #734 = STri
    { 733,	3,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	478,	0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #733 = STXrr
    { 732,	3,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	471,	0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #732 = STXri
    { 731,	2,	0,	4,	1,	1,	0,	SparcImpOpBase + 10,	182,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #731 = STXFSRrr
    { 730,	2,	0,	4,	1,	1,	0,	SparcImpOpBase + 10,	35,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #730 = STXFSRri
    { 729,	4,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	474,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #729 = STXArr
    { 728,	3,	0,	4,	19,	1,	0,	SparcImpOpBase + 8,	471,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #728 = STXAri
    { 727,	3,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	468,	0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #727 = STQFrr
    { 726,	3,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	461,	0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #726 = STQFri
    { 725,	4,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	464,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #725 = STQFArr
    { 724,	3,	0,	4,	19,	1,	0,	SparcImpOpBase + 8,	461,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #724 = STQFAri
    { 723,	3,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	416,	0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #723 = STHrr
    { 722,	3,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	409,	0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #722 = STHri
    { 721,	4,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	412,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #721 = STHArr
    { 720,	3,	0,	4,	19,	1,	0,	SparcImpOpBase + 8,	409,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #720 = STHAri
    { 719,	3,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	458,	0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #719 = STFrr
    { 718,	3,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	451,	0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #718 = STFri
    { 717,	2,	0,	4,	19,	1,	0,	SparcImpOpBase + 10,	182,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #717 = STFSRrr
    { 716,	2,	0,	4,	19,	1,	0,	SparcImpOpBase + 10,	35,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #716 = STFSRri
    { 715,	4,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	454,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #715 = STFArr
    { 714,	3,	0,	4,	19,	1,	0,	SparcImpOpBase + 8,	451,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #714 = STFAri
    { 713,	3,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	448,	0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #713 = STDrr
    { 712,	3,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	425,	0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #712 = STDri
    { 711,	3,	0,	4,	20,	0,	0,	SparcImpOpBase + 0,	445,	0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #711 = STDFrr
    { 710,	3,	0,	4,	20,	0,	0,	SparcImpOpBase + 0,	438,	0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #710 = STDFri
    { 709,	2,	0,	4,	20,	0,	1,	SparcImpOpBase + 16,	182,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #709 = STDFQrr
    { 708,	2,	0,	4,	20,	0,	1,	SparcImpOpBase + 16,	35,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #708 = STDFQri
    { 707,	4,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	441,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #707 = STDFArr
    { 706,	3,	0,	4,	19,	1,	0,	SparcImpOpBase + 8,	438,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #706 = STDFAri
    { 705,	3,	0,	4,	20,	0,	0,	SparcImpOpBase + 0,	435,	0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #705 = STDCrr
    { 704,	3,	0,	4,	20,	0,	0,	SparcImpOpBase + 0,	432,	0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #704 = STDCri
    { 703,	2,	0,	4,	20,	1,	0,	SparcImpOpBase + 31,	182,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #703 = STDCQrr
    { 702,	2,	0,	4,	20,	1,	0,	SparcImpOpBase + 31,	35,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #702 = STDCQri
    { 701,	4,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	428,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #701 = STDArr
    { 700,	3,	0,	4,	19,	1,	0,	SparcImpOpBase + 8,	425,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #700 = STDAri
    { 699,	3,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	422,	0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #699 = STCrr
    { 698,	3,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	419,	0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #698 = STCri
    { 697,	2,	0,	4,	19,	1,	0,	SparcImpOpBase + 9,	182,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #697 = STCSRrr
    { 696,	2,	0,	4,	19,	1,	0,	SparcImpOpBase + 9,	35,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #696 = STCSRri
    { 695,	3,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	416,	0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #695 = STBrr
    { 694,	3,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	409,	0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #694 = STBri
    { 693,	4,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	412,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #693 = STBArr
    { 692,	3,	0,	4,	19,	1,	0,	SparcImpOpBase + 8,	409,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #692 = STBAri
    { 691,	0,	0,	4,	1,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #691 = STBAR
    { 690,	4,	0,	4,	19,	0,	0,	SparcImpOpBase + 0,	412,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #690 = STArr
    { 689,	3,	0,	4,	19,	1,	0,	SparcImpOpBase + 8,	409,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #689 = STAri
    { 688,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	176,	0, 0x0ULL },  // Inst #688 = SRLrr
    { 687,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	398,	0, 0x0ULL },  // Inst #687 = SRLri
    { 686,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	395,	0, 0x0ULL },  // Inst #686 = SRLXrr
    { 685,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	392,	0, 0x0ULL },  // Inst #685 = SRLXri
    { 684,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	176,	0, 0x0ULL },  // Inst #684 = SRArr
    { 683,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	398,	0, 0x0ULL },  // Inst #683 = SRAri
    { 682,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	395,	0, 0x0ULL },  // Inst #682 = SRAXrr
    { 681,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	392,	0, 0x0ULL },  // Inst #681 = SRAXri
    { 680,	3,	1,	4,	18,	0,	1,	SparcImpOpBase + 30,	176,	0, 0x0ULL },  // Inst #680 = SMULrr
    { 679,	3,	1,	4,	18,	0,	1,	SparcImpOpBase + 30,	173,	0, 0x0ULL },  // Inst #679 = SMULri
    { 678,	3,	1,	4,	18,	0,	2,	SparcImpOpBase + 28,	176,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #678 = SMULCCrr
    { 677,	3,	1,	4,	18,	0,	2,	SparcImpOpBase + 28,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #677 = SMULCCri
    { 676,	4,	1,	4,	17,	2,	2,	SparcImpOpBase + 24,	405,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #676 = SMACrr
    { 675,	4,	1,	4,	17,	2,	2,	SparcImpOpBase + 24,	401,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #675 = SMACri
    { 674,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	176,	0, 0x0ULL },  // Inst #674 = SLLrr
    { 673,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	398,	0, 0x0ULL },  // Inst #673 = SLLri
    { 672,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	395,	0, 0x0ULL },  // Inst #672 = SLLXrr
    { 671,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	392,	0, 0x0ULL },  // Inst #671 = SLLXri
    { 670,	1,	0,	4,	1,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #670 = SIR
    { 669,	0,	0,	4,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #669 = SIAM
    { 668,	0,	0,	4,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #668 = SHUTDOWN
    { 667,	2,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	168,	0, 0x0ULL },  // Inst #667 = SETHIi
    { 666,	3,	1,	4,	16,	1,	1,	SparcImpOpBase + 22,	176,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #666 = SDIVrr
    { 665,	3,	1,	4,	16,	1,	1,	SparcImpOpBase + 22,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #665 = SDIVri
    { 664,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #664 = SDIVXrr
    { 663,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #663 = SDIVXri
    { 662,	3,	1,	4,	16,	1,	2,	SparcImpOpBase + 19,	176,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #662 = SDIVCCrr
    { 661,	3,	1,	4,	16,	1,	2,	SparcImpOpBase + 19,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #661 = SDIVCCri
    { 660,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	176,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #660 = SAVErr
    { 659,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #659 = SAVEri
    { 658,	0,	0,	4,	1,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #658 = SAVED
    { 657,	2,	0,	4,	3,	0,	0,	SparcImpOpBase + 0,	182,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #657 = RETTrr
    { 656,	2,	0,	4,	3,	0,	0,	SparcImpOpBase + 0,	35,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #656 = RETTri
    { 655,	0,	0,	4,	1,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #655 = RETRY
    { 654,	1,	0,	4,	3,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #654 = RETL
    { 653,	1,	0,	4,	3,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #653 = RET
    { 652,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	176,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #652 = RESTORErr
    { 651,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #651 = RESTOREri
    { 650,	0,	0,	4,	1,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #650 = RESTORED
    { 649,	1,	1,	4,	1,	1,	0,	SparcImpOpBase + 18,	389,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #649 = RDWIM
    { 648,	1,	1,	4,	1,	1,	0,	SparcImpOpBase + 17,	389,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #648 = RDTBR
    { 647,	1,	1,	4,	1,	1,	0,	SparcImpOpBase + 15,	389,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #647 = RDPSR
    { 646,	2,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	390,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #646 = RDPR
    { 645,	1,	1,	4,	1,	1,	0,	SparcImpOpBase + 16,	389,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #645 = RDFQ
    { 644,	2,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	387,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #644 = RDASR
    { 643,	2,	0,	4,	1,	0,	1,	SparcImpOpBase + 15,	375,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #643 = PWRPSRrr
    { 642,	2,	0,	4,	1,	0,	1,	SparcImpOpBase + 15,	168,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #642 = PWRPSRri
    { 641,	3,	0,	4,	1,	0,	0,	SparcImpOpBase + 0,	384,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #641 = PREFETCHr
    { 640,	3,	0,	4,	1,	0,	0,	SparcImpOpBase + 0,	377,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #640 = PREFETCHi
    { 639,	4,	0,	4,	0,	0,	0,	SparcImpOpBase + 0,	380,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #639 = PREFETCHAr
    { 638,	3,	0,	4,	1,	1,	0,	SparcImpOpBase + 8,	377,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #638 = PREFETCHAi
    { 637,	2,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	375,	0, 0x0ULL },  // Inst #637 = POPCrr
    { 636,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #636 = PDISTN
    { 635,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #635 = PDIST
    { 634,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	176,	0, 0x0ULL },  // Inst #634 = ORrr
    { 633,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	173,	0, 0x0ULL },  // Inst #633 = ORri
    { 632,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	176,	0, 0x0ULL },  // Inst #632 = ORNrr
    { 631,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #631 = ORNri
    { 630,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	176,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #630 = ORNCCrr
    { 629,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #629 = ORNCCri
    { 628,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	176,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #628 = ORCCrr
    { 627,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #627 = ORCCri
    { 626,	0,	0,	4,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #626 = NOP
    { 625,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	179,	0, 0x0ULL },  // Inst #625 = MULXrr
    { 624,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	173,	0, 0x0ULL },  // Inst #624 = MULXri
    { 623,	3,	1,	4,	1,	2,	2,	SparcImpOpBase + 11,	176,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #623 = MULSCCrr
    { 622,	3,	1,	4,	1,	2,	2,	SparcImpOpBase + 11,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #622 = MULSCCri
    { 621,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	373,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #621 = MOVXTOD
    { 620,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 4,	359,	0, 0x0ULL },  // Inst #620 = MOVXCCrr
    { 619,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 4,	355,	0, 0x0ULL },  // Inst #619 = MOVXCCri
    { 618,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	373,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #618 = MOVWTOS
    { 617,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	353,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #617 = MOVSTOUW
    { 616,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	353,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #616 = MOVSTOSW
    { 615,	5,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	368,	0, 0x0ULL },  // Inst #615 = MOVRrr
    { 614,	5,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	363,	0, 0x0ULL },  // Inst #614 = MOVRri
    { 613,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 4,	359,	0, 0x0ULL },  // Inst #613 = MOVICCrr
    { 612,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 4,	355,	0, 0x0ULL },  // Inst #612 = MOVICCri
    { 611,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 3,	359,	0, 0x0ULL },  // Inst #611 = MOVFCCrr
    { 610,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 3,	355,	0, 0x0ULL },  // Inst #610 = MOVFCCri
    { 609,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	353,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #609 = MOVDTOX
    { 608,	1,	0,	4,	1,	0,	0,	SparcImpOpBase + 0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #608 = MEMBARi
    { 607,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	351,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #607 = LZCNT
    { 606,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	290,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #606 = LDrr
    { 605,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	287,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #605 = LDri
    { 604,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	348,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #604 = LDXrr
    { 603,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	345,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #603 = LDXri
    { 602,	2,	0,	4,	1,	0,	1,	SparcImpOpBase + 10,	182,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #602 = LDXFSRrr
    { 601,	2,	0,	4,	1,	0,	1,	SparcImpOpBase + 10,	35,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #601 = LDXFSRri
    { 600,	4,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	279,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #600 = LDXArr
    { 599,	3,	1,	4,	1,	1,	0,	SparcImpOpBase + 8,	345,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #599 = LDXAri
    { 598,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	290,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #598 = LDUHrr
    { 597,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	287,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #597 = LDUHri
    { 596,	4,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	283,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #596 = LDUHArr
    { 595,	3,	1,	4,	1,	1,	0,	SparcImpOpBase + 8,	287,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #595 = LDUHAri
    { 594,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	290,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #594 = LDUBrr
    { 593,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	287,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #593 = LDUBri
    { 592,	4,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	283,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #592 = LDUBArr
    { 591,	3,	1,	4,	1,	1,	0,	SparcImpOpBase + 8,	287,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #591 = LDUBAri
    { 590,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	348,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #590 = LDSWrr
    { 589,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	345,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #589 = LDSWri
    { 588,	4,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	279,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #588 = LDSWArr
    { 587,	3,	1,	4,	1,	1,	0,	SparcImpOpBase + 8,	345,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #587 = LDSWAri
    { 586,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	290,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #586 = LDSTUBrr
    { 585,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	287,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #585 = LDSTUBri
    { 584,	4,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	283,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #584 = LDSTUBArr
    { 583,	3,	1,	4,	1,	1,	0,	SparcImpOpBase + 8,	287,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #583 = LDSTUBAri
    { 582,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	290,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #582 = LDSHrr
    { 581,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	287,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #581 = LDSHri
    { 580,	4,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	283,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #580 = LDSHArr
    { 579,	3,	1,	4,	1,	1,	0,	SparcImpOpBase + 8,	287,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #579 = LDSHAri
    { 578,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	290,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #578 = LDSBrr
    { 577,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	287,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #577 = LDSBri
    { 576,	4,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	283,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #576 = LDSBArr
    { 575,	3,	1,	4,	1,	1,	0,	SparcImpOpBase + 8,	287,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #575 = LDSBAri
    { 574,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	342,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #574 = LDQFrr
    { 573,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	335,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #573 = LDQFri
    { 572,	4,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	338,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #572 = LDQFArr
    { 571,	3,	1,	4,	1,	1,	0,	SparcImpOpBase + 8,	335,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #571 = LDQFAri
    { 570,	3,	1,	4,	15,	0,	0,	SparcImpOpBase + 0,	332,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #570 = LDFrr
    { 569,	3,	1,	4,	15,	0,	0,	SparcImpOpBase + 0,	325,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #569 = LDFri
    { 568,	2,	0,	4,	15,	0,	1,	SparcImpOpBase + 10,	182,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #568 = LDFSRrr
    { 567,	2,	0,	4,	15,	0,	1,	SparcImpOpBase + 10,	35,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #567 = LDFSRri
    { 566,	4,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	328,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #566 = LDFArr
    { 565,	3,	1,	4,	1,	1,	0,	SparcImpOpBase + 8,	325,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #565 = LDFAri
    { 564,	3,	1,	4,	14,	0,	0,	SparcImpOpBase + 0,	322,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #564 = LDDrr
    { 563,	3,	1,	4,	14,	0,	0,	SparcImpOpBase + 0,	299,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #563 = LDDri
    { 562,	3,	1,	4,	14,	0,	0,	SparcImpOpBase + 0,	319,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #562 = LDDFrr
    { 561,	3,	1,	4,	14,	0,	0,	SparcImpOpBase + 0,	312,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #561 = LDDFri
    { 560,	4,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	315,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #560 = LDDFArr
    { 559,	3,	1,	4,	1,	1,	0,	SparcImpOpBase + 8,	312,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #559 = LDDFAri
    { 558,	3,	1,	4,	14,	0,	0,	SparcImpOpBase + 0,	309,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #558 = LDDCrr
    { 557,	3,	1,	4,	14,	0,	0,	SparcImpOpBase + 0,	306,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #557 = LDDCri
    { 556,	4,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	302,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #556 = LDDArr
    { 555,	3,	1,	4,	1,	1,	0,	SparcImpOpBase + 8,	299,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #555 = LDDAri
    { 554,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	296,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #554 = LDCrr
    { 553,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	293,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #553 = LDCri
    { 552,	2,	0,	4,	1,	0,	1,	SparcImpOpBase + 9,	182,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #552 = LDCSRrr
    { 551,	2,	0,	4,	1,	0,	1,	SparcImpOpBase + 9,	35,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #551 = LDCSRri
    { 550,	4,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	283,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #550 = LDArr
    { 549,	3,	1,	4,	1,	1,	0,	SparcImpOpBase + 8,	287,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #549 = LDAri
    { 548,	3,	1,	4,	3,	0,	0,	SparcImpOpBase + 0,	290,	0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #548 = JMPLrr
    { 547,	3,	1,	4,	3,	0,	0,	SparcImpOpBase + 0,	287,	0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #547 = JMPLri
    { 546,	4,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	283,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #546 = GDOP_LDrr
    { 545,	4,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	279,	0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #545 = GDOP_LDXrr
    { 544,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	270,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #544 = FZEROS
    { 543,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	268,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #543 = FZERO
    { 542,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	230,	0, 0x0ULL },  // Inst #542 = FXTOS
    { 541,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	232,	0, 0x0ULL },  // Inst #541 = FXTOQ
    { 540,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	212,	0, 0x0ULL },  // Inst #540 = FXTOD
    { 539,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #539 = FXORS
    { 538,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #538 = FXOR
    { 537,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #537 = FXNORS
    { 536,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #536 = FXNOR
    { 535,	3,	1,	4,	5,	0,	0,	SparcImpOpBase + 0,	221,	0, 0x0ULL },  // Inst #535 = FSUBS
    { 534,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	218,	0, 0x0ULL },  // Inst #534 = FSUBQ
    { 533,	3,	1,	4,	5,	0,	0,	SparcImpOpBase + 0,	190,	0, 0x0ULL },  // Inst #533 = FSUBD
    { 532,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	234,	0, 0x0ULL },  // Inst #532 = FSTOX
    { 531,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	236,	0, 0x0ULL },  // Inst #531 = FSTOQ
    { 530,	2,	1,	4,	5,	0,	0,	SparcImpOpBase + 0,	216,	0, 0x0ULL },  // Inst #530 = FSTOI
    { 529,	2,	1,	4,	13,	0,	0,	SparcImpOpBase + 0,	234,	0, 0x0ULL },  // Inst #529 = FSTOD
    { 528,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #528 = FSRL32
    { 527,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #527 = FSRL16
    { 526,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	216,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #526 = FSRC2S
    { 525,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	212,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #525 = FSRC2
    { 524,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	216,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #524 = FSRC1S
    { 523,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	212,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #523 = FSRC1
    { 522,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #522 = FSRA32
    { 521,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #521 = FSRA16
    { 520,	2,	1,	4,	12,	0,	0,	SparcImpOpBase + 0,	216,	0, 0x0ULL },  // Inst #520 = FSQRTS
    { 519,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	214,	0, 0x0ULL },  // Inst #519 = FSQRTQ
    { 518,	2,	1,	4,	11,	0,	0,	SparcImpOpBase + 0,	212,	0, 0x0ULL },  // Inst #518 = FSQRTD
    { 517,	3,	1,	4,	8,	0,	0,	SparcImpOpBase + 0,	276,	0, 0x0ULL },  // Inst #517 = FSMULD
    { 516,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #516 = FSLL32
    { 515,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #515 = FSLL16
    { 514,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #514 = FSLAS32
    { 513,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #513 = FSLAS16
    { 512,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	272,	0, 0x0ULL },  // Inst #512 = FQTOX
    { 511,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	274,	0, 0x0ULL },  // Inst #511 = FQTOS
    { 510,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	274,	0, 0x0ULL },  // Inst #510 = FQTOI
    { 509,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	272,	0, 0x0ULL },  // Inst #509 = FQTOD
    { 508,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #508 = FPSUB32S
    { 507,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #507 = FPSUB32
    { 506,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #506 = FPSUB16S
    { 505,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #505 = FPSUB16
    { 504,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #504 = FPMERGE
    { 503,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #503 = FPADD64
    { 502,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #502 = FPADD32S
    { 501,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #501 = FPADD32
    { 500,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #500 = FPADD16S
    { 499,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #499 = FPADD16
    { 498,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	212,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #498 = FPACKFIX
    { 497,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #497 = FPACK32
    { 496,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	212,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #496 = FPACK16
    { 495,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #495 = FORS
    { 494,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #494 = FORNOT2S
    { 493,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #493 = FORNOT2
    { 492,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #492 = FORNOT1S
    { 491,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #491 = FORNOT1
    { 490,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #490 = FOR
    { 489,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	270,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #489 = FONES
    { 488,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	268,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #488 = FONE
    { 487,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #487 = FNSMULD
    { 486,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	216,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #486 = FNOT2S
    { 485,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	212,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #485 = FNOT2
    { 484,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	216,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #484 = FNOT1S
    { 483,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	212,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #483 = FNOT1
    { 482,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #482 = FNORS
    { 481,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #481 = FNOR
    { 480,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #480 = FNMULS
    { 479,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #479 = FNMULD
    { 478,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #478 = FNHADDS
    { 477,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #477 = FNHADDD
    { 476,	2,	1,	4,	10,	0,	0,	SparcImpOpBase + 0,	216,	0, 0x0ULL },  // Inst #476 = FNEGS
    { 475,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	214,	0, 0x0ULL },  // Inst #475 = FNEGQ
    { 474,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	212,	0, 0x0ULL },  // Inst #474 = FNEGD
    { 473,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #473 = FNANDS
    { 472,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #472 = FNAND
    { 471,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #471 = FNADDS
    { 470,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #470 = FNADDD
    { 469,	3,	1,	4,	9,	0,	0,	SparcImpOpBase + 0,	221,	0, 0x0ULL },  // Inst #469 = FMULS
    { 468,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	218,	0, 0x0ULL },  // Inst #468 = FMULQ
    { 467,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #467 = FMULD8ULX16
    { 466,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #466 = FMULD8SUX16
    { 465,	3,	1,	4,	8,	0,	0,	SparcImpOpBase + 0,	190,	0, 0x0ULL },  // Inst #465 = FMULD
    { 464,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #464 = FMUL8X16AU
    { 463,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #463 = FMUL8X16AL
    { 462,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #462 = FMUL8X16
    { 461,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #461 = FMUL8ULX16
    { 460,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #460 = FMUL8SUX16
    { 459,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 4,	264,	0, 0x0ULL },  // Inst #459 = FMOVS_XCC
    { 458,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 4,	264,	0, 0x0ULL },  // Inst #458 = FMOVS_ICC
    { 457,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 3,	264,	0, 0x0ULL },  // Inst #457 = FMOVS_FCC
    { 456,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	216,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #456 = FMOVS
    { 455,	5,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	259,	0, 0x0ULL },  // Inst #455 = FMOVRS
    { 454,	5,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	254,	0, 0x0ULL },  // Inst #454 = FMOVRQ
    { 453,	5,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	249,	0, 0x0ULL },  // Inst #453 = FMOVRD
    { 452,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 4,	245,	0, 0x0ULL },  // Inst #452 = FMOVQ_XCC
    { 451,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 4,	245,	0, 0x0ULL },  // Inst #451 = FMOVQ_ICC
    { 450,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 3,	245,	0, 0x0ULL },  // Inst #450 = FMOVQ_FCC
    { 449,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	214,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #449 = FMOVQ
    { 448,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 4,	241,	0, 0x0ULL },  // Inst #448 = FMOVD_XCC
    { 447,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 4,	241,	0, 0x0ULL },  // Inst #447 = FMOVD_ICC
    { 446,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 3,	241,	0, 0x0ULL },  // Inst #446 = FMOVD_FCC
    { 445,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	212,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #445 = FMOVD
    { 444,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #444 = FMEAN16
    { 443,	2,	0,	4,	1,	0,	0,	SparcImpOpBase + 0,	182,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #443 = FLUSHrr
    { 442,	2,	0,	4,	1,	0,	0,	SparcImpOpBase + 0,	35,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #442 = FLUSHri
    { 441,	0,	0,	4,	1,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #441 = FLUSHW
    { 440,	0,	0,	4,	1,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #440 = FLUSH
    { 439,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	238,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #439 = FLCMPS
    { 438,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	238,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #438 = FLCMPD
    { 437,	2,	1,	4,	5,	0,	0,	SparcImpOpBase + 0,	216,	0, 0x0ULL },  // Inst #437 = FITOS
    { 436,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	236,	0, 0x0ULL },  // Inst #436 = FITOQ
    { 435,	2,	1,	4,	5,	0,	0,	SparcImpOpBase + 0,	234,	0, 0x0ULL },  // Inst #435 = FITOD
    { 434,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #434 = FHSUBS
    { 433,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #433 = FHSUBD
    { 432,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #432 = FHADDS
    { 431,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #431 = FHADDD
    { 430,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	212,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #430 = FEXPAND
    { 429,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	212,	0, 0x0ULL },  // Inst #429 = FDTOX
    { 428,	2,	1,	4,	5,	0,	0,	SparcImpOpBase + 0,	230,	0, 0x0ULL },  // Inst #428 = FDTOS
    { 427,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	232,	0, 0x0ULL },  // Inst #427 = FDTOQ
    { 426,	2,	1,	4,	5,	0,	0,	SparcImpOpBase + 0,	230,	0, 0x0ULL },  // Inst #426 = FDTOI
    { 425,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	227,	0, 0x0ULL },  // Inst #425 = FDMULQ
    { 424,	3,	1,	4,	7,	0,	0,	SparcImpOpBase + 0,	221,	0, 0x0ULL },  // Inst #424 = FDIVS
    { 423,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	218,	0, 0x0ULL },  // Inst #423 = FDIVQ
    { 422,	3,	1,	4,	6,	0,	0,	SparcImpOpBase + 0,	190,	0, 0x0ULL },  // Inst #422 = FDIVD
    { 421,	2,	0,	4,	5,	0,	1,	SparcImpOpBase + 3,	216,	0, 0x0ULL },  // Inst #421 = FCMPS_V9
    { 420,	2,	0,	4,	5,	0,	1,	SparcImpOpBase + 3,	216,	0, 0x0ULL },  // Inst #420 = FCMPS
    { 419,	2,	0,	4,	0,	0,	1,	SparcImpOpBase + 3,	214,	0, 0x0ULL },  // Inst #419 = FCMPQ_V9
    { 418,	2,	0,	4,	0,	0,	1,	SparcImpOpBase + 3,	214,	0, 0x0ULL },  // Inst #418 = FCMPQ
    { 417,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	224,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #417 = FCMPNE32
    { 416,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	224,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #416 = FCMPNE16
    { 415,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	224,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #415 = FCMPLE32
    { 414,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	224,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #414 = FCMPLE16
    { 413,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	224,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #413 = FCMPGT32
    { 412,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	224,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #412 = FCMPGT16
    { 411,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	224,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #411 = FCMPEQ32
    { 410,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	224,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #410 = FCMPEQ16
    { 409,	2,	0,	4,	5,	0,	1,	SparcImpOpBase + 3,	212,	0, 0x0ULL },  // Inst #409 = FCMPD_V9
    { 408,	2,	0,	4,	5,	0,	1,	SparcImpOpBase + 3,	212,	0, 0x0ULL },  // Inst #408 = FCMPD
    { 407,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #407 = FCHKSM16
    { 406,	2,	0,	4,	2,	1,	0,	SparcImpOpBase + 3,	13,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #406 = FBCOND_V9
    { 405,	2,	0,	4,	2,	1,	0,	SparcImpOpBase + 3,	13,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #405 = FBCONDA_V9
    { 404,	2,	0,	4,	2,	1,	0,	SparcImpOpBase + 3,	13,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #404 = FBCONDA
    { 403,	2,	0,	4,	2,	1,	0,	SparcImpOpBase + 3,	13,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #403 = FBCOND
    { 402,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #402 = FANDS
    { 401,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #401 = FANDNOT2S
    { 400,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #400 = FANDNOT2
    { 399,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #399 = FANDNOT1S
    { 398,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #398 = FANDNOT1
    { 397,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #397 = FAND
    { 396,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #396 = FALIGNADATA
    { 395,	3,	1,	4,	5,	0,	0,	SparcImpOpBase + 0,	221,	0, 0x0ULL },  // Inst #395 = FADDS
    { 394,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	218,	0, 0x0ULL },  // Inst #394 = FADDQ
    { 393,	3,	1,	4,	5,	0,	0,	SparcImpOpBase + 0,	190,	0, 0x0ULL },  // Inst #393 = FADDD
    { 392,	2,	1,	4,	4,	0,	0,	SparcImpOpBase + 0,	216,	0, 0x0ULL },  // Inst #392 = FABSS
    { 391,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	214,	0, 0x0ULL },  // Inst #391 = FABSQ
    { 390,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	212,	0, 0x0ULL },  // Inst #390 = FABSD
    { 389,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #389 = EDGE8N
    { 388,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #388 = EDGE8LN
    { 387,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #387 = EDGE8L
    { 386,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #386 = EDGE8
    { 385,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #385 = EDGE32N
    { 384,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #384 = EDGE32LN
    { 383,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #383 = EDGE32L
    { 382,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #382 = EDGE32
    { 381,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #381 = EDGE16N
    { 380,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #380 = EDGE16LN
    { 379,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #379 = EDGE16L
    { 378,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #378 = EDGE16
    { 377,	0,	0,	4,	1,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #377 = DONE
    { 376,	1,	0,	4,	0,	0,	0,	SparcImpOpBase + 0,	211,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #376 = CMASK8
    { 375,	1,	0,	4,	0,	0,	0,	SparcImpOpBase + 0,	211,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #375 = CMASK32
    { 374,	1,	0,	4,	0,	0,	0,	SparcImpOpBase + 0,	211,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #374 = CMASK16
    { 373,	2,	0,	4,	0,	0,	0,	SparcImpOpBase + 0,	13,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #373 = CBCONDA
    { 372,	2,	0,	4,	0,	0,	0,	SparcImpOpBase + 0,	13,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #372 = CBCOND
    { 371,	5,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	206,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #371 = CASXArr
    { 370,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 8,	202,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #370 = CASXAri
    { 369,	5,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	197,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #369 = CASArr
    { 368,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 8,	193,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #368 = CASAri
    { 367,	2,	0,	4,	3,	1,	0,	SparcImpOpBase + 7,	182,	0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #367 = CALLrr
    { 366,	2,	0,	4,	3,	1,	0,	SparcImpOpBase + 7,	35,	0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #366 = CALLri
    { 365,	1,	0,	4,	3,	1,	0,	SparcImpOpBase + 7,	0,	0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #365 = CALL
    { 364,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	190,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #364 = BSHUFFLE
    { 363,	2,	0,	4,	1,	1,	0,	SparcImpOpBase + 4,	13,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #363 = BPXCCNT
    { 362,	2,	0,	4,	1,	1,	0,	SparcImpOpBase + 4,	13,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #362 = BPXCCANT
    { 361,	2,	0,	4,	1,	1,	0,	SparcImpOpBase + 4,	13,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #361 = BPXCCA
    { 360,	2,	0,	4,	1,	1,	0,	SparcImpOpBase + 4,	13,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #360 = BPXCC
    { 359,	3,	0,	4,	0,	0,	0,	SparcImpOpBase + 0,	187,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #359 = BPRNT
    { 358,	3,	0,	4,	0,	0,	0,	SparcImpOpBase + 0,	187,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #358 = BPRANT
    { 357,	3,	0,	4,	0,	0,	0,	SparcImpOpBase + 0,	187,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #357 = BPRA
    { 356,	3,	0,	4,	0,	0,	0,	SparcImpOpBase + 0,	187,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #356 = BPR
    { 355,	2,	0,	4,	1,	1,	0,	SparcImpOpBase + 4,	13,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #355 = BPICCNT
    { 354,	2,	0,	4,	1,	1,	0,	SparcImpOpBase + 4,	13,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #354 = BPICCANT
    { 353,	2,	0,	4,	1,	1,	0,	SparcImpOpBase + 4,	13,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #353 = BPICCA
    { 352,	2,	0,	4,	1,	1,	0,	SparcImpOpBase + 4,	13,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #352 = BPICC
    { 351,	3,	0,	4,	2,	0,	0,	SparcImpOpBase + 0,	184,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #351 = BPFCCNT
    { 350,	3,	0,	4,	2,	0,	0,	SparcImpOpBase + 0,	184,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #350 = BPFCCANT
    { 349,	3,	0,	4,	2,	0,	0,	SparcImpOpBase + 0,	184,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #349 = BPFCCA
    { 348,	3,	0,	4,	2,	0,	0,	SparcImpOpBase + 0,	184,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #348 = BPFCC
    { 347,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #347 = BMASK
    { 346,	2,	0,	4,	1,	0,	0,	SparcImpOpBase + 0,	182,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #346 = BINDrr
    { 345,	2,	0,	4,	1,	0,	0,	SparcImpOpBase + 0,	35,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #345 = BINDri
    { 344,	2,	0,	4,	1,	1,	0,	SparcImpOpBase + 4,	13,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #344 = BCONDA
    { 343,	2,	0,	4,	1,	1,	0,	SparcImpOpBase + 4,	13,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #343 = BCOND
    { 342,	1,	0,	4,	0,	0,	0,	SparcImpOpBase + 0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #342 = BA
    { 341,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #341 = ARRAY8
    { 340,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #340 = ARRAY32
    { 339,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #339 = ARRAY16
    { 338,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	176,	0, 0x0ULL },  // Inst #338 = ANDrr
    { 337,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	173,	0, 0x0ULL },  // Inst #337 = ANDri
    { 336,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	176,	0, 0x0ULL },  // Inst #336 = ANDNrr
    { 335,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #335 = ANDNri
    { 334,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	176,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #334 = ANDNCCrr
    { 333,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #333 = ANDNCCri
    { 332,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	176,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #332 = ANDCCrr
    { 331,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #331 = ANDCCri
    { 330,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #330 = ALIGNADDRL
    { 329,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #329 = ALIGNADDR
    { 328,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	176,	0, 0x0ULL },  // Inst #328 = ADDrr
    { 327,	3,	1,	4,	1,	0,	0,	SparcImpOpBase + 0,	173,	0, 0x0ULL },  // Inst #327 = ADDri
    { 326,	3,	1,	4,	0,	1,	1,	SparcImpOpBase + 5,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #326 = ADDXCCC
    { 325,	3,	1,	4,	0,	1,	0,	SparcImpOpBase + 4,	179,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #325 = ADDXC
    { 324,	3,	1,	4,	1,	1,	1,	SparcImpOpBase + 5,	176,	0, 0x0ULL },  // Inst #324 = ADDErr
    { 323,	3,	1,	4,	1,	1,	1,	SparcImpOpBase + 5,	173,	0, 0x0ULL },  // Inst #323 = ADDEri
    { 322,	3,	1,	4,	1,	1,	0,	SparcImpOpBase + 4,	176,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #322 = ADDCrr
    { 321,	3,	1,	4,	1,	1,	0,	SparcImpOpBase + 4,	173,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #321 = ADDCri
    { 320,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	176,	0, 0x0ULL },  // Inst #320 = ADDCCrr
    { 319,	3,	1,	4,	1,	0,	1,	SparcImpOpBase + 4,	173,	0, 0x0ULL },  // Inst #319 = ADDCCri
    { 318,	3,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	170,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #318 = SETX
    { 317,	2,	1,	4,	0,	0,	0,	SparcImpOpBase + 0,	168,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #317 = SET
    { 316,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 4,	164,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #316 = SELECT_CC_QFP_XCC
    { 315,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 4,	164,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #315 = SELECT_CC_QFP_ICC
    { 314,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 3,	164,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #314 = SELECT_CC_QFP_FCC
    { 313,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 4,	160,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #313 = SELECT_CC_Int_XCC
    { 312,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 4,	160,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #312 = SELECT_CC_Int_ICC
    { 311,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 3,	160,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #311 = SELECT_CC_Int_FCC
    { 310,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 4,	156,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #310 = SELECT_CC_FP_XCC
    { 309,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 4,	156,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #309 = SELECT_CC_FP_ICC
    { 308,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 3,	156,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #308 = SELECT_CC_FP_FCC
    { 307,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 4,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #307 = SELECT_CC_DFP_XCC
    { 306,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 4,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #306 = SELECT_CC_DFP_ICC
    { 305,	4,	1,	4,	0,	1,	0,	SparcImpOpBase + 3,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #305 = SELECT_CC_DFP_FCC
    { 304,	1,	1,	4,	0,	0,	1,	SparcImpOpBase + 2,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #304 = GETPCX
    { 303,	2,	0,	4,	0,	1,	1,	SparcImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #303 = ADJCALLSTACKUP
    { 302,	2,	0,	4,	0,	1,	1,	SparcImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #302 = ADJCALLSTACKDOWN
    { 301,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #301 = G_UBFX
    { 300,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #300 = G_SBFX
    { 299,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #299 = G_VECREDUCE_UMIN
    { 298,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #298 = G_VECREDUCE_UMAX
    { 297,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #297 = G_VECREDUCE_SMIN
    { 296,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #296 = G_VECREDUCE_SMAX
    { 295,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #295 = G_VECREDUCE_XOR
    { 294,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #294 = G_VECREDUCE_OR
    { 293,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #293 = G_VECREDUCE_AND
    { 292,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #292 = G_VECREDUCE_MUL
    { 291,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #291 = G_VECREDUCE_ADD
    { 290,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #290 = G_VECREDUCE_FMINIMUM
    { 289,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #289 = G_VECREDUCE_FMAXIMUM
    { 288,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #288 = G_VECREDUCE_FMIN
    { 287,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #287 = G_VECREDUCE_FMAX
    { 286,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #286 = G_VECREDUCE_FMUL
    { 285,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #285 = G_VECREDUCE_FADD
    { 284,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #284 = G_VECREDUCE_SEQ_FMUL
    { 283,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #283 = G_VECREDUCE_SEQ_FADD
    { 282,	1,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #282 = G_UBSANTRAP
    { 281,	0,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #281 = G_DEBUGTRAP
    { 280,	0,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #280 = G_TRAP
    { 279,	3,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #279 = G_BZERO
    { 278,	4,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #278 = G_MEMSET
    { 277,	4,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #277 = G_MEMMOVE
    { 276,	3,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #276 = G_MEMCPY_INLINE
    { 275,	4,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #275 = G_MEMCPY
    { 274,	2,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	142,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #274 = G_WRITE_REGISTER
    { 273,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #273 = G_READ_REGISTER
    { 272,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #272 = G_STRICT_FLDEXP
    { 271,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #271 = G_STRICT_FSQRT
    { 270,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #270 = G_STRICT_FMA
    { 269,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #269 = G_STRICT_FREM
    { 268,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #268 = G_STRICT_FDIV
    { 267,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #267 = G_STRICT_FMUL
    { 266,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #266 = G_STRICT_FSUB
    { 265,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #265 = G_STRICT_FADD
    { 264,	1,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #264 = G_STACKRESTORE
    { 263,	1,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #263 = G_STACKSAVE
    { 262,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #262 = G_DYN_STACKALLOC
    { 261,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #261 = G_JUMP_TABLE
    { 260,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #260 = G_BLOCK_ADDR
    { 259,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #259 = G_ADDRSPACE_CAST
    { 258,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #258 = G_FNEARBYINT
    { 257,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #257 = G_FRINT
    { 256,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #256 = G_FFLOOR
    { 255,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #255 = G_FSQRT
    { 254,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #254 = G_FTANH
    { 253,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #253 = G_FSINH
    { 252,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #252 = G_FCOSH
    { 251,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #251 = G_FATAN2
    { 250,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #250 = G_FATAN
    { 249,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #249 = G_FASIN
    { 248,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #248 = G_FACOS
    { 247,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #247 = G_FTAN
    { 246,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #246 = G_FSIN
    { 245,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #245 = G_FCOS
    { 244,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #244 = G_FCEIL
    { 243,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #243 = G_BITREVERSE
    { 242,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #242 = G_BSWAP
    { 241,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #241 = G_CTPOP
    { 240,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #240 = G_CTLZ_ZERO_UNDEF
    { 239,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #239 = G_CTLZ
    { 238,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #238 = G_CTTZ_ZERO_UNDEF
    { 237,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #237 = G_CTTZ
    { 236,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	138,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #236 = G_VECTOR_COMPRESS
    { 235,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #235 = G_SPLAT_VECTOR
    { 234,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	134,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #234 = G_SHUFFLE_VECTOR
    { 233,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #233 = G_EXTRACT_VECTOR_ELT
    { 232,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	127,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #232 = G_INSERT_VECTOR_ELT
    { 231,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #231 = G_EXTRACT_SUBVECTOR
    { 230,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #230 = G_INSERT_SUBVECTOR
    { 229,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #229 = G_VSCALE
    { 228,	3,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	124,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #228 = G_BRJT
    { 227,	1,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #227 = G_BR
    { 226,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #226 = G_LLROUND
    { 225,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #225 = G_LROUND
    { 224,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #224 = G_ABS
    { 223,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #223 = G_UMAX
    { 222,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #222 = G_UMIN
    { 221,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #221 = G_SMAX
    { 220,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #220 = G_SMIN
    { 219,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #219 = G_PTRMASK
    { 218,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #218 = G_PTR_ADD
    { 217,	0,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #217 = G_RESET_FPMODE
    { 216,	1,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #216 = G_SET_FPMODE
    { 215,	1,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #215 = G_GET_FPMODE
    { 214,	0,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #214 = G_RESET_FPENV
    { 213,	1,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #213 = G_SET_FPENV
    { 212,	1,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #212 = G_GET_FPENV
    { 211,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #211 = G_FMAXIMUM
    { 210,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #210 = G_FMINIMUM
    { 209,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #209 = G_FMAXNUM_IEEE
    { 208,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #208 = G_FMINNUM_IEEE
    { 207,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #207 = G_FMAXNUM
    { 206,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #206 = G_FMINNUM
    { 205,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #205 = G_FCANONICALIZE
    { 204,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #204 = G_IS_FPCLASS
    { 203,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #203 = G_FCOPYSIGN
    { 202,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #202 = G_FABS
    { 201,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #201 = G_FPTOUI_SAT
    { 200,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #200 = G_FPTOSI_SAT
    { 199,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #199 = G_UITOFP
    { 198,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #198 = G_SITOFP
    { 197,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #197 = G_FPTOUI
    { 196,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #196 = G_FPTOSI
    { 195,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #195 = G_FPTRUNC
    { 194,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #194 = G_FPEXT
    { 193,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #193 = G_FNEG
    { 192,	3,	2,	0,	0,	0,	0,	SparcImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #192 = G_FFREXP
    { 191,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #191 = G_FLDEXP
    { 190,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #190 = G_FLOG10
    { 189,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #189 = G_FLOG2
    { 188,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #188 = G_FLOG
    { 187,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #187 = G_FEXP10
    { 186,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #186 = G_FEXP2
    { 185,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #185 = G_FEXP
    { 184,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #184 = G_FPOWI
    { 183,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #183 = G_FPOW
    { 182,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #182 = G_FREM
    { 181,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #181 = G_FDIV
    { 180,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #180 = G_FMAD
    { 179,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #179 = G_FMA
    { 178,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #178 = G_FMUL
    { 177,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #177 = G_FSUB
    { 176,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #176 = G_FADD
    { 175,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #175 = G_UDIVFIXSAT
    { 174,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #174 = G_SDIVFIXSAT
    { 173,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #173 = G_UDIVFIX
    { 172,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #172 = G_SDIVFIX
    { 171,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #171 = G_UMULFIXSAT
    { 170,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #170 = G_SMULFIXSAT
    { 169,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #169 = G_UMULFIX
    { 168,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #168 = G_SMULFIX
    { 167,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #167 = G_SSHLSAT
    { 166,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #166 = G_USHLSAT
    { 165,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #165 = G_SSUBSAT
    { 164,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #164 = G_USUBSAT
    { 163,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #163 = G_SADDSAT
    { 162,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #162 = G_UADDSAT
    { 161,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #161 = G_SMULH
    { 160,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #160 = G_UMULH
    { 159,	4,	2,	0,	0,	0,	0,	SparcImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #159 = G_SMULO
    { 158,	4,	2,	0,	0,	0,	0,	SparcImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #158 = G_UMULO
    { 157,	5,	2,	0,	0,	0,	0,	SparcImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #157 = G_SSUBE
    { 156,	4,	2,	0,	0,	0,	0,	SparcImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #156 = G_SSUBO
    { 155,	5,	2,	0,	0,	0,	0,	SparcImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #155 = G_SADDE
    { 154,	4,	2,	0,	0,	0,	0,	SparcImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #154 = G_SADDO
    { 153,	5,	2,	0,	0,	0,	0,	SparcImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #153 = G_USUBE
    { 152,	4,	2,	0,	0,	0,	0,	SparcImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #152 = G_USUBO
    { 151,	5,	2,	0,	0,	0,	0,	SparcImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #151 = G_UADDE
    { 150,	4,	2,	0,	0,	0,	0,	SparcImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #150 = G_UADDO
    { 149,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #149 = G_SELECT
    { 148,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #148 = G_UCMP
    { 147,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #147 = G_SCMP
    { 146,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #146 = G_FCMP
    { 145,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #145 = G_ICMP
    { 144,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #144 = G_ROTL
    { 143,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #143 = G_ROTR
    { 142,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #142 = G_FSHR
    { 141,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #141 = G_FSHL
    { 140,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #140 = G_ASHR
    { 139,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #139 = G_LSHR
    { 138,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #138 = G_SHL
    { 137,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #137 = G_ZEXT
    { 136,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #136 = G_SEXT_INREG
    { 135,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #135 = G_SEXT
    { 134,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #134 = G_VAARG
    { 133,	1,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #133 = G_VASTART
    { 132,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #132 = G_FCONSTANT
    { 131,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #131 = G_CONSTANT
    { 130,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #130 = G_TRUNC
    { 129,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #129 = G_ANYEXT
    { 128,	1,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #128 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
    { 127,	1,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #127 = G_INTRINSIC_CONVERGENT
    { 126,	1,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #126 = G_INTRINSIC_W_SIDE_EFFECTS
    { 125,	1,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #125 = G_INTRINSIC
    { 124,	0,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #124 = G_INVOKE_REGION_START
    { 123,	1,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #123 = G_BRINDIRECT
    { 122,	2,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #122 = G_BRCOND
    { 121,	4,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	94,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #121 = G_PREFETCH
    { 120,	2,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	21,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #120 = G_FENCE
    { 119,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #119 = G_ATOMICRMW_USUB_SAT
    { 118,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #118 = G_ATOMICRMW_USUB_COND
    { 117,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #117 = G_ATOMICRMW_UDEC_WRAP
    { 116,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #116 = G_ATOMICRMW_UINC_WRAP
    { 115,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #115 = G_ATOMICRMW_FMIN
    { 114,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #114 = G_ATOMICRMW_FMAX
    { 113,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #113 = G_ATOMICRMW_FSUB
    { 112,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #112 = G_ATOMICRMW_FADD
    { 111,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #111 = G_ATOMICRMW_UMIN
    { 110,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #110 = G_ATOMICRMW_UMAX
    { 109,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #109 = G_ATOMICRMW_MIN
    { 108,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #108 = G_ATOMICRMW_MAX
    { 107,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #107 = G_ATOMICRMW_XOR
    { 106,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #106 = G_ATOMICRMW_OR
    { 105,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #105 = G_ATOMICRMW_NAND
    { 104,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #104 = G_ATOMICRMW_AND
    { 103,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #103 = G_ATOMICRMW_SUB
    { 102,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #102 = G_ATOMICRMW_ADD
    { 101,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #101 = G_ATOMICRMW_XCHG
    { 100,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #100 = G_ATOMIC_CMPXCHG
    { 99,	5,	2,	0,	0,	0,	0,	SparcImpOpBase + 0,	82,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #99 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
    { 98,	5,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	77,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #98 = G_INDEXED_STORE
    { 97,	2,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #97 = G_STORE
    { 96,	5,	2,	0,	0,	0,	0,	SparcImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #96 = G_INDEXED_ZEXTLOAD
    { 95,	5,	2,	0,	0,	0,	0,	SparcImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #95 = G_INDEXED_SEXTLOAD
    { 94,	5,	2,	0,	0,	0,	0,	SparcImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #94 = G_INDEXED_LOAD
    { 93,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #93 = G_ZEXTLOAD
    { 92,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #92 = G_SEXTLOAD
    { 91,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #91 = G_LOAD
    { 90,	1,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #90 = G_READSTEADYCOUNTER
    { 89,	1,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #89 = G_READCYCLECOUNTER
    { 88,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #88 = G_INTRINSIC_ROUNDEVEN
    { 87,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #87 = G_INTRINSIC_LLRINT
    { 86,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #86 = G_INTRINSIC_LRINT
    { 85,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #85 = G_INTRINSIC_ROUND
    { 84,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #84 = G_INTRINSIC_TRUNC
    { 83,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #83 = G_INTRINSIC_FPTRUNC_ROUND
    { 82,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #82 = G_CONSTANT_FOLD_BARRIER
    { 81,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #81 = G_FREEZE
    { 80,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #80 = G_BITCAST
    { 79,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #79 = G_INTTOPTR
    { 78,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #78 = G_PTRTOINT
    { 77,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #77 = G_CONCAT_VECTORS
    { 76,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #76 = G_BUILD_VECTOR_TRUNC
    { 75,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #75 = G_BUILD_VECTOR
    { 74,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #74 = G_MERGE_VALUES
    { 73,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #73 = G_INSERT
    { 72,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #72 = G_UNMERGE_VALUES
    { 71,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #71 = G_EXTRACT
    { 70,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #70 = G_CONSTANT_POOL
    { 69,	5,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	53,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #69 = G_PTRAUTH_GLOBAL_VALUE
    { 68,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #68 = G_GLOBAL_VALUE
    { 67,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #67 = G_FRAME_INDEX
    { 66,	1,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #66 = G_PHI
    { 65,	1,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #65 = G_IMPLICIT_DEF
    { 64,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #64 = G_XOR
    { 63,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #63 = G_OR
    { 62,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #62 = G_AND
    { 61,	4,	2,	0,	0,	0,	0,	SparcImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #61 = G_UDIVREM
    { 60,	4,	2,	0,	0,	0,	0,	SparcImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #60 = G_SDIVREM
    { 59,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #59 = G_UREM
    { 58,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #58 = G_SREM
    { 57,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #57 = G_UDIV
    { 56,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #56 = G_SDIV
    { 55,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #55 = G_MUL
    { 54,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #54 = G_SUB
    { 53,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #53 = G_ADD
    { 52,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #52 = G_ASSERT_ALIGN
    { 51,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #51 = G_ASSERT_ZEXT
    { 50,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #50 = G_ASSERT_SEXT
    { 49,	1,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #49 = CONVERGENCECTRL_GLUE
    { 48,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #48 = CONVERGENCECTRL_LOOP
    { 47,	1,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #47 = CONVERGENCECTRL_ANCHOR
    { 46,	1,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #46 = CONVERGENCECTRL_ENTRY
    { 45,	1,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // Inst #45 = JUMP_TABLE_DEBUG_INFO
    { 44,	0,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #44 = MEMBARRIER
    { 43,	0,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #43 = FAKE_USE
    { 42,	0,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #42 = ICALL_BRANCH_FUNNEL
    { 41,	3,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	37,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #41 = PATCHABLE_TYPED_EVENT_CALL
    { 40,	2,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	35,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #40 = PATCHABLE_EVENT_CALL
    { 39,	0,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #39 = PATCHABLE_TAIL_CALL
    { 38,	0,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #38 = PATCHABLE_FUNCTION_EXIT
    { 37,	0,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #37 = PATCHABLE_RET
    { 36,	0,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #36 = PATCHABLE_FUNCTION_ENTER
    { 35,	0,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #35 = PATCHABLE_OP
    { 34,	1,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #34 = FAULTING_OP
    { 33,	2,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	33,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #33 = LOCAL_ESCAPE
    { 32,	0,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #32 = STATEPOINT
    { 31,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	30,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #31 = PREALLOCATED_ARG
    { 30,	1,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #30 = PREALLOCATED_SETUP
    { 29,	1,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	29,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL },  // Inst #29 = LOAD_STACK_GUARD
    { 28,	6,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	23,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #28 = PATCHPOINT
    { 27,	0,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #27 = FENTRY_CALL
    { 26,	2,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #26 = STACKMAP
    { 25,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	19,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // Inst #25 = ARITH_FENCE
    { 24,	4,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	15,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #24 = PSEUDO_PROBE
    { 23,	1,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // Inst #23 = LIFETIME_END
    { 22,	1,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // Inst #22 = LIFETIME_START
    { 21,	0,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #21 = BUNDLE
    { 20,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // Inst #20 = COPY
    { 19,	2,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // Inst #19 = REG_SEQUENCE
    { 18,	1,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // Inst #18 = DBG_LABEL
    { 17,	0,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #17 = DBG_PHI
    { 16,	0,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #16 = DBG_INSTR_REF
    { 15,	0,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #15 = DBG_VALUE_LIST
    { 14,	0,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #14 = DBG_VALUE
    { 13,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // Inst #13 = COPY_TO_REGCLASS
    { 12,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	9,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #12 = SUBREG_TO_REG
    { 11,	1,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #11 = INIT_UNDEF
    { 10,	1,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // Inst #10 = IMPLICIT_DEF
    { 9,	4,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	5,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #9 = INSERT_SUBREG
    { 8,	3,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #8 = EXTRACT_SUBREG
    { 7,	0,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #7 = KILL
    { 6,	1,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL },  // Inst #6 = ANNOTATION_LABEL
    { 5,	1,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL },  // Inst #5 = GC_LABEL
    { 4,	1,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL },  // Inst #4 = EH_LABEL
    { 3,	1,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL },  // Inst #3 = CFI_INSTRUCTION
    { 2,	0,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #2 = INLINEASM_BR
    { 1,	0,	0,	0,	0,	0,	0,	SparcImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #1 = INLINEASM
    { 0,	1,	1,	0,	0,	0,	0,	SparcImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #0 = PHI
  }, {
    /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 1 */
    /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
    /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
    /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 152 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 156 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 160 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 164 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 168 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 170 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 173 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 176 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 179 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 182 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
    /* 184 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 187 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 190 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 193 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
    /* 197 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 202 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
    /* 206 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 211 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 212 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 214 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 216 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 218 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 221 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 224 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 227 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 230 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 232 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 234 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 236 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 238 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 241 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 245 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 249 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 254 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 259 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 264 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 268 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
    /* 270 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
    /* 272 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 274 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 276 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 279 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 283 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 287 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 290 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
    /* 293 */ { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 296 */ { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
    /* 299 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 302 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 306 */ { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 309 */ { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
    /* 312 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 315 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 319 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
    /* 322 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
    /* 325 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 328 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 332 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
    /* 335 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 338 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 342 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
    /* 345 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 348 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
    /* 351 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 353 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 355 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 359 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 363 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 368 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 373 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 375 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 377 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 380 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 384 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 387 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 389 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 390 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 392 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 395 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 398 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 401 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 405 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 409 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 412 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 416 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 419 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 422 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 425 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 428 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 432 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 435 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 438 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 441 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 445 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 448 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 451 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 454 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 458 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 461 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 464 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 468 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 471 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 474 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 478 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 481 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
    /* 485 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
    /* 490 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
    /* 494 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 497 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 501 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 504 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 507 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 512 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 517 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 522 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 527 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 532 */ { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 535 */ { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 538 */ { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 541 */ { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
  }, {
    /* 0 */
    /* 0 */ SP::O6, SP::O6,
    /* 2 */ SP::O7,
    /* 3 */ SP::FCC0,
    /* 4 */ SP::ICC,
    /* 5 */ SP::ICC, SP::ICC,
    /* 7 */ SP::O6,
    /* 8 */ SP::ASR3,
    /* 9 */ SP::CPSR,
    /* 10 */ SP::FSR,
    /* 11 */ SP::Y, SP::ICC, SP::Y, SP::ICC,
    /* 15 */ SP::PSR,
    /* 16 */ SP::FQ,
    /* 17 */ SP::TBR,
    /* 18 */ SP::WIM,
    /* 19 */ SP::Y, SP::Y, SP::ICC,
    /* 22 */ SP::Y, SP::Y,
    /* 24 */ SP::Y, SP::ASR18, SP::Y, SP::ASR18,
    /* 28 */ SP::Y, SP::ICC,
    /* 30 */ SP::Y,
    /* 31 */ SP::CPQ,
  }
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char SparcInstrNameData[] = {
  /* 0 */ "G_FLOG10\0"
  /* 9 */ "G_FEXP10\0"
  /* 18 */ "TA1\0"
  /* 22 */ "FSRC1\0"
  /* 28 */ "FANDNOT1\0"
  /* 37 */ "FNOT1\0"
  /* 43 */ "FORNOT1\0"
  /* 51 */ "FSRA32\0"
  /* 58 */ "FPSUB32\0"
  /* 66 */ "FPADD32\0"
  /* 74 */ "EDGE32\0"
  /* 81 */ "FCMPLE32\0"
  /* 90 */ "FCMPNE32\0"
  /* 99 */ "FPACK32\0"
  /* 107 */ "CMASK32\0"
  /* 115 */ "FSLL32\0"
  /* 122 */ "FSRL32\0"
  /* 129 */ "FCMPEQ32\0"
  /* 138 */ "FSLAS32\0"
  /* 146 */ "FCMPGT32\0"
  /* 155 */ "ARRAY32\0"
  /* 163 */ "FSRC2\0"
  /* 169 */ "G_FLOG2\0"
  /* 177 */ "G_FATAN2\0"
  /* 186 */ "G_FEXP2\0"
  /* 194 */ "FANDNOT2\0"
  /* 203 */ "FNOT2\0"
  /* 209 */ "FORNOT2\0"
  /* 217 */ "TA3\0"
  /* 221 */ "FPADD64\0"
  /* 229 */ "TA5\0"
  /* 233 */ "FSRA16\0"
  /* 240 */ "FPSUB16\0"
  /* 248 */ "FPADD16\0"
  /* 256 */ "EDGE16\0"
  /* 263 */ "FCMPLE16\0"
  /* 272 */ "FCMPNE16\0"
  /* 281 */ "FPACK16\0"
  /* 289 */ "CMASK16\0"
  /* 297 */ "FSLL16\0"
  /* 304 */ "FSRL16\0"
  /* 311 */ "FCHKSM16\0"
  /* 320 */ "FMEAN16\0"
  /* 328 */ "FCMPEQ16\0"
  /* 337 */ "FSLAS16\0"
  /* 345 */ "FCMPGT16\0"
  /* 354 */ "FMUL8X16\0"
  /* 363 */ "FMULD8ULX16\0"
  /* 375 */ "FMUL8ULX16\0"
  /* 386 */ "FMULD8SUX16\0"
  /* 398 */ "FMUL8SUX16\0"
  /* 409 */ "ARRAY16\0"
  /* 417 */ "EDGE8\0"
  /* 423 */ "CMASK8\0"
  /* 430 */ "ARRAY8\0"
  /* 437 */ "FBCONDA_V9\0"
  /* 448 */ "FBCOND_V9\0"
  /* 458 */ "FCMPD_V9\0"
  /* 467 */ "FCMPQ_V9\0"
  /* 476 */ "FCMPS_V9\0"
  /* 485 */ "BA\0"
  /* 488 */ "BPFCCA\0"
  /* 495 */ "BPICCA\0"
  /* 502 */ "BPXCCA\0"
  /* 509 */ "CBCONDA\0"
  /* 517 */ "FBCONDA\0"
  /* 525 */ "G_FMA\0"
  /* 531 */ "G_STRICT_FMA\0"
  /* 544 */ "BPRA\0"
  /* 549 */ "FALIGNADATA\0"
  /* 561 */ "G_FSUB\0"
  /* 568 */ "G_STRICT_FSUB\0"
  /* 582 */ "G_ATOMICRMW_FSUB\0"
  /* 599 */ "G_SUB\0"
  /* 605 */ "G_ATOMICRMW_SUB\0"
  /* 621 */ "ADDXCCC\0"
  /* 629 */ "BPFCC\0"
  /* 635 */ "V9FMOVD_FCC\0"
  /* 647 */ "SELECT_CC_DFP_FCC\0"
  /* 665 */ "SELECT_CC_QFP_FCC\0"
  /* 683 */ "SELECT_CC_FP_FCC\0"
  /* 700 */ "V9FMOVQ_FCC\0"
  /* 712 */ "V9FMOVS_FCC\0"
  /* 724 */ "SELECT_CC_Int_FCC\0"
  /* 742 */ "BPICC\0"
  /* 748 */ "FMOVD_ICC\0"
  /* 758 */ "SELECT_CC_DFP_ICC\0"
  /* 776 */ "SELECT_CC_QFP_ICC\0"
  /* 794 */ "SELECT_CC_FP_ICC\0"
  /* 811 */ "FMOVQ_ICC\0"
  /* 821 */ "FMOVS_ICC\0"
  /* 831 */ "SELECT_CC_Int_ICC\0"
  /* 849 */ "BPXCC\0"
  /* 855 */ "FMOVD_XCC\0"
  /* 865 */ "SELECT_CC_DFP_XCC\0"
  /* 883 */ "SELECT_CC_QFP_XCC\0"
  /* 901 */ "SELECT_CC_FP_XCC\0"
  /* 918 */ "FMOVQ_XCC\0"
  /* 928 */ "FMOVS_XCC\0"
  /* 938 */ "SELECT_CC_Int_XCC\0"
  /* 956 */ "G_INTRINSIC\0"
  /* 968 */ "G_FPTRUNC\0"
  /* 978 */ "G_INTRINSIC_TRUNC\0"
  /* 996 */ "G_TRUNC\0"
  /* 1004 */ "G_BUILD_VECTOR_TRUNC\0"
  /* 1025 */ "G_DYN_STACKALLOC\0"
  /* 1042 */ "ADDXC\0"
  /* 1048 */ "G_FMAD\0"
  /* 1055 */ "G_INDEXED_SEXTLOAD\0"
  /* 1074 */ "G_SEXTLOAD\0"
  /* 1085 */ "G_INDEXED_ZEXTLOAD\0"
  /* 1104 */ "G_ZEXTLOAD\0"
  /* 1115 */ "G_INDEXED_LOAD\0"
  /* 1130 */ "G_LOAD\0"
  /* 1137 */ "FSUBD\0"
  /* 1143 */ "FHSUBD\0"
  /* 1150 */ "G_VECREDUCE_FADD\0"
  /* 1167 */ "G_FADD\0"
  /* 1174 */ "G_VECREDUCE_SEQ_FADD\0"
  /* 1195 */ "G_STRICT_FADD\0"
  /* 1209 */ "G_ATOMICRMW_FADD\0"
  /* 1226 */ "G_VECREDUCE_ADD\0"
  /* 1242 */ "G_ADD\0"
  /* 1248 */ "G_PTR_ADD\0"
  /* 1258 */ "G_ATOMICRMW_ADD\0"
  /* 1274 */ "FADDD\0"
  /* 1280 */ "FHADDD\0"
  /* 1287 */ "FNHADDD\0"
  /* 1295 */ "FNADDD\0"
  /* 1302 */ "V9FCMPED\0"
  /* 1311 */ "RESTORED\0"
  /* 1320 */ "SAVED\0"
  /* 1326 */ "FNEGD\0"
  /* 1332 */ "FMULD\0"
  /* 1338 */ "FNMULD\0"
  /* 1345 */ "FSMULD\0"
  /* 1352 */ "FNSMULD\0"
  /* 1360 */ "FAND\0"
  /* 1365 */ "FNAND\0"
  /* 1371 */ "G_ATOMICRMW_NAND\0"
  /* 1388 */ "FEXPAND\0"
  /* 1396 */ "G_VECREDUCE_AND\0"
  /* 1412 */ "G_AND\0"
  /* 1418 */ "G_ATOMICRMW_AND\0"
  /* 1434 */ "LIFETIME_END\0"
  /* 1447 */ "CBCOND\0"
  /* 1454 */ "FBCOND\0"
  /* 1461 */ "G_BRCOND\0"
  /* 1470 */ "G_ATOMICRMW_USUB_COND\0"
  /* 1492 */ "G_LLROUND\0"
  /* 1502 */ "G_LROUND\0"
  /* 1511 */ "G_INTRINSIC_ROUND\0"
  /* 1529 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
  /* 1555 */ "FITOD\0"
  /* 1561 */ "FQTOD\0"
  /* 1567 */ "FSTOD\0"
  /* 1573 */ "FXTOD\0"
  /* 1579 */ "MOVXTOD\0"
  /* 1587 */ "V9FCMPD\0"
  /* 1595 */ "FLCMPD\0"
  /* 1602 */ "LOAD_STACK_GUARD\0"
  /* 1619 */ "FMOVRD\0"
  /* 1626 */ "FABSD\0"
  /* 1632 */ "FSQRTD\0"
  /* 1639 */ "FDIVD\0"
  /* 1645 */ "FMOVD\0"
  /* 1651 */ "PSEUDO_PROBE\0"
  /* 1664 */ "G_SSUBE\0"
  /* 1672 */ "G_USUBE\0"
  /* 1680 */ "G_FENCE\0"
  /* 1688 */ "ARITH_FENCE\0"
  /* 1700 */ "REG_SEQUENCE\0"
  /* 1713 */ "G_SADDE\0"
  /* 1721 */ "G_UADDE\0"
  /* 1729 */ "G_GET_FPMODE\0"
  /* 1742 */ "G_RESET_FPMODE\0"
  /* 1757 */ "G_SET_FPMODE\0"
  /* 1770 */ "G_FMINNUM_IEEE\0"
  /* 1785 */ "G_FMAXNUM_IEEE\0"
  /* 1800 */ "FPMERGE\0"
  /* 1808 */ "G_VSCALE\0"
  /* 1817 */ "G_JUMP_TABLE\0"
  /* 1830 */ "BUNDLE\0"
  /* 1837 */ "BSHUFFLE\0"
  /* 1846 */ "G_MEMCPY_INLINE\0"
  /* 1862 */ "DONE\0"
  /* 1867 */ "FONE\0"
  /* 1872 */ "LOCAL_ESCAPE\0"
  /* 1885 */ "G_STACKRESTORE\0"
  /* 1900 */ "G_INDEXED_STORE\0"
  /* 1916 */ "G_STORE\0"
  /* 1924 */ "G_BITREVERSE\0"
  /* 1937 */ "FAKE_USE\0"
  /* 1946 */ "DBG_VALUE\0"
  /* 1956 */ "G_GLOBAL_VALUE\0"
  /* 1971 */ "G_PTRAUTH_GLOBAL_VALUE\0"
  /* 1994 */ "CONVERGENCECTRL_GLUE\0"
  /* 2015 */ "G_STACKSAVE\0"
  /* 2027 */ "G_MEMMOVE\0"
  /* 2037 */ "G_FREEZE\0"
  /* 2046 */ "G_FCANONICALIZE\0"
  /* 2062 */ "G_CTLZ_ZERO_UNDEF\0"
  /* 2080 */ "G_CTTZ_ZERO_UNDEF\0"
  /* 2098 */ "INIT_UNDEF\0"
  /* 2109 */ "G_IMPLICIT_DEF\0"
  /* 2124 */ "DBG_INSTR_REF\0"
  /* 2138 */ "G_FNEG\0"
  /* 2145 */ "EXTRACT_SUBREG\0"
  /* 2160 */ "INSERT_SUBREG\0"
  /* 2174 */ "G_SEXT_INREG\0"
  /* 2187 */ "SUBREG_TO_REG\0"
  /* 2201 */ "G_ATOMIC_CMPXCHG\0"
  /* 2218 */ "G_ATOMICRMW_XCHG\0"
  /* 2235 */ "G_FLOG\0"
  /* 2242 */ "G_VAARG\0"
  /* 2250 */ "PREALLOCATED_ARG\0"
  /* 2267 */ "G_PREFETCH\0"
  /* 2278 */ "G_SMULH\0"
  /* 2286 */ "G_UMULH\0"
  /* 2294 */ "G_FTANH\0"
  /* 2302 */ "G_FSINH\0"
  /* 2310 */ "G_FCOSH\0"
  /* 2318 */ "FLUSH\0"
  /* 2324 */ "DBG_PHI\0"
  /* 2332 */ "UMULXHI\0"
  /* 2340 */ "XMULXHI\0"
  /* 2348 */ "FDTOI\0"
  /* 2354 */ "FQTOI\0"
  /* 2360 */ "FSTOI\0"
  /* 2366 */ "G_FPTOSI\0"
  /* 2375 */ "G_FPTOUI\0"
  /* 2384 */ "G_FPOWI\0"
  /* 2392 */ "BMASK\0"
  /* 2398 */ "G_PTRMASK\0"
  /* 2408 */ "EDGE32L\0"
  /* 2416 */ "EDGE16L\0"
  /* 2424 */ "EDGE8L\0"
  /* 2431 */ "FMUL8X16AL\0"
  /* 2442 */ "GC_LABEL\0"
  /* 2451 */ "DBG_LABEL\0"
  /* 2461 */ "EH_LABEL\0"
  /* 2470 */ "ANNOTATION_LABEL\0"
  /* 2487 */ "ICALL_BRANCH_FUNNEL\0"
  /* 2507 */ "G_FSHL\0"
  /* 2514 */ "G_SHL\0"
  /* 2520 */ "G_FCEIL\0"
  /* 2528 */ "PATCHABLE_TAIL_CALL\0"
  /* 2548 */ "TLS_CALL\0"
  /* 2557 */ "PATCHABLE_TYPED_EVENT_CALL\0"
  /* 2584 */ "PATCHABLE_EVENT_CALL\0"
  /* 2605 */ "FENTRY_CALL\0"
  /* 2617 */ "KILL\0"
  /* 2622 */ "G_CONSTANT_POOL\0"
  /* 2638 */ "ALIGNADDRL\0"
  /* 2649 */ "RETL\0"
  /* 2654 */ "G_ROTL\0"
  /* 2661 */ "G_VECREDUCE_FMUL\0"
  /* 2678 */ "G_FMUL\0"
  /* 2685 */ "G_VECREDUCE_SEQ_FMUL\0"
  /* 2706 */ "G_STRICT_FMUL\0"
  /* 2720 */ "G_VECREDUCE_MUL\0"
  /* 2736 */ "G_MUL\0"
  /* 2742 */ "SIAM\0"
  /* 2747 */ "G_FREM\0"
  /* 2754 */ "G_STRICT_FREM\0"
  /* 2768 */ "G_SREM\0"
  /* 2775 */ "G_UREM\0"
  /* 2782 */ "G_SDIVREM\0"
  /* 2792 */ "G_UDIVREM\0"
  /* 2802 */ "RDWIM\0"
  /* 2808 */ "INLINEASM\0"
  /* 2818 */ "G_VECREDUCE_FMINIMUM\0"
  /* 2839 */ "G_FMINIMUM\0"
  /* 2850 */ "G_VECREDUCE_FMAXIMUM\0"
  /* 2871 */ "G_FMAXIMUM\0"
  /* 2882 */ "G_FMINNUM\0"
  /* 2892 */ "G_FMAXNUM\0"
  /* 2902 */ "EDGE32N\0"
  /* 2910 */ "EDGE16N\0"
  /* 2918 */ "EDGE8N\0"
  /* 2925 */ "G_FATAN\0"
  /* 2933 */ "G_FTAN\0"
  /* 2940 */ "G_INTRINSIC_ROUNDEVEN\0"
  /* 2962 */ "G_ASSERT_ALIGN\0"
  /* 2977 */ "G_FCOPYSIGN\0"
  /* 2989 */ "G_VECREDUCE_FMIN\0"
  /* 3006 */ "G_ATOMICRMW_FMIN\0"
  /* 3023 */ "G_VECREDUCE_SMIN\0"
  /* 3040 */ "G_SMIN\0"
  /* 3047 */ "G_VECREDUCE_UMIN\0"
  /* 3064 */ "G_UMIN\0"
  /* 3071 */ "G_ATOMICRMW_UMIN\0"
  /* 3088 */ "G_ATOMICRMW_MIN\0"
  /* 3104 */ "G_FASIN\0"
  /* 3112 */ "G_FSIN\0"
  /* 3119 */ "EDGE32LN\0"
  /* 3128 */ "EDGE16LN\0"
  /* 3137 */ "EDGE8LN\0"
  /* 3145 */ "CFI_INSTRUCTION\0"
  /* 3161 */ "PDISTN\0"
  /* 3168 */ "ADJCALLSTACKDOWN\0"
  /* 3185 */ "SHUTDOWN\0"
  /* 3194 */ "G_SSUBO\0"
  /* 3202 */ "G_USUBO\0"
  /* 3210 */ "G_SADDO\0"
  /* 3218 */ "G_UADDO\0"
  /* 3226 */ "JUMP_TABLE_DEBUG_INFO\0"
  /* 3248 */ "G_SMULO\0"
  /* 3256 */ "G_UMULO\0"
  /* 3264 */ "G_BZERO\0"
  /* 3272 */ "FZERO\0"
  /* 3278 */ "STACKMAP\0"
  /* 3287 */ "G_DEBUGTRAP\0"
  /* 3299 */ "G_UBSANTRAP\0"
  /* 3311 */ "G_TRAP\0"
  /* 3318 */ "G_ATOMICRMW_UDEC_WRAP\0"
  /* 3340 */ "G_ATOMICRMW_UINC_WRAP\0"
  /* 3362 */ "G_BSWAP\0"
  /* 3370 */ "G_SITOFP\0"
  /* 3379 */ "G_UITOFP\0"
  /* 3388 */ "G_FCMP\0"
  /* 3395 */ "G_ICMP\0"
  /* 3402 */ "G_SCMP\0"
  /* 3409 */ "G_UCMP\0"
  /* 3416 */ "UNIMP\0"
  /* 3422 */ "NOP\0"
  /* 3426 */ "CONVERGENCECTRL_LOOP\0"
  /* 3447 */ "G_CTPOP\0"
  /* 3455 */ "PATCHABLE_OP\0"
  /* 3468 */ "FAULTING_OP\0"
  /* 3480 */ "ADJCALLSTACKUP\0"
  /* 3495 */ "PREALLOCATED_SETUP\0"
  /* 3514 */ "G_FLDEXP\0"
  /* 3523 */ "G_STRICT_FLDEXP\0"
  /* 3539 */ "G_FEXP\0"
  /* 3546 */ "G_FFREXP\0"
  /* 3555 */ "FSUBQ\0"
  /* 3561 */ "FADDQ\0"
  /* 3567 */ "V9FCMPEQ\0"
  /* 3576 */ "RDFQ\0"
  /* 3581 */ "FNEGQ\0"
  /* 3587 */ "FDMULQ\0"
  /* 3594 */ "FMULQ\0"
  /* 3600 */ "FDTOQ\0"
  /* 3606 */ "FITOQ\0"
  /* 3612 */ "FSTOQ\0"
  /* 3618 */ "FXTOQ\0"
  /* 3624 */ "V9FCMPQ\0"
  /* 3632 */ "FMOVRQ\0"
  /* 3639 */ "FABSQ\0"
  /* 3645 */ "FSQRTQ\0"
  /* 3652 */ "FDIVQ\0"
  /* 3658 */ "FMOVQ\0"
  /* 3664 */ "STBAR\0"
  /* 3670 */ "RDTBR\0"
  /* 3676 */ "G_BR\0"
  /* 3681 */ "INLINEASM_BR\0"
  /* 3694 */ "ALIGNADDR\0"
  /* 3704 */ "G_BLOCK_ADDR\0"
  /* 3717 */ "MEMBARRIER\0"
  /* 3728 */ "G_CONSTANT_FOLD_BARRIER\0"
  /* 3752 */ "PATCHABLE_FUNCTION_ENTER\0"
  /* 3777 */ "G_READCYCLECOUNTER\0"
  /* 3796 */ "G_READSTEADYCOUNTER\0"
  /* 3816 */ "G_READ_REGISTER\0"
  /* 3832 */ "G_WRITE_REGISTER\0"
  /* 3849 */ "G_ASHR\0"
  /* 3856 */ "G_FSHR\0"
  /* 3863 */ "G_LSHR\0"
  /* 3870 */ "SIR\0"
  /* 3874 */ "FOR\0"
  /* 3878 */ "CONVERGENCECTRL_ANCHOR\0"
  /* 3901 */ "FNOR\0"
  /* 3906 */ "FXNOR\0"
  /* 3912 */ "G_FFLOOR\0"
  /* 3921 */ "G_EXTRACT_SUBVECTOR\0"
  /* 3941 */ "G_INSERT_SUBVECTOR\0"
  /* 3960 */ "G_BUILD_VECTOR\0"
  /* 3975 */ "G_SHUFFLE_VECTOR\0"
  /* 3992 */ "G_SPLAT_VECTOR\0"
  /* 4007 */ "FXOR\0"
  /* 4012 */ "G_VECREDUCE_XOR\0"
  /* 4028 */ "G_XOR\0"
  /* 4034 */ "G_ATOMICRMW_XOR\0"
  /* 4050 */ "G_VECREDUCE_OR\0"
  /* 4065 */ "G_OR\0"
  /* 4070 */ "G_ATOMICRMW_OR\0"
  /* 4085 */ "BPR\0"
  /* 4089 */ "RDPR\0"
  /* 4094 */ "RDASR\0"
  /* 4100 */ "RDPSR\0"
  /* 4106 */ "G_ROTR\0"
  /* 4113 */ "G_INTTOPTR\0"
  /* 4124 */ "FSRC1S\0"
  /* 4131 */ "FANDNOT1S\0"
  /* 4141 */ "FNOT1S\0"
  /* 4148 */ "FORNOT1S\0"
  /* 4157 */ "FPSUB32S\0"
  /* 4166 */ "FPADD32S\0"
  /* 4175 */ "FSRC2S\0"
  /* 4182 */ "FANDNOT2S\0"
  /* 4192 */ "FNOT2S\0"
  /* 4199 */ "FORNOT2S\0"
  /* 4208 */ "FPSUB16S\0"
  /* 4217 */ "FPADD16S\0"
  /* 4226 */ "G_FABS\0"
  /* 4233 */ "G_ABS\0"
  /* 4239 */ "FSUBS\0"
  /* 4245 */ "FHSUBS\0"
  /* 4252 */ "FADDS\0"
  /* 4258 */ "FHADDS\0"
  /* 4265 */ "FNHADDS\0"
  /* 4273 */ "FNADDS\0"
  /* 4280 */ "FANDS\0"
  /* 4286 */ "FNANDS\0"
  /* 4293 */ "FONES\0"
  /* 4299 */ "V9FCMPES\0"
  /* 4308 */ "G_UNMERGE_VALUES\0"
  /* 4325 */ "G_MERGE_VALUES\0"
  /* 4340 */ "FNEGS\0"
  /* 4346 */ "FMULS\0"
  /* 4352 */ "FNMULS\0"
  /* 4359 */ "G_FACOS\0"
  /* 4367 */ "G_FCOS\0"
  /* 4374 */ "FZEROS\0"
  /* 4381 */ "FDTOS\0"
  /* 4387 */ "FITOS\0"
  /* 4393 */ "FQTOS\0"
  /* 4399 */ "MOVWTOS\0"
  /* 4407 */ "FXTOS\0"
  /* 4413 */ "V9FCMPS\0"
  /* 4421 */ "FLCMPS\0"
  /* 4428 */ "FORS\0"
  /* 4433 */ "FNORS\0"
  /* 4439 */ "FXNORS\0"
  /* 4446 */ "G_CONCAT_VECTORS\0"
  /* 4463 */ "FXORS\0"
  /* 4469 */ "FMOVRS\0"
  /* 4476 */ "COPY_TO_REGCLASS\0"
  /* 4493 */ "G_IS_FPCLASS\0"
  /* 4506 */ "FABSS\0"
  /* 4512 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
  /* 4542 */ "G_VECTOR_COMPRESS\0"
  /* 4560 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
  /* 4587 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
  /* 4625 */ "FSQRTS\0"
  /* 4632 */ "FDIVS\0"
  /* 4638 */ "FMOVS\0"
  /* 4644 */ "G_SSUBSAT\0"
  /* 4654 */ "G_USUBSAT\0"
  /* 4664 */ "G_SADDSAT\0"
  /* 4674 */ "G_UADDSAT\0"
  /* 4684 */ "G_SSHLSAT\0"
  /* 4694 */ "G_USHLSAT\0"
  /* 4704 */ "G_SMULFIXSAT\0"
  /* 4717 */ "G_UMULFIXSAT\0"
  /* 4730 */ "G_SDIVFIXSAT\0"
  /* 4743 */ "G_UDIVFIXSAT\0"
  /* 4756 */ "G_ATOMICRMW_USUB_SAT\0"
  /* 4777 */ "G_FPTOSI_SAT\0"
  /* 4790 */ "G_FPTOUI_SAT\0"
  /* 4803 */ "G_EXTRACT\0"
  /* 4813 */ "G_SELECT\0"
  /* 4822 */ "G_BRINDIRECT\0"
  /* 4835 */ "PATCHABLE_RET\0"
  /* 4849 */ "G_MEMSET\0"
  /* 4858 */ "PATCHABLE_FUNCTION_EXIT\0"
  /* 4882 */ "G_BRJT\0"
  /* 4889 */ "G_EXTRACT_VECTOR_ELT\0"
  /* 4910 */ "G_INSERT_VECTOR_ELT\0"
  /* 4930 */ "BPFCCANT\0"
  /* 4939 */ "BPICCANT\0"
  /* 4948 */ "BPXCCANT\0"
  /* 4957 */ "BPRANT\0"
  /* 4964 */ "G_FCONSTANT\0"
  /* 4976 */ "G_CONSTANT\0"
  /* 4987 */ "BPFCCNT\0"
  /* 4995 */ "BPICCNT\0"
  /* 5003 */ "BPXCCNT\0"
  /* 5011 */ "LZCNT\0"
  /* 5017 */ "G_INTRINSIC_CONVERGENT\0"
  /* 5040 */ "STATEPOINT\0"
  /* 5051 */ "PATCHPOINT\0"
  /* 5062 */ "G_PTRTOINT\0"
  /* 5073 */ "G_FRINT\0"
  /* 5081 */ "G_INTRINSIC_LLRINT\0"
  /* 5100 */ "G_INTRINSIC_LRINT\0"
  /* 5118 */ "G_FNEARBYINT\0"
  /* 5131 */ "BPRNT\0"
  /* 5137 */ "G_VASTART\0"
  /* 5147 */ "LIFETIME_START\0"
  /* 5162 */ "G_INVOKE_REGION_START\0"
  /* 5184 */ "G_INSERT\0"
  /* 5193 */ "G_FSQRT\0"
  /* 5201 */ "G_STRICT_FSQRT\0"
  /* 5216 */ "G_BITCAST\0"
  /* 5226 */ "G_ADDRSPACE_CAST\0"
  /* 5243 */ "PDIST\0"
  /* 5249 */ "DBG_VALUE_LIST\0"
  /* 5264 */ "G_FPEXT\0"
  /* 5272 */ "G_SEXT\0"
  /* 5279 */ "G_ASSERT_SEXT\0"
  /* 5293 */ "G_ANYEXT\0"
  /* 5302 */ "G_ZEXT\0"
  /* 5309 */ "G_ASSERT_ZEXT\0"
  /* 5323 */ "FMUL8X16AU\0"
  /* 5334 */ "G_FDIV\0"
  /* 5341 */ "G_STRICT_FDIV\0"
  /* 5355 */ "G_SDIV\0"
  /* 5362 */ "G_UDIV\0"
  /* 5369 */ "G_GET_FPENV\0"
  /* 5381 */ "G_RESET_FPENV\0"
  /* 5395 */ "G_SET_FPENV\0"
  /* 5407 */ "FLUSHW\0"
  /* 5414 */ "G_FPOW\0"
  /* 5421 */ "MOVSTOSW\0"
  /* 5430 */ "MOVSTOUW\0"
  /* 5439 */ "G_VECREDUCE_FMAX\0"
  /* 5456 */ "G_ATOMICRMW_FMAX\0"
  /* 5473 */ "G_VECREDUCE_SMAX\0"
  /* 5490 */ "G_SMAX\0"
  /* 5497 */ "G_VECREDUCE_UMAX\0"
  /* 5514 */ "G_UMAX\0"
  /* 5521 */ "G_ATOMICRMW_UMAX\0"
  /* 5538 */ "G_ATOMICRMW_MAX\0"
  /* 5554 */ "GETPCX\0"
  /* 5561 */ "G_FRAME_INDEX\0"
  /* 5575 */ "G_SBFX\0"
  /* 5582 */ "G_UBFX\0"
  /* 5589 */ "FPACKFIX\0"
  /* 5598 */ "G_SMULFIX\0"
  /* 5608 */ "G_UMULFIX\0"
  /* 5618 */ "G_SDIVFIX\0"
  /* 5628 */ "G_UDIVFIX\0"
  /* 5638 */ "XMULX\0"
  /* 5644 */ "FDTOX\0"
  /* 5650 */ "MOVDTOX\0"
  /* 5658 */ "FQTOX\0"
  /* 5664 */ "FSTOX\0"
  /* 5670 */ "SETX\0"
  /* 5675 */ "G_MEMCPY\0"
  /* 5684 */ "COPY\0"
  /* 5689 */ "RETRY\0"
  /* 5695 */ "CONVERGENCECTRL_ENTRY\0"
  /* 5717 */ "G_CTLZ\0"
  /* 5724 */ "G_CTTZ\0"
  /* 5731 */ "PREFETCHAi\0"
  /* 5742 */ "PREFETCHi\0"
  /* 5752 */ "SETHIi\0"
  /* 5759 */ "MEMBARi\0"
  /* 5767 */ "LDSBAri\0"
  /* 5775 */ "STBAri\0"
  /* 5782 */ "LDUBAri\0"
  /* 5790 */ "LDSTUBAri\0"
  /* 5800 */ "LDDAri\0"
  /* 5807 */ "LDAri\0"
  /* 5813 */ "STDAri\0"
  /* 5820 */ "LDDFAri\0"
  /* 5828 */ "LDFAri\0"
  /* 5835 */ "STDFAri\0"
  /* 5843 */ "LDQFAri\0"
  /* 5851 */ "STQFAri\0"
  /* 5859 */ "STFAri\0"
  /* 5866 */ "LDSHAri\0"
  /* 5874 */ "STHAri\0"
  /* 5881 */ "LDUHAri\0"
  /* 5889 */ "SWAPAri\0"
  /* 5897 */ "SRAri\0"
  /* 5903 */ "CASAri\0"
  /* 5910 */ "STAri\0"
  /* 5916 */ "LDSWAri\0"
  /* 5924 */ "LDXAri\0"
  /* 5931 */ "CASXAri\0"
  /* 5939 */ "STXAri\0"
  /* 5946 */ "LDSBri\0"
  /* 5953 */ "STBri\0"
  /* 5959 */ "LDUBri\0"
  /* 5966 */ "SUBri\0"
  /* 5972 */ "LDSTUBri\0"
  /* 5981 */ "SMACri\0"
  /* 5988 */ "UMACri\0"
  /* 5995 */ "SUBCri\0"
  /* 6002 */ "TSUBCCri\0"
  /* 6011 */ "TADDCCri\0"
  /* 6020 */ "ANDCCri\0"
  /* 6028 */ "V9MOVFCCri\0"
  /* 6039 */ "TICCri\0"
  /* 6046 */ "MOVICCri\0"
  /* 6055 */ "SMULCCri\0"
  /* 6064 */ "UMULCCri\0"
  /* 6073 */ "ANDNCCri\0"
  /* 6082 */ "ORNCCri\0"
  /* 6090 */ "XNORCCri\0"
  /* 6099 */ "XORCCri\0"
  /* 6107 */ "MULSCCri\0"
  /* 6116 */ "SDIVCCri\0"
  /* 6125 */ "UDIVCCri\0"
  /* 6134 */ "TXCCri\0"
  /* 6141 */ "MOVXCCri\0"
  /* 6150 */ "ADDCri\0"
  /* 6157 */ "LDDCri\0"
  /* 6164 */ "LDCri\0"
  /* 6170 */ "STDCri\0"
  /* 6177 */ "STCri\0"
  /* 6183 */ "ADDri\0"
  /* 6189 */ "LDDri\0"
  /* 6195 */ "LDri\0"
  /* 6200 */ "ANDri\0"
  /* 6206 */ "BINDri\0"
  /* 6213 */ "STDri\0"
  /* 6219 */ "SUBEri\0"
  /* 6226 */ "ADDEri\0"
  /* 6233 */ "RESTOREri\0"
  /* 6243 */ "SAVEri\0"
  /* 6250 */ "LDDFri\0"
  /* 6257 */ "LDFri\0"
  /* 6263 */ "STDFri\0"
  /* 6270 */ "LDQFri\0"
  /* 6277 */ "STQFri\0"
  /* 6284 */ "STFri\0"
  /* 6290 */ "LDSHri\0"
  /* 6297 */ "FLUSHri\0"
  /* 6305 */ "STHri\0"
  /* 6311 */ "LDUHri\0"
  /* 6318 */ "TAIL_CALLri\0"
  /* 6330 */ "SLLri\0"
  /* 6336 */ "JMPLri\0"
  /* 6343 */ "SRLri\0"
  /* 6349 */ "SMULri\0"
  /* 6356 */ "UMULri\0"
  /* 6363 */ "WRWIMri\0"
  /* 6371 */ "ANDNri\0"
  /* 6378 */ "ORNri\0"
  /* 6384 */ "TRAPri\0"
  /* 6391 */ "SWAPri\0"
  /* 6398 */ "STDCQri\0"
  /* 6406 */ "STDFQri\0"
  /* 6414 */ "WRTBRri\0"
  /* 6422 */ "XNORri\0"
  /* 6429 */ "XORri\0"
  /* 6435 */ "WRPRri\0"
  /* 6442 */ "WRASRri\0"
  /* 6450 */ "LDCSRri\0"
  /* 6458 */ "STCSRri\0"
  /* 6466 */ "LDFSRri\0"
  /* 6474 */ "STFSRri\0"
  /* 6482 */ "LDXFSRri\0"
  /* 6491 */ "STXFSRri\0"
  /* 6500 */ "PWRPSRri\0"
  /* 6509 */ "MOVRri\0"
  /* 6516 */ "STri\0"
  /* 6521 */ "RETTri\0"
  /* 6528 */ "SDIVri\0"
  /* 6535 */ "UDIVri\0"
  /* 6542 */ "TSUBCCTVri\0"
  /* 6553 */ "TADDCCTVri\0"
  /* 6564 */ "LDSWri\0"
  /* 6571 */ "SRAXri\0"
  /* 6578 */ "LDXri\0"
  /* 6584 */ "SLLXri\0"
  /* 6591 */ "SRLXri\0"
  /* 6598 */ "MULXri\0"
  /* 6605 */ "STXri\0"
  /* 6611 */ "SDIVXri\0"
  /* 6619 */ "UDIVXri\0"
  /* 6627 */ "PREFETCHAr\0"
  /* 6638 */ "PREFETCHr\0"
  /* 6648 */ "LDSBArr\0"
  /* 6656 */ "STBArr\0"
  /* 6663 */ "LDUBArr\0"
  /* 6671 */ "LDSTUBArr\0"
  /* 6681 */ "LDDArr\0"
  /* 6688 */ "LDArr\0"
  /* 6694 */ "STDArr\0"
  /* 6701 */ "LDDFArr\0"
  /* 6709 */ "LDFArr\0"
  /* 6716 */ "STDFArr\0"
  /* 6724 */ "LDQFArr\0"
  /* 6732 */ "STQFArr\0"
  /* 6740 */ "STFArr\0"
  /* 6747 */ "LDSHArr\0"
  /* 6755 */ "STHArr\0"
  /* 6762 */ "LDUHArr\0"
  /* 6770 */ "SWAPArr\0"
  /* 6778 */ "SRArr\0"
  /* 6784 */ "CASArr\0"
  /* 6791 */ "STArr\0"
  /* 6797 */ "LDSWArr\0"
  /* 6805 */ "LDXArr\0"
  /* 6812 */ "CASXArr\0"
  /* 6820 */ "STXArr\0"
  /* 6827 */ "LDSBrr\0"
  /* 6834 */ "STBrr\0"
  /* 6840 */ "LDUBrr\0"
  /* 6847 */ "SUBrr\0"
  /* 6853 */ "LDSTUBrr\0"
  /* 6862 */ "SMACrr\0"
  /* 6869 */ "UMACrr\0"
  /* 6876 */ "SUBCrr\0"
  /* 6883 */ "TSUBCCrr\0"
  /* 6892 */ "TADDCCrr\0"
  /* 6901 */ "ANDCCrr\0"
  /* 6909 */ "V9MOVFCCrr\0"
  /* 6920 */ "TICCrr\0"
  /* 6927 */ "MOVICCrr\0"
  /* 6936 */ "SMULCCrr\0"
  /* 6945 */ "UMULCCrr\0"
  /* 6954 */ "ANDNCCrr\0"
  /* 6963 */ "ORNCCrr\0"
  /* 6971 */ "XNORCCrr\0"
  /* 6980 */ "XORCCrr\0"
  /* 6988 */ "MULSCCrr\0"
  /* 6997 */ "SDIVCCrr\0"
  /* 7006 */ "UDIVCCrr\0"
  /* 7015 */ "TXCCrr\0"
  /* 7022 */ "MOVXCCrr\0"
  /* 7031 */ "ADDCrr\0"
  /* 7038 */ "LDDCrr\0"
  /* 7045 */ "LDCrr\0"
  /* 7051 */ "STDCrr\0"
  /* 7058 */ "POPCrr\0"
  /* 7065 */ "STCrr\0"
  /* 7071 */ "TLS_ADDrr\0"
  /* 7081 */ "LDDrr\0"
  /* 7087 */ "GDOP_LDrr\0"
  /* 7097 */ "TLS_LDrr\0"
  /* 7106 */ "ANDrr\0"
  /* 7112 */ "BINDrr\0"
  /* 7119 */ "STDrr\0"
  /* 7125 */ "SUBErr\0"
  /* 7132 */ "ADDErr\0"
  /* 7139 */ "RESTORErr\0"
  /* 7149 */ "SAVErr\0"
  /* 7156 */ "LDDFrr\0"
  /* 7163 */ "LDFrr\0"
  /* 7169 */ "STDFrr\0"
  /* 7176 */ "LDQFrr\0"
  /* 7183 */ "STQFrr\0"
  /* 7190 */ "STFrr\0"
  /* 7196 */ "LDSHrr\0"
  /* 7203 */ "FLUSHrr\0"
  /* 7211 */ "STHrr\0"
  /* 7217 */ "LDUHrr\0"
  /* 7224 */ "CALLrr\0"
  /* 7231 */ "SLLrr\0"
  /* 7237 */ "JMPLrr\0"
  /* 7244 */ "SRLrr\0"
  /* 7250 */ "SMULrr\0"
  /* 7257 */ "UMULrr\0"
  /* 7264 */ "WRWIMrr\0"
  /* 7272 */ "ANDNrr\0"
  /* 7279 */ "ORNrr\0"
  /* 7285 */ "TRAPrr\0"
  /* 7292 */ "SWAPrr\0"
  /* 7299 */ "STDCQrr\0"
  /* 7307 */ "STDFQrr\0"
  /* 7315 */ "WRTBRrr\0"
  /* 7323 */ "XNORrr\0"
  /* 7330 */ "XORrr\0"
  /* 7336 */ "WRPRrr\0"
  /* 7343 */ "WRASRrr\0"
  /* 7351 */ "LDCSRrr\0"
  /* 7359 */ "STCSRrr\0"
  /* 7367 */ "LDFSRrr\0"
  /* 7375 */ "STFSRrr\0"
  /* 7383 */ "LDXFSRrr\0"
  /* 7392 */ "STXFSRrr\0"
  /* 7401 */ "PWRPSRrr\0"
  /* 7410 */ "MOVRrr\0"
  /* 7417 */ "STrr\0"
  /* 7422 */ "RETTrr\0"
  /* 7429 */ "SDIVrr\0"
  /* 7436 */ "UDIVrr\0"
  /* 7443 */ "TSUBCCTVrr\0"
  /* 7454 */ "TADDCCTVrr\0"
  /* 7465 */ "LDSWrr\0"
  /* 7472 */ "SRAXrr\0"
  /* 7479 */ "GDOP_LDXrr\0"
  /* 7490 */ "TLS_LDXrr\0"
  /* 7500 */ "SLLXrr\0"
  /* 7507 */ "SRLXrr\0"
  /* 7514 */ "MULXrr\0"
  /* 7521 */ "STXrr\0"
  /* 7527 */ "SDIVXrr\0"
  /* 7535 */ "UDIVXrr\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const unsigned SparcInstrNameIndices[] = {
    2328U, 2808U, 3681U, 3145U, 2461U, 2442U, 2470U, 2617U, 
    2145U, 2160U, 2111U, 2098U, 2187U, 4476U, 1946U, 5249U, 
    2124U, 2324U, 2451U, 1700U, 5684U, 1830U, 5147U, 1434U, 
    1651U, 1688U, 3278U, 2605U, 5051U, 1602U, 3495U, 2250U, 
    5040U, 1872U, 3468U, 3455U, 3752U, 4835U, 4858U, 2528U, 
    2584U, 2557U, 2487U, 1937U, 3717U, 3226U, 5695U, 3878U, 
    3426U, 1994U, 5279U, 5309U, 2962U, 1242U, 599U, 2736U, 
    5355U, 5362U, 2768U, 2775U, 2782U, 2792U, 1412U, 4065U, 
    4028U, 2109U, 2326U, 5561U, 1956U, 1971U, 2622U, 4803U, 
    4308U, 5184U, 4325U, 3960U, 1004U, 4446U, 5062U, 4113U, 
    5216U, 2037U, 3728U, 1529U, 978U, 1511U, 5100U, 5081U, 
    2940U, 3777U, 3796U, 1130U, 1074U, 1104U, 1115U, 1055U, 
    1085U, 1916U, 1900U, 4512U, 2201U, 2218U, 1258U, 605U, 
    1418U, 1371U, 4070U, 4034U, 5538U, 3088U, 5521U, 3071U, 
    1209U, 582U, 5456U, 3006U, 3340U, 3318U, 1470U, 4756U, 
    1680U, 2267U, 1461U, 4822U, 5162U, 956U, 4560U, 5017U, 
    4587U, 5293U, 996U, 4976U, 4964U, 5137U, 2242U, 5272U, 
    2174U, 5302U, 2514U, 3863U, 3849U, 2507U, 3856U, 4106U, 
    2654U, 3395U, 3388U, 3402U, 3409U, 4813U, 3218U, 1721U, 
    3202U, 1672U, 3210U, 1713U, 3194U, 1664U, 3256U, 3248U, 
    2286U, 2278U, 4674U, 4664U, 4654U, 4644U, 4694U, 4684U, 
    5598U, 5608U, 4704U, 4717U, 5618U, 5628U, 4730U, 4743U, 
    1167U, 561U, 2678U, 525U, 1048U, 5334U, 2747U, 5414U, 
    2384U, 3539U, 186U, 9U, 2235U, 169U, 0U, 3514U, 
    3546U, 2138U, 5264U, 968U, 2366U, 2375U, 3370U, 3379U, 
    4777U, 4790U, 4226U, 2977U, 4493U, 2046U, 2882U, 2892U, 
    1770U, 1785U, 2839U, 2871U, 5369U, 5395U, 5381U, 1729U, 
    1757U, 1742U, 1248U, 2398U, 3040U, 5490U, 3064U, 5514U, 
    4233U, 1502U, 1492U, 3676U, 4882U, 1808U, 3941U, 3921U, 
    4910U, 4889U, 3975U, 3992U, 4542U, 5724U, 2080U, 5717U, 
    2062U, 3447U, 3362U, 1924U, 2520U, 4367U, 3112U, 2933U, 
    4359U, 3104U, 2925U, 177U, 2310U, 2302U, 2294U, 5193U, 
    3912U, 5073U, 5118U, 5226U, 3704U, 1817U, 1025U, 2015U, 
    1885U, 1195U, 568U, 2706U, 5341U, 2754U, 531U, 5201U, 
    3523U, 3816U, 3832U, 5675U, 1846U, 2027U, 4849U, 3264U, 
    3311U, 3287U, 3299U, 1174U, 2685U, 1150U, 2661U, 5439U, 
    2989U, 2850U, 2818U, 1226U, 2720U, 1396U, 4050U, 4012U, 
    5473U, 3023U, 5497U, 3047U, 5575U, 5582U, 3168U, 3480U, 
    5554U, 647U, 758U, 865U, 683U, 794U, 901U, 724U, 
    831U, 938U, 665U, 776U, 883U, 4854U, 5670U, 6012U, 
    6893U, 6150U, 7031U, 6226U, 7132U, 1042U, 621U, 6183U, 
    7075U, 3694U, 2638U, 6020U, 6901U, 6073U, 6954U, 6371U, 
    7272U, 6200U, 7106U, 409U, 155U, 430U, 485U, 1448U, 
    510U, 6206U, 7112U, 2392U, 629U, 488U, 4930U, 4987U, 
    742U, 495U, 4939U, 4995U, 4085U, 544U, 4957U, 5131U, 
    849U, 502U, 4948U, 5003U, 1837U, 2543U, 6323U, 7224U, 
    5903U, 6784U, 5931U, 6812U, 1447U, 509U, 289U, 107U, 
    423U, 1862U, 256U, 2416U, 3128U, 2910U, 74U, 2408U, 
    3119U, 2902U, 417U, 2424U, 3137U, 2918U, 1626U, 3639U, 
    4506U, 1274U, 3561U, 4252U, 549U, 1360U, 28U, 4131U, 
    194U, 4182U, 4280U, 1454U, 517U, 437U, 448U, 311U, 
    1589U, 458U, 328U, 129U, 345U, 146U, 263U, 81U, 
    272U, 90U, 3626U, 467U, 4415U, 476U, 1639U, 3652U, 
    4632U, 3587U, 2348U, 3600U, 4381U, 5644U, 1388U, 1280U, 
    4258U, 1143U, 4245U, 1555U, 3606U, 4387U, 1595U, 4421U, 
    2318U, 5407U, 6297U, 7203U, 320U, 1645U, 637U, 748U, 
    855U, 3658U, 702U, 811U, 918U, 1619U, 3632U, 4469U, 
    4638U, 714U, 821U, 928U, 398U, 375U, 354U, 2431U, 
    5323U, 1332U, 386U, 363U, 3594U, 4346U, 1295U, 4273U, 
    1365U, 4286U, 1326U, 3581U, 4340U, 1287U, 4265U, 1338U, 
    4352U, 3901U, 4433U, 37U, 4141U, 203U, 4192U, 1352U, 
    1867U, 4293U, 3874U, 43U, 4148U, 209U, 4199U, 4428U, 
    281U, 99U, 5589U, 248U, 4217U, 66U, 4166U, 221U, 
    1800U, 240U, 4208U, 58U, 4157U, 1561U, 2354U, 4393U, 
    5658U, 337U, 138U, 297U, 115U, 1345U, 1632U, 3645U, 
    4625U, 233U, 51U, 22U, 4124U, 163U, 4175U, 304U, 
    122U, 1567U, 2360U, 3612U, 5664U, 1137U, 3555U, 4239U, 
    3906U, 4439U, 4007U, 4463U, 1573U, 3618U, 4407U, 3272U, 
    4374U, 7479U, 7087U, 6336U, 7237U, 5807U, 6688U, 6450U, 
    7351U, 6164U, 7045U, 5800U, 6681U, 6157U, 7038U, 5820U, 
    6701U, 6250U, 7156U, 6189U, 7081U, 5828U, 6709U, 6466U, 
    7367U, 6257U, 7163U, 5843U, 6724U, 6270U, 7176U, 5767U, 
    6648U, 5946U, 6827U, 5866U, 6747U, 6290U, 7196U, 5790U, 
    6671U, 5972U, 6853U, 5916U, 6797U, 6564U, 7465U, 5782U, 
    6663U, 5959U, 6840U, 5881U, 6762U, 6311U, 7217U, 5924U, 
    6805U, 6482U, 7383U, 6578U, 7484U, 6195U, 7092U, 5011U, 
    5759U, 5650U, 6030U, 6911U, 6046U, 6927U, 6509U, 7410U, 
    5421U, 5430U, 4399U, 6141U, 7022U, 1579U, 6107U, 6988U, 
    6598U, 7514U, 3422U, 6092U, 6973U, 6082U, 6963U, 6378U, 
    7279U, 6424U, 7325U, 5243U, 3161U, 7058U, 5731U, 6627U, 
    5742U, 6638U, 6500U, 7401U, 4094U, 3576U, 4089U, 4100U, 
    3670U, 2802U, 1311U, 6233U, 7139U, 4845U, 2649U, 5689U, 
    6521U, 7422U, 1320U, 6243U, 7149U, 6116U, 6997U, 6611U, 
    7527U, 6528U, 7429U, 5752U, 3185U, 2742U, 3870U, 6584U, 
    7500U, 6330U, 7231U, 5981U, 6862U, 6055U, 6936U, 6349U, 
    7250U, 6571U, 7472U, 5897U, 6778U, 6591U, 7507U, 6343U, 
    7244U, 5910U, 6791U, 3664U, 5775U, 6656U, 5953U, 6834U, 
    6458U, 7359U, 6177U, 7065U, 5813U, 6694U, 6398U, 7299U, 
    6170U, 7051U, 5835U, 6716U, 6406U, 7307U, 6263U, 7169U, 
    6213U, 7119U, 5859U, 6740U, 6474U, 7375U, 6284U, 7190U, 
    5874U, 6755U, 6305U, 7211U, 5851U, 6732U, 6277U, 7183U, 
    5939U, 6820U, 6491U, 7392U, 6605U, 7521U, 6516U, 7417U, 
    6003U, 6884U, 5995U, 6876U, 6219U, 7125U, 5966U, 6847U, 
    5889U, 6770U, 6391U, 7292U, 18U, 217U, 229U, 6553U, 
    7454U, 6011U, 6892U, 2538U, 6318U, 6039U, 6920U, 7071U, 
    2548U, 7490U, 7097U, 6384U, 7285U, 6542U, 7443U, 6002U, 
    6883U, 6134U, 7015U, 6125U, 7006U, 6619U, 7535U, 6535U, 
    7436U, 5988U, 6869U, 6064U, 6945U, 2332U, 6356U, 7257U, 
    3416U, 1587U, 1302U, 3567U, 4299U, 3624U, 4413U, 635U, 
    700U, 712U, 6028U, 6909U, 6442U, 7343U, 6435U, 7336U, 
    6501U, 7402U, 6414U, 7315U, 6363U, 7264U, 5638U, 2340U, 
    6090U, 6971U, 6422U, 7323U, 6099U, 6980U, 6429U, 7330U, 
};

static inline void InitSparcMCInstrInfo(MCInstrInfo *II) {
  II->InitMCInstrInfo(SparcDescs.Insts, SparcInstrNameIndices, SparcInstrNameData, nullptr, nullptr, 816);
}

} // end namespace llvm
#endif // GET_INSTRINFO_MC_DESC

#ifdef GET_INSTRINFO_HEADER
#undef GET_INSTRINFO_HEADER
namespace llvm {
struct SparcGenInstrInfo : public TargetInstrInfo {
  explicit SparcGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
  ~SparcGenInstrInfo() override = default;

};
} // end namespace llvm
#endif // GET_INSTRINFO_HEADER

#ifdef GET_INSTRINFO_HELPER_DECLS
#undef GET_INSTRINFO_HELPER_DECLS


#endif // GET_INSTRINFO_HELPER_DECLS

#ifdef GET_INSTRINFO_HELPERS
#undef GET_INSTRINFO_HELPERS

#endif // GET_INSTRINFO_HELPERS

#ifdef GET_INSTRINFO_CTOR_DTOR
#undef GET_INSTRINFO_CTOR_DTOR
namespace llvm {
extern const SparcInstrTable SparcDescs;
extern const unsigned SparcInstrNameIndices[];
extern const char SparcInstrNameData[];
SparcGenInstrInfo::SparcGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
  InitMCInstrInfo(SparcDescs.Insts, SparcInstrNameIndices, SparcInstrNameData, nullptr, nullptr, 816);
}
} // end namespace llvm
#endif // GET_INSTRINFO_CTOR_DTOR

#ifdef GET_INSTRINFO_OPERAND_ENUM
#undef GET_INSTRINFO_OPERAND_ENUM
namespace llvm {
namespace SP {
namespace OpName {
enum {
  OPERAND_LAST
};
} // end namespace OpName
} // end namespace SP
} // end namespace llvm
#endif //GET_INSTRINFO_OPERAND_ENUM

#ifdef GET_INSTRINFO_NAMED_OPS
#undef GET_INSTRINFO_NAMED_OPS
namespace llvm {
namespace SP {
LLVM_READONLY
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
  return -1;
}
} // end namespace SP
} // end namespace llvm
#endif //GET_INSTRINFO_NAMED_OPS

#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
namespace llvm {
namespace SP {
namespace OpTypes {
enum OperandType {
  ASITag = 0,
  CCOp = 1,
  MEMri = 2,
  MEMrr = 3,
  MembarTag = 4,
  PrefetchTag = 5,
  RegCCOp = 6,
  TailRelocSymGOTLoad = 7,
  TailRelocSymTLSAdd = 8,
  TailRelocSymTLSCall = 9,
  TailRelocSymTLSLoad = 10,
  bprtarget = 11,
  bprtarget16 = 12,
  brtarget = 13,
  calltarget = 14,
  f32imm = 15,
  f64imm = 16,
  getPCX = 17,
  i1imm = 18,
  i8imm = 19,
  i16imm = 20,
  i32imm = 21,
  i64imm = 22,
  ptype0 = 23,
  ptype1 = 24,
  ptype2 = 25,
  ptype3 = 26,
  ptype4 = 27,
  ptype5 = 28,
  shift_imm5 = 29,
  shift_imm6 = 30,
  simm13Op = 31,
  type0 = 32,
  type1 = 33,
  type2 = 34,
  type3 = 35,
  type4 = 36,
  type5 = 37,
  untyped_imm_0 = 38,
  ASRRegs = 39,
  CoprocPair = 40,
  CoprocRegs = 41,
  DFPRegs = 42,
  FCCRegs = 43,
  FPRegs = 44,
  GPRIncomingArg = 45,
  GPROutgoingArg = 46,
  I64Regs = 47,
  IntPair = 48,
  IntRegs = 49,
  LowDFPRegs = 50,
  LowQFPRegs = 51,
  PRRegs = 52,
  QFPRegs = 53,
  OPERAND_TYPE_LIST_END
};
} // end namespace OpTypes
} // end namespace SP
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM

#ifdef GET_INSTRINFO_OPERAND_TYPE
#undef GET_INSTRINFO_OPERAND_TYPE
namespace llvm {
namespace SP {
LLVM_READONLY
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
  static const uint16_t Offsets[] = {
    /* PHI */
    0,
    /* INLINEASM */
    1,
    /* INLINEASM_BR */
    1,
    /* CFI_INSTRUCTION */
    1,
    /* EH_LABEL */
    2,
    /* GC_LABEL */
    3,
    /* ANNOTATION_LABEL */
    4,
    /* KILL */
    5,
    /* EXTRACT_SUBREG */
    5,
    /* INSERT_SUBREG */
    8,
    /* IMPLICIT_DEF */
    12,
    /* INIT_UNDEF */
    13,
    /* SUBREG_TO_REG */
    14,
    /* COPY_TO_REGCLASS */
    18,
    /* DBG_VALUE */
    21,
    /* DBG_VALUE_LIST */
    21,
    /* DBG_INSTR_REF */
    21,
    /* DBG_PHI */
    21,
    /* DBG_LABEL */
    21,
    /* REG_SEQUENCE */
    22,
    /* COPY */
    24,
    /* BUNDLE */
    26,
    /* LIFETIME_START */
    26,
    /* LIFETIME_END */
    27,
    /* PSEUDO_PROBE */
    28,
    /* ARITH_FENCE */
    32,
    /* STACKMAP */
    34,
    /* FENTRY_CALL */
    36,
    /* PATCHPOINT */
    36,
    /* LOAD_STACK_GUARD */
    42,
    /* PREALLOCATED_SETUP */
    43,
    /* PREALLOCATED_ARG */
    44,
    /* STATEPOINT */
    47,
    /* LOCAL_ESCAPE */
    47,
    /* FAULTING_OP */
    49,
    /* PATCHABLE_OP */
    50,
    /* PATCHABLE_FUNCTION_ENTER */
    50,
    /* PATCHABLE_RET */
    50,
    /* PATCHABLE_FUNCTION_EXIT */
    50,
    /* PATCHABLE_TAIL_CALL */
    50,
    /* PATCHABLE_EVENT_CALL */
    50,
    /* PATCHABLE_TYPED_EVENT_CALL */
    52,
    /* ICALL_BRANCH_FUNNEL */
    55,
    /* FAKE_USE */
    55,
    /* MEMBARRIER */
    55,
    /* JUMP_TABLE_DEBUG_INFO */
    55,
    /* CONVERGENCECTRL_ENTRY */
    56,
    /* CONVERGENCECTRL_ANCHOR */
    57,
    /* CONVERGENCECTRL_LOOP */
    58,
    /* CONVERGENCECTRL_GLUE */
    60,
    /* G_ASSERT_SEXT */
    61,
    /* G_ASSERT_ZEXT */
    64,
    /* G_ASSERT_ALIGN */
    67,
    /* G_ADD */
    70,
    /* G_SUB */
    73,
    /* G_MUL */
    76,
    /* G_SDIV */
    79,
    /* G_UDIV */
    82,
    /* G_SREM */
    85,
    /* G_UREM */
    88,
    /* G_SDIVREM */
    91,
    /* G_UDIVREM */
    95,
    /* G_AND */
    99,
    /* G_OR */
    102,
    /* G_XOR */
    105,
    /* G_IMPLICIT_DEF */
    108,
    /* G_PHI */
    109,
    /* G_FRAME_INDEX */
    110,
    /* G_GLOBAL_VALUE */
    112,
    /* G_PTRAUTH_GLOBAL_VALUE */
    114,
    /* G_CONSTANT_POOL */
    119,
    /* G_EXTRACT */
    121,
    /* G_UNMERGE_VALUES */
    124,
    /* G_INSERT */
    126,
    /* G_MERGE_VALUES */
    130,
    /* G_BUILD_VECTOR */
    132,
    /* G_BUILD_VECTOR_TRUNC */
    134,
    /* G_CONCAT_VECTORS */
    136,
    /* G_PTRTOINT */
    138,
    /* G_INTTOPTR */
    140,
    /* G_BITCAST */
    142,
    /* G_FREEZE */
    144,
    /* G_CONSTANT_FOLD_BARRIER */
    146,
    /* G_INTRINSIC_FPTRUNC_ROUND */
    148,
    /* G_INTRINSIC_TRUNC */
    151,
    /* G_INTRINSIC_ROUND */
    153,
    /* G_INTRINSIC_LRINT */
    155,
    /* G_INTRINSIC_LLRINT */
    157,
    /* G_INTRINSIC_ROUNDEVEN */
    159,
    /* G_READCYCLECOUNTER */
    161,
    /* G_READSTEADYCOUNTER */
    162,
    /* G_LOAD */
    163,
    /* G_SEXTLOAD */
    165,
    /* G_ZEXTLOAD */
    167,
    /* G_INDEXED_LOAD */
    169,
    /* G_INDEXED_SEXTLOAD */
    174,
    /* G_INDEXED_ZEXTLOAD */
    179,
    /* G_STORE */
    184,
    /* G_INDEXED_STORE */
    186,
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    191,
    /* G_ATOMIC_CMPXCHG */
    196,
    /* G_ATOMICRMW_XCHG */
    200,
    /* G_ATOMICRMW_ADD */
    203,
    /* G_ATOMICRMW_SUB */
    206,
    /* G_ATOMICRMW_AND */
    209,
    /* G_ATOMICRMW_NAND */
    212,
    /* G_ATOMICRMW_OR */
    215,
    /* G_ATOMICRMW_XOR */
    218,
    /* G_ATOMICRMW_MAX */
    221,
    /* G_ATOMICRMW_MIN */
    224,
    /* G_ATOMICRMW_UMAX */
    227,
    /* G_ATOMICRMW_UMIN */
    230,
    /* G_ATOMICRMW_FADD */
    233,
    /* G_ATOMICRMW_FSUB */
    236,
    /* G_ATOMICRMW_FMAX */
    239,
    /* G_ATOMICRMW_FMIN */
    242,
    /* G_ATOMICRMW_UINC_WRAP */
    245,
    /* G_ATOMICRMW_UDEC_WRAP */
    248,
    /* G_ATOMICRMW_USUB_COND */
    251,
    /* G_ATOMICRMW_USUB_SAT */
    254,
    /* G_FENCE */
    257,
    /* G_PREFETCH */
    259,
    /* G_BRCOND */
    263,
    /* G_BRINDIRECT */
    265,
    /* G_INVOKE_REGION_START */
    266,
    /* G_INTRINSIC */
    266,
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    267,
    /* G_INTRINSIC_CONVERGENT */
    268,
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    269,
    /* G_ANYEXT */
    270,
    /* G_TRUNC */
    272,
    /* G_CONSTANT */
    274,
    /* G_FCONSTANT */
    276,
    /* G_VASTART */
    278,
    /* G_VAARG */
    279,
    /* G_SEXT */
    282,
    /* G_SEXT_INREG */
    284,
    /* G_ZEXT */
    287,
    /* G_SHL */
    289,
    /* G_LSHR */
    292,
    /* G_ASHR */
    295,
    /* G_FSHL */
    298,
    /* G_FSHR */
    302,
    /* G_ROTR */
    306,
    /* G_ROTL */
    309,
    /* G_ICMP */
    312,
    /* G_FCMP */
    316,
    /* G_SCMP */
    320,
    /* G_UCMP */
    323,
    /* G_SELECT */
    326,
    /* G_UADDO */
    330,
    /* G_UADDE */
    334,
    /* G_USUBO */
    339,
    /* G_USUBE */
    343,
    /* G_SADDO */
    348,
    /* G_SADDE */
    352,
    /* G_SSUBO */
    357,
    /* G_SSUBE */
    361,
    /* G_UMULO */
    366,
    /* G_SMULO */
    370,
    /* G_UMULH */
    374,
    /* G_SMULH */
    377,
    /* G_UADDSAT */
    380,
    /* G_SADDSAT */
    383,
    /* G_USUBSAT */
    386,
    /* G_SSUBSAT */
    389,
    /* G_USHLSAT */
    392,
    /* G_SSHLSAT */
    395,
    /* G_SMULFIX */
    398,
    /* G_UMULFIX */
    402,
    /* G_SMULFIXSAT */
    406,
    /* G_UMULFIXSAT */
    410,
    /* G_SDIVFIX */
    414,
    /* G_UDIVFIX */
    418,
    /* G_SDIVFIXSAT */
    422,
    /* G_UDIVFIXSAT */
    426,
    /* G_FADD */
    430,
    /* G_FSUB */
    433,
    /* G_FMUL */
    436,
    /* G_FMA */
    439,
    /* G_FMAD */
    443,
    /* G_FDIV */
    447,
    /* G_FREM */
    450,
    /* G_FPOW */
    453,
    /* G_FPOWI */
    456,
    /* G_FEXP */
    459,
    /* G_FEXP2 */
    461,
    /* G_FEXP10 */
    463,
    /* G_FLOG */
    465,
    /* G_FLOG2 */
    467,
    /* G_FLOG10 */
    469,
    /* G_FLDEXP */
    471,
    /* G_FFREXP */
    474,
    /* G_FNEG */
    477,
    /* G_FPEXT */
    479,
    /* G_FPTRUNC */
    481,
    /* G_FPTOSI */
    483,
    /* G_FPTOUI */
    485,
    /* G_SITOFP */
    487,
    /* G_UITOFP */
    489,
    /* G_FPTOSI_SAT */
    491,
    /* G_FPTOUI_SAT */
    493,
    /* G_FABS */
    495,
    /* G_FCOPYSIGN */
    497,
    /* G_IS_FPCLASS */
    500,
    /* G_FCANONICALIZE */
    503,
    /* G_FMINNUM */
    505,
    /* G_FMAXNUM */
    508,
    /* G_FMINNUM_IEEE */
    511,
    /* G_FMAXNUM_IEEE */
    514,
    /* G_FMINIMUM */
    517,
    /* G_FMAXIMUM */
    520,
    /* G_GET_FPENV */
    523,
    /* G_SET_FPENV */
    524,
    /* G_RESET_FPENV */
    525,
    /* G_GET_FPMODE */
    525,
    /* G_SET_FPMODE */
    526,
    /* G_RESET_FPMODE */
    527,
    /* G_PTR_ADD */
    527,
    /* G_PTRMASK */
    530,
    /* G_SMIN */
    533,
    /* G_SMAX */
    536,
    /* G_UMIN */
    539,
    /* G_UMAX */
    542,
    /* G_ABS */
    545,
    /* G_LROUND */
    547,
    /* G_LLROUND */
    549,
    /* G_BR */
    551,
    /* G_BRJT */
    552,
    /* G_VSCALE */
    555,
    /* G_INSERT_SUBVECTOR */
    557,
    /* G_EXTRACT_SUBVECTOR */
    561,
    /* G_INSERT_VECTOR_ELT */
    564,
    /* G_EXTRACT_VECTOR_ELT */
    568,
    /* G_SHUFFLE_VECTOR */
    571,
    /* G_SPLAT_VECTOR */
    575,
    /* G_VECTOR_COMPRESS */
    577,
    /* G_CTTZ */
    581,
    /* G_CTTZ_ZERO_UNDEF */
    583,
    /* G_CTLZ */
    585,
    /* G_CTLZ_ZERO_UNDEF */
    587,
    /* G_CTPOP */
    589,
    /* G_BSWAP */
    591,
    /* G_BITREVERSE */
    593,
    /* G_FCEIL */
    595,
    /* G_FCOS */
    597,
    /* G_FSIN */
    599,
    /* G_FTAN */
    601,
    /* G_FACOS */
    603,
    /* G_FASIN */
    605,
    /* G_FATAN */
    607,
    /* G_FATAN2 */
    609,
    /* G_FCOSH */
    612,
    /* G_FSINH */
    614,
    /* G_FTANH */
    616,
    /* G_FSQRT */
    618,
    /* G_FFLOOR */
    620,
    /* G_FRINT */
    622,
    /* G_FNEARBYINT */
    624,
    /* G_ADDRSPACE_CAST */
    626,
    /* G_BLOCK_ADDR */
    628,
    /* G_JUMP_TABLE */
    630,
    /* G_DYN_STACKALLOC */
    632,
    /* G_STACKSAVE */
    635,
    /* G_STACKRESTORE */
    636,
    /* G_STRICT_FADD */
    637,
    /* G_STRICT_FSUB */
    640,
    /* G_STRICT_FMUL */
    643,
    /* G_STRICT_FDIV */
    646,
    /* G_STRICT_FREM */
    649,
    /* G_STRICT_FMA */
    652,
    /* G_STRICT_FSQRT */
    656,
    /* G_STRICT_FLDEXP */
    658,
    /* G_READ_REGISTER */
    661,
    /* G_WRITE_REGISTER */
    663,
    /* G_MEMCPY */
    665,
    /* G_MEMCPY_INLINE */
    669,
    /* G_MEMMOVE */
    672,
    /* G_MEMSET */
    676,
    /* G_BZERO */
    680,
    /* G_TRAP */
    683,
    /* G_DEBUGTRAP */
    683,
    /* G_UBSANTRAP */
    683,
    /* G_VECREDUCE_SEQ_FADD */
    684,
    /* G_VECREDUCE_SEQ_FMUL */
    687,
    /* G_VECREDUCE_FADD */
    690,
    /* G_VECREDUCE_FMUL */
    692,
    /* G_VECREDUCE_FMAX */
    694,
    /* G_VECREDUCE_FMIN */
    696,
    /* G_VECREDUCE_FMAXIMUM */
    698,
    /* G_VECREDUCE_FMINIMUM */
    700,
    /* G_VECREDUCE_ADD */
    702,
    /* G_VECREDUCE_MUL */
    704,
    /* G_VECREDUCE_AND */
    706,
    /* G_VECREDUCE_OR */
    708,
    /* G_VECREDUCE_XOR */
    710,
    /* G_VECREDUCE_SMAX */
    712,
    /* G_VECREDUCE_SMIN */
    714,
    /* G_VECREDUCE_UMAX */
    716,
    /* G_VECREDUCE_UMIN */
    718,
    /* G_SBFX */
    720,
    /* G_UBFX */
    724,
    /* ADJCALLSTACKDOWN */
    728,
    /* ADJCALLSTACKUP */
    730,
    /* GETPCX */
    732,
    /* SELECT_CC_DFP_FCC */
    733,
    /* SELECT_CC_DFP_ICC */
    737,
    /* SELECT_CC_DFP_XCC */
    741,
    /* SELECT_CC_FP_FCC */
    745,
    /* SELECT_CC_FP_ICC */
    749,
    /* SELECT_CC_FP_XCC */
    753,
    /* SELECT_CC_Int_FCC */
    757,
    /* SELECT_CC_Int_ICC */
    761,
    /* SELECT_CC_Int_XCC */
    765,
    /* SELECT_CC_QFP_FCC */
    769,
    /* SELECT_CC_QFP_ICC */
    773,
    /* SELECT_CC_QFP_XCC */
    777,
    /* SET */
    781,
    /* SETX */
    783,
    /* ADDCCri */
    786,
    /* ADDCCrr */
    789,
    /* ADDCri */
    792,
    /* ADDCrr */
    795,
    /* ADDEri */
    798,
    /* ADDErr */
    801,
    /* ADDXC */
    804,
    /* ADDXCCC */
    807,
    /* ADDri */
    810,
    /* ADDrr */
    813,
    /* ALIGNADDR */
    816,
    /* ALIGNADDRL */
    819,
    /* ANDCCri */
    822,
    /* ANDCCrr */
    825,
    /* ANDNCCri */
    828,
    /* ANDNCCrr */
    831,
    /* ANDNri */
    834,
    /* ANDNrr */
    837,
    /* ANDri */
    840,
    /* ANDrr */
    843,
    /* ARRAY16 */
    846,
    /* ARRAY32 */
    849,
    /* ARRAY8 */
    852,
    /* BA */
    855,
    /* BCOND */
    856,
    /* BCONDA */
    858,
    /* BINDri */
    860,
    /* BINDrr */
    862,
    /* BMASK */
    864,
    /* BPFCC */
    867,
    /* BPFCCA */
    870,
    /* BPFCCANT */
    873,
    /* BPFCCNT */
    876,
    /* BPICC */
    879,
    /* BPICCA */
    881,
    /* BPICCANT */
    883,
    /* BPICCNT */
    885,
    /* BPR */
    887,
    /* BPRA */
    890,
    /* BPRANT */
    893,
    /* BPRNT */
    896,
    /* BPXCC */
    899,
    /* BPXCCA */
    901,
    /* BPXCCANT */
    903,
    /* BPXCCNT */
    905,
    /* BSHUFFLE */
    907,
    /* CALL */
    910,
    /* CALLri */
    911,
    /* CALLrr */
    913,
    /* CASAri */
    915,
    /* CASArr */
    919,
    /* CASXAri */
    924,
    /* CASXArr */
    928,
    /* CBCOND */
    933,
    /* CBCONDA */
    935,
    /* CMASK16 */
    937,
    /* CMASK32 */
    938,
    /* CMASK8 */
    939,
    /* DONE */
    940,
    /* EDGE16 */
    940,
    /* EDGE16L */
    943,
    /* EDGE16LN */
    946,
    /* EDGE16N */
    949,
    /* EDGE32 */
    952,
    /* EDGE32L */
    955,
    /* EDGE32LN */
    958,
    /* EDGE32N */
    961,
    /* EDGE8 */
    964,
    /* EDGE8L */
    967,
    /* EDGE8LN */
    970,
    /* EDGE8N */
    973,
    /* FABSD */
    976,
    /* FABSQ */
    978,
    /* FABSS */
    980,
    /* FADDD */
    982,
    /* FADDQ */
    985,
    /* FADDS */
    988,
    /* FALIGNADATA */
    991,
    /* FAND */
    994,
    /* FANDNOT1 */
    997,
    /* FANDNOT1S */
    1000,
    /* FANDNOT2 */
    1003,
    /* FANDNOT2S */
    1006,
    /* FANDS */
    1009,
    /* FBCOND */
    1012,
    /* FBCONDA */
    1014,
    /* FBCONDA_V9 */
    1016,
    /* FBCOND_V9 */
    1018,
    /* FCHKSM16 */
    1020,
    /* FCMPD */
    1023,
    /* FCMPD_V9 */
    1025,
    /* FCMPEQ16 */
    1027,
    /* FCMPEQ32 */
    1030,
    /* FCMPGT16 */
    1033,
    /* FCMPGT32 */
    1036,
    /* FCMPLE16 */
    1039,
    /* FCMPLE32 */
    1042,
    /* FCMPNE16 */
    1045,
    /* FCMPNE32 */
    1048,
    /* FCMPQ */
    1051,
    /* FCMPQ_V9 */
    1053,
    /* FCMPS */
    1055,
    /* FCMPS_V9 */
    1057,
    /* FDIVD */
    1059,
    /* FDIVQ */
    1062,
    /* FDIVS */
    1065,
    /* FDMULQ */
    1068,
    /* FDTOI */
    1071,
    /* FDTOQ */
    1073,
    /* FDTOS */
    1075,
    /* FDTOX */
    1077,
    /* FEXPAND */
    1079,
    /* FHADDD */
    1081,
    /* FHADDS */
    1084,
    /* FHSUBD */
    1087,
    /* FHSUBS */
    1090,
    /* FITOD */
    1093,
    /* FITOQ */
    1095,
    /* FITOS */
    1097,
    /* FLCMPD */
    1099,
    /* FLCMPS */
    1102,
    /* FLUSH */
    1105,
    /* FLUSHW */
    1105,
    /* FLUSHri */
    1105,
    /* FLUSHrr */
    1107,
    /* FMEAN16 */
    1109,
    /* FMOVD */
    1112,
    /* FMOVD_FCC */
    1114,
    /* FMOVD_ICC */
    1118,
    /* FMOVD_XCC */
    1122,
    /* FMOVQ */
    1126,
    /* FMOVQ_FCC */
    1128,
    /* FMOVQ_ICC */
    1132,
    /* FMOVQ_XCC */
    1136,
    /* FMOVRD */
    1140,
    /* FMOVRQ */
    1145,
    /* FMOVRS */
    1150,
    /* FMOVS */
    1155,
    /* FMOVS_FCC */
    1157,
    /* FMOVS_ICC */
    1161,
    /* FMOVS_XCC */
    1165,
    /* FMUL8SUX16 */
    1169,
    /* FMUL8ULX16 */
    1172,
    /* FMUL8X16 */
    1175,
    /* FMUL8X16AL */
    1178,
    /* FMUL8X16AU */
    1181,
    /* FMULD */
    1184,
    /* FMULD8SUX16 */
    1187,
    /* FMULD8ULX16 */
    1190,
    /* FMULQ */
    1193,
    /* FMULS */
    1196,
    /* FNADDD */
    1199,
    /* FNADDS */
    1202,
    /* FNAND */
    1205,
    /* FNANDS */
    1208,
    /* FNEGD */
    1211,
    /* FNEGQ */
    1213,
    /* FNEGS */
    1215,
    /* FNHADDD */
    1217,
    /* FNHADDS */
    1220,
    /* FNMULD */
    1223,
    /* FNMULS */
    1226,
    /* FNOR */
    1229,
    /* FNORS */
    1232,
    /* FNOT1 */
    1235,
    /* FNOT1S */
    1237,
    /* FNOT2 */
    1239,
    /* FNOT2S */
    1241,
    /* FNSMULD */
    1243,
    /* FONE */
    1246,
    /* FONES */
    1248,
    /* FOR */
    1250,
    /* FORNOT1 */
    1253,
    /* FORNOT1S */
    1256,
    /* FORNOT2 */
    1259,
    /* FORNOT2S */
    1262,
    /* FORS */
    1265,
    /* FPACK16 */
    1268,
    /* FPACK32 */
    1270,
    /* FPACKFIX */
    1273,
    /* FPADD16 */
    1275,
    /* FPADD16S */
    1278,
    /* FPADD32 */
    1281,
    /* FPADD32S */
    1284,
    /* FPADD64 */
    1287,
    /* FPMERGE */
    1290,
    /* FPSUB16 */
    1293,
    /* FPSUB16S */
    1296,
    /* FPSUB32 */
    1299,
    /* FPSUB32S */
    1302,
    /* FQTOD */
    1305,
    /* FQTOI */
    1307,
    /* FQTOS */
    1309,
    /* FQTOX */
    1311,
    /* FSLAS16 */
    1313,
    /* FSLAS32 */
    1316,
    /* FSLL16 */
    1319,
    /* FSLL32 */
    1322,
    /* FSMULD */
    1325,
    /* FSQRTD */
    1328,
    /* FSQRTQ */
    1330,
    /* FSQRTS */
    1332,
    /* FSRA16 */
    1334,
    /* FSRA32 */
    1337,
    /* FSRC1 */
    1340,
    /* FSRC1S */
    1342,
    /* FSRC2 */
    1344,
    /* FSRC2S */
    1346,
    /* FSRL16 */
    1348,
    /* FSRL32 */
    1351,
    /* FSTOD */
    1354,
    /* FSTOI */
    1356,
    /* FSTOQ */
    1358,
    /* FSTOX */
    1360,
    /* FSUBD */
    1362,
    /* FSUBQ */
    1365,
    /* FSUBS */
    1368,
    /* FXNOR */
    1371,
    /* FXNORS */
    1374,
    /* FXOR */
    1377,
    /* FXORS */
    1380,
    /* FXTOD */
    1383,
    /* FXTOQ */
    1385,
    /* FXTOS */
    1387,
    /* FZERO */
    1389,
    /* FZEROS */
    1391,
    /* GDOP_LDXrr */
    1393,
    /* GDOP_LDrr */
    1397,
    /* JMPLri */
    1401,
    /* JMPLrr */
    1404,
    /* LDAri */
    1407,
    /* LDArr */
    1410,
    /* LDCSRri */
    1414,
    /* LDCSRrr */
    1416,
    /* LDCri */
    1418,
    /* LDCrr */
    1421,
    /* LDDAri */
    1424,
    /* LDDArr */
    1427,
    /* LDDCri */
    1431,
    /* LDDCrr */
    1434,
    /* LDDFAri */
    1437,
    /* LDDFArr */
    1440,
    /* LDDFri */
    1444,
    /* LDDFrr */
    1447,
    /* LDDri */
    1450,
    /* LDDrr */
    1453,
    /* LDFAri */
    1456,
    /* LDFArr */
    1459,
    /* LDFSRri */
    1463,
    /* LDFSRrr */
    1465,
    /* LDFri */
    1467,
    /* LDFrr */
    1470,
    /* LDQFAri */
    1473,
    /* LDQFArr */
    1476,
    /* LDQFri */
    1480,
    /* LDQFrr */
    1483,
    /* LDSBAri */
    1486,
    /* LDSBArr */
    1489,
    /* LDSBri */
    1493,
    /* LDSBrr */
    1496,
    /* LDSHAri */
    1499,
    /* LDSHArr */
    1502,
    /* LDSHri */
    1506,
    /* LDSHrr */
    1509,
    /* LDSTUBAri */
    1512,
    /* LDSTUBArr */
    1515,
    /* LDSTUBri */
    1519,
    /* LDSTUBrr */
    1522,
    /* LDSWAri */
    1525,
    /* LDSWArr */
    1528,
    /* LDSWri */
    1532,
    /* LDSWrr */
    1535,
    /* LDUBAri */
    1538,
    /* LDUBArr */
    1541,
    /* LDUBri */
    1545,
    /* LDUBrr */
    1548,
    /* LDUHAri */
    1551,
    /* LDUHArr */
    1554,
    /* LDUHri */
    1558,
    /* LDUHrr */
    1561,
    /* LDXAri */
    1564,
    /* LDXArr */
    1567,
    /* LDXFSRri */
    1571,
    /* LDXFSRrr */
    1573,
    /* LDXri */
    1575,
    /* LDXrr */
    1578,
    /* LDri */
    1581,
    /* LDrr */
    1584,
    /* LZCNT */
    1587,
    /* MEMBARi */
    1589,
    /* MOVDTOX */
    1590,
    /* MOVFCCri */
    1592,
    /* MOVFCCrr */
    1596,
    /* MOVICCri */
    1600,
    /* MOVICCrr */
    1604,
    /* MOVRri */
    1608,
    /* MOVRrr */
    1613,
    /* MOVSTOSW */
    1618,
    /* MOVSTOUW */
    1620,
    /* MOVWTOS */
    1622,
    /* MOVXCCri */
    1624,
    /* MOVXCCrr */
    1628,
    /* MOVXTOD */
    1632,
    /* MULSCCri */
    1634,
    /* MULSCCrr */
    1637,
    /* MULXri */
    1640,
    /* MULXrr */
    1643,
    /* NOP */
    1646,
    /* ORCCri */
    1646,
    /* ORCCrr */
    1649,
    /* ORNCCri */
    1652,
    /* ORNCCrr */
    1655,
    /* ORNri */
    1658,
    /* ORNrr */
    1661,
    /* ORri */
    1664,
    /* ORrr */
    1667,
    /* PDIST */
    1670,
    /* PDISTN */
    1673,
    /* POPCrr */
    1676,
    /* PREFETCHAi */
    1678,
    /* PREFETCHAr */
    1681,
    /* PREFETCHi */
    1685,
    /* PREFETCHr */
    1688,
    /* PWRPSRri */
    1691,
    /* PWRPSRrr */
    1693,
    /* RDASR */
    1695,
    /* RDFQ */
    1697,
    /* RDPR */
    1698,
    /* RDPSR */
    1700,
    /* RDTBR */
    1701,
    /* RDWIM */
    1702,
    /* RESTORED */
    1703,
    /* RESTOREri */
    1703,
    /* RESTORErr */
    1706,
    /* RET */
    1709,
    /* RETL */
    1710,
    /* RETRY */
    1711,
    /* RETTri */
    1711,
    /* RETTrr */
    1713,
    /* SAVED */
    1715,
    /* SAVEri */
    1715,
    /* SAVErr */
    1718,
    /* SDIVCCri */
    1721,
    /* SDIVCCrr */
    1724,
    /* SDIVXri */
    1727,
    /* SDIVXrr */
    1730,
    /* SDIVri */
    1733,
    /* SDIVrr */
    1736,
    /* SETHIi */
    1739,
    /* SHUTDOWN */
    1741,
    /* SIAM */
    1741,
    /* SIR */
    1741,
    /* SLLXri */
    1742,
    /* SLLXrr */
    1745,
    /* SLLri */
    1748,
    /* SLLrr */
    1751,
    /* SMACri */
    1754,
    /* SMACrr */
    1758,
    /* SMULCCri */
    1762,
    /* SMULCCrr */
    1765,
    /* SMULri */
    1768,
    /* SMULrr */
    1771,
    /* SRAXri */
    1774,
    /* SRAXrr */
    1777,
    /* SRAri */
    1780,
    /* SRArr */
    1783,
    /* SRLXri */
    1786,
    /* SRLXrr */
    1789,
    /* SRLri */
    1792,
    /* SRLrr */
    1795,
    /* STAri */
    1798,
    /* STArr */
    1801,
    /* STBAR */
    1805,
    /* STBAri */
    1805,
    /* STBArr */
    1808,
    /* STBri */
    1812,
    /* STBrr */
    1815,
    /* STCSRri */
    1818,
    /* STCSRrr */
    1820,
    /* STCri */
    1822,
    /* STCrr */
    1825,
    /* STDAri */
    1828,
    /* STDArr */
    1831,
    /* STDCQri */
    1835,
    /* STDCQrr */
    1837,
    /* STDCri */
    1839,
    /* STDCrr */
    1842,
    /* STDFAri */
    1845,
    /* STDFArr */
    1848,
    /* STDFQri */
    1852,
    /* STDFQrr */
    1854,
    /* STDFri */
    1856,
    /* STDFrr */
    1859,
    /* STDri */
    1862,
    /* STDrr */
    1865,
    /* STFAri */
    1868,
    /* STFArr */
    1871,
    /* STFSRri */
    1875,
    /* STFSRrr */
    1877,
    /* STFri */
    1879,
    /* STFrr */
    1882,
    /* STHAri */
    1885,
    /* STHArr */
    1888,
    /* STHri */
    1892,
    /* STHrr */
    1895,
    /* STQFAri */
    1898,
    /* STQFArr */
    1901,
    /* STQFri */
    1905,
    /* STQFrr */
    1908,
    /* STXAri */
    1911,
    /* STXArr */
    1914,
    /* STXFSRri */
    1918,
    /* STXFSRrr */
    1920,
    /* STXri */
    1922,
    /* STXrr */
    1925,
    /* STri */
    1928,
    /* STrr */
    1931,
    /* SUBCCri */
    1934,
    /* SUBCCrr */
    1937,
    /* SUBCri */
    1940,
    /* SUBCrr */
    1943,
    /* SUBEri */
    1946,
    /* SUBErr */
    1949,
    /* SUBri */
    1952,
    /* SUBrr */
    1955,
    /* SWAPAri */
    1958,
    /* SWAPArr */
    1962,
    /* SWAPri */
    1967,
    /* SWAPrr */
    1971,
    /* TA1 */
    1975,
    /* TA3 */
    1975,
    /* TA5 */
    1975,
    /* TADDCCTVri */
    1975,
    /* TADDCCTVrr */
    1978,
    /* TADDCCri */
    1981,
    /* TADDCCrr */
    1984,
    /* TAIL_CALL */
    1987,
    /* TAIL_CALLri */
    1988,
    /* TICCri */
    1990,
    /* TICCrr */
    1993,
    /* TLS_ADDrr */
    1996,
    /* TLS_CALL */
    2000,
    /* TLS_LDXrr */
    2002,
    /* TLS_LDrr */
    2006,
    /* TRAPri */
    2010,
    /* TRAPrr */
    2013,
    /* TSUBCCTVri */
    2016,
    /* TSUBCCTVrr */
    2019,
    /* TSUBCCri */
    2022,
    /* TSUBCCrr */
    2025,
    /* TXCCri */
    2028,
    /* TXCCrr */
    2031,
    /* UDIVCCri */
    2034,
    /* UDIVCCrr */
    2037,
    /* UDIVXri */
    2040,
    /* UDIVXrr */
    2043,
    /* UDIVri */
    2046,
    /* UDIVrr */
    2049,
    /* UMACri */
    2052,
    /* UMACrr */
    2056,
    /* UMULCCri */
    2060,
    /* UMULCCrr */
    2063,
    /* UMULXHI */
    2066,
    /* UMULri */
    2069,
    /* UMULrr */
    2072,
    /* UNIMP */
    2075,
    /* V9FCMPD */
    2076,
    /* V9FCMPED */
    2079,
    /* V9FCMPEQ */
    2082,
    /* V9FCMPES */
    2085,
    /* V9FCMPQ */
    2088,
    /* V9FCMPS */
    2091,
    /* V9FMOVD_FCC */
    2094,
    /* V9FMOVQ_FCC */
    2099,
    /* V9FMOVS_FCC */
    2104,
    /* V9MOVFCCri */
    2109,
    /* V9MOVFCCrr */
    2114,
    /* WRASRri */
    2119,
    /* WRASRrr */
    2122,
    /* WRPRri */
    2125,
    /* WRPRrr */
    2128,
    /* WRPSRri */
    2131,
    /* WRPSRrr */
    2133,
    /* WRTBRri */
    2135,
    /* WRTBRrr */
    2137,
    /* WRWIMri */
    2139,
    /* WRWIMrr */
    2141,
    /* XMULX */
    2143,
    /* XMULXHI */
    2146,
    /* XNORCCri */
    2149,
    /* XNORCCrr */
    2152,
    /* XNORri */
    2155,
    /* XNORrr */
    2158,
    /* XORCCri */
    2161,
    /* XORCCrr */
    2164,
    /* XORri */
    2167,
    /* XORrr */
    2170,
  };

  using namespace OpTypes;
  static const int8_t OpcodeOperandTypes[] = {
    
    /* PHI */
    -1, 
    /* INLINEASM */
    /* INLINEASM_BR */
    /* CFI_INSTRUCTION */
    i32imm, 
    /* EH_LABEL */
    i32imm, 
    /* GC_LABEL */
    i32imm, 
    /* ANNOTATION_LABEL */
    i32imm, 
    /* KILL */
    /* EXTRACT_SUBREG */
    -1, -1, i32imm, 
    /* INSERT_SUBREG */
    -1, -1, -1, i32imm, 
    /* IMPLICIT_DEF */
    -1, 
    /* INIT_UNDEF */
    -1, 
    /* SUBREG_TO_REG */
    -1, -1, -1, i32imm, 
    /* COPY_TO_REGCLASS */
    -1, -1, i32imm, 
    /* DBG_VALUE */
    /* DBG_VALUE_LIST */
    /* DBG_INSTR_REF */
    /* DBG_PHI */
    /* DBG_LABEL */
    -1, 
    /* REG_SEQUENCE */
    -1, -1, 
    /* COPY */
    -1, -1, 
    /* BUNDLE */
    /* LIFETIME_START */
    i32imm, 
    /* LIFETIME_END */
    i32imm, 
    /* PSEUDO_PROBE */
    i64imm, i64imm, i8imm, i32imm, 
    /* ARITH_FENCE */
    -1, -1, 
    /* STACKMAP */
    i64imm, i32imm, 
    /* FENTRY_CALL */
    /* PATCHPOINT */
    -1, i64imm, i32imm, -1, i32imm, i32imm, 
    /* LOAD_STACK_GUARD */
    -1, 
    /* PREALLOCATED_SETUP */
    i32imm, 
    /* PREALLOCATED_ARG */
    -1, i32imm, i32imm, 
    /* STATEPOINT */
    /* LOCAL_ESCAPE */
    -1, i32imm, 
    /* FAULTING_OP */
    -1, 
    /* PATCHABLE_OP */
    /* PATCHABLE_FUNCTION_ENTER */
    /* PATCHABLE_RET */
    /* PATCHABLE_FUNCTION_EXIT */
    /* PATCHABLE_TAIL_CALL */
    /* PATCHABLE_EVENT_CALL */
    -1, -1, 
    /* PATCHABLE_TYPED_EVENT_CALL */
    -1, -1, -1, 
    /* ICALL_BRANCH_FUNNEL */
    /* FAKE_USE */
    /* MEMBARRIER */
    /* JUMP_TABLE_DEBUG_INFO */
    i64imm, 
    /* CONVERGENCECTRL_ENTRY */
    -1, 
    /* CONVERGENCECTRL_ANCHOR */
    -1, 
    /* CONVERGENCECTRL_LOOP */
    -1, -1, 
    /* CONVERGENCECTRL_GLUE */
    -1, 
    /* G_ASSERT_SEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ZEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ALIGN */
    type0, type0, untyped_imm_0, 
    /* G_ADD */
    type0, type0, type0, 
    /* G_SUB */
    type0, type0, type0, 
    /* G_MUL */
    type0, type0, type0, 
    /* G_SDIV */
    type0, type0, type0, 
    /* G_UDIV */
    type0, type0, type0, 
    /* G_SREM */
    type0, type0, type0, 
    /* G_UREM */
    type0, type0, type0, 
    /* G_SDIVREM */
    type0, type0, type0, type0, 
    /* G_UDIVREM */
    type0, type0, type0, type0, 
    /* G_AND */
    type0, type0, type0, 
    /* G_OR */
    type0, type0, type0, 
    /* G_XOR */
    type0, type0, type0, 
    /* G_IMPLICIT_DEF */
    type0, 
    /* G_PHI */
    type0, 
    /* G_FRAME_INDEX */
    type0, -1, 
    /* G_GLOBAL_VALUE */
    type0, -1, 
    /* G_PTRAUTH_GLOBAL_VALUE */
    type0, -1, i32imm, type1, i64imm, 
    /* G_CONSTANT_POOL */
    type0, -1, 
    /* G_EXTRACT */
    type0, type1, untyped_imm_0, 
    /* G_UNMERGE_VALUES */
    type0, type1, 
    /* G_INSERT */
    type0, type0, type1, untyped_imm_0, 
    /* G_MERGE_VALUES */
    type0, type1, 
    /* G_BUILD_VECTOR */
    type0, type1, 
    /* G_BUILD_VECTOR_TRUNC */
    type0, type1, 
    /* G_CONCAT_VECTORS */
    type0, type1, 
    /* G_PTRTOINT */
    type0, type1, 
    /* G_INTTOPTR */
    type0, type1, 
    /* G_BITCAST */
    type0, type1, 
    /* G_FREEZE */
    type0, type0, 
    /* G_CONSTANT_FOLD_BARRIER */
    type0, type0, 
    /* G_INTRINSIC_FPTRUNC_ROUND */
    type0, type1, i32imm, 
    /* G_INTRINSIC_TRUNC */
    type0, type0, 
    /* G_INTRINSIC_ROUND */
    type0, type0, 
    /* G_INTRINSIC_LRINT */
    type0, type1, 
    /* G_INTRINSIC_LLRINT */
    type0, type1, 
    /* G_INTRINSIC_ROUNDEVEN */
    type0, type0, 
    /* G_READCYCLECOUNTER */
    type0, 
    /* G_READSTEADYCOUNTER */
    type0, 
    /* G_LOAD */
    type0, ptype1, 
    /* G_SEXTLOAD */
    type0, ptype1, 
    /* G_ZEXTLOAD */
    type0, ptype1, 
    /* G_INDEXED_LOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_SEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_ZEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_STORE */
    type0, ptype1, 
    /* G_INDEXED_STORE */
    ptype0, type1, ptype0, ptype2, -1, 
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    type0, type1, type2, type0, type0, 
    /* G_ATOMIC_CMPXCHG */
    type0, ptype1, type0, type0, 
    /* G_ATOMICRMW_XCHG */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_ADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_SUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_AND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_NAND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_OR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_XOR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FSUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UINC_WRAP */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UDEC_WRAP */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_USUB_COND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_USUB_SAT */
    type0, ptype1, type0, 
    /* G_FENCE */
    i32imm, i32imm, 
    /* G_PREFETCH */
    ptype0, i32imm, i32imm, i32imm, 
    /* G_BRCOND */
    type0, -1, 
    /* G_BRINDIRECT */
    type0, 
    /* G_INVOKE_REGION_START */
    /* G_INTRINSIC */
    -1, 
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    -1, 
    /* G_INTRINSIC_CONVERGENT */
    -1, 
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    -1, 
    /* G_ANYEXT */
    type0, type1, 
    /* G_TRUNC */
    type0, type1, 
    /* G_CONSTANT */
    type0, -1, 
    /* G_FCONSTANT */
    type0, -1, 
    /* G_VASTART */
    type0, 
    /* G_VAARG */
    type0, type1, -1, 
    /* G_SEXT */
    type0, type1, 
    /* G_SEXT_INREG */
    type0, type0, untyped_imm_0, 
    /* G_ZEXT */
    type0, type1, 
    /* G_SHL */
    type0, type0, type1, 
    /* G_LSHR */
    type0, type0, type1, 
    /* G_ASHR */
    type0, type0, type1, 
    /* G_FSHL */
    type0, type0, type0, type1, 
    /* G_FSHR */
    type0, type0, type0, type1, 
    /* G_ROTR */
    type0, type0, type1, 
    /* G_ROTL */
    type0, type0, type1, 
    /* G_ICMP */
    type0, -1, type1, type1, 
    /* G_FCMP */
    type0, -1, type1, type1, 
    /* G_SCMP */
    type0, type1, type1, 
    /* G_UCMP */
    type0, type1, type1, 
    /* G_SELECT */
    type0, type1, type0, type0, 
    /* G_UADDO */
    type0, type1, type0, type0, 
    /* G_UADDE */
    type0, type1, type0, type0, type1, 
    /* G_USUBO */
    type0, type1, type0, type0, 
    /* G_USUBE */
    type0, type1, type0, type0, type1, 
    /* G_SADDO */
    type0, type1, type0, type0, 
    /* G_SADDE */
    type0, type1, type0, type0, type1, 
    /* G_SSUBO */
    type0, type1, type0, type0, 
    /* G_SSUBE */
    type0, type1, type0, type0, type1, 
    /* G_UMULO */
    type0, type1, type0, type0, 
    /* G_SMULO */
    type0, type1, type0, type0, 
    /* G_UMULH */
    type0, type0, type0, 
    /* G_SMULH */
    type0, type0, type0, 
    /* G_UADDSAT */
    type0, type0, type0, 
    /* G_SADDSAT */
    type0, type0, type0, 
    /* G_USUBSAT */
    type0, type0, type0, 
    /* G_SSUBSAT */
    type0, type0, type0, 
    /* G_USHLSAT */
    type0, type0, type1, 
    /* G_SSHLSAT */
    type0, type0, type1, 
    /* G_SMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_FADD */
    type0, type0, type0, 
    /* G_FSUB */
    type0, type0, type0, 
    /* G_FMUL */
    type0, type0, type0, 
    /* G_FMA */
    type0, type0, type0, type0, 
    /* G_FMAD */
    type0, type0, type0, type0, 
    /* G_FDIV */
    type0, type0, type0, 
    /* G_FREM */
    type0, type0, type0, 
    /* G_FPOW */
    type0, type0, type0, 
    /* G_FPOWI */
    type0, type0, type1, 
    /* G_FEXP */
    type0, type0, 
    /* G_FEXP2 */
    type0, type0, 
    /* G_FEXP10 */
    type0, type0, 
    /* G_FLOG */
    type0, type0, 
    /* G_FLOG2 */
    type0, type0, 
    /* G_FLOG10 */
    type0, type0, 
    /* G_FLDEXP */
    type0, type0, type1, 
    /* G_FFREXP */
    type0, type1, type0, 
    /* G_FNEG */
    type0, type0, 
    /* G_FPEXT */
    type0, type1, 
    /* G_FPTRUNC */
    type0, type1, 
    /* G_FPTOSI */
    type0, type1, 
    /* G_FPTOUI */
    type0, type1, 
    /* G_SITOFP */
    type0, type1, 
    /* G_UITOFP */
    type0, type1, 
    /* G_FPTOSI_SAT */
    type0, type1, 
    /* G_FPTOUI_SAT */
    type0, type1, 
    /* G_FABS */
    type0, type0, 
    /* G_FCOPYSIGN */
    type0, type0, type1, 
    /* G_IS_FPCLASS */
    type0, type1, -1, 
    /* G_FCANONICALIZE */
    type0, type0, 
    /* G_FMINNUM */
    type0, type0, type0, 
    /* G_FMAXNUM */
    type0, type0, type0, 
    /* G_FMINNUM_IEEE */
    type0, type0, type0, 
    /* G_FMAXNUM_IEEE */
    type0, type0, type0, 
    /* G_FMINIMUM */
    type0, type0, type0, 
    /* G_FMAXIMUM */
    type0, type0, type0, 
    /* G_GET_FPENV */
    type0, 
    /* G_SET_FPENV */
    type0, 
    /* G_RESET_FPENV */
    /* G_GET_FPMODE */
    type0, 
    /* G_SET_FPMODE */
    type0, 
    /* G_RESET_FPMODE */
    /* G_PTR_ADD */
    ptype0, ptype0, type1, 
    /* G_PTRMASK */
    ptype0, ptype0, type1, 
    /* G_SMIN */
    type0, type0, type0, 
    /* G_SMAX */
    type0, type0, type0, 
    /* G_UMIN */
    type0, type0, type0, 
    /* G_UMAX */
    type0, type0, type0, 
    /* G_ABS */
    type0, type0, 
    /* G_LROUND */
    type0, type1, 
    /* G_LLROUND */
    type0, type1, 
    /* G_BR */
    -1, 
    /* G_BRJT */
    ptype0, -1, type1, 
    /* G_VSCALE */
    type0, -1, 
    /* G_INSERT_SUBVECTOR */
    type0, type0, type1, untyped_imm_0, 
    /* G_EXTRACT_SUBVECTOR */
    type0, type1, untyped_imm_0, 
    /* G_INSERT_VECTOR_ELT */
    type0, type0, type1, type2, 
    /* G_EXTRACT_VECTOR_ELT */
    type0, type1, type2, 
    /* G_SHUFFLE_VECTOR */
    type0, type1, type1, -1, 
    /* G_SPLAT_VECTOR */
    type0, type1, 
    /* G_VECTOR_COMPRESS */
    type0, type0, type1, type0, 
    /* G_CTTZ */
    type0, type1, 
    /* G_CTTZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTLZ */
    type0, type1, 
    /* G_CTLZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTPOP */
    type0, type1, 
    /* G_BSWAP */
    type0, type0, 
    /* G_BITREVERSE */
    type0, type0, 
    /* G_FCEIL */
    type0, type0, 
    /* G_FCOS */
    type0, type0, 
    /* G_FSIN */
    type0, type0, 
    /* G_FTAN */
    type0, type0, 
    /* G_FACOS */
    type0, type0, 
    /* G_FASIN */
    type0, type0, 
    /* G_FATAN */
    type0, type0, 
    /* G_FATAN2 */
    type0, type0, type0, 
    /* G_FCOSH */
    type0, type0, 
    /* G_FSINH */
    type0, type0, 
    /* G_FTANH */
    type0, type0, 
    /* G_FSQRT */
    type0, type0, 
    /* G_FFLOOR */
    type0, type0, 
    /* G_FRINT */
    type0, type0, 
    /* G_FNEARBYINT */
    type0, type0, 
    /* G_ADDRSPACE_CAST */
    type0, type1, 
    /* G_BLOCK_ADDR */
    type0, -1, 
    /* G_JUMP_TABLE */
    type0, -1, 
    /* G_DYN_STACKALLOC */
    ptype0, type1, i32imm, 
    /* G_STACKSAVE */
    ptype0, 
    /* G_STACKRESTORE */
    ptype0, 
    /* G_STRICT_FADD */
    type0, type0, type0, 
    /* G_STRICT_FSUB */
    type0, type0, type0, 
    /* G_STRICT_FMUL */
    type0, type0, type0, 
    /* G_STRICT_FDIV */
    type0, type0, type0, 
    /* G_STRICT_FREM */
    type0, type0, type0, 
    /* G_STRICT_FMA */
    type0, type0, type0, type0, 
    /* G_STRICT_FSQRT */
    type0, type0, 
    /* G_STRICT_FLDEXP */
    type0, type0, type1, 
    /* G_READ_REGISTER */
    type0, -1, 
    /* G_WRITE_REGISTER */
    -1, type0, 
    /* G_MEMCPY */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMCPY_INLINE */
    ptype0, ptype1, type2, 
    /* G_MEMMOVE */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMSET */
    ptype0, type1, type2, untyped_imm_0, 
    /* G_BZERO */
    ptype0, type1, untyped_imm_0, 
    /* G_TRAP */
    /* G_DEBUGTRAP */
    /* G_UBSANTRAP */
    i8imm, 
    /* G_VECREDUCE_SEQ_FADD */
    type0, type1, type2, 
    /* G_VECREDUCE_SEQ_FMUL */
    type0, type1, type2, 
    /* G_VECREDUCE_FADD */
    type0, type1, 
    /* G_VECREDUCE_FMUL */
    type0, type1, 
    /* G_VECREDUCE_FMAX */
    type0, type1, 
    /* G_VECREDUCE_FMIN */
    type0, type1, 
    /* G_VECREDUCE_FMAXIMUM */
    type0, type1, 
    /* G_VECREDUCE_FMINIMUM */
    type0, type1, 
    /* G_VECREDUCE_ADD */
    type0, type1, 
    /* G_VECREDUCE_MUL */
    type0, type1, 
    /* G_VECREDUCE_AND */
    type0, type1, 
    /* G_VECREDUCE_OR */
    type0, type1, 
    /* G_VECREDUCE_XOR */
    type0, type1, 
    /* G_VECREDUCE_SMAX */
    type0, type1, 
    /* G_VECREDUCE_SMIN */
    type0, type1, 
    /* G_VECREDUCE_UMAX */
    type0, type1, 
    /* G_VECREDUCE_UMIN */
    type0, type1, 
    /* G_SBFX */
    type0, type0, type1, type1, 
    /* G_UBFX */
    type0, type0, type1, type1, 
    /* ADJCALLSTACKDOWN */
    i32imm, i32imm, 
    /* ADJCALLSTACKUP */
    i32imm, i32imm, 
    /* GETPCX */
    getPCX, 
    /* SELECT_CC_DFP_FCC */
    DFPRegs, DFPRegs, DFPRegs, i32imm, 
    /* SELECT_CC_DFP_ICC */
    DFPRegs, DFPRegs, DFPRegs, i32imm, 
    /* SELECT_CC_DFP_XCC */
    DFPRegs, DFPRegs, DFPRegs, i32imm, 
    /* SELECT_CC_FP_FCC */
    FPRegs, FPRegs, FPRegs, i32imm, 
    /* SELECT_CC_FP_ICC */
    FPRegs, FPRegs, FPRegs, i32imm, 
    /* SELECT_CC_FP_XCC */
    FPRegs, FPRegs, FPRegs, i32imm, 
    /* SELECT_CC_Int_FCC */
    IntRegs, IntRegs, IntRegs, i32imm, 
    /* SELECT_CC_Int_ICC */
    IntRegs, IntRegs, IntRegs, i32imm, 
    /* SELECT_CC_Int_XCC */
    IntRegs, IntRegs, IntRegs, i32imm, 
    /* SELECT_CC_QFP_FCC */
    QFPRegs, QFPRegs, QFPRegs, i32imm, 
    /* SELECT_CC_QFP_ICC */
    QFPRegs, QFPRegs, QFPRegs, i32imm, 
    /* SELECT_CC_QFP_XCC */
    QFPRegs, QFPRegs, QFPRegs, i32imm, 
    /* SET */
    IntRegs, i32imm, 
    /* SETX */
    I64Regs, i64imm, I64Regs, 
    /* ADDCCri */
    IntRegs, IntRegs, simm13Op, 
    /* ADDCCrr */
    IntRegs, IntRegs, IntRegs, 
    /* ADDCri */
    IntRegs, IntRegs, simm13Op, 
    /* ADDCrr */
    IntRegs, IntRegs, IntRegs, 
    /* ADDEri */
    IntRegs, IntRegs, simm13Op, 
    /* ADDErr */
    IntRegs, IntRegs, IntRegs, 
    /* ADDXC */
    I64Regs, I64Regs, I64Regs, 
    /* ADDXCCC */
    I64Regs, I64Regs, I64Regs, 
    /* ADDri */
    IntRegs, IntRegs, simm13Op, 
    /* ADDrr */
    IntRegs, IntRegs, IntRegs, 
    /* ALIGNADDR */
    I64Regs, I64Regs, I64Regs, 
    /* ALIGNADDRL */
    I64Regs, I64Regs, I64Regs, 
    /* ANDCCri */
    IntRegs, IntRegs, simm13Op, 
    /* ANDCCrr */
    IntRegs, IntRegs, IntRegs, 
    /* ANDNCCri */
    IntRegs, IntRegs, simm13Op, 
    /* ANDNCCrr */
    IntRegs, IntRegs, IntRegs, 
    /* ANDNri */
    IntRegs, IntRegs, simm13Op, 
    /* ANDNrr */
    IntRegs, IntRegs, IntRegs, 
    /* ANDri */
    IntRegs, IntRegs, simm13Op, 
    /* ANDrr */
    IntRegs, IntRegs, IntRegs, 
    /* ARRAY16 */
    I64Regs, I64Regs, I64Regs, 
    /* ARRAY32 */
    I64Regs, I64Regs, I64Regs, 
    /* ARRAY8 */
    I64Regs, I64Regs, I64Regs, 
    /* BA */
    brtarget, 
    /* BCOND */
    brtarget, CCOp, 
    /* BCONDA */
    brtarget, CCOp, 
    /* BINDri */
    -1, i32imm, 
    /* BINDrr */
    -1, -1, 
    /* BMASK */
    I64Regs, I64Regs, I64Regs, 
    /* BPFCC */
    bprtarget, CCOp, FCCRegs, 
    /* BPFCCA */
    bprtarget, CCOp, FCCRegs, 
    /* BPFCCANT */
    bprtarget, CCOp, FCCRegs, 
    /* BPFCCNT */
    bprtarget, CCOp, FCCRegs, 
    /* BPICC */
    bprtarget, CCOp, 
    /* BPICCA */
    bprtarget, CCOp, 
    /* BPICCANT */
    bprtarget, CCOp, 
    /* BPICCNT */
    bprtarget, CCOp, 
    /* BPR */
    bprtarget16, RegCCOp, I64Regs, 
    /* BPRA */
    bprtarget16, RegCCOp, I64Regs, 
    /* BPRANT */
    bprtarget16, RegCCOp, I64Regs, 
    /* BPRNT */
    bprtarget16, RegCCOp, I64Regs, 
    /* BPXCC */
    bprtarget, CCOp, 
    /* BPXCCA */
    bprtarget, CCOp, 
    /* BPXCCANT */
    bprtarget, CCOp, 
    /* BPXCCNT */
    bprtarget, CCOp, 
    /* BSHUFFLE */
    DFPRegs, DFPRegs, DFPRegs, 
    /* CALL */
    calltarget, 
    /* CALLri */
    -1, i32imm, 
    /* CALLrr */
    -1, -1, 
    /* CASAri */
    IntRegs, IntRegs, IntRegs, IntRegs, 
    /* CASArr */
    IntRegs, IntRegs, IntRegs, IntRegs, ASITag, 
    /* CASXAri */
    I64Regs, I64Regs, I64Regs, I64Regs, 
    /* CASXArr */
    I64Regs, I64Regs, I64Regs, I64Regs, ASITag, 
    /* CBCOND */
    brtarget, CCOp, 
    /* CBCONDA */
    brtarget, CCOp, 
    /* CMASK16 */
    I64Regs, 
    /* CMASK32 */
    I64Regs, 
    /* CMASK8 */
    I64Regs, 
    /* DONE */
    /* EDGE16 */
    I64Regs, I64Regs, I64Regs, 
    /* EDGE16L */
    I64Regs, I64Regs, I64Regs, 
    /* EDGE16LN */
    I64Regs, I64Regs, I64Regs, 
    /* EDGE16N */
    I64Regs, I64Regs, I64Regs, 
    /* EDGE32 */
    I64Regs, I64Regs, I64Regs, 
    /* EDGE32L */
    I64Regs, I64Regs, I64Regs, 
    /* EDGE32LN */
    I64Regs, I64Regs, I64Regs, 
    /* EDGE32N */
    I64Regs, I64Regs, I64Regs, 
    /* EDGE8 */
    I64Regs, I64Regs, I64Regs, 
    /* EDGE8L */
    I64Regs, I64Regs, I64Regs, 
    /* EDGE8LN */
    I64Regs, I64Regs, I64Regs, 
    /* EDGE8N */
    I64Regs, I64Regs, I64Regs, 
    /* FABSD */
    DFPRegs, DFPRegs, 
    /* FABSQ */
    QFPRegs, QFPRegs, 
    /* FABSS */
    FPRegs, FPRegs, 
    /* FADDD */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FADDQ */
    QFPRegs, QFPRegs, QFPRegs, 
    /* FADDS */
    FPRegs, FPRegs, FPRegs, 
    /* FALIGNADATA */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FAND */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FANDNOT1 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FANDNOT1S */
    FPRegs, FPRegs, FPRegs, 
    /* FANDNOT2 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FANDNOT2S */
    FPRegs, FPRegs, FPRegs, 
    /* FANDS */
    FPRegs, FPRegs, FPRegs, 
    /* FBCOND */
    brtarget, CCOp, 
    /* FBCONDA */
    brtarget, CCOp, 
    /* FBCONDA_V9 */
    bprtarget, CCOp, 
    /* FBCOND_V9 */
    bprtarget, CCOp, 
    /* FCHKSM16 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FCMPD */
    DFPRegs, DFPRegs, 
    /* FCMPD_V9 */
    DFPRegs, DFPRegs, 
    /* FCMPEQ16 */
    I64Regs, DFPRegs, DFPRegs, 
    /* FCMPEQ32 */
    I64Regs, DFPRegs, DFPRegs, 
    /* FCMPGT16 */
    I64Regs, DFPRegs, DFPRegs, 
    /* FCMPGT32 */
    I64Regs, DFPRegs, DFPRegs, 
    /* FCMPLE16 */
    I64Regs, DFPRegs, DFPRegs, 
    /* FCMPLE32 */
    I64Regs, DFPRegs, DFPRegs, 
    /* FCMPNE16 */
    I64Regs, DFPRegs, DFPRegs, 
    /* FCMPNE32 */
    I64Regs, DFPRegs, DFPRegs, 
    /* FCMPQ */
    QFPRegs, QFPRegs, 
    /* FCMPQ_V9 */
    QFPRegs, QFPRegs, 
    /* FCMPS */
    FPRegs, FPRegs, 
    /* FCMPS_V9 */
    FPRegs, FPRegs, 
    /* FDIVD */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FDIVQ */
    QFPRegs, QFPRegs, QFPRegs, 
    /* FDIVS */
    FPRegs, FPRegs, FPRegs, 
    /* FDMULQ */
    QFPRegs, DFPRegs, DFPRegs, 
    /* FDTOI */
    FPRegs, DFPRegs, 
    /* FDTOQ */
    QFPRegs, DFPRegs, 
    /* FDTOS */
    FPRegs, DFPRegs, 
    /* FDTOX */
    DFPRegs, DFPRegs, 
    /* FEXPAND */
    DFPRegs, DFPRegs, 
    /* FHADDD */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FHADDS */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FHSUBD */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FHSUBS */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FITOD */
    DFPRegs, FPRegs, 
    /* FITOQ */
    QFPRegs, FPRegs, 
    /* FITOS */
    FPRegs, FPRegs, 
    /* FLCMPD */
    FCCRegs, DFPRegs, DFPRegs, 
    /* FLCMPS */
    FCCRegs, DFPRegs, DFPRegs, 
    /* FLUSH */
    /* FLUSHW */
    /* FLUSHri */
    -1, i32imm, 
    /* FLUSHrr */
    -1, -1, 
    /* FMEAN16 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FMOVD */
    DFPRegs, DFPRegs, 
    /* FMOVD_FCC */
    DFPRegs, DFPRegs, DFPRegs, CCOp, 
    /* FMOVD_ICC */
    DFPRegs, DFPRegs, DFPRegs, CCOp, 
    /* FMOVD_XCC */
    DFPRegs, DFPRegs, DFPRegs, CCOp, 
    /* FMOVQ */
    QFPRegs, QFPRegs, 
    /* FMOVQ_FCC */
    QFPRegs, QFPRegs, QFPRegs, CCOp, 
    /* FMOVQ_ICC */
    QFPRegs, QFPRegs, QFPRegs, CCOp, 
    /* FMOVQ_XCC */
    QFPRegs, QFPRegs, QFPRegs, CCOp, 
    /* FMOVRD */
    DFPRegs, I64Regs, DFPRegs, DFPRegs, RegCCOp, 
    /* FMOVRQ */
    QFPRegs, I64Regs, QFPRegs, QFPRegs, RegCCOp, 
    /* FMOVRS */
    FPRegs, I64Regs, FPRegs, FPRegs, RegCCOp, 
    /* FMOVS */
    FPRegs, FPRegs, 
    /* FMOVS_FCC */
    FPRegs, FPRegs, FPRegs, CCOp, 
    /* FMOVS_ICC */
    FPRegs, FPRegs, FPRegs, CCOp, 
    /* FMOVS_XCC */
    FPRegs, FPRegs, FPRegs, CCOp, 
    /* FMUL8SUX16 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FMUL8ULX16 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FMUL8X16 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FMUL8X16AL */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FMUL8X16AU */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FMULD */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FMULD8SUX16 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FMULD8ULX16 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FMULQ */
    QFPRegs, QFPRegs, QFPRegs, 
    /* FMULS */
    FPRegs, FPRegs, FPRegs, 
    /* FNADDD */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FNADDS */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FNAND */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FNANDS */
    FPRegs, FPRegs, FPRegs, 
    /* FNEGD */
    DFPRegs, DFPRegs, 
    /* FNEGQ */
    QFPRegs, QFPRegs, 
    /* FNEGS */
    FPRegs, FPRegs, 
    /* FNHADDD */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FNHADDS */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FNMULD */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FNMULS */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FNOR */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FNORS */
    FPRegs, FPRegs, FPRegs, 
    /* FNOT1 */
    DFPRegs, DFPRegs, 
    /* FNOT1S */
    FPRegs, FPRegs, 
    /* FNOT2 */
    DFPRegs, DFPRegs, 
    /* FNOT2S */
    FPRegs, FPRegs, 
    /* FNSMULD */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FONE */
    DFPRegs, DFPRegs, 
    /* FONES */
    FPRegs, FPRegs, 
    /* FOR */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FORNOT1 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FORNOT1S */
    FPRegs, FPRegs, FPRegs, 
    /* FORNOT2 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FORNOT2S */
    FPRegs, FPRegs, FPRegs, 
    /* FORS */
    FPRegs, FPRegs, FPRegs, 
    /* FPACK16 */
    DFPRegs, DFPRegs, 
    /* FPACK32 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FPACKFIX */
    DFPRegs, DFPRegs, 
    /* FPADD16 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FPADD16S */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FPADD32 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FPADD32S */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FPADD64 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FPMERGE */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FPSUB16 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FPSUB16S */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FPSUB32 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FPSUB32S */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FQTOD */
    DFPRegs, QFPRegs, 
    /* FQTOI */
    FPRegs, QFPRegs, 
    /* FQTOS */
    FPRegs, QFPRegs, 
    /* FQTOX */
    DFPRegs, QFPRegs, 
    /* FSLAS16 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FSLAS32 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FSLL16 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FSLL32 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FSMULD */
    DFPRegs, FPRegs, FPRegs, 
    /* FSQRTD */
    DFPRegs, DFPRegs, 
    /* FSQRTQ */
    QFPRegs, QFPRegs, 
    /* FSQRTS */
    FPRegs, FPRegs, 
    /* FSRA16 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FSRA32 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FSRC1 */
    DFPRegs, DFPRegs, 
    /* FSRC1S */
    FPRegs, FPRegs, 
    /* FSRC2 */
    DFPRegs, DFPRegs, 
    /* FSRC2S */
    FPRegs, FPRegs, 
    /* FSRL16 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FSRL32 */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FSTOD */
    DFPRegs, FPRegs, 
    /* FSTOI */
    FPRegs, FPRegs, 
    /* FSTOQ */
    QFPRegs, FPRegs, 
    /* FSTOX */
    DFPRegs, FPRegs, 
    /* FSUBD */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FSUBQ */
    QFPRegs, QFPRegs, QFPRegs, 
    /* FSUBS */
    FPRegs, FPRegs, FPRegs, 
    /* FXNOR */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FXNORS */
    FPRegs, FPRegs, FPRegs, 
    /* FXOR */
    DFPRegs, DFPRegs, DFPRegs, 
    /* FXORS */
    FPRegs, FPRegs, FPRegs, 
    /* FXTOD */
    DFPRegs, DFPRegs, 
    /* FXTOQ */
    QFPRegs, DFPRegs, 
    /* FXTOS */
    FPRegs, DFPRegs, 
    /* FZERO */
    DFPRegs, DFPRegs, 
    /* FZEROS */
    FPRegs, FPRegs, 
    /* GDOP_LDXrr */
    I64Regs, -1, -1, TailRelocSymGOTLoad, 
    /* GDOP_LDrr */
    IntRegs, -1, -1, TailRelocSymGOTLoad, 
    /* JMPLri */
    IntRegs, -1, i32imm, 
    /* JMPLrr */
    IntRegs, -1, -1, 
    /* LDAri */
    IntRegs, -1, i32imm, 
    /* LDArr */
    IntRegs, -1, -1, ASITag, 
    /* LDCSRri */
    -1, i32imm, 
    /* LDCSRrr */
    -1, -1, 
    /* LDCri */
    CoprocRegs, -1, i32imm, 
    /* LDCrr */
    CoprocRegs, -1, -1, 
    /* LDDAri */
    IntPair, -1, i32imm, 
    /* LDDArr */
    IntPair, -1, -1, ASITag, 
    /* LDDCri */
    CoprocPair, -1, i32imm, 
    /* LDDCrr */
    CoprocPair, -1, -1, 
    /* LDDFAri */
    DFPRegs, -1, i32imm, 
    /* LDDFArr */
    DFPRegs, -1, -1, ASITag, 
    /* LDDFri */
    DFPRegs, -1, i32imm, 
    /* LDDFrr */
    DFPRegs, -1, -1, 
    /* LDDri */
    IntPair, -1, i32imm, 
    /* LDDrr */
    IntPair, -1, -1, 
    /* LDFAri */
    FPRegs, -1, i32imm, 
    /* LDFArr */
    FPRegs, -1, -1, ASITag, 
    /* LDFSRri */
    -1, i32imm, 
    /* LDFSRrr */
    -1, -1, 
    /* LDFri */
    FPRegs, -1, i32imm, 
    /* LDFrr */
    FPRegs, -1, -1, 
    /* LDQFAri */
    QFPRegs, -1, i32imm, 
    /* LDQFArr */
    QFPRegs, -1, -1, ASITag, 
    /* LDQFri */
    QFPRegs, -1, i32imm, 
    /* LDQFrr */
    QFPRegs, -1, -1, 
    /* LDSBAri */
    IntRegs, -1, i32imm, 
    /* LDSBArr */
    IntRegs, -1, -1, ASITag, 
    /* LDSBri */
    IntRegs, -1, i32imm, 
    /* LDSBrr */
    IntRegs, -1, -1, 
    /* LDSHAri */
    IntRegs, -1, i32imm, 
    /* LDSHArr */
    IntRegs, -1, -1, ASITag, 
    /* LDSHri */
    IntRegs, -1, i32imm, 
    /* LDSHrr */
    IntRegs, -1, -1, 
    /* LDSTUBAri */
    IntRegs, -1, i32imm, 
    /* LDSTUBArr */
    IntRegs, -1, -1, ASITag, 
    /* LDSTUBri */
    IntRegs, -1, i32imm, 
    /* LDSTUBrr */
    IntRegs, -1, -1, 
    /* LDSWAri */
    I64Regs, -1, i32imm, 
    /* LDSWArr */
    I64Regs, -1, -1, ASITag, 
    /* LDSWri */
    I64Regs, -1, i32imm, 
    /* LDSWrr */
    I64Regs, -1, -1, 
    /* LDUBAri */
    IntRegs, -1, i32imm, 
    /* LDUBArr */
    IntRegs, -1, -1, ASITag, 
    /* LDUBri */
    IntRegs, -1, i32imm, 
    /* LDUBrr */
    IntRegs, -1, -1, 
    /* LDUHAri */
    IntRegs, -1, i32imm, 
    /* LDUHArr */
    IntRegs, -1, -1, ASITag, 
    /* LDUHri */
    IntRegs, -1, i32imm, 
    /* LDUHrr */
    IntRegs, -1, -1, 
    /* LDXAri */
    I64Regs, -1, i32imm, 
    /* LDXArr */
    I64Regs, -1, -1, ASITag, 
    /* LDXFSRri */
    -1, i32imm, 
    /* LDXFSRrr */
    -1, -1, 
    /* LDXri */
    I64Regs, -1, i32imm, 
    /* LDXrr */
    I64Regs, -1, -1, 
    /* LDri */
    IntRegs, -1, i32imm, 
    /* LDrr */
    IntRegs, -1, -1, 
    /* LZCNT */
    I64Regs, I64Regs, 
    /* MEMBARi */
    MembarTag, 
    /* MOVDTOX */
    I64Regs, DFPRegs, 
    /* MOVFCCri */
    IntRegs, i32imm, IntRegs, CCOp, 
    /* MOVFCCrr */
    IntRegs, IntRegs, IntRegs, CCOp, 
    /* MOVICCri */
    IntRegs, i32imm, IntRegs, CCOp, 
    /* MOVICCrr */
    IntRegs, IntRegs, IntRegs, CCOp, 
    /* MOVRri */
    IntRegs, I64Regs, i32imm, IntRegs, RegCCOp, 
    /* MOVRrr */
    IntRegs, I64Regs, IntRegs, IntRegs, RegCCOp, 
    /* MOVSTOSW */
    I64Regs, DFPRegs, 
    /* MOVSTOUW */
    I64Regs, DFPRegs, 
    /* MOVWTOS */
    DFPRegs, I64Regs, 
    /* MOVXCCri */
    IntRegs, i32imm, IntRegs, CCOp, 
    /* MOVXCCrr */
    IntRegs, IntRegs, IntRegs, CCOp, 
    /* MOVXTOD */
    DFPRegs, I64Regs, 
    /* MULSCCri */
    IntRegs, IntRegs, simm13Op, 
    /* MULSCCrr */
    IntRegs, IntRegs, IntRegs, 
    /* MULXri */
    IntRegs, IntRegs, i64imm, 
    /* MULXrr */
    I64Regs, I64Regs, I64Regs, 
    /* NOP */
    /* ORCCri */
    IntRegs, IntRegs, simm13Op, 
    /* ORCCrr */
    IntRegs, IntRegs, IntRegs, 
    /* ORNCCri */
    IntRegs, IntRegs, simm13Op, 
    /* ORNCCrr */
    IntRegs, IntRegs, IntRegs, 
    /* ORNri */
    IntRegs, IntRegs, simm13Op, 
    /* ORNrr */
    IntRegs, IntRegs, IntRegs, 
    /* ORri */
    IntRegs, IntRegs, simm13Op, 
    /* ORrr */
    IntRegs, IntRegs, IntRegs, 
    /* PDIST */
    DFPRegs, DFPRegs, DFPRegs, 
    /* PDISTN */
    DFPRegs, DFPRegs, DFPRegs, 
    /* POPCrr */
    IntRegs, IntRegs, 
    /* PREFETCHAi */
    -1, i32imm, PrefetchTag, 
    /* PREFETCHAr */
    -1, -1, ASITag, PrefetchTag, 
    /* PREFETCHi */
    -1, i32imm, PrefetchTag, 
    /* PREFETCHr */
    -1, -1, PrefetchTag, 
    /* PWRPSRri */
    IntRegs, simm13Op, 
    /* PWRPSRrr */
    IntRegs, IntRegs, 
    /* RDASR */
    IntRegs, ASRRegs, 
    /* RDFQ */
    IntRegs, 
    /* RDPR */
    IntRegs, PRRegs, 
    /* RDPSR */
    IntRegs, 
    /* RDTBR */
    IntRegs, 
    /* RDWIM */
    IntRegs, 
    /* RESTORED */
    /* RESTOREri */
    IntRegs, IntRegs, simm13Op, 
    /* RESTORErr */
    IntRegs, IntRegs, IntRegs, 
    /* RET */
    i32imm, 
    /* RETL */
    i32imm, 
    /* RETRY */
    /* RETTri */
    -1, i32imm, 
    /* RETTrr */
    -1, -1, 
    /* SAVED */
    /* SAVEri */
    IntRegs, IntRegs, simm13Op, 
    /* SAVErr */
    IntRegs, IntRegs, IntRegs, 
    /* SDIVCCri */
    IntRegs, IntRegs, simm13Op, 
    /* SDIVCCrr */
    IntRegs, IntRegs, IntRegs, 
    /* SDIVXri */
    IntRegs, IntRegs, i64imm, 
    /* SDIVXrr */
    I64Regs, I64Regs, I64Regs, 
    /* SDIVri */
    IntRegs, IntRegs, simm13Op, 
    /* SDIVrr */
    IntRegs, IntRegs, IntRegs, 
    /* SETHIi */
    IntRegs, i32imm, 
    /* SHUTDOWN */
    /* SIAM */
    /* SIR */
    simm13Op, 
    /* SLLXri */
    I64Regs, I64Regs, shift_imm6, 
    /* SLLXrr */
    I64Regs, I64Regs, IntRegs, 
    /* SLLri */
    IntRegs, IntRegs, shift_imm5, 
    /* SLLrr */
    IntRegs, IntRegs, IntRegs, 
    /* SMACri */
    IntRegs, IntRegs, simm13Op, ASRRegs, 
    /* SMACrr */
    IntRegs, IntRegs, IntRegs, ASRRegs, 
    /* SMULCCri */
    IntRegs, IntRegs, simm13Op, 
    /* SMULCCrr */
    IntRegs, IntRegs, IntRegs, 
    /* SMULri */
    IntRegs, IntRegs, simm13Op, 
    /* SMULrr */
    IntRegs, IntRegs, IntRegs, 
    /* SRAXri */
    I64Regs, I64Regs, shift_imm6, 
    /* SRAXrr */
    I64Regs, I64Regs, IntRegs, 
    /* SRAri */
    IntRegs, IntRegs, shift_imm5, 
    /* SRArr */
    IntRegs, IntRegs, IntRegs, 
    /* SRLXri */
    I64Regs, I64Regs, shift_imm6, 
    /* SRLXrr */
    I64Regs, I64Regs, IntRegs, 
    /* SRLri */
    IntRegs, IntRegs, shift_imm5, 
    /* SRLrr */
    IntRegs, IntRegs, IntRegs, 
    /* STAri */
    -1, i32imm, IntRegs, 
    /* STArr */
    -1, -1, IntRegs, ASITag, 
    /* STBAR */
    /* STBAri */
    -1, i32imm, IntRegs, 
    /* STBArr */
    -1, -1, IntRegs, ASITag, 
    /* STBri */
    -1, i32imm, IntRegs, 
    /* STBrr */
    -1, -1, IntRegs, 
    /* STCSRri */
    -1, i32imm, 
    /* STCSRrr */
    -1, -1, 
    /* STCri */
    -1, i32imm, CoprocRegs, 
    /* STCrr */
    -1, -1, CoprocRegs, 
    /* STDAri */
    -1, i32imm, IntPair, 
    /* STDArr */
    -1, -1, IntPair, ASITag, 
    /* STDCQri */
    -1, i32imm, 
    /* STDCQrr */
    -1, -1, 
    /* STDCri */
    -1, i32imm, CoprocPair, 
    /* STDCrr */
    -1, -1, CoprocPair, 
    /* STDFAri */
    -1, i32imm, DFPRegs, 
    /* STDFArr */
    -1, -1, DFPRegs, ASITag, 
    /* STDFQri */
    -1, i32imm, 
    /* STDFQrr */
    -1, -1, 
    /* STDFri */
    -1, i32imm, DFPRegs, 
    /* STDFrr */
    -1, -1, DFPRegs, 
    /* STDri */
    -1, i32imm, IntPair, 
    /* STDrr */
    -1, -1, IntPair, 
    /* STFAri */
    -1, i32imm, FPRegs, 
    /* STFArr */
    -1, -1, FPRegs, ASITag, 
    /* STFSRri */
    -1, i32imm, 
    /* STFSRrr */
    -1, -1, 
    /* STFri */
    -1, i32imm, FPRegs, 
    /* STFrr */
    -1, -1, FPRegs, 
    /* STHAri */
    -1, i32imm, IntRegs, 
    /* STHArr */
    -1, -1, IntRegs, ASITag, 
    /* STHri */
    -1, i32imm, IntRegs, 
    /* STHrr */
    -1, -1, IntRegs, 
    /* STQFAri */
    -1, i32imm, QFPRegs, 
    /* STQFArr */
    -1, -1, QFPRegs, ASITag, 
    /* STQFri */
    -1, i32imm, QFPRegs, 
    /* STQFrr */
    -1, -1, QFPRegs, 
    /* STXAri */
    -1, i32imm, I64Regs, 
    /* STXArr */
    -1, -1, I64Regs, ASITag, 
    /* STXFSRri */
    -1, i32imm, 
    /* STXFSRrr */
    -1, -1, 
    /* STXri */
    -1, i32imm, I64Regs, 
    /* STXrr */
    -1, -1, I64Regs, 
    /* STri */
    -1, i32imm, IntRegs, 
    /* STrr */
    -1, -1, IntRegs, 
    /* SUBCCri */
    IntRegs, IntRegs, simm13Op, 
    /* SUBCCrr */
    IntRegs, IntRegs, IntRegs, 
    /* SUBCri */
    IntRegs, IntRegs, simm13Op, 
    /* SUBCrr */
    IntRegs, IntRegs, IntRegs, 
    /* SUBEri */
    IntRegs, IntRegs, simm13Op, 
    /* SUBErr */
    IntRegs, IntRegs, IntRegs, 
    /* SUBri */
    IntRegs, IntRegs, simm13Op, 
    /* SUBrr */
    IntRegs, IntRegs, IntRegs, 
    /* SWAPAri */
    IntRegs, -1, i32imm, IntRegs, 
    /* SWAPArr */
    IntRegs, -1, -1, ASITag, IntRegs, 
    /* SWAPri */
    IntRegs, -1, i32imm, IntRegs, 
    /* SWAPrr */
    IntRegs, -1, -1, IntRegs, 
    /* TA1 */
    /* TA3 */
    /* TA5 */
    /* TADDCCTVri */
    IntRegs, IntRegs, simm13Op, 
    /* TADDCCTVrr */
    IntRegs, IntRegs, IntRegs, 
    /* TADDCCri */
    IntRegs, IntRegs, simm13Op, 
    /* TADDCCrr */
    IntRegs, IntRegs, IntRegs, 
    /* TAIL_CALL */
    calltarget, 
    /* TAIL_CALLri */
    -1, i32imm, 
    /* TICCri */
    IntRegs, i32imm, CCOp, 
    /* TICCrr */
    IntRegs, IntRegs, CCOp, 
    /* TLS_ADDrr */
    IntRegs, IntRegs, IntRegs, TailRelocSymTLSAdd, 
    /* TLS_CALL */
    calltarget, TailRelocSymTLSCall, 
    /* TLS_LDXrr */
    IntRegs, -1, -1, TailRelocSymTLSLoad, 
    /* TLS_LDrr */
    IntRegs, -1, -1, TailRelocSymTLSLoad, 
    /* TRAPri */
    IntRegs, i32imm, CCOp, 
    /* TRAPrr */
    IntRegs, IntRegs, CCOp, 
    /* TSUBCCTVri */
    IntRegs, IntRegs, simm13Op, 
    /* TSUBCCTVrr */
    IntRegs, IntRegs, IntRegs, 
    /* TSUBCCri */
    IntRegs, IntRegs, simm13Op, 
    /* TSUBCCrr */
    IntRegs, IntRegs, IntRegs, 
    /* TXCCri */
    IntRegs, i32imm, CCOp, 
    /* TXCCrr */
    IntRegs, IntRegs, CCOp, 
    /* UDIVCCri */
    IntRegs, IntRegs, simm13Op, 
    /* UDIVCCrr */
    IntRegs, IntRegs, IntRegs, 
    /* UDIVXri */
    IntRegs, IntRegs, i64imm, 
    /* UDIVXrr */
    I64Regs, I64Regs, I64Regs, 
    /* UDIVri */
    IntRegs, IntRegs, simm13Op, 
    /* UDIVrr */
    IntRegs, IntRegs, IntRegs, 
    /* UMACri */
    IntRegs, IntRegs, simm13Op, ASRRegs, 
    /* UMACrr */
    IntRegs, IntRegs, IntRegs, ASRRegs, 
    /* UMULCCri */
    IntRegs, IntRegs, simm13Op, 
    /* UMULCCrr */
    IntRegs, IntRegs, IntRegs, 
    /* UMULXHI */
    I64Regs, I64Regs, I64Regs, 
    /* UMULri */
    IntRegs, IntRegs, simm13Op, 
    /* UMULrr */
    IntRegs, IntRegs, IntRegs, 
    /* UNIMP */
    i32imm, 
    /* V9FCMPD */
    FCCRegs, DFPRegs, DFPRegs, 
    /* V9FCMPED */
    FCCRegs, DFPRegs, DFPRegs, 
    /* V9FCMPEQ */
    FCCRegs, QFPRegs, QFPRegs, 
    /* V9FCMPES */
    FCCRegs, FPRegs, FPRegs, 
    /* V9FCMPQ */
    FCCRegs, QFPRegs, QFPRegs, 
    /* V9FCMPS */
    FCCRegs, FPRegs, FPRegs, 
    /* V9FMOVD_FCC */
    DFPRegs, FCCRegs, DFPRegs, DFPRegs, CCOp, 
    /* V9FMOVQ_FCC */
    QFPRegs, FCCRegs, QFPRegs, QFPRegs, CCOp, 
    /* V9FMOVS_FCC */
    FPRegs, FCCRegs, FPRegs, FPRegs, CCOp, 
    /* V9MOVFCCri */
    IntRegs, FCCRegs, i32imm, IntRegs, CCOp, 
    /* V9MOVFCCrr */
    IntRegs, FCCRegs, IntRegs, IntRegs, CCOp, 
    /* WRASRri */
    ASRRegs, IntRegs, simm13Op, 
    /* WRASRrr */
    ASRRegs, IntRegs, IntRegs, 
    /* WRPRri */
    PRRegs, IntRegs, simm13Op, 
    /* WRPRrr */
    PRRegs, IntRegs, IntRegs, 
    /* WRPSRri */
    IntRegs, simm13Op, 
    /* WRPSRrr */
    IntRegs, IntRegs, 
    /* WRTBRri */
    IntRegs, simm13Op, 
    /* WRTBRrr */
    IntRegs, IntRegs, 
    /* WRWIMri */
    IntRegs, simm13Op, 
    /* WRWIMrr */
    IntRegs, IntRegs, 
    /* XMULX */
    I64Regs, I64Regs, I64Regs, 
    /* XMULXHI */
    I64Regs, I64Regs, I64Regs, 
    /* XNORCCri */
    IntRegs, IntRegs, simm13Op, 
    /* XNORCCrr */
    IntRegs, IntRegs, IntRegs, 
    /* XNORri */
    IntRegs, IntRegs, simm13Op, 
    /* XNORrr */
    IntRegs, IntRegs, IntRegs, 
    /* XORCCri */
    IntRegs, IntRegs, simm13Op, 
    /* XORCCrr */
    IntRegs, IntRegs, IntRegs, 
    /* XORri */
    IntRegs, IntRegs, simm13Op, 
    /* XORrr */
    IntRegs, IntRegs, IntRegs, 
  };
  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
}
} // end namespace SP
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPE

#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
#undef GET_INSTRINFO_MEM_OPERAND_SIZE
namespace llvm {
namespace SP {
LLVM_READONLY
static int getMemOperandSize(int OpType) {
  switch (OpType) {
  default: return 0;
  }
}
} // end namespace SP
} // end namespace llvm
#endif // GET_INSTRINFO_MEM_OPERAND_SIZE

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
namespace llvm {
namespace Sparc {
LLVM_READONLY static unsigned
getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return LogicalOpIdx;
}
LLVM_READONLY static inline unsigned
getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
  auto S = 0U;
  for (auto i = 0U; i < LogicalOpIdx; ++i)
    S += getLogicalOperandSize(Opcode, i);
  return S;
}
} // end namespace Sparc
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
namespace llvm {
namespace Sparc {
LLVM_READONLY static int
getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return -1;
}
} // end namespace Sparc
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP

#ifdef GET_INSTRINFO_MC_HELPER_DECLS
#undef GET_INSTRINFO_MC_HELPER_DECLS

namespace llvm {
class MCInst;
class FeatureBitset;

namespace Sparc_MC {

void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);

} // end namespace Sparc_MC
} // end namespace llvm

#endif // GET_INSTRINFO_MC_HELPER_DECLS

#ifdef GET_INSTRINFO_MC_HELPERS
#undef GET_INSTRINFO_MC_HELPERS

namespace llvm {
namespace Sparc_MC {

} // end namespace Sparc_MC
} // end namespace llvm

#endif // GET_GENISTRINFO_MC_HELPERS

#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
    defined(GET_AVAILABLE_OPCODE_CHECKER)
#define GET_COMPUTE_FEATURES
#endif
#ifdef GET_COMPUTE_FEATURES
#undef GET_COMPUTE_FEATURES
namespace llvm {
namespace Sparc_MC {

// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
  Feature_UseSoftMulDivBit = 6,
  Feature_HasV9Bit = 2,
  Feature_HasVISBit = 3,
  Feature_HasVIS2Bit = 4,
  Feature_HasVIS3Bit = 5,
  Feature_HasCASABit = 0,
  Feature_HasPWRPSRBit = 1,
};

inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
  FeatureBitset Features;
  if (FB[Sparc::FeatureSoftMulDiv])
    Features.set(Feature_UseSoftMulDivBit);
  if (FB[Sparc::FeatureV9])
    Features.set(Feature_HasV9Bit);
  if (FB[Sparc::FeatureVIS])
    Features.set(Feature_HasVISBit);
  if (FB[Sparc::FeatureVIS2])
    Features.set(Feature_HasVIS2Bit);
  if (FB[Sparc::FeatureVIS3])
    Features.set(Feature_HasVIS3Bit);
  if (FB[Sparc::LeonCASA] || FB[Sparc::FeatureV9])
    Features.set(Feature_HasCASABit);
  if (FB[Sparc::FeaturePWRPSR])
    Features.set(Feature_HasPWRPSRBit);
  return Features;
}

inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
  enum : uint8_t {
    CEFBS_None,
    CEFBS_HasCASA,
    CEFBS_HasPWRPSR,
    CEFBS_HasV9,
    CEFBS_HasVIS,
    CEFBS_HasVIS2,
    CEFBS_HasVIS3,
  };

  static constexpr FeatureBitset FeatureBitsets[] = {
    {}, // CEFBS_None
    {Feature_HasCASABit, },
    {Feature_HasPWRPSRBit, },
    {Feature_HasV9Bit, },
    {Feature_HasVISBit, },
    {Feature_HasVIS2Bit, },
    {Feature_HasVIS3Bit, },
  };
  static constexpr uint8_t RequiredFeaturesRefs[] = {
    CEFBS_None, // PHI = 0
    CEFBS_None, // INLINEASM = 1
    CEFBS_None, // INLINEASM_BR = 2
    CEFBS_None, // CFI_INSTRUCTION = 3
    CEFBS_None, // EH_LABEL = 4
    CEFBS_None, // GC_LABEL = 5
    CEFBS_None, // ANNOTATION_LABEL = 6
    CEFBS_None, // KILL = 7
    CEFBS_None, // EXTRACT_SUBREG = 8
    CEFBS_None, // INSERT_SUBREG = 9
    CEFBS_None, // IMPLICIT_DEF = 10
    CEFBS_None, // INIT_UNDEF = 11
    CEFBS_None, // SUBREG_TO_REG = 12
    CEFBS_None, // COPY_TO_REGCLASS = 13
    CEFBS_None, // DBG_VALUE = 14
    CEFBS_None, // DBG_VALUE_LIST = 15
    CEFBS_None, // DBG_INSTR_REF = 16
    CEFBS_None, // DBG_PHI = 17
    CEFBS_None, // DBG_LABEL = 18
    CEFBS_None, // REG_SEQUENCE = 19
    CEFBS_None, // COPY = 20
    CEFBS_None, // BUNDLE = 21
    CEFBS_None, // LIFETIME_START = 22
    CEFBS_None, // LIFETIME_END = 23
    CEFBS_None, // PSEUDO_PROBE = 24
    CEFBS_None, // ARITH_FENCE = 25
    CEFBS_None, // STACKMAP = 26
    CEFBS_None, // FENTRY_CALL = 27
    CEFBS_None, // PATCHPOINT = 28
    CEFBS_None, // LOAD_STACK_GUARD = 29
    CEFBS_None, // PREALLOCATED_SETUP = 30
    CEFBS_None, // PREALLOCATED_ARG = 31
    CEFBS_None, // STATEPOINT = 32
    CEFBS_None, // LOCAL_ESCAPE = 33
    CEFBS_None, // FAULTING_OP = 34
    CEFBS_None, // PATCHABLE_OP = 35
    CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 36
    CEFBS_None, // PATCHABLE_RET = 37
    CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 38
    CEFBS_None, // PATCHABLE_TAIL_CALL = 39
    CEFBS_None, // PATCHABLE_EVENT_CALL = 40
    CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 41
    CEFBS_None, // ICALL_BRANCH_FUNNEL = 42
    CEFBS_None, // FAKE_USE = 43
    CEFBS_None, // MEMBARRIER = 44
    CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 45
    CEFBS_None, // CONVERGENCECTRL_ENTRY = 46
    CEFBS_None, // CONVERGENCECTRL_ANCHOR = 47
    CEFBS_None, // CONVERGENCECTRL_LOOP = 48
    CEFBS_None, // CONVERGENCECTRL_GLUE = 49
    CEFBS_None, // G_ASSERT_SEXT = 50
    CEFBS_None, // G_ASSERT_ZEXT = 51
    CEFBS_None, // G_ASSERT_ALIGN = 52
    CEFBS_None, // G_ADD = 53
    CEFBS_None, // G_SUB = 54
    CEFBS_None, // G_MUL = 55
    CEFBS_None, // G_SDIV = 56
    CEFBS_None, // G_UDIV = 57
    CEFBS_None, // G_SREM = 58
    CEFBS_None, // G_UREM = 59
    CEFBS_None, // G_SDIVREM = 60
    CEFBS_None, // G_UDIVREM = 61
    CEFBS_None, // G_AND = 62
    CEFBS_None, // G_OR = 63
    CEFBS_None, // G_XOR = 64
    CEFBS_None, // G_IMPLICIT_DEF = 65
    CEFBS_None, // G_PHI = 66
    CEFBS_None, // G_FRAME_INDEX = 67
    CEFBS_None, // G_GLOBAL_VALUE = 68
    CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 69
    CEFBS_None, // G_CONSTANT_POOL = 70
    CEFBS_None, // G_EXTRACT = 71
    CEFBS_None, // G_UNMERGE_VALUES = 72
    CEFBS_None, // G_INSERT = 73
    CEFBS_None, // G_MERGE_VALUES = 74
    CEFBS_None, // G_BUILD_VECTOR = 75
    CEFBS_None, // G_BUILD_VECTOR_TRUNC = 76
    CEFBS_None, // G_CONCAT_VECTORS = 77
    CEFBS_None, // G_PTRTOINT = 78
    CEFBS_None, // G_INTTOPTR = 79
    CEFBS_None, // G_BITCAST = 80
    CEFBS_None, // G_FREEZE = 81
    CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 82
    CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 83
    CEFBS_None, // G_INTRINSIC_TRUNC = 84
    CEFBS_None, // G_INTRINSIC_ROUND = 85
    CEFBS_None, // G_INTRINSIC_LRINT = 86
    CEFBS_None, // G_INTRINSIC_LLRINT = 87
    CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 88
    CEFBS_None, // G_READCYCLECOUNTER = 89
    CEFBS_None, // G_READSTEADYCOUNTER = 90
    CEFBS_None, // G_LOAD = 91
    CEFBS_None, // G_SEXTLOAD = 92
    CEFBS_None, // G_ZEXTLOAD = 93
    CEFBS_None, // G_INDEXED_LOAD = 94
    CEFBS_None, // G_INDEXED_SEXTLOAD = 95
    CEFBS_None, // G_INDEXED_ZEXTLOAD = 96
    CEFBS_None, // G_STORE = 97
    CEFBS_None, // G_INDEXED_STORE = 98
    CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 99
    CEFBS_None, // G_ATOMIC_CMPXCHG = 100
    CEFBS_None, // G_ATOMICRMW_XCHG = 101
    CEFBS_None, // G_ATOMICRMW_ADD = 102
    CEFBS_None, // G_ATOMICRMW_SUB = 103
    CEFBS_None, // G_ATOMICRMW_AND = 104
    CEFBS_None, // G_ATOMICRMW_NAND = 105
    CEFBS_None, // G_ATOMICRMW_OR = 106
    CEFBS_None, // G_ATOMICRMW_XOR = 107
    CEFBS_None, // G_ATOMICRMW_MAX = 108
    CEFBS_None, // G_ATOMICRMW_MIN = 109
    CEFBS_None, // G_ATOMICRMW_UMAX = 110
    CEFBS_None, // G_ATOMICRMW_UMIN = 111
    CEFBS_None, // G_ATOMICRMW_FADD = 112
    CEFBS_None, // G_ATOMICRMW_FSUB = 113
    CEFBS_None, // G_ATOMICRMW_FMAX = 114
    CEFBS_None, // G_ATOMICRMW_FMIN = 115
    CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 116
    CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 117
    CEFBS_None, // G_ATOMICRMW_USUB_COND = 118
    CEFBS_None, // G_ATOMICRMW_USUB_SAT = 119
    CEFBS_None, // G_FENCE = 120
    CEFBS_None, // G_PREFETCH = 121
    CEFBS_None, // G_BRCOND = 122
    CEFBS_None, // G_BRINDIRECT = 123
    CEFBS_None, // G_INVOKE_REGION_START = 124
    CEFBS_None, // G_INTRINSIC = 125
    CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 126
    CEFBS_None, // G_INTRINSIC_CONVERGENT = 127
    CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 128
    CEFBS_None, // G_ANYEXT = 129
    CEFBS_None, // G_TRUNC = 130
    CEFBS_None, // G_CONSTANT = 131
    CEFBS_None, // G_FCONSTANT = 132
    CEFBS_None, // G_VASTART = 133
    CEFBS_None, // G_VAARG = 134
    CEFBS_None, // G_SEXT = 135
    CEFBS_None, // G_SEXT_INREG = 136
    CEFBS_None, // G_ZEXT = 137
    CEFBS_None, // G_SHL = 138
    CEFBS_None, // G_LSHR = 139
    CEFBS_None, // G_ASHR = 140
    CEFBS_None, // G_FSHL = 141
    CEFBS_None, // G_FSHR = 142
    CEFBS_None, // G_ROTR = 143
    CEFBS_None, // G_ROTL = 144
    CEFBS_None, // G_ICMP = 145
    CEFBS_None, // G_FCMP = 146
    CEFBS_None, // G_SCMP = 147
    CEFBS_None, // G_UCMP = 148
    CEFBS_None, // G_SELECT = 149
    CEFBS_None, // G_UADDO = 150
    CEFBS_None, // G_UADDE = 151
    CEFBS_None, // G_USUBO = 152
    CEFBS_None, // G_USUBE = 153
    CEFBS_None, // G_SADDO = 154
    CEFBS_None, // G_SADDE = 155
    CEFBS_None, // G_SSUBO = 156
    CEFBS_None, // G_SSUBE = 157
    CEFBS_None, // G_UMULO = 158
    CEFBS_None, // G_SMULO = 159
    CEFBS_None, // G_UMULH = 160
    CEFBS_None, // G_SMULH = 161
    CEFBS_None, // G_UADDSAT = 162
    CEFBS_None, // G_SADDSAT = 163
    CEFBS_None, // G_USUBSAT = 164
    CEFBS_None, // G_SSUBSAT = 165
    CEFBS_None, // G_USHLSAT = 166
    CEFBS_None, // G_SSHLSAT = 167
    CEFBS_None, // G_SMULFIX = 168
    CEFBS_None, // G_UMULFIX = 169
    CEFBS_None, // G_SMULFIXSAT = 170
    CEFBS_None, // G_UMULFIXSAT = 171
    CEFBS_None, // G_SDIVFIX = 172
    CEFBS_None, // G_UDIVFIX = 173
    CEFBS_None, // G_SDIVFIXSAT = 174
    CEFBS_None, // G_UDIVFIXSAT = 175
    CEFBS_None, // G_FADD = 176
    CEFBS_None, // G_FSUB = 177
    CEFBS_None, // G_FMUL = 178
    CEFBS_None, // G_FMA = 179
    CEFBS_None, // G_FMAD = 180
    CEFBS_None, // G_FDIV = 181
    CEFBS_None, // G_FREM = 182
    CEFBS_None, // G_FPOW = 183
    CEFBS_None, // G_FPOWI = 184
    CEFBS_None, // G_FEXP = 185
    CEFBS_None, // G_FEXP2 = 186
    CEFBS_None, // G_FEXP10 = 187
    CEFBS_None, // G_FLOG = 188
    CEFBS_None, // G_FLOG2 = 189
    CEFBS_None, // G_FLOG10 = 190
    CEFBS_None, // G_FLDEXP = 191
    CEFBS_None, // G_FFREXP = 192
    CEFBS_None, // G_FNEG = 193
    CEFBS_None, // G_FPEXT = 194
    CEFBS_None, // G_FPTRUNC = 195
    CEFBS_None, // G_FPTOSI = 196
    CEFBS_None, // G_FPTOUI = 197
    CEFBS_None, // G_SITOFP = 198
    CEFBS_None, // G_UITOFP = 199
    CEFBS_None, // G_FPTOSI_SAT = 200
    CEFBS_None, // G_FPTOUI_SAT = 201
    CEFBS_None, // G_FABS = 202
    CEFBS_None, // G_FCOPYSIGN = 203
    CEFBS_None, // G_IS_FPCLASS = 204
    CEFBS_None, // G_FCANONICALIZE = 205
    CEFBS_None, // G_FMINNUM = 206
    CEFBS_None, // G_FMAXNUM = 207
    CEFBS_None, // G_FMINNUM_IEEE = 208
    CEFBS_None, // G_FMAXNUM_IEEE = 209
    CEFBS_None, // G_FMINIMUM = 210
    CEFBS_None, // G_FMAXIMUM = 211
    CEFBS_None, // G_GET_FPENV = 212
    CEFBS_None, // G_SET_FPENV = 213
    CEFBS_None, // G_RESET_FPENV = 214
    CEFBS_None, // G_GET_FPMODE = 215
    CEFBS_None, // G_SET_FPMODE = 216
    CEFBS_None, // G_RESET_FPMODE = 217
    CEFBS_None, // G_PTR_ADD = 218
    CEFBS_None, // G_PTRMASK = 219
    CEFBS_None, // G_SMIN = 220
    CEFBS_None, // G_SMAX = 221
    CEFBS_None, // G_UMIN = 222
    CEFBS_None, // G_UMAX = 223
    CEFBS_None, // G_ABS = 224
    CEFBS_None, // G_LROUND = 225
    CEFBS_None, // G_LLROUND = 226
    CEFBS_None, // G_BR = 227
    CEFBS_None, // G_BRJT = 228
    CEFBS_None, // G_VSCALE = 229
    CEFBS_None, // G_INSERT_SUBVECTOR = 230
    CEFBS_None, // G_EXTRACT_SUBVECTOR = 231
    CEFBS_None, // G_INSERT_VECTOR_ELT = 232
    CEFBS_None, // G_EXTRACT_VECTOR_ELT = 233
    CEFBS_None, // G_SHUFFLE_VECTOR = 234
    CEFBS_None, // G_SPLAT_VECTOR = 235
    CEFBS_None, // G_VECTOR_COMPRESS = 236
    CEFBS_None, // G_CTTZ = 237
    CEFBS_None, // G_CTTZ_ZERO_UNDEF = 238
    CEFBS_None, // G_CTLZ = 239
    CEFBS_None, // G_CTLZ_ZERO_UNDEF = 240
    CEFBS_None, // G_CTPOP = 241
    CEFBS_None, // G_BSWAP = 242
    CEFBS_None, // G_BITREVERSE = 243
    CEFBS_None, // G_FCEIL = 244
    CEFBS_None, // G_FCOS = 245
    CEFBS_None, // G_FSIN = 246
    CEFBS_None, // G_FTAN = 247
    CEFBS_None, // G_FACOS = 248
    CEFBS_None, // G_FASIN = 249
    CEFBS_None, // G_FATAN = 250
    CEFBS_None, // G_FATAN2 = 251
    CEFBS_None, // G_FCOSH = 252
    CEFBS_None, // G_FSINH = 253
    CEFBS_None, // G_FTANH = 254
    CEFBS_None, // G_FSQRT = 255
    CEFBS_None, // G_FFLOOR = 256
    CEFBS_None, // G_FRINT = 257
    CEFBS_None, // G_FNEARBYINT = 258
    CEFBS_None, // G_ADDRSPACE_CAST = 259
    CEFBS_None, // G_BLOCK_ADDR = 260
    CEFBS_None, // G_JUMP_TABLE = 261
    CEFBS_None, // G_DYN_STACKALLOC = 262
    CEFBS_None, // G_STACKSAVE = 263
    CEFBS_None, // G_STACKRESTORE = 264
    CEFBS_None, // G_STRICT_FADD = 265
    CEFBS_None, // G_STRICT_FSUB = 266
    CEFBS_None, // G_STRICT_FMUL = 267
    CEFBS_None, // G_STRICT_FDIV = 268
    CEFBS_None, // G_STRICT_FREM = 269
    CEFBS_None, // G_STRICT_FMA = 270
    CEFBS_None, // G_STRICT_FSQRT = 271
    CEFBS_None, // G_STRICT_FLDEXP = 272
    CEFBS_None, // G_READ_REGISTER = 273
    CEFBS_None, // G_WRITE_REGISTER = 274
    CEFBS_None, // G_MEMCPY = 275
    CEFBS_None, // G_MEMCPY_INLINE = 276
    CEFBS_None, // G_MEMMOVE = 277
    CEFBS_None, // G_MEMSET = 278
    CEFBS_None, // G_BZERO = 279
    CEFBS_None, // G_TRAP = 280
    CEFBS_None, // G_DEBUGTRAP = 281
    CEFBS_None, // G_UBSANTRAP = 282
    CEFBS_None, // G_VECREDUCE_SEQ_FADD = 283
    CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 284
    CEFBS_None, // G_VECREDUCE_FADD = 285
    CEFBS_None, // G_VECREDUCE_FMUL = 286
    CEFBS_None, // G_VECREDUCE_FMAX = 287
    CEFBS_None, // G_VECREDUCE_FMIN = 288
    CEFBS_None, // G_VECREDUCE_FMAXIMUM = 289
    CEFBS_None, // G_VECREDUCE_FMINIMUM = 290
    CEFBS_None, // G_VECREDUCE_ADD = 291
    CEFBS_None, // G_VECREDUCE_MUL = 292
    CEFBS_None, // G_VECREDUCE_AND = 293
    CEFBS_None, // G_VECREDUCE_OR = 294
    CEFBS_None, // G_VECREDUCE_XOR = 295
    CEFBS_None, // G_VECREDUCE_SMAX = 296
    CEFBS_None, // G_VECREDUCE_SMIN = 297
    CEFBS_None, // G_VECREDUCE_UMAX = 298
    CEFBS_None, // G_VECREDUCE_UMIN = 299
    CEFBS_None, // G_SBFX = 300
    CEFBS_None, // G_UBFX = 301
    CEFBS_None, // ADJCALLSTACKDOWN = 302
    CEFBS_None, // ADJCALLSTACKUP = 303
    CEFBS_None, // GETPCX = 304
    CEFBS_None, // SELECT_CC_DFP_FCC = 305
    CEFBS_None, // SELECT_CC_DFP_ICC = 306
    CEFBS_None, // SELECT_CC_DFP_XCC = 307
    CEFBS_None, // SELECT_CC_FP_FCC = 308
    CEFBS_None, // SELECT_CC_FP_ICC = 309
    CEFBS_None, // SELECT_CC_FP_XCC = 310
    CEFBS_None, // SELECT_CC_Int_FCC = 311
    CEFBS_None, // SELECT_CC_Int_ICC = 312
    CEFBS_None, // SELECT_CC_Int_XCC = 313
    CEFBS_None, // SELECT_CC_QFP_FCC = 314
    CEFBS_None, // SELECT_CC_QFP_ICC = 315
    CEFBS_None, // SELECT_CC_QFP_XCC = 316
    CEFBS_None, // SET = 317
    CEFBS_HasV9, // SETX = 318
    CEFBS_None, // ADDCCri = 319
    CEFBS_None, // ADDCCrr = 320
    CEFBS_None, // ADDCri = 321
    CEFBS_None, // ADDCrr = 322
    CEFBS_None, // ADDEri = 323
    CEFBS_None, // ADDErr = 324
    CEFBS_HasVIS3, // ADDXC = 325
    CEFBS_HasVIS3, // ADDXCCC = 326
    CEFBS_None, // ADDri = 327
    CEFBS_None, // ADDrr = 328
    CEFBS_HasVIS, // ALIGNADDR = 329
    CEFBS_HasVIS, // ALIGNADDRL = 330
    CEFBS_None, // ANDCCri = 331
    CEFBS_None, // ANDCCrr = 332
    CEFBS_None, // ANDNCCri = 333
    CEFBS_None, // ANDNCCrr = 334
    CEFBS_None, // ANDNri = 335
    CEFBS_None, // ANDNrr = 336
    CEFBS_None, // ANDri = 337
    CEFBS_None, // ANDrr = 338
    CEFBS_HasVIS, // ARRAY16 = 339
    CEFBS_HasVIS, // ARRAY32 = 340
    CEFBS_HasVIS, // ARRAY8 = 341
    CEFBS_None, // BA = 342
    CEFBS_None, // BCOND = 343
    CEFBS_None, // BCONDA = 344
    CEFBS_None, // BINDri = 345
    CEFBS_None, // BINDrr = 346
    CEFBS_HasVIS2, // BMASK = 347
    CEFBS_HasV9, // BPFCC = 348
    CEFBS_HasV9, // BPFCCA = 349
    CEFBS_HasV9, // BPFCCANT = 350
    CEFBS_HasV9, // BPFCCNT = 351
    CEFBS_HasV9, // BPICC = 352
    CEFBS_HasV9, // BPICCA = 353
    CEFBS_HasV9, // BPICCANT = 354
    CEFBS_HasV9, // BPICCNT = 355
    CEFBS_None, // BPR = 356
    CEFBS_None, // BPRA = 357
    CEFBS_None, // BPRANT = 358
    CEFBS_None, // BPRNT = 359
    CEFBS_None, // BPXCC = 360
    CEFBS_None, // BPXCCA = 361
    CEFBS_None, // BPXCCANT = 362
    CEFBS_None, // BPXCCNT = 363
    CEFBS_HasVIS2, // BSHUFFLE = 364
    CEFBS_None, // CALL = 365
    CEFBS_None, // CALLri = 366
    CEFBS_None, // CALLrr = 367
    CEFBS_HasV9, // CASAri = 368
    CEFBS_HasCASA, // CASArr = 369
    CEFBS_HasV9, // CASXAri = 370
    CEFBS_HasV9, // CASXArr = 371
    CEFBS_None, // CBCOND = 372
    CEFBS_None, // CBCONDA = 373
    CEFBS_HasVIS3, // CMASK16 = 374
    CEFBS_HasVIS3, // CMASK32 = 375
    CEFBS_HasVIS3, // CMASK8 = 376
    CEFBS_HasV9, // DONE = 377
    CEFBS_HasVIS, // EDGE16 = 378
    CEFBS_HasVIS, // EDGE16L = 379
    CEFBS_HasVIS2, // EDGE16LN = 380
    CEFBS_HasVIS2, // EDGE16N = 381
    CEFBS_HasVIS, // EDGE32 = 382
    CEFBS_HasVIS, // EDGE32L = 383
    CEFBS_HasVIS2, // EDGE32LN = 384
    CEFBS_HasVIS2, // EDGE32N = 385
    CEFBS_HasVIS, // EDGE8 = 386
    CEFBS_HasVIS, // EDGE8L = 387
    CEFBS_HasVIS2, // EDGE8LN = 388
    CEFBS_HasVIS2, // EDGE8N = 389
    CEFBS_HasV9, // FABSD = 390
    CEFBS_HasV9, // FABSQ = 391
    CEFBS_None, // FABSS = 392
    CEFBS_None, // FADDD = 393
    CEFBS_None, // FADDQ = 394
    CEFBS_None, // FADDS = 395
    CEFBS_HasVIS, // FALIGNADATA = 396
    CEFBS_HasVIS, // FAND = 397
    CEFBS_HasVIS, // FANDNOT1 = 398
    CEFBS_HasVIS, // FANDNOT1S = 399
    CEFBS_HasVIS, // FANDNOT2 = 400
    CEFBS_HasVIS, // FANDNOT2S = 401
    CEFBS_HasVIS, // FANDS = 402
    CEFBS_None, // FBCOND = 403
    CEFBS_None, // FBCONDA = 404
    CEFBS_HasV9, // FBCONDA_V9 = 405
    CEFBS_HasV9, // FBCOND_V9 = 406
    CEFBS_HasVIS3, // FCHKSM16 = 407
    CEFBS_None, // FCMPD = 408
    CEFBS_HasV9, // FCMPD_V9 = 409
    CEFBS_HasVIS, // FCMPEQ16 = 410
    CEFBS_HasVIS, // FCMPEQ32 = 411
    CEFBS_HasVIS, // FCMPGT16 = 412
    CEFBS_HasVIS, // FCMPGT32 = 413
    CEFBS_HasVIS, // FCMPLE16 = 414
    CEFBS_HasVIS, // FCMPLE32 = 415
    CEFBS_HasVIS, // FCMPNE16 = 416
    CEFBS_HasVIS, // FCMPNE32 = 417
    CEFBS_None, // FCMPQ = 418
    CEFBS_HasV9, // FCMPQ_V9 = 419
    CEFBS_None, // FCMPS = 420
    CEFBS_HasV9, // FCMPS_V9 = 421
    CEFBS_None, // FDIVD = 422
    CEFBS_None, // FDIVQ = 423
    CEFBS_None, // FDIVS = 424
    CEFBS_None, // FDMULQ = 425
    CEFBS_None, // FDTOI = 426
    CEFBS_None, // FDTOQ = 427
    CEFBS_None, // FDTOS = 428
    CEFBS_None, // FDTOX = 429
    CEFBS_HasVIS, // FEXPAND = 430
    CEFBS_HasVIS3, // FHADDD = 431
    CEFBS_HasVIS3, // FHADDS = 432
    CEFBS_HasVIS3, // FHSUBD = 433
    CEFBS_HasVIS3, // FHSUBS = 434
    CEFBS_None, // FITOD = 435
    CEFBS_None, // FITOQ = 436
    CEFBS_None, // FITOS = 437
    CEFBS_HasVIS3, // FLCMPD = 438
    CEFBS_HasVIS3, // FLCMPS = 439
    CEFBS_None, // FLUSH = 440
    CEFBS_HasV9, // FLUSHW = 441
    CEFBS_None, // FLUSHri = 442
    CEFBS_None, // FLUSHrr = 443
    CEFBS_HasVIS3, // FMEAN16 = 444
    CEFBS_HasV9, // FMOVD = 445
    CEFBS_HasV9, // FMOVD_FCC = 446
    CEFBS_HasV9, // FMOVD_ICC = 447
    CEFBS_None, // FMOVD_XCC = 448
    CEFBS_HasV9, // FMOVQ = 449
    CEFBS_HasV9, // FMOVQ_FCC = 450
    CEFBS_HasV9, // FMOVQ_ICC = 451
    CEFBS_None, // FMOVQ_XCC = 452
    CEFBS_None, // FMOVRD = 453
    CEFBS_None, // FMOVRQ = 454
    CEFBS_None, // FMOVRS = 455
    CEFBS_None, // FMOVS = 456
    CEFBS_HasV9, // FMOVS_FCC = 457
    CEFBS_HasV9, // FMOVS_ICC = 458
    CEFBS_None, // FMOVS_XCC = 459
    CEFBS_HasVIS, // FMUL8SUX16 = 460
    CEFBS_HasVIS, // FMUL8ULX16 = 461
    CEFBS_HasVIS, // FMUL8X16 = 462
    CEFBS_HasVIS, // FMUL8X16AL = 463
    CEFBS_HasVIS, // FMUL8X16AU = 464
    CEFBS_None, // FMULD = 465
    CEFBS_HasVIS, // FMULD8SUX16 = 466
    CEFBS_HasVIS, // FMULD8ULX16 = 467
    CEFBS_None, // FMULQ = 468
    CEFBS_None, // FMULS = 469
    CEFBS_HasVIS3, // FNADDD = 470
    CEFBS_HasVIS3, // FNADDS = 471
    CEFBS_HasVIS, // FNAND = 472
    CEFBS_HasVIS, // FNANDS = 473
    CEFBS_HasV9, // FNEGD = 474
    CEFBS_HasV9, // FNEGQ = 475
    CEFBS_None, // FNEGS = 476
    CEFBS_HasVIS3, // FNHADDD = 477
    CEFBS_HasVIS3, // FNHADDS = 478
    CEFBS_HasVIS3, // FNMULD = 479
    CEFBS_HasVIS3, // FNMULS = 480
    CEFBS_HasVIS, // FNOR = 481
    CEFBS_HasVIS, // FNORS = 482
    CEFBS_HasVIS, // FNOT1 = 483
    CEFBS_HasVIS, // FNOT1S = 484
    CEFBS_HasVIS, // FNOT2 = 485
    CEFBS_HasVIS, // FNOT2S = 486
    CEFBS_HasVIS3, // FNSMULD = 487
    CEFBS_HasVIS, // FONE = 488
    CEFBS_HasVIS, // FONES = 489
    CEFBS_HasVIS, // FOR = 490
    CEFBS_HasVIS, // FORNOT1 = 491
    CEFBS_HasVIS, // FORNOT1S = 492
    CEFBS_HasVIS, // FORNOT2 = 493
    CEFBS_HasVIS, // FORNOT2S = 494
    CEFBS_HasVIS, // FORS = 495
    CEFBS_HasVIS, // FPACK16 = 496
    CEFBS_HasVIS, // FPACK32 = 497
    CEFBS_HasVIS, // FPACKFIX = 498
    CEFBS_HasVIS, // FPADD16 = 499
    CEFBS_HasVIS, // FPADD16S = 500
    CEFBS_HasVIS, // FPADD32 = 501
    CEFBS_HasVIS, // FPADD32S = 502
    CEFBS_HasVIS3, // FPADD64 = 503
    CEFBS_HasVIS, // FPMERGE = 504
    CEFBS_HasVIS, // FPSUB16 = 505
    CEFBS_HasVIS, // FPSUB16S = 506
    CEFBS_HasVIS, // FPSUB32 = 507
    CEFBS_HasVIS, // FPSUB32S = 508
    CEFBS_None, // FQTOD = 509
    CEFBS_None, // FQTOI = 510
    CEFBS_None, // FQTOS = 511
    CEFBS_None, // FQTOX = 512
    CEFBS_HasVIS3, // FSLAS16 = 513
    CEFBS_HasVIS3, // FSLAS32 = 514
    CEFBS_HasVIS3, // FSLL16 = 515
    CEFBS_HasVIS3, // FSLL32 = 516
    CEFBS_None, // FSMULD = 517
    CEFBS_None, // FSQRTD = 518
    CEFBS_None, // FSQRTQ = 519
    CEFBS_None, // FSQRTS = 520
    CEFBS_HasVIS3, // FSRA16 = 521
    CEFBS_HasVIS3, // FSRA32 = 522
    CEFBS_HasVIS, // FSRC1 = 523
    CEFBS_HasVIS, // FSRC1S = 524
    CEFBS_HasVIS, // FSRC2 = 525
    CEFBS_HasVIS, // FSRC2S = 526
    CEFBS_HasVIS3, // FSRL16 = 527
    CEFBS_HasVIS3, // FSRL32 = 528
    CEFBS_None, // FSTOD = 529
    CEFBS_None, // FSTOI = 530
    CEFBS_None, // FSTOQ = 531
    CEFBS_None, // FSTOX = 532
    CEFBS_None, // FSUBD = 533
    CEFBS_None, // FSUBQ = 534
    CEFBS_None, // FSUBS = 535
    CEFBS_HasVIS, // FXNOR = 536
    CEFBS_HasVIS, // FXNORS = 537
    CEFBS_HasVIS, // FXOR = 538
    CEFBS_HasVIS, // FXORS = 539
    CEFBS_None, // FXTOD = 540
    CEFBS_None, // FXTOQ = 541
    CEFBS_None, // FXTOS = 542
    CEFBS_HasVIS, // FZERO = 543
    CEFBS_HasVIS, // FZEROS = 544
    CEFBS_None, // GDOP_LDXrr = 545
    CEFBS_None, // GDOP_LDrr = 546
    CEFBS_None, // JMPLri = 547
    CEFBS_None, // JMPLrr = 548
    CEFBS_HasV9, // LDAri = 549
    CEFBS_None, // LDArr = 550
    CEFBS_None, // LDCSRri = 551
    CEFBS_None, // LDCSRrr = 552
    CEFBS_None, // LDCri = 553
    CEFBS_None, // LDCrr = 554
    CEFBS_HasV9, // LDDAri = 555
    CEFBS_None, // LDDArr = 556
    CEFBS_None, // LDDCri = 557
    CEFBS_None, // LDDCrr = 558
    CEFBS_HasV9, // LDDFAri = 559
    CEFBS_HasV9, // LDDFArr = 560
    CEFBS_None, // LDDFri = 561
    CEFBS_None, // LDDFrr = 562
    CEFBS_None, // LDDri = 563
    CEFBS_None, // LDDrr = 564
    CEFBS_HasV9, // LDFAri = 565
    CEFBS_HasV9, // LDFArr = 566
    CEFBS_None, // LDFSRri = 567
    CEFBS_None, // LDFSRrr = 568
    CEFBS_None, // LDFri = 569
    CEFBS_None, // LDFrr = 570
    CEFBS_HasV9, // LDQFAri = 571
    CEFBS_HasV9, // LDQFArr = 572
    CEFBS_HasV9, // LDQFri = 573
    CEFBS_HasV9, // LDQFrr = 574
    CEFBS_HasV9, // LDSBAri = 575
    CEFBS_None, // LDSBArr = 576
    CEFBS_None, // LDSBri = 577
    CEFBS_None, // LDSBrr = 578
    CEFBS_HasV9, // LDSHAri = 579
    CEFBS_None, // LDSHArr = 580
    CEFBS_None, // LDSHri = 581
    CEFBS_None, // LDSHrr = 582
    CEFBS_HasV9, // LDSTUBAri = 583
    CEFBS_None, // LDSTUBArr = 584
    CEFBS_None, // LDSTUBri = 585
    CEFBS_None, // LDSTUBrr = 586
    CEFBS_None, // LDSWAri = 587
    CEFBS_None, // LDSWArr = 588
    CEFBS_None, // LDSWri = 589
    CEFBS_None, // LDSWrr = 590
    CEFBS_HasV9, // LDUBAri = 591
    CEFBS_None, // LDUBArr = 592
    CEFBS_None, // LDUBri = 593
    CEFBS_None, // LDUBrr = 594
    CEFBS_HasV9, // LDUHAri = 595
    CEFBS_None, // LDUHArr = 596
    CEFBS_None, // LDUHri = 597
    CEFBS_None, // LDUHrr = 598
    CEFBS_None, // LDXAri = 599
    CEFBS_None, // LDXArr = 600
    CEFBS_HasV9, // LDXFSRri = 601
    CEFBS_HasV9, // LDXFSRrr = 602
    CEFBS_None, // LDXri = 603
    CEFBS_None, // LDXrr = 604
    CEFBS_None, // LDri = 605
    CEFBS_None, // LDrr = 606
    CEFBS_HasVIS3, // LZCNT = 607
    CEFBS_HasV9, // MEMBARi = 608
    CEFBS_HasVIS3, // MOVDTOX = 609
    CEFBS_HasV9, // MOVFCCri = 610
    CEFBS_HasV9, // MOVFCCrr = 611
    CEFBS_HasV9, // MOVICCri = 612
    CEFBS_HasV9, // MOVICCrr = 613
    CEFBS_None, // MOVRri = 614
    CEFBS_None, // MOVRrr = 615
    CEFBS_HasVIS3, // MOVSTOSW = 616
    CEFBS_HasVIS3, // MOVSTOUW = 617
    CEFBS_HasVIS3, // MOVWTOS = 618
    CEFBS_None, // MOVXCCri = 619
    CEFBS_None, // MOVXCCrr = 620
    CEFBS_HasVIS3, // MOVXTOD = 621
    CEFBS_None, // MULSCCri = 622
    CEFBS_None, // MULSCCrr = 623
    CEFBS_None, // MULXri = 624
    CEFBS_None, // MULXrr = 625
    CEFBS_None, // NOP = 626
    CEFBS_None, // ORCCri = 627
    CEFBS_None, // ORCCrr = 628
    CEFBS_None, // ORNCCri = 629
    CEFBS_None, // ORNCCrr = 630
    CEFBS_None, // ORNri = 631
    CEFBS_None, // ORNrr = 632
    CEFBS_None, // ORri = 633
    CEFBS_None, // ORrr = 634
    CEFBS_HasVIS, // PDIST = 635
    CEFBS_HasVIS3, // PDISTN = 636
    CEFBS_HasV9, // POPCrr = 637
    CEFBS_HasV9, // PREFETCHAi = 638
    CEFBS_HasV9, // PREFETCHAr = 639
    CEFBS_HasV9, // PREFETCHi = 640
    CEFBS_HasV9, // PREFETCHr = 641
    CEFBS_HasPWRPSR, // PWRPSRri = 642
    CEFBS_HasPWRPSR, // PWRPSRrr = 643
    CEFBS_None, // RDASR = 644
    CEFBS_HasV9, // RDFQ = 645
    CEFBS_HasV9, // RDPR = 646
    CEFBS_None, // RDPSR = 647
    CEFBS_None, // RDTBR = 648
    CEFBS_None, // RDWIM = 649
    CEFBS_HasV9, // RESTORED = 650
    CEFBS_None, // RESTOREri = 651
    CEFBS_None, // RESTORErr = 652
    CEFBS_None, // RET = 653
    CEFBS_None, // RETL = 654
    CEFBS_HasV9, // RETRY = 655
    CEFBS_None, // RETTri = 656
    CEFBS_None, // RETTrr = 657
    CEFBS_HasV9, // SAVED = 658
    CEFBS_None, // SAVEri = 659
    CEFBS_None, // SAVErr = 660
    CEFBS_None, // SDIVCCri = 661
    CEFBS_None, // SDIVCCrr = 662
    CEFBS_None, // SDIVXri = 663
    CEFBS_None, // SDIVXrr = 664
    CEFBS_None, // SDIVri = 665
    CEFBS_None, // SDIVrr = 666
    CEFBS_None, // SETHIi = 667
    CEFBS_HasVIS, // SHUTDOWN = 668
    CEFBS_HasVIS2, // SIAM = 669
    CEFBS_HasV9, // SIR = 670
    CEFBS_None, // SLLXri = 671
    CEFBS_None, // SLLXrr = 672
    CEFBS_None, // SLLri = 673
    CEFBS_None, // SLLrr = 674
    CEFBS_None, // SMACri = 675
    CEFBS_None, // SMACrr = 676
    CEFBS_None, // SMULCCri = 677
    CEFBS_None, // SMULCCrr = 678
    CEFBS_None, // SMULri = 679
    CEFBS_None, // SMULrr = 680
    CEFBS_None, // SRAXri = 681
    CEFBS_None, // SRAXrr = 682
    CEFBS_None, // SRAri = 683
    CEFBS_None, // SRArr = 684
    CEFBS_None, // SRLXri = 685
    CEFBS_None, // SRLXrr = 686
    CEFBS_None, // SRLri = 687
    CEFBS_None, // SRLrr = 688
    CEFBS_HasV9, // STAri = 689
    CEFBS_None, // STArr = 690
    CEFBS_None, // STBAR = 691
    CEFBS_HasV9, // STBAri = 692
    CEFBS_None, // STBArr = 693
    CEFBS_None, // STBri = 694
    CEFBS_None, // STBrr = 695
    CEFBS_None, // STCSRri = 696
    CEFBS_None, // STCSRrr = 697
    CEFBS_None, // STCri = 698
    CEFBS_None, // STCrr = 699
    CEFBS_HasV9, // STDAri = 700
    CEFBS_None, // STDArr = 701
    CEFBS_None, // STDCQri = 702
    CEFBS_None, // STDCQrr = 703
    CEFBS_None, // STDCri = 704
    CEFBS_None, // STDCrr = 705
    CEFBS_HasV9, // STDFAri = 706
    CEFBS_HasV9, // STDFArr = 707
    CEFBS_None, // STDFQri = 708
    CEFBS_None, // STDFQrr = 709
    CEFBS_None, // STDFri = 710
    CEFBS_None, // STDFrr = 711
    CEFBS_None, // STDri = 712
    CEFBS_None, // STDrr = 713
    CEFBS_HasV9, // STFAri = 714
    CEFBS_HasV9, // STFArr = 715
    CEFBS_None, // STFSRri = 716
    CEFBS_None, // STFSRrr = 717
    CEFBS_None, // STFri = 718
    CEFBS_None, // STFrr = 719
    CEFBS_HasV9, // STHAri = 720
    CEFBS_None, // STHArr = 721
    CEFBS_None, // STHri = 722
    CEFBS_None, // STHrr = 723
    CEFBS_HasV9, // STQFAri = 724
    CEFBS_HasV9, // STQFArr = 725
    CEFBS_HasV9, // STQFri = 726
    CEFBS_HasV9, // STQFrr = 727
    CEFBS_None, // STXAri = 728
    CEFBS_None, // STXArr = 729
    CEFBS_HasV9, // STXFSRri = 730
    CEFBS_HasV9, // STXFSRrr = 731
    CEFBS_None, // STXri = 732
    CEFBS_None, // STXrr = 733
    CEFBS_None, // STri = 734
    CEFBS_None, // STrr = 735
    CEFBS_None, // SUBCCri = 736
    CEFBS_None, // SUBCCrr = 737
    CEFBS_None, // SUBCri = 738
    CEFBS_None, // SUBCrr = 739
    CEFBS_None, // SUBEri = 740
    CEFBS_None, // SUBErr = 741
    CEFBS_None, // SUBri = 742
    CEFBS_None, // SUBrr = 743
    CEFBS_HasV9, // SWAPAri = 744
    CEFBS_None, // SWAPArr = 745
    CEFBS_None, // SWAPri = 746
    CEFBS_None, // SWAPrr = 747
    CEFBS_None, // TA1 = 748
    CEFBS_None, // TA3 = 749
    CEFBS_None, // TA5 = 750
    CEFBS_None, // TADDCCTVri = 751
    CEFBS_None, // TADDCCTVrr = 752
    CEFBS_None, // TADDCCri = 753
    CEFBS_None, // TADDCCrr = 754
    CEFBS_None, // TAIL_CALL = 755
    CEFBS_None, // TAIL_CALLri = 756
    CEFBS_HasV9, // TICCri = 757
    CEFBS_HasV9, // TICCrr = 758
    CEFBS_None, // TLS_ADDrr = 759
    CEFBS_None, // TLS_CALL = 760
    CEFBS_None, // TLS_LDXrr = 761
    CEFBS_None, // TLS_LDrr = 762
    CEFBS_None, // TRAPri = 763
    CEFBS_None, // TRAPrr = 764
    CEFBS_None, // TSUBCCTVri = 765
    CEFBS_None, // TSUBCCTVrr = 766
    CEFBS_None, // TSUBCCri = 767
    CEFBS_None, // TSUBCCrr = 768
    CEFBS_None, // TXCCri = 769
    CEFBS_None, // TXCCrr = 770
    CEFBS_None, // UDIVCCri = 771
    CEFBS_None, // UDIVCCrr = 772
    CEFBS_None, // UDIVXri = 773
    CEFBS_None, // UDIVXrr = 774
    CEFBS_None, // UDIVri = 775
    CEFBS_None, // UDIVrr = 776
    CEFBS_None, // UMACri = 777
    CEFBS_None, // UMACrr = 778
    CEFBS_None, // UMULCCri = 779
    CEFBS_None, // UMULCCrr = 780
    CEFBS_HasVIS3, // UMULXHI = 781
    CEFBS_None, // UMULri = 782
    CEFBS_None, // UMULrr = 783
    CEFBS_None, // UNIMP = 784
    CEFBS_None, // V9FCMPD = 785
    CEFBS_None, // V9FCMPED = 786
    CEFBS_None, // V9FCMPEQ = 787
    CEFBS_None, // V9FCMPES = 788
    CEFBS_None, // V9FCMPQ = 789
    CEFBS_None, // V9FCMPS = 790
    CEFBS_HasV9, // V9FMOVD_FCC = 791
    CEFBS_HasV9, // V9FMOVQ_FCC = 792
    CEFBS_HasV9, // V9FMOVS_FCC = 793
    CEFBS_HasV9, // V9MOVFCCri = 794
    CEFBS_HasV9, // V9MOVFCCrr = 795
    CEFBS_None, // WRASRri = 796
    CEFBS_None, // WRASRrr = 797
    CEFBS_HasV9, // WRPRri = 798
    CEFBS_HasV9, // WRPRrr = 799
    CEFBS_None, // WRPSRri = 800
    CEFBS_None, // WRPSRrr = 801
    CEFBS_None, // WRTBRri = 802
    CEFBS_None, // WRTBRrr = 803
    CEFBS_None, // WRWIMri = 804
    CEFBS_None, // WRWIMrr = 805
    CEFBS_HasVIS3, // XMULX = 806
    CEFBS_HasVIS3, // XMULXHI = 807
    CEFBS_None, // XNORCCri = 808
    CEFBS_None, // XNORCCrr = 809
    CEFBS_None, // XNORri = 810
    CEFBS_None, // XNORrr = 811
    CEFBS_None, // XORCCri = 812
    CEFBS_None, // XORCCrr = 813
    CEFBS_None, // XORri = 814
    CEFBS_None, // XORrr = 815
  };

  assert(Opcode < 816);
  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
}

} // end namespace Sparc_MC
} // end namespace llvm
#endif // GET_COMPUTE_FEATURES

#ifdef GET_AVAILABLE_OPCODE_CHECKER
#undef GET_AVAILABLE_OPCODE_CHECKER
namespace llvm {
namespace Sparc_MC {
bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  return !MissingFeatures.any();
}
} // end namespace Sparc_MC
} // end namespace llvm
#endif // GET_AVAILABLE_OPCODE_CHECKER

#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
#undef ENABLE_INSTR_PREDICATE_VERIFIER
#include <sstream>

namespace llvm {
namespace Sparc_MC {

#ifndef NDEBUG
static const char *SubtargetFeatureNames[] = {
  "Feature_HasCASA",
  "Feature_HasPWRPSR",
  "Feature_HasV9",
  "Feature_HasVIS",
  "Feature_HasVIS2",
  "Feature_HasVIS3",
  "Feature_UseSoftMulDiv",
  nullptr
};

#endif // NDEBUG

void verifyInstructionPredicates(
    unsigned Opcode, const FeatureBitset &Features) {
#ifndef NDEBUG
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  if (MissingFeatures.any()) {
    std::ostringstream Msg;
    Msg << "Attempting to emit " << &SparcInstrNameData[SparcInstrNameIndices[Opcode]]
        << " instruction but the ";
    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
      if (MissingFeatures.test(i))
        Msg << SubtargetFeatureNames[i] << " ";
    Msg << "predicate(s) are not met";
    report_fatal_error(Msg.str().c_str());
  }
#endif // NDEBUG
}
} // end namespace Sparc_MC
} // end namespace llvm
#endif // ENABLE_INSTR_PREDICATE_VERIFIER