/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM namespace llvm { namespace SystemZ { enum { … }; } // end namespace SystemZ } // end namespace llvm #endif // GET_INSTRINFO_ENUM #ifdef GET_INSTRINFO_SCHED_ENUM #undef GET_INSTRINFO_SCHED_ENUM namespace llvm { namespace SystemZ { namespace Sched { enum { NoInstrModel = 0, ADJDYNALLOC = 1, CallBRCL_BRC_BRCAsm_BRCL_BRCLAsm = 2, CallJG_J_JAsmE_JAsmH_JAsmHE_JAsmL_JAsmLE_JAsmLH_JAsmM_JAsmNE_JAsmNH_JAsmNHE_JAsmNL_JAsmNLE_JAsmNLH_JAsmNM_JAsmNO_JAsmNP_JAsmNZ_JAsmO_JAsmP_JAsmZ_JG_JGAsmE_JGAsmH_JGAsmHE_JGAsmL_JGAsmLE_JGAsmLH_JGAsmM_JGAsmNE_JGAsmNH_JGAsmNHE_JGAsmNL_JGAsmNLE_JGAsmNLH_JGAsmNM_JGAsmNO_JGAsmNP_JGAsmNZ_JGAsmO_JGAsmP_JGAsmZ = 3, CallBCR_BC_BCAsm_BCR_BCRAsm = 4, CallBR_B_BAsmE_BAsmH_BAsmHE_BAsmL_BAsmLE_BAsmLH_BAsmM_BAsmNE_BAsmNH_BAsmNHE_BAsmNL_BAsmNLE_BAsmNLH_BAsmNM_BAsmNO_BAsmNP_BAsmNZ_BAsmO_BAsmP_BAsmZ_BR_BRAsmE_BRAsmH_BRAsmHE_BRAsmL_BRAsmLE_BRAsmLH_BRAsmM_BRAsmNE_BRAsmNH_BRAsmNHE_BRAsmNL_BRAsmNLE_BRAsmNLH_BRAsmNM_BRAsmNO_BRAsmNP_BRAsmNZ_BRAsmO_BRAsmP_BRAsmZ = 5, BI_BIAsmE_BIAsmH_BIAsmHE_BIAsmL_BIAsmLE_BIAsmLH_BIAsmM_BIAsmNE_BIAsmNH_BIAsmNHE_BIAsmNL_BIAsmNLE_BIAsmNLH_BIAsmNM_BIAsmNO_BIAsmNP_BIAsmNZ_BIAsmO_BIAsmP_BIAsmZ_BIC_BICAsm = 6, BRCT_BRCTG = 7, BRCTH = 8, BCT_BCTG_BCTGR_BCTR = 9, BRXH_BRXHG_BRXLE_BRXLG_BXH_BXHG_BXLE_BXLEG = 10, CGIJ_CGIJAsm_CGIJAsmE_CGIJAsmH_CGIJAsmHE_CGIJAsmL_CGIJAsmLE_CGIJAsmLH_CGIJAsmNE_CGIJAsmNH_CGIJAsmNHE_CGIJAsmNL_CGIJAsmNLE_CGIJAsmNLH_CGRJ_CGRJAsm_CGRJAsmE_CGRJAsmH_CGRJAsmHE_CGRJAsmL_CGRJAsmLE_CGRJAsmLH_CGRJAsmNE_CGRJAsmNH_CGRJAsmNHE_CGRJAsmNL_CGRJAsmNLE_CGRJAsmNLH_CIJ_CIJAsm_CIJAsmE_CIJAsmH_CIJAsmHE_CIJAsmL_CIJAsmLE_CIJAsmLH_CIJAsmNE_CIJAsmNH_CIJAsmNHE_CIJAsmNL_CIJAsmNLE_CIJAsmNLH_CLGIJ_CLGIJAsm_CLGIJAsmE_CLGIJAsmH_CLGIJAsmHE_CLGIJAsmL_CLGIJAsmLE_CLGIJAsmLH_CLGIJAsmNE_CLGIJAsmNH_CLGIJAsmNHE_CLGIJAsmNL_CLGIJAsmNLE_CLGIJAsmNLH_CLGRJ_CLGRJAsm_CLGRJAsmE_CLGRJAsmH_CLGRJAsmHE_CLGRJAsmL_CLGRJAsmLE_CLGRJAsmLH_CLGRJAsmNE_CLGRJAsmNH_CLGRJAsmNHE_CLGRJAsmNL_CLGRJAsmNLE_CLGRJAsmNLH_CLIJ_CLIJAsm_CLIJAsmE_CLIJAsmH_CLIJAsmHE_CLIJAsmL_CLIJAsmLE_CLIJAsmLH_CLIJAsmNE_CLIJAsmNH_CLIJAsmNHE_CLIJAsmNL_CLIJAsmNLE_CLIJAsmNLH_CLRJ_CLRJAsm_CLRJAsmE_CLRJAsmH_CLRJAsmHE_CLRJAsmL_CLRJAsmLE_CLRJAsmLH_CLRJAsmNE_CLRJAsmNH_CLRJAsmNHE_CLRJAsmNL_CLRJAsmNLE_CLRJAsmNLH_CRJ_CRJAsm_CRJAsmE_CRJAsmH_CRJAsmHE_CRJAsmL_CRJAsmLE_CRJAsmLH_CRJAsmNE_CRJAsmNH_CRJAsmNHE_CRJAsmNL_CRJAsmNLE_CRJAsmNLH = 11, CGIBCall_CGIBReturn_CGRBCall_CGRBReturn_CIBCall_CIBReturn_CLGIBCall_CLGIBReturn_CLGRBCall_CLGRBReturn_CLIBCall_CLIBReturn_CLRBCall_CLRBReturn_CRBCall_CRBReturn_CGIB_CGIBAsm_CGIBAsmE_CGIBAsmH_CGIBAsmHE_CGIBAsmL_CGIBAsmLE_CGIBAsmLH_CGIBAsmNE_CGIBAsmNH_CGIBAsmNHE_CGIBAsmNL_CGIBAsmNLE_CGIBAsmNLH_CGRB_CGRBAsm_CGRBAsmE_CGRBAsmH_CGRBAsmHE_CGRBAsmL_CGRBAsmLE_CGRBAsmLH_CGRBAsmNE_CGRBAsmNH_CGRBAsmNHE_CGRBAsmNL_CGRBAsmNLE_CGRBAsmNLH_CIB_CIBAsm_CIBAsmE_CIBAsmH_CIBAsmHE_CIBAsmL_CIBAsmLE_CIBAsmLH_CIBAsmNE_CIBAsmNH_CIBAsmNHE_CIBAsmNL_CIBAsmNLE_CIBAsmNLH_CLGIB_CLGIBAsm_CLGIBAsmE_CLGIBAsmH_CLGIBAsmHE_CLGIBAsmL_CLGIBAsmLE_CLGIBAsmLH_CLGIBAsmNE_CLGIBAsmNH_CLGIBAsmNHE_CLGIBAsmNL_CLGIBAsmNLE_CLGIBAsmNLH_CLGRB_CLGRBAsm_CLGRBAsmE_CLGRBAsmH_CLGRBAsmHE_CLGRBAsmL_CLGRBAsmLE_CLGRBAsmLH_CLGRBAsmNE_CLGRBAsmNH_CLGRBAsmNHE_CLGRBAsmNL_CLGRBAsmNLE_CLGRBAsmNLH_CLIB_CLIBAsm_CLIBAsmE_CLIBAsmH_CLIBAsmHE_CLIBAsmL_CLIBAsmLE_CLIBAsmLH_CLIBAsmNE_CLIBAsmNH_CLIBAsmNHE_CLIBAsmNL_CLIBAsmNLE_CLIBAsmNLH_CLRB_CLRBAsm_CLRBAsmE_CLRBAsmH_CLRBAsmHE_CLRBAsmL_CLRBAsmLE_CLRBAsmLH_CLRBAsmNE_CLRBAsmNH_CLRBAsmNHE_CLRBAsmNL_CLRBAsmNLE_CLRBAsmNLH_CRB_CRBAsm_CRBAsmE_CRBAsmH_CRBAsmHE_CRBAsmL_CRBAsmLE_CRBAsmLH_CRBAsmNE_CRBAsmNH_CRBAsmNHE_CRBAsmNL_CRBAsmNLE_CRBAsmNLH = 12, CondTrap_Trap = 13, CGIT_CGITAsm_CGITAsmE_CGITAsmH_CGITAsmHE_CGITAsmL_CGITAsmLE_CGITAsmLH_CGITAsmNE_CGITAsmNH_CGITAsmNHE_CGITAsmNL_CGITAsmNLE_CGITAsmNLH_CGRT_CGRTAsm_CGRTAsmE_CGRTAsmH_CGRTAsmHE_CGRTAsmL_CGRTAsmLE_CGRTAsmLH_CGRTAsmNE_CGRTAsmNH_CGRTAsmNHE_CGRTAsmNL_CGRTAsmNLE_CGRTAsmNLH_CIT_CITAsm_CITAsmE_CITAsmH_CITAsmHE_CITAsmL_CITAsmLE_CITAsmLH_CITAsmNE_CITAsmNH_CITAsmNHE_CITAsmNL_CITAsmNLE_CITAsmNLH_CRT_CRTAsm_CRTAsmE_CRTAsmH_CRTAsmHE_CRTAsmL_CRTAsmLE_CRTAsmLH_CRTAsmNE_CRTAsmNH_CRTAsmNHE_CRTAsmNL_CRTAsmNLE_CRTAsmNLH = 14, CLGRT_CLGRTAsm_CLGRTAsmE_CLGRTAsmH_CLGRTAsmHE_CLGRTAsmL_CLGRTAsmLE_CLGRTAsmLH_CLGRTAsmNE_CLGRTAsmNH_CLGRTAsmNHE_CLGRTAsmNL_CLGRTAsmNLE_CLGRTAsmNLH_CLRT_CLRTAsm_CLRTAsmE_CLRTAsmH_CLRTAsmHE_CLRTAsmL_CLRTAsmLE_CLRTAsmLH_CLRTAsmNE_CLRTAsmNH_CLRTAsmNHE_CLRTAsmNL_CLRTAsmNLE_CLRTAsmNLH = 15, CLFIT_CLFITAsm_CLFITAsmE_CLFITAsmH_CLFITAsmHE_CLFITAsmL_CLFITAsmLE_CLFITAsmLH_CLFITAsmNE_CLFITAsmNH_CLFITAsmNHE_CLFITAsmNL_CLFITAsmNLE_CLFITAsmNLH_CLGIT_CLGITAsm_CLGITAsmE_CLGITAsmH_CLGITAsmHE_CLGITAsmL_CLGITAsmLE_CLGITAsmLH_CLGITAsmNE_CLGITAsmNH_CLGITAsmNHE_CLGITAsmNL_CLGITAsmNLE_CLGITAsmNLH = 16, CLGT_CLGTAsm_CLGTAsmE_CLGTAsmH_CLGTAsmHE_CLGTAsmL_CLGTAsmLE_CLGTAsmLH_CLGTAsmNE_CLGTAsmNH_CLGTAsmNHE_CLGTAsmNL_CLGTAsmNLE_CLGTAsmNLH_CLT_CLTAsm_CLTAsmE_CLTAsmH_CLTAsmHE_CLTAsmL_CLTAsmLE_CLTAsmLH_CLTAsmNE_CLTAsmNH_CLTAsmNHE_CLTAsmNL_CLTAsmNLE_CLTAsmNLH = 17, BRAS = 18, CallBRASL_CallBRASL_XPLINK64_BRASL = 19, CallBASR_CallBASR_STACKEXT_CallBASR_XPLINK64_BAS_BASR = 20, TLS_GDCALL_TLS_LDCALL = 21, Return_Return_XPLINK = 22, CondReturn_CondReturn_XPLINK = 23, MVGHI_MVHHI_MVHI = 24, MVI_MVIY = 25, MVC = 26, MVCL_MVCLE_MVCLU = 27, MVCRL = 28, COPY_TO_REGCLASS_COPY = 29, EXTRACT_SUBREG = 30, INSERT_SUBREG = 31, REG_SEQUENCE = 32, LMux_L_LFH_LRL_LY = 33, LCBB = 34, LG_LGRL = 35, L128 = 36, LLIHF_LLIHH_LLIHL = 37, LLILF_LLILH_LLILL = 38, LGFI_LGHI = 39, LHIMux_LHI = 40, LR = 41, LZRF_LZRG = 42, LAT_LFHAT_LGAT = 43, LT_LTG = 44, LTGR_LTR = 45, STG_STGRL = 46, ST128 = 47, STMux_ST_STFH_STRL_STY = 48, MVST = 49, LOCRMux = 50, LOCFHR_LOCFHRAsm_LOCFHRAsmE_LOCFHRAsmH_LOCFHRAsmHE_LOCFHRAsmL_LOCFHRAsmLE_LOCFHRAsmLH_LOCFHRAsmM_LOCFHRAsmNE_LOCFHRAsmNH_LOCFHRAsmNHE_LOCFHRAsmNL_LOCFHRAsmNLE_LOCFHRAsmNLH_LOCFHRAsmNM_LOCFHRAsmNO_LOCFHRAsmNP_LOCFHRAsmNZ_LOCFHRAsmO_LOCFHRAsmP_LOCFHRAsmZ_LOCGR_LOCGRAsm_LOCGRAsmE_LOCGRAsmH_LOCGRAsmHE_LOCGRAsmL_LOCGRAsmLE_LOCGRAsmLH_LOCGRAsmM_LOCGRAsmNE_LOCGRAsmNH_LOCGRAsmNHE_LOCGRAsmNL_LOCGRAsmNLE_LOCGRAsmNLH_LOCGRAsmNM_LOCGRAsmNO_LOCGRAsmNP_LOCGRAsmNZ_LOCGRAsmO_LOCGRAsmP_LOCGRAsmZ_LOCR_LOCRAsm_LOCRAsmE_LOCRAsmH_LOCRAsmHE_LOCRAsmL_LOCRAsmLE_LOCRAsmLH_LOCRAsmM_LOCRAsmNE_LOCRAsmNH_LOCRAsmNHE_LOCRAsmNL_LOCRAsmNLE_LOCRAsmNLH_LOCRAsmNM_LOCRAsmNO_LOCRAsmNP_LOCRAsmNZ_LOCRAsmO_LOCRAsmP_LOCRAsmZ = 51, LOCHIMux_LOCGHI_LOCGHIAsm_LOCGHIAsmE_LOCGHIAsmH_LOCGHIAsmHE_LOCGHIAsmL_LOCGHIAsmLE_LOCGHIAsmLH_LOCGHIAsmM_LOCGHIAsmNE_LOCGHIAsmNH_LOCGHIAsmNHE_LOCGHIAsmNL_LOCGHIAsmNLE_LOCGHIAsmNLH_LOCGHIAsmNM_LOCGHIAsmNO_LOCGHIAsmNP_LOCGHIAsmNZ_LOCGHIAsmO_LOCGHIAsmP_LOCGHIAsmZ_LOCHHI_LOCHHIAsm_LOCHHIAsmE_LOCHHIAsmH_LOCHHIAsmHE_LOCHHIAsmL_LOCHHIAsmLE_LOCHHIAsmLH_LOCHHIAsmM_LOCHHIAsmNE_LOCHHIAsmNH_LOCHHIAsmNHE_LOCHHIAsmNL_LOCHHIAsmNLE_LOCHHIAsmNLH_LOCHHIAsmNM_LOCHHIAsmNO_LOCHHIAsmNP_LOCHHIAsmNZ_LOCHHIAsmO_LOCHHIAsmP_LOCHHIAsmZ_LOCHI_LOCHIAsm_LOCHIAsmE_LOCHIAsmH_LOCHIAsmHE_LOCHIAsmL_LOCHIAsmLE_LOCHIAsmLH_LOCHIAsmM_LOCHIAsmNE_LOCHIAsmNH_LOCHIAsmNHE_LOCHIAsmNL_LOCHIAsmNLE_LOCHIAsmNLH_LOCHIAsmNM_LOCHIAsmNO_LOCHIAsmNP_LOCHIAsmNZ_LOCHIAsmO_LOCHIAsmP_LOCHIAsmZ = 52, LOCMux_LOC_LOCAsm_LOCAsmE_LOCAsmH_LOCAsmHE_LOCAsmL_LOCAsmLE_LOCAsmLH_LOCAsmM_LOCAsmNE_LOCAsmNH_LOCAsmNHE_LOCAsmNL_LOCAsmNLE_LOCAsmNLH_LOCAsmNM_LOCAsmNO_LOCAsmNP_LOCAsmNZ_LOCAsmO_LOCAsmP_LOCAsmZ_LOCFH_LOCFHAsm_LOCFHAsmE_LOCFHAsmH_LOCFHAsmHE_LOCFHAsmL_LOCFHAsmLE_LOCFHAsmLH_LOCFHAsmM_LOCFHAsmNE_LOCFHAsmNH_LOCFHAsmNHE_LOCFHAsmNL_LOCFHAsmNLE_LOCFHAsmNLH_LOCFHAsmNM_LOCFHAsmNO_LOCFHAsmNP_LOCFHAsmNZ_LOCFHAsmO_LOCFHAsmP_LOCFHAsmZ_LOCG_LOCGAsm_LOCGAsmE_LOCGAsmH_LOCGAsmHE_LOCGAsmL_LOCGAsmLE_LOCGAsmLH_LOCGAsmM_LOCGAsmNE_LOCGAsmNH_LOCGAsmNHE_LOCGAsmNL_LOCGAsmNLE_LOCGAsmNLH_LOCGAsmNM_LOCGAsmNO_LOCGAsmNP_LOCGAsmNZ_LOCGAsmO_LOCGAsmP_LOCGAsmZ = 53, STOCMux_STOC_STOCAsm_STOCAsmE_STOCAsmH_STOCAsmHE_STOCAsmL_STOCAsmLE_STOCAsmLH_STOCAsmM_STOCAsmNE_STOCAsmNH_STOCAsmNHE_STOCAsmNL_STOCAsmNLE_STOCAsmNLH_STOCAsmNM_STOCAsmNO_STOCAsmNP_STOCAsmNZ_STOCAsmO_STOCAsmP_STOCAsmZ_STOCFH_STOCFHAsm_STOCFHAsmE_STOCFHAsmH_STOCFHAsmHE_STOCFHAsmL_STOCFHAsmLE_STOCFHAsmLH_STOCFHAsmM_STOCFHAsmNE_STOCFHAsmNH_STOCFHAsmNHE_STOCFHAsmNL_STOCFHAsmNLE_STOCFHAsmNLH_STOCFHAsmNM_STOCFHAsmNO_STOCFHAsmNP_STOCFHAsmNZ_STOCFHAsmO_STOCFHAsmP_STOCFHAsmZ_STOCG_STOCGAsm_STOCGAsmE_STOCGAsmH_STOCGAsmHE_STOCGAsmL_STOCGAsmLE_STOCGAsmLH_STOCGAsmM_STOCGAsmNE_STOCGAsmNH_STOCGAsmNHE_STOCGAsmNL_STOCGAsmNLE_STOCGAsmNLH_STOCGAsmNM_STOCGAsmNO_STOCGAsmNP_STOCGAsmNZ_STOCGAsmO_STOCGAsmP_STOCGAsmZ = 54, SELRMux = 55, SELFHR_SELFHRAsm_SELFHRAsmE_SELFHRAsmH_SELFHRAsmHE_SELFHRAsmL_SELFHRAsmLE_SELFHRAsmLH_SELFHRAsmM_SELFHRAsmNE_SELFHRAsmNH_SELFHRAsmNHE_SELFHRAsmNL_SELFHRAsmNLE_SELFHRAsmNLH_SELFHRAsmNM_SELFHRAsmNO_SELFHRAsmNP_SELFHRAsmNZ_SELFHRAsmO_SELFHRAsmP_SELFHRAsmZ_SELGR_SELGRAsm_SELGRAsmE_SELGRAsmH_SELGRAsmHE_SELGRAsmL_SELGRAsmLE_SELGRAsmLH_SELGRAsmM_SELGRAsmNE_SELGRAsmNH_SELGRAsmNHE_SELGRAsmNL_SELGRAsmNLE_SELGRAsmNLH_SELGRAsmNM_SELGRAsmNO_SELGRAsmNP_SELGRAsmNZ_SELGRAsmO_SELGRAsmP_SELGRAsmZ_SELR_SELRAsm_SELRAsmE_SELRAsmH_SELRAsmHE_SELRAsmL_SELRAsmLE_SELRAsmLH_SELRAsmM_SELRAsmNE_SELRAsmNH_SELRAsmNHE_SELRAsmNL_SELRAsmNLE_SELRAsmNLH_SELRAsmNM_SELRAsmNO_SELRAsmNP_SELRAsmNZ_SELRAsmO_SELRAsmP_SELRAsmZ = 56, LBR_LGR_LHR = 57, LGBR_LGFR_LGHR = 58, LTGF = 59, LTGFR = 60, LBMux_LB_LBH = 61, LH_LHY = 62, LHMux_LHH_LHRL = 63, LGB_LGF_LGH = 64, LGFRL_LGHRL = 65, LLCRMux_LLCR = 66, LLHRMux_LLHR = 67, LLGCR_LLGFR_LLGHR_LLGTR = 68, LLCMux_LLC = 69, LLHMux_LLH = 70, LLCH_LLHH = 71, LLHRL = 72, LLGC_LLGF_LLGFRL_LLGH_LLGHRL_LLGT = 73, LLZRGF = 74, LLGFAT_LLGTAT = 75, STCMux_STC_STCH_STCY = 76, STHMux_STH_STHH_STHRL_STHY = 77, STCM_STCMH_STCMY = 78, LM_LMG_LMH_LMY = 79, LMD = 80, STM_STMG_STMH_STMY = 81, LRVGR_LRVR = 82, LRV_LRVG_LRVH = 83, STRV_STRVG_STRVH = 84, MVCIN = 85, LA_LARL_LAY = 86, GOT = 87, LPGR_LPR = 88, LNGFR_LPGFR = 89, LNGR_LNR = 90, LCGR_LCR = 91, LCGFR = 92, IC_ICY = 93, IC32_IC32Y = 94, ICM_ICMH_ICMY = 95, IIFMux_IIHMux_IILMux = 96, IIHF64_IIHF = 97, IIHH64_IIHH = 98, IIHL64_IIHL = 99, IILF64_IILF = 100, IILH64_IILH = 101, IILL64_IILL = 102, A_AY = 103, AH_AHY = 104, AIH = 105, AFIMux_AFI = 106, AG = 107, AGFI = 108, AGHI_AGHIK = 109, AGR_AGRK = 110, AHI_AHIK = 111, AHIMux_AHIMuxK = 112, AL_ALY = 113, ALFI_ALHSIK = 114, ALG_ALGF = 115, ALGHSIK = 116, ALGFI_ALGFR = 117, ALGR_ALGRK = 118, ALR_ALRK = 119, AR_ARK = 120, AHHHR_ALHHHR = 121, AHHLR_ALHHLR = 122, ALSIH_ALSIHN = 123, AGSI_ALGSI_ALSI_ASI = 124, ALC_ALCG = 125, ALCGR_ALCR = 126, AGF_AGH = 127, AGFR = 128, S_SG_SY = 129, SH_SHY = 130, SGR_SGRK = 131, SLFI = 132, SL_SLG_SLGF_SLY = 133, SLGFI_SLGFR = 134, SLGR_SLGRK = 135, SLR_SLRK = 136, SR_SRK = 137, SHHHR_SLHHHR = 138, SHHLR_SLHHLR = 139, SLB_SLBG = 140, SLBGR_SLBR = 141, SGF_SGH = 142, SGFR = 143, N_NG_NY = 144, NGR_NGRK = 145, NIFMux_NIHMux_NILMux = 146, NI_NIY = 147, NIHF64_NIHF = 148, NIHH64_NIHH = 149, NIHL64_NIHL = 150, NILF64_NILF = 151, NILH64_NILH = 152, NILL64_NILL = 153, NR_NRK = 154, NC = 155, O_OG_OY = 156, OGR_OGRK = 157, OI_OIY = 158, OIFMux_OIHMux_OILMux = 159, OIHF64_OIHF = 160, OIHH64_OIHH = 161, OIHL64_OIHL = 162, OILF64_OILF = 163, OILH64_OILH = 164, OILL64_OILL = 165, OR_ORK = 166, OC = 167, X_XG_XY = 168, XI_XIY = 169, XIFMux = 170, XGR_XGRK = 171, XIHF64_XIHF = 172, XILF64_XILF = 173, XR_XRK = 174, XC = 175, NCGRK_NCRK = 176, OCGRK_OCRK = 177, NNGRK_NNRK = 178, NOGRK_NORK = 179, NOTGR_NOTR = 180, NXGRK_NXRK = 181, MS_MSGF_MSY = 182, MSFI_MSR = 183, MSG = 184, MSGR = 185, MSGFI_MSGFR = 186, MLG = 187, MLGR = 188, MGHI = 189, MHI = 190, MH_MHY = 191, MLR_MR = 192, M_MFY_ML = 193, MGH = 194, MG = 195, MGRK = 196, MSC = 197, MSGC = 198, MSRKC = 199, MSGRKC = 200, DR = 201, D = 202, DSGFR_DSGR = 203, DSG_DSGF = 204, DLR = 205, DLGR = 206, DL_DLG = 207, SLL_SLLG_SLLK = 208, SRL_SRLG_SRLK = 209, SRA_SRAG_SRAK = 210, SLA_SLAG_SLAK = 211, SLDA_SLDL_SRDA_SRDL = 212, RLL_RLLG = 213, RISBHH_RISBHL_RISBHG = 214, RISBLH_RISBLL_RISBLG = 215, RISBG_RISBG32_RISBGN_RISBGNZ_RISBGZ = 216, RISBMux = 217, RNSBG_ROSBG_RXSBG = 218, CMux_C_CG_CY = 219, CRL = 220, CFIMux_CHIMux_CFI_CHI = 221, CGFI_CGHI = 222, CGHSI_CGRL = 223, CGR_CR = 224, CIH = 225, CHF = 226, CHSI = 227, CLMux_CL_CLY = 228, CLFHSI = 229, CLFIMux_CLFI = 230, CLG = 231, CLGHRL_CLGHSI = 232, CLGF = 233, CLGFRL = 234, CLGFI_CLGFR = 235, CLGR = 236, CLGRL = 237, CLHF = 238, CLHHSI_CLHRL = 239, CLIH = 240, CLI_CLIY = 241, CLR = 242, CLRL = 243, CHHR_CLHHR = 244, CHLR_CLHLR = 245, CH_CHY = 246, CHRL = 247, CGH = 248, CGHRL = 249, CHHSI = 250, CGF = 251, CGFRL = 252, CGFR = 253, CLC = 254, CLCL_CLCLE_CLCLU = 255, CLST = 256, TM_TMY = 257, TMHMux_TMLMux = 258, TMHH64_TMHH = 259, TMHL64_TMHL = 260, TMLH64_TMLH = 261, TMLL64_TMLL = 262, CLM_CLMH_CLMY = 263, PFD_PFDRL = 264, BPP = 265, BPRP = 266, NIAI = 267, Serialize = 268, LAA_LAAG = 269, LAAL_LAALG = 270, LAN_LANG = 271, LAO_LAOG = 272, LAX_LAXG = 273, TS = 274, CS_CSG_CSY = 275, CDS_CDSY = 276, CDSG = 277, CSST = 278, PLO = 279, LPQ = 280, STPQ = 281, LPD_LPDG = 282, TR = 283, TRT = 284, TRTR = 285, TRE = 286, TRTE_TRTEOpt_TRTRE_TRTREOpt = 287, TROO_TROOOpt_TROT_TROTOpt_TRTO_TRTOOpt_TRTT_TRTTOpt = 288, CU12_CU12Opt_CU14_CU14Opt_CU21_CU21Opt_CU24_CU24Opt_CU41_CU42 = 289, CUTFU_CUTFUOpt_CUUTF_CUUTFOpt = 290, KM_KMA_KMC_KMCTR_KMF_KMO = 291, KDSA_KIMD_KLMD_KMAC = 292, PCC_PPNO_PRNO = 293, LGG = 294, LLGFSG = 295, LGSC_STGSC = 296, CVBG = 297, CVB_CVBY = 298, CVDG = 299, CVD_CVDY = 300, MVN_MVO_MVZ = 301, PACK_PKA_PKU = 302, UNPKA_UNPKU = 303, UNPK = 304, AP_SP_ZAP = 305, MP = 306, DP = 307, SRP = 308, CP = 309, TP = 310, ED_EDMK = 311, CPYA_EAR_SAR = 312, LAE_LAEY = 313, LAM_LAMY = 314, STAM_STAMY = 315, IPM = 316, SPM = 317, BAL_BALR = 318, TAM = 319, SAM24_SAM31_SAM64 = 320, BSM = 321, BASSM = 322, TBEGIN_TBEGINC = 323, TEND = 324, TABORT = 325, ETND = 326, NTSTG = 327, PPA = 328, FLOGR = 329, POPCNT_POPCNTOpt = 330, SRST_SRSTU = 331, CUSE = 332, CFC = 333, UPT = 334, CKSM = 335, CMPSC = 336, SORTL = 337, DFLTCC = 338, NNPA = 339, EX_EXRL = 340, InsnE_InsnRI_InsnRIE_InsnRIL_InsnRILU_InsnRIS_InsnRR_InsnRRE_InsnRRF_InsnRRS_InsnRS_InsnRSE_InsnRSI_InsnRSY_InsnRX_InsnRXE_InsnRXF_InsnRXY_InsnS_InsnSI_InsnSIL_InsnSIY_InsnSS_InsnSSE_InsnSSF_InsnVRI_InsnVRR_InsnVRS_InsnVRV_InsnVRX_InsnVSI = 341, LZDR_LZER = 342, LZXR = 343, LER = 344, LDGR_LDR_LDR32 = 345, LGDR = 346, LXR = 347, LTDBR_LTEBR = 348, LTXBR = 349, CPSDRdd_CPSDRds_CPSDRsd_CPSDRss = 350, LE_LEY = 351, LD_LDE32_LDY = 352, LX = 353, STD_STDY_STE_STEY = 354, STX = 355, LEDBR_LEDBRA = 356, LDXBR_LDXBRA_LEXBR_LEXBRA = 357, LDEB = 358, LDEBR = 359, LXDB_LXEB = 360, LXDBR_LXEBR = 361, CDFBR_CDFBRA_CDGBR_CDGBRA_CEFBR_CEFBRA_CEGBR_CEGBRA = 362, CXFBR_CXFBRA_CXGBR_CXGBRA = 363, CDLFBR_CDLGBR_CELFBR_CELGBR = 364, CXLFBR_CXLGBR = 365, CFDBR_CFDBRA_CFEBR_CFEBRA_CGDBR_CGDBRA_CGEBR_CGEBRA = 366, CFXBR_CFXBRA_CGXBR_CGXBRA = 367, CLFEBR = 368, CLFDBR = 369, CLGDBR_CLGEBR = 370, CLFXBR_CLGXBR = 371, LCDBR_LCEBR_LNDBR_LNEBR_LPDBR_LPEBR = 372, LCDFR_LCDFR_32_LNDFR_LNDFR_32_LPDFR_LPDFR_32 = 373, LCXBR_LNXBR_LPXBR = 374, SQDB_SQEB = 375, SQEBR = 376, SQDBR = 377, SQXBR = 378, FIDBR_FIDBRA_FIEBR_FIEBRA = 379, FIXBR_FIXBRA = 380, ADB_AEB = 381, ADBR_AEBR = 382, AXBR = 383, SDB_SEB = 384, SDBR_SEBR = 385, SXBR = 386, MDB_MDEB_MEEB = 387, MDBR_MDEBR_MEEBR = 388, MXDB = 389, MXDBR = 390, MXBR = 391, MAEB_MSEB = 392, MAEBR_MSEBR = 393, MADB_MSDB = 394, MADBR_MSDBR = 395, DEB = 396, DDB = 397, DEBR = 398, DDBR = 399, DXBR = 400, DIDBR_DIEBR = 401, CDB_CEB_KDB_KEB = 402, CDBR_CEBR_KDBR_KEBR = 403, CXBR_KXBR = 404, TCDB_TCEB = 405, TCXB = 406, EFPC = 407, STFPC = 408, SFPC = 409, LFPC = 410, SFASR = 411, LFAS = 412, SRNM_SRNMB_SRNMT = 413, LTDR_LTER = 414, LTXR = 415, LEDR_LRER = 416, LEXR = 417, LDXR_LRDR = 418, LDE = 419, LDER = 420, LXD_LXE = 421, LXDR_LXER = 422, CDFR_CDGR_CEFR_CEGR = 423, CXFR_CXGR = 424, CFDR_CFER_CGDR_CGER = 425, CFXR_CGXR = 426, THDER_THDR = 427, TBDR_TBEDR = 428, LCDR_LCER_LNDR_LNER_LPDR_LPER = 429, LCXR_LNXR_LPXR = 430, HDR_HER = 431, SQD_SQE = 432, SQER = 433, SQDR = 434, SQXR = 435, FIDR_FIER = 436, FIXR = 437, AD_AE_AU_AW = 438, ADR_AER_AUR_AWR = 439, AXR = 440, SD_SE_SU_SW = 441, SDR_SER_SUR_SWR = 442, SXR = 443, MD_MDE_ME_MEE = 444, MDER_MDR_MEER_MER = 445, MXD = 446, MXDR = 447, MXR = 448, MY = 449, MYH_MYL = 450, MYR = 451, MYHR_MYLR = 452, MAD_MAE_MSD_MSE = 453, MADR_MAER_MSDR_MSER = 454, MAY = 455, MAYH_MAYL = 456, MAYR = 457, MAYHR_MAYLR = 458, DE = 459, DD = 460, DER = 461, DDR = 462, DXR = 463, CD_CE = 464, CDR_CER = 465, CXR = 466, LTDTR = 467, LTXTR = 468, LEDTR = 469, LDXTR = 470, LDETR = 471, LXDTR = 472, CDFTR = 473, CDGTR_CDGTRA = 474, CXFTR = 475, CXGTR_CXGTRA = 476, CDLFTR = 477, CDLGTR = 478, CXLFTR = 479, CXLGTR = 480, CFDTR_CGDTR_CGDTRA = 481, CFXTR_CGXTR_CGXTRA = 482, CLFDTR_CLGDTR = 483, CLFXTR_CLGXTR = 484, CDSTR_CDUTR = 485, CXSTR_CXUTR = 486, CSDTR_CUDTR = 487, CSXTR_CUXTR = 488, CDZT = 489, CXZT = 490, CZDT = 491, CZXT = 492, CDPT = 493, CXPT = 494, CPDT = 495, CPXT = 496, PFPO = 497, FIDTR = 498, FIXTR = 499, EEDTR = 500, EEXTR = 501, ESDTR = 502, ESXTR = 503, ADTR_ADTRA = 504, AXTR_AXTRA = 505, SDTR_SDTRA = 506, SXTR_SXTRA = 507, MDTR_MDTRA = 508, MXTR_MXTRA = 509, DDTR_DDTRA = 510, DXTR_DXTRA = 511, QADTR = 512, QAXTR = 513, RRDTR = 514, RRXTR = 515, SLDT_SRDT = 516, SLXT_SRXT = 517, IEDTR = 518, IEXTR = 519, CDTR_KDTR = 520, CXTR_KXTR = 521, CEDTR = 522, CEXTR = 523, TDCDT_TDCET_TDGDT_TDGET = 524, TDCXT_TDGXT = 525, VLR32_VLR64_VLR = 526, VLGV_VLGVB_VLGVF_VLGVG_VLGVH = 527, VLVG_VLVGB_VLVGF_VLVGG_VLVGH = 528, VLVGP32_VLVGP = 529, VZERO = 530, VONE = 531, VGBM = 532, VGM_VGMB_VGMF_VGMG_VGMH = 533, VREPI_VREPIB_VREPIF_VREPIG_VREPIH = 534, VLEIB_VLEIF_VLEIG_VLEIH = 535, VL_VLAlign = 536, VLBB_VLL = 537, VL32_VL64 = 538, VLLEZ_VLLEZB_VLLEZF_VLLEZG_VLLEZH_VLLEZLF = 539, VLREP_VLREPB_VLREPF_VLREPG_VLREPH = 540, VLEB_VLEF_VLEG_VLEH = 541, VGEF_VGEG = 542, VLM_VLMAlign = 543, VLRL_VLRLR = 544, VST32_VST64_VST_VSTAlign_VSTL = 545, VSTEF_VSTEG = 546, VSTEB_VSTEH = 547, VSTM_VSTMAlign = 548, VSCEF_VSCEG = 549, VSTRL_VSTRLR = 550, VLBR_VLBRF_VLBRG_VLBRH_VLBRQ = 551, VLER_VLERF_VLERG_VLERH = 552, VLEBRF_VLEBRG_VLEBRH = 553, VLLEBRZ_VLLEBRZE_VLLEBRZF_VLLEBRZG_VLLEBRZH = 554, VLBRREP_VLBRREPF_VLBRREPG_VLBRREPH = 555, VSTBR_VSTBRF_VSTBRG_VSTBRH_VSTBRQ = 556, VSTER_VSTERF_VSTERG_VSTERH = 557, VSTEBRH = 558, VSTEBRF_VSTEBRG = 559, VMRH_VMRHB_VMRHF_VMRHG_VMRHH = 560, VMRL_VMRLB_VMRLF_VMRLG_VMRLH = 561, VPERM = 562, VPDI = 563, VBPERM = 564, VREP_VREPB_VREPF_VREPG_VREPH = 565, VSEL = 566, VPK_VPKF_VPKG_VPKH = 567, VPKS_VPKSF_VPKSG_VPKSH = 568, VPKSFS_VPKSGS_VPKSHS = 569, VPKLS_VPKLSF_VPKLSG_VPKLSH = 570, VPKLSFS_VPKLSGS_VPKLSHS = 571, VSEG_VSEGB_VSEGF_VSEGH = 572, VUPH_VUPHB_VUPHF_VUPHH = 573, VUPL_VUPLB_VUPLF = 574, VUPLH_VUPLHB_VUPLHF_VUPLHH_VUPLHW = 575, VUPLL_VUPLLB_VUPLLF_VUPLLH = 576, VA_VAB_VAC_VACQ_VAF_VAG_VAH_VAQ = 577, VACC_VACCB_VACCC_VACCCQ_VACCF_VACCG_VACCH_VACCQ = 578, VAVG_VAVGB_VAVGF_VAVGG_VAVGH = 579, VAVGL_VAVGLB_VAVGLF_VAVGLG_VAVGLH = 580, VN_VNC_VNN_VNO_VNX = 581, VO_VOC = 582, VCKSM = 583, VCLZ_VCLZB_VCLZF_VCLZG_VCLZH = 584, VCTZ_VCTZB_VCTZF_VCTZG_VCTZH = 585, VX = 586, VGFM = 587, VGFMA_VGFMAB_VGFMAF_VGFMAG_VGFMAH = 588, VGFMB_VGFMF_VGFMG_VGFMH = 589, VLC_VLCB_VLCF_VLCG_VLCH = 590, VLP_VLPB_VLPF_VLPG_VLPH = 591, VMX_VMXB_VMXF_VMXG_VMXH = 592, VMXL_VMXLB_VMXLF_VMXLG_VMXLH = 593, VMN_VMNB_VMNF_VMNG_VMNH = 594, VMNL_VMNLB_VMNLF_VMNLG_VMNLH = 595, VMAL_VMALB_VMALF = 596, VMALE_VMALEB_VMALEF_VMALEH = 597, VMALH_VMALHB_VMALHF_VMALHH_VMALHW = 598, VMALO_VMALOB_VMALOF_VMALOH = 599, VMAO_VMAOB_VMAOF_VMAOH = 600, VMAE_VMAEB_VMAEF_VMAEH = 601, VMAH_VMAHB_VMAHF_VMAHH = 602, VME_VMEB_VMEF_VMEH = 603, VMH_VMHB_VMHF_VMHH = 604, VML_VMLB_VMLF = 605, VMLE_VMLEB_VMLEF_VMLEH = 606, VMLH_VMLHB_VMLHF_VMLHH_VMLHW = 607, VMLO_VMLOB_VMLOF_VMLOH = 608, VMO_VMOB_VMOF_VMOH = 609, VMSL_VMSLG = 610, VPOPCT_VPOPCTB_VPOPCTF_VPOPCTG_VPOPCTH = 611, VERLL_VERLLB_VERLLF_VERLLG_VERLLH = 612, VERLLV_VERLLVB_VERLLVF_VERLLVG_VERLLVH = 613, VERIM_VERIMB_VERIMF_VERIMG_VERIMH = 614, VESL_VESLB_VESLF_VESLG_VESLH = 615, VESLV_VESLVB_VESLVF_VESLVG_VESLVH = 616, VESRA_VESRAB_VESRAF_VESRAG_VESRAH = 617, VESRAV_VESRAVB_VESRAVF_VESRAVG_VESRAVH = 618, VESRL_VESRLB_VESRLF_VESRLG_VESRLH = 619, VESRLV_VESRLVB_VESRLVF_VESRLVG_VESRLVH = 620, VSL_VSLDB = 621, VSLB = 622, VSRA_VSRL = 623, VSRAB_VSRLB = 624, VSLD = 625, VSRD = 626, VSB_VSBCBI_VSBCBIQ_VSBI_VSBIQ = 627, VSCBI_VSCBIB_VSCBIF_VSCBIG_VSCBIH_VSCBIQ = 628, VS_VSF_VSG_VSH_VSQ = 629, VSUM_VSUMB_VSUMH = 630, VSUMG_VSUMGF_VSUMGH = 631, VSUMQ_VSUMQF_VSUMQG = 632, VEC_VECB_VECF_VECG_VECH = 633, VECL_VECLB_VECLF_VECLG_VECLH = 634, VCEQ_VCEQB_VCEQF_VCEQG_VCEQH = 635, VCEQBS_VCEQFS_VCEQGS_VCEQHS = 636, VCH_VCHB_VCHF_VCHG_VCHH = 637, VCHBS_VCHFS_VCHGS_VCHHS = 638, VCHL_VCHLB_VCHLF_VCHLG_VCHLH = 639, VCHLBS_VCHLFS_VCHLGS_VCHLHS = 640, VTM = 641, VCFPL_VCFPS = 642, VCDG_VCDLG = 643, VCDGB_VCDLGB = 644, WCDGB_WCDLGB = 645, VCEFB_VCELFB = 646, WCEFB_WCELFB = 647, VCLFP_VCSFP = 648, VCGD_VCLGD = 649, VCGDB_VCLGDB = 650, WCGDB_WCLGDB = 651, VCFEB_VCLFEB = 652, WCFEB_WCLFEB = 653, VLDE_VLED = 654, VLDEB_VLEDB = 655, WLDEB_WLEDB = 656, VFLL_VFLR = 657, VFLLS_VFLRD = 658, WFLLS_WFLRD = 659, WFLLD = 660, WFLRX = 661, VFI_VFIDB = 662, WFIDB = 663, VFISB = 664, WFISB = 665, WFIXB = 666, VFPSO = 667, VFPSODB_WFPSODB = 668, VFPSOSB_WFPSOSB = 669, WFPSOXB = 670, VFLCDB_VFLNDB_VFLPDB_WFLCDB_WFLNDB_WFLPDB = 671, VFLCSB_VFLNSB_VFLPSB_WFLCSB_WFLNSB_WFLPSB = 672, WFLCXB_WFLNXB_WFLPXB = 673, VFMAX_VFMIN = 674, VFMAXDB_VFMINDB = 675, WFMAXDB_WFMINDB = 676, VFMAXSB_VFMINSB = 677, WFMAXSB_WFMINSB = 678, WFMAXXB_WFMINXB = 679, VFTCI = 680, VFTCIDB_WFTCIDB = 681, VFTCISB_WFTCISB = 682, WFTCIXB = 683, VFA_VFS = 684, VFADB_VFSDB = 685, WFADB_WFSDB = 686, VFASB_VFSSB = 687, WFASB_WFSSB = 688, WFAXB_WFSXB = 689, VFM_VFMDB = 690, WFMDB_WFMSB = 691, VFMSB = 692, WFMXB = 693, VFMA_VFMS_VFNMA_VFNMS = 694, VFMADB_VFMSDB_VFNMADB_VFNMSDB = 695, WFMADB_WFMSDB_WFNMADB_WFNMSDB = 696, VFMASB_VFMSSB_VFNMASB_VFNMSSB = 697, WFMASB_WFMSSB_WFNMASB_WFNMSSB = 698, WFMAXB_WFMSXB_WFNMAXB_WFNMSXB = 699, VFD = 700, VFDDB_WFDDB = 701, WFDSB = 702, VFDSB = 703, WFDXB = 704, VFSQ = 705, VFSQDB_WFSQDB = 706, WFSQSB = 707, VFSQSB = 708, WFSQXB = 709, VFCE_VFCH_VFCHE = 710, VFCEDB_VFCHDB_VFCHEDB_VFKEDB_VFKHDB_VFKHEDB = 711, WFCEDB_WFCHDB_WFCHEDB = 712, WFKEDB_WFKHDB_WFKHEDB = 713, VFCESB_VFCHESB_VFCHSB_VFKESB_VFKHESB_VFKHSB = 714, WFCESB_WFCHESB_WFCHSB = 715, WFKESB_WFKHESB_WFKHSB = 716, WFCEXB_WFCHEXB_WFCHXB = 717, WFKEXB_WFKHEXB_WFKHXB = 718, VFCEDBS_VFCHDBS_VFCHEDBS = 719, VFKEDBS_VFKHDBS_VFKHEDBS = 720, WFCEDBS_WFCHDBS_WFCHEDBS_WFKEDBS_WFKHDBS_WFKHEDBS = 721, VFCESBS_VFCHESBS_VFCHSBS_VFKESBS_VFKHESBS_VFKHSBS = 722, WFCESBS_WFCHESBS_WFCHSBS = 723, WFKESBS_WFKHESBS_WFKHSBS = 724, WFCEXBS_WFCHEXBS_WFCHXBS = 725, WFKEXBS_WFKHEXBS_WFKHXBS = 726, WFC_WFK = 727, WFCDB_WFKDB = 728, WFCSB_WFKSB = 729, WFCXB_WFKXB = 730, LEFR = 731, LFER = 732, VFAE_VFAEB = 733, VFAEF_VFAEH = 734, VFAEBS_VFAEFS_VFAEHS = 735, VFAEZB_VFAEZF_VFAEZH = 736, VFAEZBS_VFAEZFS_VFAEZHS = 737, VFEE_VFEEB_VFEEF_VFEEH_VFEEZB_VFEEZF_VFEEZH = 738, VFEEBS_VFEEFS_VFEEHS_VFEEZBS_VFEEZFS_VFEEZHS = 739, VFENE_VFENEB_VFENEF_VFENEH_VFENEZB_VFENEZF_VFENEZH = 740, VFENEBS_VFENEFS_VFENEHS_VFENEZBS_VFENEZFS_VFENEZHS = 741, VISTR_VISTRB_VISTRF_VISTRH = 742, VISTRBS_VISTRFS_VISTRHS = 743, VSTRC_VSTRCB_VSTRCF_VSTRCH = 744, VSTRCBS_VSTRCFS_VSTRCHS = 745, VSTRCZB_VSTRCZF_VSTRCZH = 746, VSTRCZBS_VSTRCZFS_VSTRCZHS = 747, VSTRS_VSTRSB_VSTRSF_VSTRSH = 748, VSTRSZB_VSTRSZF_VSTRSZH = 749, VCFN = 750, VCLFNH_VCLFNL = 751, VCNF_VCRNF = 752, VLIP = 753, VPKZ = 754, VUPKZ = 755, VCVB_VCVBG_VCVBGOpt_VCVBOpt = 756, VCVD_VCVDG = 757, VAP_VSP = 758, VMP_VMSP = 759, VDP_VRP = 760, VSDP = 761, VSRP = 762, VPSOP = 763, VCP_VTP = 764, VSCHDP_VSCHP_VSCHSP_VSCHXP = 765, VSCSHP = 766, VCSPH = 767, VCLZDP = 768, VSRPR = 769, VPKZR = 770, VUPKZH = 771, VUPKZL = 772, EPSW = 773, LPSW_LPSWE_LPSWEY = 774, IPK = 775, SPKA = 776, SSM = 777, STNSM_STOSM = 778, IAC = 779, SAC_SACF = 780, LCTL_LCTLG = 781, STCTG_STCTL = 782, EPAIR_EPAR_ESAIR_ESAR = 783, SSAIR_SSAR = 784, ESEA = 785, SPX_STPX = 786, LBEAR = 787, STBEAR = 788, ISKE = 789, IVSK = 790, SSKE_SSKEOpt = 791, RRBE_RRBM = 792, IRBM = 793, PFMF = 794, TB = 795, PGIN = 796, PGOUT = 797, IPTE_IPTEOpt_IPTEOptOpt = 798, IDTE_IDTEOpt = 799, RDP_RDPOpt = 800, CRDTE_CRDTEOpt = 801, PTLB = 802, CSP_CSPG = 803, LPTEA = 804, LRA_LRAG_LRAY = 805, STRAG = 806, LURA_LURAG = 807, STURA_STURG = 808, TPROT = 809, MVCK_MVCP_MVCS = 810, MVCDK_MVCSK = 811, MVCOS = 812, MVPG = 813, LASP = 814, PALB = 815, PC = 816, PR = 817, PT_PTI = 818, RP = 819, BSA_BSG = 820, TAR = 821, BAKR = 822, EREG_EREGG = 823, ESTA_MSTA = 824, PTFF = 825, SCK_SCKC_SCKPF = 826, SPT = 827, STCK_STCKF = 828, STCKE = 829, STCKC = 830, STPT = 831, STAP = 832, STIDP = 833, STSI = 834, STFL_STFLE = 835, ECAG = 836, ECTG = 837, PTF = 838, PCKMO = 839, QPACI = 840, SVC = 841, MC = 842, DIAG = 843, TRACE_TRACG = 844, TRAP2_TRAP4 = 845, SIGA_SIGP = 846, SIE = 847, LPP = 848, ECPGA = 849, ECCTR_EPCTR = 850, LCCTL = 851, LPCTL_LSCTL = 852, QCTRI_QSI = 853, SCCTR_SPCTR = 854, CSCH_HSCH_RSCH_XSCH = 855, MSCH_SSCH_STSCH_TSCH = 856, RCHP = 857, SCHM = 858, STCPS_STCRW = 859, TPEI_TPI = 860, SAL = 861, NOP_NOPR = 862, LPSW_LPSWE = 863, KIMD_KLMD_KMAC = 864, POPCNT = 865, VFI = 866, VFM = 867, VCVB_VCVBG = 868, AGF = 869, SGF = 870, KM_KMC_KMCTR_KMF_KMO = 871, PCC_PPNO = 872, VLLEZ_VLLEZB_VLLEZF_VLLEZG_VLLEZH = 873, VN_VNC_VNO = 874, VO = 875, VPOPCT = 876, WFMDB = 877, VFMA_VFMS = 878, VFMADB_VFMSDB = 879, WFMADB_WFMSDB = 880, VFCEDB_VFCHDB_VFCHEDB = 881, WFCEDBS_WFCHDBS_WFCHEDBS = 882, TPI = 883, LOCGR_LOCGRAsm_LOCGRAsmE_LOCGRAsmH_LOCGRAsmHE_LOCGRAsmL_LOCGRAsmLE_LOCGRAsmLH_LOCGRAsmM_LOCGRAsmNE_LOCGRAsmNH_LOCGRAsmNHE_LOCGRAsmNL_LOCGRAsmNLE_LOCGRAsmNLH_LOCGRAsmNM_LOCGRAsmNO_LOCGRAsmNP_LOCGRAsmNZ_LOCGRAsmO_LOCGRAsmP_LOCGRAsmZ_LOCR_LOCRAsm_LOCRAsmE_LOCRAsmH_LOCRAsmHE_LOCRAsmL_LOCRAsmLE_LOCRAsmLH_LOCRAsmM_LOCRAsmNE_LOCRAsmNH_LOCRAsmNHE_LOCRAsmNL_LOCRAsmNLE_LOCRAsmNLH_LOCRAsmNM_LOCRAsmNO_LOCRAsmNP_LOCRAsmNZ_LOCRAsmO_LOCRAsmP_LOCRAsmZ = 884, LOC_LOCAsm_LOCAsmE_LOCAsmH_LOCAsmHE_LOCAsmL_LOCAsmLE_LOCAsmLH_LOCAsmM_LOCAsmNE_LOCAsmNH_LOCAsmNHE_LOCAsmNL_LOCAsmNLE_LOCAsmNLH_LOCAsmNM_LOCAsmNO_LOCAsmNP_LOCAsmNZ_LOCAsmO_LOCAsmP_LOCAsmZ_LOCG_LOCGAsm_LOCGAsmE_LOCGAsmH_LOCGAsmHE_LOCGAsmL_LOCGAsmLE_LOCGAsmLH_LOCGAsmM_LOCGAsmNE_LOCGAsmNH_LOCGAsmNHE_LOCGAsmNL_LOCGAsmNLE_LOCGAsmNLH_LOCGAsmNM_LOCGAsmNO_LOCGAsmNP_LOCGAsmNZ_LOCGAsmO_LOCGAsmP_LOCGAsmZ = 885, STOC_STOCAsm_STOCAsmE_STOCAsmH_STOCAsmHE_STOCAsmL_STOCAsmLE_STOCAsmLH_STOCAsmM_STOCAsmNE_STOCAsmNH_STOCAsmNHE_STOCAsmNL_STOCAsmNLE_STOCAsmNLH_STOCAsmNM_STOCAsmNO_STOCAsmNP_STOCAsmNZ_STOCAsmO_STOCAsmP_STOCAsmZ_STOCG_STOCGAsm_STOCGAsmE_STOCGAsmH_STOCGAsmHE_STOCGAsmL_STOCGAsmLE_STOCGAsmLH_STOCGAsmM_STOCGAsmNE_STOCGAsmNH_STOCGAsmNHE_STOCGAsmNL_STOCGAsmNLE_STOCGAsmNLH_STOCGAsmNM_STOCGAsmNO_STOCGAsmNP_STOCGAsmNZ_STOCGAsmO_STOCGAsmP_STOCGAsmZ = 886, ALSI_ASI = 887, ALGF = 888, PCC = 889, CELFBR_CELGBR = 890, MD_MEE = 891, MDR_MEER = 892, CFDTR = 893, CFXTR = 894, TDCDT_TDGDT = 895, SCK = 896, SCKPF = 897, RISBG_RISBG32_RISBGZ = 898, SCHED_LIST_END = 899 }; } // end namespace Sched } // end namespace SystemZ } // end namespace llvm #endif // GET_INSTRINFO_SCHED_ENUM #if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) namespace llvm { struct SystemZInstrTable { MCInstrDesc Insts[3143]; static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo"); MCOperandInfo OperandInfo[1652]; static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps"); MCPhysReg ImplicitOps[102]; }; } // end namespace llvm #endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) #ifdef GET_INSTRINFO_MC_DESC #undef GET_INSTRINFO_MC_DESC namespace llvm { static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0); static constexpr unsigned SystemZImpOpBase = sizeof SystemZInstrTable::OperandInfo / (sizeof(MCPhysReg)); extern const SystemZInstrTable SystemZDescs = { { { 3142, 6, 0, 6, 305, 0, 1, SystemZImpOpBase + 0, 544, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #3142 = ZAP { 3141, 5, 1, 6, 168, 0, 1, SystemZImpOpBase + 0, 487, 0|(1ULL<<MCID::MayLoad), 0x2308cULL }, // Inst #3141 = XY { 3140, 0, 0, 4, 855, 1, 1, SystemZImpOpBase + 41, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #3140 = XSCH { 3139, 3, 1, 4, 174, 0, 1, SystemZImpOpBase + 0, 541, 0|(1ULL<<MCID::Commutable), 0x23000ULL }, // Inst #3139 = XRK { 3138, 3, 1, 2, 174, 0, 1, SystemZImpOpBase + 0, 538, 0|(1ULL<<MCID::Commutable), 0x23000ULL }, // Inst #3138 = XR { 3137, 3, 0, 6, 169, 0, 1, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #3137 = XIY { 3136, 3, 1, 6, 173, 0, 1, SystemZImpOpBase + 0, 515, 0, 0x23000ULL }, // Inst #3136 = XILF { 3135, 3, 1, 6, 172, 0, 1, SystemZImpOpBase + 0, 535, 0, 0x23000ULL }, // Inst #3135 = XIHF { 3134, 3, 0, 4, 169, 0, 1, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #3134 = XI { 3133, 3, 1, 4, 171, 0, 1, SystemZImpOpBase + 0, 382, 0|(1ULL<<MCID::Commutable), 0x23000ULL }, // Inst #3133 = XGRK { 3132, 3, 1, 4, 171, 0, 1, SystemZImpOpBase + 0, 526, 0|(1ULL<<MCID::Commutable), 0x23000ULL }, // Inst #3132 = XGR { 3131, 5, 1, 6, 168, 0, 1, SystemZImpOpBase + 0, 518, 0|(1ULL<<MCID::MayLoad), 0x2310cULL }, // Inst #3131 = XG { 3130, 5, 0, 6, 175, 0, 1, SystemZImpOpBase + 0, 789, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #3130 = XC { 3129, 5, 1, 4, 168, 0, 1, SystemZImpOpBase + 0, 487, 0|(1ULL<<MCID::MayLoad), 0x23088ULL }, // Inst #3129 = X { 3128, 4, 1, 6, 656, 1, 0, SystemZImpOpBase + 12, 1622, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3128 = WLEDB { 3127, 2, 1, 6, 656, 1, 0, SystemZImpOpBase + 12, 1620, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3127 = WLDEB { 3126, 3, 1, 6, 683, 0, 1, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #3126 = WFTCIXB { 3125, 3, 1, 6, 682, 0, 1, SystemZImpOpBase + 0, 1649, 0, 0x0ULL }, // Inst #3125 = WFTCISB { 3124, 3, 1, 6, 681, 0, 1, SystemZImpOpBase + 0, 1646, 0, 0x0ULL }, // Inst #3124 = WFTCIDB { 3123, 3, 1, 6, 689, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3123 = WFSXB { 3122, 3, 1, 6, 688, 1, 0, SystemZImpOpBase + 12, 1615, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3122 = WFSSB { 3121, 2, 1, 6, 709, 1, 0, SystemZImpOpBase + 12, 415, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3121 = WFSQXB { 3120, 2, 1, 6, 707, 1, 0, SystemZImpOpBase + 12, 480, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3120 = WFSQSB { 3119, 2, 1, 6, 706, 1, 0, SystemZImpOpBase + 12, 482, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3119 = WFSQDB { 3118, 3, 1, 6, 686, 1, 0, SystemZImpOpBase + 12, 1612, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3118 = WFSDB { 3117, 3, 1, 6, 670, 0, 0, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #3117 = WFPSOXB { 3116, 3, 1, 6, 669, 0, 0, SystemZImpOpBase + 0, 1649, 0, 0x0ULL }, // Inst #3116 = WFPSOSB { 3115, 3, 1, 6, 668, 0, 0, SystemZImpOpBase + 0, 1646, 0, 0x0ULL }, // Inst #3115 = WFPSODB { 3114, 4, 1, 6, 699, 1, 0, SystemZImpOpBase + 12, 1449, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3114 = WFNMSXB { 3113, 4, 1, 6, 698, 1, 0, SystemZImpOpBase + 12, 1634, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3113 = WFNMSSB { 3112, 4, 1, 6, 696, 1, 0, SystemZImpOpBase + 12, 1630, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3112 = WFNMSDB { 3111, 4, 1, 6, 699, 1, 0, SystemZImpOpBase + 12, 1449, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3111 = WFNMAXB { 3110, 4, 1, 6, 698, 1, 0, SystemZImpOpBase + 12, 1634, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3110 = WFNMASB { 3109, 4, 1, 6, 696, 1, 0, SystemZImpOpBase + 12, 1630, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3109 = WFNMADB { 3108, 3, 1, 6, 693, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3108 = WFMXB { 3107, 4, 1, 6, 699, 1, 0, SystemZImpOpBase + 12, 1449, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3107 = WFMSXB { 3106, 4, 1, 6, 698, 1, 0, SystemZImpOpBase + 12, 1634, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3106 = WFMSSB { 3105, 4, 1, 6, 880, 1, 0, SystemZImpOpBase + 12, 1630, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3105 = WFMSDB { 3104, 3, 1, 6, 691, 1, 0, SystemZImpOpBase + 12, 1615, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3104 = WFMSB { 3103, 4, 1, 6, 679, 1, 0, SystemZImpOpBase + 12, 1437, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3103 = WFMINXB { 3102, 4, 1, 6, 678, 1, 0, SystemZImpOpBase + 12, 1642, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3102 = WFMINSB { 3101, 4, 1, 6, 676, 1, 0, SystemZImpOpBase + 12, 1638, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3101 = WFMINDB { 3100, 3, 1, 6, 877, 1, 0, SystemZImpOpBase + 12, 1612, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3100 = WFMDB { 3099, 4, 1, 6, 679, 1, 0, SystemZImpOpBase + 12, 1437, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3099 = WFMAXXB { 3098, 4, 1, 6, 678, 1, 0, SystemZImpOpBase + 12, 1642, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3098 = WFMAXSB { 3097, 4, 1, 6, 676, 1, 0, SystemZImpOpBase + 12, 1638, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3097 = WFMAXDB { 3096, 4, 1, 6, 699, 1, 0, SystemZImpOpBase + 12, 1449, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3096 = WFMAXB { 3095, 4, 1, 6, 698, 1, 0, SystemZImpOpBase + 12, 1634, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3095 = WFMASB { 3094, 4, 1, 6, 880, 1, 0, SystemZImpOpBase + 12, 1630, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3094 = WFMADB { 3093, 4, 1, 6, 661, 1, 0, SystemZImpOpBase + 12, 1626, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3093 = WFLRX { 3092, 4, 1, 6, 659, 1, 0, SystemZImpOpBase + 12, 1622, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3092 = WFLRD { 3091, 2, 1, 6, 673, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #3091 = WFLPXB { 3090, 2, 1, 6, 672, 0, 0, SystemZImpOpBase + 0, 480, 0, 0x0ULL }, // Inst #3090 = WFLPSB { 3089, 2, 1, 6, 671, 0, 0, SystemZImpOpBase + 0, 482, 0, 0x0ULL }, // Inst #3089 = WFLPDB { 3088, 2, 1, 6, 673, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #3088 = WFLNXB { 3087, 2, 1, 6, 672, 0, 0, SystemZImpOpBase + 0, 480, 0, 0x0ULL }, // Inst #3087 = WFLNSB { 3086, 2, 1, 6, 671, 0, 0, SystemZImpOpBase + 0, 482, 0, 0x0ULL }, // Inst #3086 = WFLNDB { 3085, 2, 1, 6, 659, 1, 0, SystemZImpOpBase + 12, 1620, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3085 = WFLLS { 3084, 2, 1, 6, 660, 1, 0, SystemZImpOpBase + 12, 1618, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3084 = WFLLD { 3083, 2, 1, 6, 673, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #3083 = WFLCXB { 3082, 2, 1, 6, 672, 0, 0, SystemZImpOpBase + 0, 480, 0, 0x0ULL }, // Inst #3082 = WFLCSB { 3081, 2, 1, 6, 671, 0, 0, SystemZImpOpBase + 0, 482, 0, 0x0ULL }, // Inst #3081 = WFLCDB { 3080, 2, 0, 6, 730, 1, 1, SystemZImpOpBase + 1, 415, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3080 = WFKXB { 3079, 2, 0, 6, 729, 1, 1, SystemZImpOpBase + 1, 480, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3079 = WFKSB { 3078, 3, 1, 6, 726, 1, 1, SystemZImpOpBase + 1, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3078 = WFKHXBS { 3077, 3, 1, 6, 718, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3077 = WFKHXB { 3076, 3, 1, 6, 724, 1, 1, SystemZImpOpBase + 1, 1615, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3076 = WFKHSBS { 3075, 3, 1, 6, 716, 1, 0, SystemZImpOpBase + 12, 1615, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3075 = WFKHSB { 3074, 3, 1, 6, 726, 1, 1, SystemZImpOpBase + 1, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3074 = WFKHEXBS { 3073, 3, 1, 6, 718, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3073 = WFKHEXB { 3072, 3, 1, 6, 724, 1, 1, SystemZImpOpBase + 1, 1615, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3072 = WFKHESBS { 3071, 3, 1, 6, 716, 1, 0, SystemZImpOpBase + 12, 1615, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3071 = WFKHESB { 3070, 3, 1, 6, 721, 1, 1, SystemZImpOpBase + 1, 1612, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3070 = WFKHEDBS { 3069, 3, 1, 6, 713, 1, 0, SystemZImpOpBase + 12, 1612, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3069 = WFKHEDB { 3068, 3, 1, 6, 721, 1, 1, SystemZImpOpBase + 1, 1612, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3068 = WFKHDBS { 3067, 3, 1, 6, 713, 1, 0, SystemZImpOpBase + 12, 1612, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3067 = WFKHDB { 3066, 3, 1, 6, 726, 1, 1, SystemZImpOpBase + 1, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3066 = WFKEXBS { 3065, 3, 1, 6, 718, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3065 = WFKEXB { 3064, 3, 1, 6, 724, 1, 1, SystemZImpOpBase + 1, 1615, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3064 = WFKESBS { 3063, 3, 1, 6, 716, 1, 0, SystemZImpOpBase + 12, 1615, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3063 = WFKESB { 3062, 3, 1, 6, 721, 1, 1, SystemZImpOpBase + 1, 1612, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3062 = WFKEDBS { 3061, 3, 1, 6, 713, 1, 0, SystemZImpOpBase + 12, 1612, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3061 = WFKEDB { 3060, 2, 0, 6, 728, 1, 1, SystemZImpOpBase + 1, 482, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3060 = WFKDB { 3059, 4, 0, 6, 727, 1, 1, SystemZImpOpBase + 1, 1604, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3059 = WFK { 3058, 4, 1, 6, 666, 1, 0, SystemZImpOpBase + 12, 1458, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3058 = WFIXB { 3057, 4, 1, 6, 665, 1, 0, SystemZImpOpBase + 12, 1608, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3057 = WFISB { 3056, 4, 1, 6, 663, 1, 0, SystemZImpOpBase + 12, 1604, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3056 = WFIDB { 3055, 3, 1, 6, 704, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3055 = WFDXB { 3054, 3, 1, 6, 702, 1, 0, SystemZImpOpBase + 12, 1615, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3054 = WFDSB { 3053, 3, 1, 6, 701, 1, 0, SystemZImpOpBase + 12, 1612, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3053 = WFDDB { 3052, 2, 0, 6, 730, 1, 1, SystemZImpOpBase + 1, 415, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3052 = WFCXB { 3051, 2, 0, 6, 729, 1, 1, SystemZImpOpBase + 1, 480, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3051 = WFCSB { 3050, 3, 1, 6, 725, 1, 1, SystemZImpOpBase + 1, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3050 = WFCHXBS { 3049, 3, 1, 6, 717, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3049 = WFCHXB { 3048, 3, 1, 6, 723, 1, 1, SystemZImpOpBase + 1, 1615, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3048 = WFCHSBS { 3047, 3, 1, 6, 715, 1, 0, SystemZImpOpBase + 12, 1615, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3047 = WFCHSB { 3046, 3, 1, 6, 725, 1, 1, SystemZImpOpBase + 1, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3046 = WFCHEXBS { 3045, 3, 1, 6, 717, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3045 = WFCHEXB { 3044, 3, 1, 6, 723, 1, 1, SystemZImpOpBase + 1, 1615, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3044 = WFCHESBS { 3043, 3, 1, 6, 715, 1, 0, SystemZImpOpBase + 12, 1615, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3043 = WFCHESB { 3042, 3, 1, 6, 882, 1, 1, SystemZImpOpBase + 1, 1612, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3042 = WFCHEDBS { 3041, 3, 1, 6, 712, 1, 0, SystemZImpOpBase + 12, 1612, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3041 = WFCHEDB { 3040, 3, 1, 6, 882, 1, 1, SystemZImpOpBase + 1, 1612, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3040 = WFCHDBS { 3039, 3, 1, 6, 712, 1, 0, SystemZImpOpBase + 12, 1612, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3039 = WFCHDB { 3038, 3, 1, 6, 725, 1, 1, SystemZImpOpBase + 1, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3038 = WFCEXBS { 3037, 3, 1, 6, 717, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3037 = WFCEXB { 3036, 3, 1, 6, 723, 1, 1, SystemZImpOpBase + 1, 1615, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3036 = WFCESBS { 3035, 3, 1, 6, 715, 1, 0, SystemZImpOpBase + 12, 1615, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3035 = WFCESB { 3034, 3, 1, 6, 882, 1, 1, SystemZImpOpBase + 1, 1612, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3034 = WFCEDBS { 3033, 3, 1, 6, 712, 1, 0, SystemZImpOpBase + 12, 1612, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3033 = WFCEDB { 3032, 2, 0, 6, 728, 1, 1, SystemZImpOpBase + 1, 482, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3032 = WFCDB { 3031, 4, 0, 6, 727, 1, 1, SystemZImpOpBase + 1, 1604, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3031 = WFC { 3030, 3, 1, 6, 689, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3030 = WFAXB { 3029, 3, 1, 6, 688, 1, 0, SystemZImpOpBase + 12, 1615, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3029 = WFASB { 3028, 3, 1, 6, 686, 1, 0, SystemZImpOpBase + 12, 1612, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3028 = WFADB { 3027, 4, 1, 6, 651, 1, 0, SystemZImpOpBase + 12, 1604, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3027 = WCLGDB { 3026, 4, 1, 6, 653, 1, 0, SystemZImpOpBase + 12, 1608, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3026 = WCLFEB { 3025, 4, 1, 6, 651, 1, 0, SystemZImpOpBase + 12, 1604, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3025 = WCGDB { 3024, 4, 1, 6, 653, 1, 0, SystemZImpOpBase + 12, 1608, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3024 = WCFEB { 3023, 4, 1, 6, 647, 1, 0, SystemZImpOpBase + 12, 1608, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3023 = WCELFB { 3022, 4, 1, 6, 647, 1, 0, SystemZImpOpBase + 12, 1608, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3022 = WCEFB { 3021, 4, 1, 6, 645, 1, 0, SystemZImpOpBase + 12, 1604, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3021 = WCDLGB { 3020, 4, 1, 6, 645, 1, 0, SystemZImpOpBase + 12, 1604, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #3020 = WCDGB { 3019, 1, 1, 6, 530, 0, 0, SystemZImpOpBase + 0, 1598, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #3019 = VZERO { 3018, 3, 1, 6, 586, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #3018 = VX { 3017, 2, 1, 6, 576, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #3017 = VUPLLH { 3016, 2, 1, 6, 576, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #3016 = VUPLLF { 3015, 2, 1, 6, 576, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #3015 = VUPLLB { 3014, 3, 1, 6, 576, 0, 0, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #3014 = VUPLL { 3013, 2, 1, 6, 575, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #3013 = VUPLHW { 3012, 2, 1, 6, 575, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #3012 = VUPLHH { 3011, 2, 1, 6, 575, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #3011 = VUPLHF { 3010, 2, 1, 6, 575, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #3010 = VUPLHB { 3009, 3, 1, 6, 575, 0, 0, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #3009 = VUPLH { 3008, 2, 1, 6, 574, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #3008 = VUPLF { 3007, 2, 1, 6, 574, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #3007 = VUPLB { 3006, 3, 1, 6, 574, 0, 0, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #3006 = VUPL { 3005, 3, 1, 6, 772, 0, 1, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #3005 = VUPKZL { 3004, 3, 1, 6, 771, 0, 1, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #3004 = VUPKZH { 3003, 4, 0, 6, 755, 0, 0, SystemZImpOpBase + 0, 1575, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #3003 = VUPKZ { 3002, 2, 1, 6, 573, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #3002 = VUPHH { 3001, 2, 1, 6, 573, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #3001 = VUPHF { 3000, 2, 1, 6, 573, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #3000 = VUPHB { 2999, 3, 1, 6, 573, 0, 0, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #2999 = VUPH { 2998, 1, 0, 6, 764, 0, 1, SystemZImpOpBase + 0, 1598, 0, 0x0ULL }, // Inst #2998 = VTP { 2997, 2, 0, 6, 641, 0, 1, SystemZImpOpBase + 0, 415, 0|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #2997 = VTM { 2996, 3, 1, 6, 632, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2996 = VSUMQG { 2995, 3, 1, 6, 632, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2995 = VSUMQF { 2994, 4, 1, 6, 632, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2994 = VSUMQ { 2993, 3, 1, 6, 630, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2993 = VSUMH { 2992, 3, 1, 6, 631, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2992 = VSUMGH { 2991, 3, 1, 6, 631, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2991 = VSUMGF { 2990, 4, 1, 6, 631, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2990 = VSUMG { 2989, 3, 1, 6, 630, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2989 = VSUMB { 2988, 4, 1, 6, 630, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2988 = VSUM { 2987, 4, 1, 6, 749, 0, 1, SystemZImpOpBase + 0, 1449, 0, 0x0ULL }, // Inst #2987 = VSTRSZH { 2986, 4, 1, 6, 749, 0, 1, SystemZImpOpBase + 0, 1449, 0, 0x0ULL }, // Inst #2986 = VSTRSZF { 2985, 4, 1, 6, 749, 0, 1, SystemZImpOpBase + 0, 1449, 0, 0x0ULL }, // Inst #2985 = VSTRSZB { 2984, 5, 1, 6, 748, 0, 1, SystemZImpOpBase + 0, 1444, 0, 0x0ULL }, // Inst #2984 = VSTRSH { 2983, 5, 1, 6, 748, 0, 1, SystemZImpOpBase + 0, 1444, 0, 0x0ULL }, // Inst #2983 = VSTRSF { 2982, 5, 1, 6, 748, 0, 1, SystemZImpOpBase + 0, 1444, 0, 0x0ULL }, // Inst #2982 = VSTRSB { 2981, 6, 1, 6, 748, 0, 1, SystemZImpOpBase + 0, 1513, 0, 0x0ULL }, // Inst #2981 = VSTRS { 2980, 4, 0, 6, 550, 0, 0, SystemZImpOpBase + 0, 1562, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2980 = VSTRLR { 2979, 4, 0, 6, 550, 0, 0, SystemZImpOpBase + 0, 1575, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2979 = VSTRL { 2978, 5, 1, 6, 747, 0, 1, SystemZImpOpBase + 0, 1444, 0, 0x0ULL }, // Inst #2978 = VSTRCZHS { 2977, 5, 1, 6, 746, 0, 0, SystemZImpOpBase + 0, 1444, 0, 0x0ULL }, // Inst #2977 = VSTRCZH { 2976, 5, 1, 6, 747, 0, 1, SystemZImpOpBase + 0, 1444, 0, 0x0ULL }, // Inst #2976 = VSTRCZFS { 2975, 5, 1, 6, 746, 0, 0, SystemZImpOpBase + 0, 1444, 0, 0x0ULL }, // Inst #2975 = VSTRCZF { 2974, 5, 1, 6, 747, 0, 1, SystemZImpOpBase + 0, 1444, 0, 0x0ULL }, // Inst #2974 = VSTRCZBS { 2973, 5, 1, 6, 746, 0, 0, SystemZImpOpBase + 0, 1444, 0, 0x0ULL }, // Inst #2973 = VSTRCZB { 2972, 5, 1, 6, 745, 0, 1, SystemZImpOpBase + 0, 1444, 0, 0x0ULL }, // Inst #2972 = VSTRCHS { 2971, 5, 1, 6, 744, 0, 0, SystemZImpOpBase + 0, 1444, 0, 0x0ULL }, // Inst #2971 = VSTRCH { 2970, 5, 1, 6, 745, 0, 1, SystemZImpOpBase + 0, 1444, 0, 0x0ULL }, // Inst #2970 = VSTRCFS { 2969, 5, 1, 6, 744, 0, 0, SystemZImpOpBase + 0, 1444, 0, 0x0ULL }, // Inst #2969 = VSTRCF { 2968, 5, 1, 6, 745, 0, 1, SystemZImpOpBase + 0, 1444, 0, 0x0ULL }, // Inst #2968 = VSTRCBS { 2967, 5, 1, 6, 744, 0, 0, SystemZImpOpBase + 0, 1444, 0, 0x0ULL }, // Inst #2967 = VSTRCB { 2966, 6, 1, 6, 744, 0, 1, SystemZImpOpBase + 0, 1513, 0, 0x0ULL }, // Inst #2966 = VSTRC { 2965, 5, 0, 6, 548, 0, 0, SystemZImpOpBase + 0, 1570, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2965 = VSTMAlign { 2964, 4, 0, 6, 548, 0, 0, SystemZImpOpBase + 0, 1566, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2964 = VSTM { 2963, 4, 0, 6, 545, 0, 0, SystemZImpOpBase + 0, 1562, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2963 = VSTL { 2962, 4, 0, 6, 557, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayStore), 0x200ULL }, // Inst #2962 = VSTERH { 2961, 4, 0, 6, 557, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayStore), 0x200ULL }, // Inst #2961 = VSTERG { 2960, 4, 0, 6, 557, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayStore), 0x200ULL }, // Inst #2960 = VSTERF { 2959, 5, 0, 6, 557, 0, 0, SystemZImpOpBase + 0, 1538, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2959 = VSTER { 2958, 5, 0, 6, 547, 0, 0, SystemZImpOpBase + 0, 1538, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2958 = VSTEH { 2957, 5, 0, 6, 546, 0, 0, SystemZImpOpBase + 0, 1538, 0|(1ULL<<MCID::MayStore), 0x100ULL }, // Inst #2957 = VSTEG { 2956, 5, 0, 6, 546, 0, 0, SystemZImpOpBase + 0, 1538, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #2956 = VSTEF { 2955, 5, 0, 6, 558, 0, 0, SystemZImpOpBase + 0, 1538, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2955 = VSTEBRH { 2954, 5, 0, 6, 559, 0, 0, SystemZImpOpBase + 0, 1538, 0|(1ULL<<MCID::MayStore), 0x100ULL }, // Inst #2954 = VSTEBRG { 2953, 5, 0, 6, 559, 0, 0, SystemZImpOpBase + 0, 1538, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #2953 = VSTEBRF { 2952, 5, 0, 6, 547, 0, 0, SystemZImpOpBase + 0, 1538, 0|(1ULL<<MCID::MayStore), 0x20ULL }, // Inst #2952 = VSTEB { 2951, 4, 0, 6, 556, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayStore), 0x200ULL }, // Inst #2951 = VSTBRQ { 2950, 4, 0, 6, 556, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayStore), 0x200ULL }, // Inst #2950 = VSTBRH { 2949, 4, 0, 6, 556, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayStore), 0x200ULL }, // Inst #2949 = VSTBRG { 2948, 4, 0, 6, 556, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayStore), 0x200ULL }, // Inst #2948 = VSTBRF { 2947, 5, 0, 6, 556, 0, 0, SystemZImpOpBase + 0, 1538, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2947 = VSTBR { 2946, 5, 0, 6, 545, 0, 0, SystemZImpOpBase + 0, 1538, 0|(1ULL<<MCID::MayStore), 0x200ULL }, // Inst #2946 = VSTAlign { 2945, 4, 0, 6, 545, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayStore), 0x200ULL }, // Inst #2945 = VST { 2944, 5, 1, 6, 769, 0, 1, SystemZImpOpBase + 0, 427, 0, 0x0ULL }, // Inst #2944 = VSRPR { 2943, 5, 1, 6, 762, 0, 1, SystemZImpOpBase + 0, 1453, 0, 0x0ULL }, // Inst #2943 = VSRP { 2942, 3, 1, 6, 624, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2942 = VSRLB { 2941, 3, 1, 6, 623, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2941 = VSRL { 2940, 4, 1, 6, 626, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2940 = VSRD { 2939, 3, 1, 6, 624, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2939 = VSRAB { 2938, 3, 1, 6, 623, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2938 = VSRA { 2937, 3, 1, 6, 629, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2937 = VSQ { 2936, 5, 1, 6, 758, 0, 1, SystemZImpOpBase + 0, 427, 0, 0x0ULL }, // Inst #2936 = VSP { 2935, 4, 1, 6, 621, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2935 = VSLDB { 2934, 4, 1, 6, 625, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2934 = VSLD { 2933, 3, 1, 6, 622, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2933 = VSLB { 2932, 3, 1, 6, 621, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2932 = VSL { 2931, 3, 1, 6, 629, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2931 = VSH { 2930, 3, 1, 6, 629, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2930 = VSG { 2929, 3, 1, 6, 629, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2929 = VSF { 2928, 4, 1, 6, 566, 0, 0, SystemZImpOpBase + 0, 1449, 0, 0x0ULL }, // Inst #2928 = VSEL { 2927, 2, 1, 6, 572, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2927 = VSEGH { 2926, 2, 1, 6, 572, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2926 = VSEGF { 2925, 2, 1, 6, 572, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2925 = VSEGB { 2924, 3, 1, 6, 572, 0, 0, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #2924 = VSEG { 2923, 5, 1, 6, 761, 0, 1, SystemZImpOpBase + 0, 427, 0, 0x0ULL }, // Inst #2923 = VSDP { 2922, 3, 1, 6, 766, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2922 = VSCSHP { 2921, 4, 1, 6, 765, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2921 = VSCHXP { 2920, 4, 1, 6, 765, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2920 = VSCHSP { 2919, 5, 1, 6, 765, 0, 0, SystemZImpOpBase + 0, 427, 0, 0x0ULL }, // Inst #2919 = VSCHP { 2918, 4, 1, 6, 765, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2918 = VSCHDP { 2917, 5, 0, 6, 549, 0, 0, SystemZImpOpBase + 0, 1599, 0|(1ULL<<MCID::MayStore), 0x100ULL }, // Inst #2917 = VSCEG { 2916, 5, 0, 6, 549, 0, 0, SystemZImpOpBase + 0, 1599, 0|(1ULL<<MCID::MayStore), 0x80ULL }, // Inst #2916 = VSCEF { 2915, 3, 1, 6, 628, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2915 = VSCBIQ { 2914, 3, 1, 6, 628, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2914 = VSCBIH { 2913, 3, 1, 6, 628, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2913 = VSCBIG { 2912, 3, 1, 6, 628, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2912 = VSCBIF { 2911, 3, 1, 6, 628, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2911 = VSCBIB { 2910, 4, 1, 6, 628, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2910 = VSCBI { 2909, 4, 1, 6, 627, 0, 0, SystemZImpOpBase + 0, 1449, 0, 0x0ULL }, // Inst #2909 = VSBIQ { 2908, 5, 1, 6, 627, 0, 0, SystemZImpOpBase + 0, 1444, 0, 0x0ULL }, // Inst #2908 = VSBI { 2907, 4, 1, 6, 627, 0, 0, SystemZImpOpBase + 0, 1449, 0, 0x0ULL }, // Inst #2907 = VSBCBIQ { 2906, 5, 1, 6, 627, 0, 0, SystemZImpOpBase + 0, 1444, 0, 0x0ULL }, // Inst #2906 = VSBCBI { 2905, 3, 1, 6, 627, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2905 = VSB { 2904, 4, 1, 6, 629, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2904 = VS { 2903, 5, 1, 6, 760, 0, 1, SystemZImpOpBase + 0, 427, 0, 0x0ULL }, // Inst #2903 = VRP { 2902, 2, 1, 6, 534, 0, 0, SystemZImpOpBase + 0, 1519, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #2902 = VREPIH { 2901, 2, 1, 6, 534, 0, 0, SystemZImpOpBase + 0, 1519, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #2901 = VREPIG { 2900, 2, 1, 6, 534, 0, 0, SystemZImpOpBase + 0, 1519, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #2900 = VREPIF { 2899, 2, 1, 6, 534, 0, 0, SystemZImpOpBase + 0, 1519, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #2899 = VREPIB { 2898, 3, 1, 6, 534, 0, 0, SystemZImpOpBase + 0, 1531, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #2898 = VREPI { 2897, 3, 1, 6, 565, 0, 0, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #2897 = VREPH { 2896, 3, 1, 6, 565, 0, 0, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #2896 = VREPG { 2895, 3, 1, 6, 565, 0, 0, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #2895 = VREPF { 2894, 3, 1, 6, 565, 0, 0, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #2894 = VREPB { 2893, 4, 1, 6, 565, 0, 0, SystemZImpOpBase + 0, 1458, 0, 0x0ULL }, // Inst #2893 = VREP { 2892, 5, 1, 6, 763, 0, 1, SystemZImpOpBase + 0, 1453, 0, 0x0ULL }, // Inst #2892 = VPSOP { 2891, 2, 1, 6, 611, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2891 = VPOPCTH { 2890, 2, 1, 6, 611, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2890 = VPOPCTG { 2889, 2, 1, 6, 611, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2889 = VPOPCTF { 2888, 2, 1, 6, 611, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2888 = VPOPCTB { 2887, 3, 1, 6, 876, 0, 0, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #2887 = VPOPCT { 2886, 5, 1, 6, 770, 0, 1, SystemZImpOpBase + 0, 427, 0, 0x0ULL }, // Inst #2886 = VPKZR { 2885, 4, 1, 6, 754, 0, 0, SystemZImpOpBase + 0, 1575, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2885 = VPKZ { 2884, 3, 1, 6, 569, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2884 = VPKSHS { 2883, 3, 1, 6, 568, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2883 = VPKSH { 2882, 3, 1, 6, 569, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2882 = VPKSGS { 2881, 3, 1, 6, 568, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2881 = VPKSG { 2880, 3, 1, 6, 569, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2880 = VPKSFS { 2879, 3, 1, 6, 568, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2879 = VPKSF { 2878, 5, 1, 6, 568, 0, 1, SystemZImpOpBase + 0, 427, 0, 0x0ULL }, // Inst #2878 = VPKS { 2877, 3, 1, 6, 571, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2877 = VPKLSHS { 2876, 3, 1, 6, 570, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2876 = VPKLSH { 2875, 3, 1, 6, 571, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2875 = VPKLSGS { 2874, 3, 1, 6, 570, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2874 = VPKLSG { 2873, 3, 1, 6, 571, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2873 = VPKLSFS { 2872, 3, 1, 6, 570, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2872 = VPKLSF { 2871, 5, 1, 6, 570, 0, 1, SystemZImpOpBase + 0, 427, 0, 0x0ULL }, // Inst #2871 = VPKLS { 2870, 3, 1, 6, 567, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2870 = VPKH { 2869, 3, 1, 6, 567, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2869 = VPKG { 2868, 3, 1, 6, 567, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2868 = VPKF { 2867, 4, 1, 6, 567, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2867 = VPK { 2866, 4, 1, 6, 562, 0, 0, SystemZImpOpBase + 0, 1449, 0, 0x0ULL }, // Inst #2866 = VPERM { 2865, 4, 1, 6, 563, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2865 = VPDI { 2864, 1, 1, 6, 531, 0, 0, SystemZImpOpBase + 0, 1598, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #2864 = VONE { 2863, 3, 1, 6, 582, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2863 = VOC { 2862, 3, 1, 6, 875, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2862 = VO { 2861, 3, 1, 6, 581, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2861 = VNX { 2860, 3, 1, 6, 874, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2860 = VNO { 2859, 3, 1, 6, 581, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2859 = VNN { 2858, 3, 1, 6, 874, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2858 = VNC { 2857, 3, 1, 6, 874, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2857 = VN { 2856, 3, 1, 6, 593, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2856 = VMXLH { 2855, 3, 1, 6, 593, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2855 = VMXLG { 2854, 3, 1, 6, 593, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2854 = VMXLF { 2853, 3, 1, 6, 593, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2853 = VMXLB { 2852, 4, 1, 6, 593, 0, 0, SystemZImpOpBase + 0, 1437, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2852 = VMXL { 2851, 3, 1, 6, 592, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2851 = VMXH { 2850, 3, 1, 6, 592, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2850 = VMXG { 2849, 3, 1, 6, 592, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2849 = VMXF { 2848, 3, 1, 6, 592, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2848 = VMXB { 2847, 4, 1, 6, 592, 0, 0, SystemZImpOpBase + 0, 1437, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2847 = VMX { 2846, 5, 1, 6, 759, 0, 1, SystemZImpOpBase + 0, 427, 0, 0x0ULL }, // Inst #2846 = VMSP { 2845, 5, 1, 6, 610, 0, 0, SystemZImpOpBase + 0, 1444, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2845 = VMSLG { 2844, 6, 1, 6, 610, 0, 0, SystemZImpOpBase + 0, 1513, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2844 = VMSL { 2843, 3, 1, 6, 561, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2843 = VMRLH { 2842, 3, 1, 6, 561, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2842 = VMRLG { 2841, 3, 1, 6, 561, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2841 = VMRLF { 2840, 3, 1, 6, 561, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2840 = VMRLB { 2839, 4, 1, 6, 561, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2839 = VMRL { 2838, 3, 1, 6, 560, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2838 = VMRHH { 2837, 3, 1, 6, 560, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2837 = VMRHG { 2836, 3, 1, 6, 560, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2836 = VMRHF { 2835, 3, 1, 6, 560, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2835 = VMRHB { 2834, 4, 1, 6, 560, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2834 = VMRH { 2833, 5, 1, 6, 759, 0, 1, SystemZImpOpBase + 0, 427, 0, 0x0ULL }, // Inst #2833 = VMP { 2832, 3, 1, 6, 609, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2832 = VMOH { 2831, 3, 1, 6, 609, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2831 = VMOF { 2830, 3, 1, 6, 609, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2830 = VMOB { 2829, 4, 1, 6, 609, 0, 0, SystemZImpOpBase + 0, 1437, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2829 = VMO { 2828, 3, 1, 6, 595, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2828 = VMNLH { 2827, 3, 1, 6, 595, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2827 = VMNLG { 2826, 3, 1, 6, 595, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2826 = VMNLF { 2825, 3, 1, 6, 595, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2825 = VMNLB { 2824, 4, 1, 6, 595, 0, 0, SystemZImpOpBase + 0, 1437, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2824 = VMNL { 2823, 3, 1, 6, 594, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2823 = VMNH { 2822, 3, 1, 6, 594, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2822 = VMNG { 2821, 3, 1, 6, 594, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2821 = VMNF { 2820, 3, 1, 6, 594, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2820 = VMNB { 2819, 4, 1, 6, 594, 0, 0, SystemZImpOpBase + 0, 1437, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2819 = VMN { 2818, 3, 1, 6, 608, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2818 = VMLOH { 2817, 3, 1, 6, 608, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2817 = VMLOF { 2816, 3, 1, 6, 608, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2816 = VMLOB { 2815, 4, 1, 6, 608, 0, 0, SystemZImpOpBase + 0, 1437, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2815 = VMLO { 2814, 3, 1, 6, 607, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2814 = VMLHW { 2813, 3, 1, 6, 607, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2813 = VMLHH { 2812, 3, 1, 6, 607, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2812 = VMLHF { 2811, 3, 1, 6, 607, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2811 = VMLHB { 2810, 4, 1, 6, 607, 0, 0, SystemZImpOpBase + 0, 1437, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2810 = VMLH { 2809, 3, 1, 6, 605, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2809 = VMLF { 2808, 3, 1, 6, 606, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2808 = VMLEH { 2807, 3, 1, 6, 606, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2807 = VMLEF { 2806, 3, 1, 6, 606, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2806 = VMLEB { 2805, 4, 1, 6, 606, 0, 0, SystemZImpOpBase + 0, 1437, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2805 = VMLE { 2804, 3, 1, 6, 605, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2804 = VMLB { 2803, 4, 1, 6, 605, 0, 0, SystemZImpOpBase + 0, 1437, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2803 = VML { 2802, 3, 1, 6, 604, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2802 = VMHH { 2801, 3, 1, 6, 604, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2801 = VMHF { 2800, 3, 1, 6, 604, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2800 = VMHB { 2799, 4, 1, 6, 604, 0, 0, SystemZImpOpBase + 0, 1437, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2799 = VMH { 2798, 3, 1, 6, 603, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2798 = VMEH { 2797, 3, 1, 6, 603, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2797 = VMEF { 2796, 3, 1, 6, 603, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2796 = VMEB { 2795, 4, 1, 6, 603, 0, 0, SystemZImpOpBase + 0, 1437, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2795 = VME { 2794, 4, 1, 6, 600, 0, 0, SystemZImpOpBase + 0, 1449, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2794 = VMAOH { 2793, 4, 1, 6, 600, 0, 0, SystemZImpOpBase + 0, 1449, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2793 = VMAOF { 2792, 4, 1, 6, 600, 0, 0, SystemZImpOpBase + 0, 1449, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2792 = VMAOB { 2791, 5, 1, 6, 600, 0, 0, SystemZImpOpBase + 0, 1444, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2791 = VMAO { 2790, 4, 1, 6, 599, 0, 0, SystemZImpOpBase + 0, 1449, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2790 = VMALOH { 2789, 4, 1, 6, 599, 0, 0, SystemZImpOpBase + 0, 1449, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2789 = VMALOF { 2788, 4, 1, 6, 599, 0, 0, SystemZImpOpBase + 0, 1449, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2788 = VMALOB { 2787, 5, 1, 6, 599, 0, 0, SystemZImpOpBase + 0, 1444, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2787 = VMALO { 2786, 4, 1, 6, 598, 0, 0, SystemZImpOpBase + 0, 1449, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2786 = VMALHW { 2785, 4, 1, 6, 598, 0, 0, SystemZImpOpBase + 0, 1449, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2785 = VMALHH { 2784, 4, 1, 6, 598, 0, 0, SystemZImpOpBase + 0, 1449, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2784 = VMALHF { 2783, 4, 1, 6, 598, 0, 0, SystemZImpOpBase + 0, 1449, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2783 = VMALHB { 2782, 5, 1, 6, 598, 0, 0, SystemZImpOpBase + 0, 1444, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2782 = VMALH { 2781, 4, 1, 6, 596, 0, 0, SystemZImpOpBase + 0, 1449, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2781 = VMALF { 2780, 4, 1, 6, 597, 0, 0, SystemZImpOpBase + 0, 1449, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2780 = VMALEH { 2779, 4, 1, 6, 597, 0, 0, SystemZImpOpBase + 0, 1449, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2779 = VMALEF { 2778, 4, 1, 6, 597, 0, 0, SystemZImpOpBase + 0, 1449, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2778 = VMALEB { 2777, 5, 1, 6, 597, 0, 0, SystemZImpOpBase + 0, 1444, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2777 = VMALE { 2776, 4, 1, 6, 596, 0, 0, SystemZImpOpBase + 0, 1449, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2776 = VMALB { 2775, 5, 1, 6, 596, 0, 0, SystemZImpOpBase + 0, 1444, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2775 = VMAL { 2774, 4, 1, 6, 602, 0, 0, SystemZImpOpBase + 0, 1449, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2774 = VMAHH { 2773, 4, 1, 6, 602, 0, 0, SystemZImpOpBase + 0, 1449, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2773 = VMAHF { 2772, 4, 1, 6, 602, 0, 0, SystemZImpOpBase + 0, 1449, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2772 = VMAHB { 2771, 5, 1, 6, 602, 0, 0, SystemZImpOpBase + 0, 1444, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2771 = VMAH { 2770, 4, 1, 6, 601, 0, 0, SystemZImpOpBase + 0, 1449, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2770 = VMAEH { 2769, 4, 1, 6, 601, 0, 0, SystemZImpOpBase + 0, 1449, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2769 = VMAEF { 2768, 4, 1, 6, 601, 0, 0, SystemZImpOpBase + 0, 1449, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2768 = VMAEB { 2767, 5, 1, 6, 601, 0, 0, SystemZImpOpBase + 0, 1444, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2767 = VMAE { 2766, 3, 1, 6, 529, 0, 0, SystemZImpOpBase + 0, 1595, 0, 0x0ULL }, // Inst #2766 = VLVGP { 2765, 5, 1, 6, 528, 0, 0, SystemZImpOpBase + 0, 1585, 0, 0x0ULL }, // Inst #2765 = VLVGH { 2764, 5, 1, 6, 528, 0, 0, SystemZImpOpBase + 0, 1590, 0, 0x0ULL }, // Inst #2764 = VLVGG { 2763, 5, 1, 6, 528, 0, 0, SystemZImpOpBase + 0, 1585, 0, 0x0ULL }, // Inst #2763 = VLVGF { 2762, 5, 1, 6, 528, 0, 0, SystemZImpOpBase + 0, 1585, 0, 0x0ULL }, // Inst #2762 = VLVGB { 2761, 6, 1, 6, 528, 0, 0, SystemZImpOpBase + 0, 1579, 0, 0x0ULL }, // Inst #2761 = VLVG { 2760, 4, 1, 6, 544, 0, 0, SystemZImpOpBase + 0, 1562, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2760 = VLRLR { 2759, 4, 1, 6, 544, 0, 0, SystemZImpOpBase + 0, 1575, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2759 = VLRL { 2758, 4, 1, 6, 540, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #2758 = VLREPH { 2757, 4, 1, 6, 540, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x100ULL }, // Inst #2757 = VLREPG { 2756, 4, 1, 6, 540, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #2756 = VLREPF { 2755, 4, 1, 6, 540, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x20ULL }, // Inst #2755 = VLREPB { 2754, 5, 1, 6, 540, 0, 0, SystemZImpOpBase + 0, 1538, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2754 = VLREP { 2753, 2, 1, 6, 526, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2753 = VLR { 2752, 2, 1, 6, 591, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2752 = VLPH { 2751, 2, 1, 6, 591, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2751 = VLPG { 2750, 2, 1, 6, 591, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2750 = VLPF { 2749, 2, 1, 6, 591, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2749 = VLPB { 2748, 3, 1, 6, 591, 0, 0, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #2748 = VLP { 2747, 5, 2, 6, 543, 0, 0, SystemZImpOpBase + 0, 1570, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2747 = VLMAlign { 2746, 4, 2, 6, 543, 0, 0, SystemZImpOpBase + 0, 1566, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2746 = VLM { 2745, 4, 1, 6, 539, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #2745 = VLLEZLF { 2744, 4, 1, 6, 873, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #2744 = VLLEZH { 2743, 4, 1, 6, 873, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x100ULL }, // Inst #2743 = VLLEZG { 2742, 4, 1, 6, 873, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #2742 = VLLEZF { 2741, 4, 1, 6, 873, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x20ULL }, // Inst #2741 = VLLEZB { 2740, 5, 1, 6, 873, 0, 0, SystemZImpOpBase + 0, 1538, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2740 = VLLEZ { 2739, 4, 1, 6, 554, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #2739 = VLLEBRZH { 2738, 4, 1, 6, 554, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x100ULL }, // Inst #2738 = VLLEBRZG { 2737, 4, 1, 6, 554, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #2737 = VLLEBRZF { 2736, 4, 1, 6, 554, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #2736 = VLLEBRZE { 2735, 5, 1, 6, 554, 0, 0, SystemZImpOpBase + 0, 1538, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2735 = VLLEBRZ { 2734, 4, 1, 6, 537, 0, 0, SystemZImpOpBase + 0, 1562, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2734 = VLL { 2733, 3, 1, 6, 753, 0, 0, SystemZImpOpBase + 0, 1531, 0, 0x0ULL }, // Inst #2733 = VLIP { 2732, 4, 1, 6, 527, 0, 0, SystemZImpOpBase + 0, 1558, 0, 0x0ULL }, // Inst #2732 = VLGVH { 2731, 4, 1, 6, 527, 0, 0, SystemZImpOpBase + 0, 1558, 0, 0x0ULL }, // Inst #2731 = VLGVG { 2730, 4, 1, 6, 527, 0, 0, SystemZImpOpBase + 0, 1558, 0, 0x0ULL }, // Inst #2730 = VLGVF { 2729, 4, 1, 6, 527, 0, 0, SystemZImpOpBase + 0, 1558, 0, 0x0ULL }, // Inst #2729 = VLGVB { 2728, 5, 1, 6, 527, 0, 0, SystemZImpOpBase + 0, 1553, 0, 0x0ULL }, // Inst #2728 = VLGV { 2727, 4, 1, 6, 552, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x200ULL }, // Inst #2727 = VLERH { 2726, 4, 1, 6, 552, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x200ULL }, // Inst #2726 = VLERG { 2725, 4, 1, 6, 552, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x200ULL }, // Inst #2725 = VLERF { 2724, 5, 1, 6, 552, 0, 0, SystemZImpOpBase + 0, 1538, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2724 = VLER { 2723, 4, 1, 6, 535, 0, 0, SystemZImpOpBase + 0, 1549, 0, 0x0ULL }, // Inst #2723 = VLEIH { 2722, 4, 1, 6, 535, 0, 0, SystemZImpOpBase + 0, 1549, 0, 0x0ULL }, // Inst #2722 = VLEIG { 2721, 4, 1, 6, 535, 0, 0, SystemZImpOpBase + 0, 1549, 0, 0x0ULL }, // Inst #2721 = VLEIF { 2720, 4, 1, 6, 535, 0, 0, SystemZImpOpBase + 0, 1549, 0, 0x0ULL }, // Inst #2720 = VLEIB { 2719, 6, 1, 6, 541, 0, 0, SystemZImpOpBase + 0, 1543, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #2719 = VLEH { 2718, 6, 1, 6, 541, 0, 0, SystemZImpOpBase + 0, 1543, 0|(1ULL<<MCID::MayLoad), 0x100ULL }, // Inst #2718 = VLEG { 2717, 6, 1, 6, 541, 0, 0, SystemZImpOpBase + 0, 1543, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #2717 = VLEF { 2716, 4, 1, 6, 655, 1, 0, SystemZImpOpBase + 12, 1458, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2716 = VLEDB { 2715, 5, 1, 6, 654, 1, 0, SystemZImpOpBase + 12, 1453, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2715 = VLED { 2714, 6, 1, 6, 553, 0, 0, SystemZImpOpBase + 0, 1543, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #2714 = VLEBRH { 2713, 6, 1, 6, 553, 0, 0, SystemZImpOpBase + 0, 1543, 0|(1ULL<<MCID::MayLoad), 0x100ULL }, // Inst #2713 = VLEBRG { 2712, 6, 1, 6, 553, 0, 0, SystemZImpOpBase + 0, 1543, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #2712 = VLEBRF { 2711, 6, 1, 6, 541, 0, 0, SystemZImpOpBase + 0, 1543, 0|(1ULL<<MCID::MayLoad), 0x20ULL }, // Inst #2711 = VLEB { 2710, 2, 1, 6, 655, 1, 0, SystemZImpOpBase + 12, 415, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2710 = VLDEB { 2709, 4, 1, 6, 654, 1, 0, SystemZImpOpBase + 12, 1458, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2709 = VLDE { 2708, 2, 1, 6, 590, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2708 = VLCH { 2707, 2, 1, 6, 590, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2707 = VLCG { 2706, 2, 1, 6, 590, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2706 = VLCF { 2705, 2, 1, 6, 590, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2705 = VLCB { 2704, 3, 1, 6, 590, 0, 0, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #2704 = VLC { 2703, 4, 1, 6, 555, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #2703 = VLBRREPH { 2702, 4, 1, 6, 555, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x100ULL }, // Inst #2702 = VLBRREPG { 2701, 4, 1, 6, 555, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #2701 = VLBRREPF { 2700, 5, 1, 6, 555, 0, 0, SystemZImpOpBase + 0, 1538, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2700 = VLBRREP { 2699, 4, 1, 6, 551, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x200ULL }, // Inst #2699 = VLBRQ { 2698, 4, 1, 6, 551, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x200ULL }, // Inst #2698 = VLBRH { 2697, 4, 1, 6, 551, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x200ULL }, // Inst #2697 = VLBRG { 2696, 4, 1, 6, 551, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x200ULL }, // Inst #2696 = VLBRF { 2695, 5, 1, 6, 551, 0, 0, SystemZImpOpBase + 0, 1538, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2695 = VLBR { 2694, 5, 1, 6, 537, 0, 0, SystemZImpOpBase + 0, 1538, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2694 = VLBB { 2693, 5, 1, 6, 536, 0, 0, SystemZImpOpBase + 0, 1538, 0|(1ULL<<MCID::MayLoad), 0x200ULL }, // Inst #2693 = VLAlign { 2692, 4, 1, 6, 536, 0, 0, SystemZImpOpBase + 0, 1534, 0|(1ULL<<MCID::MayLoad), 0x200ULL }, // Inst #2692 = VL { 2691, 2, 1, 6, 743, 0, 1, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2691 = VISTRHS { 2690, 3, 1, 6, 742, 0, 0, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #2690 = VISTRH { 2689, 2, 1, 6, 743, 0, 1, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2689 = VISTRFS { 2688, 3, 1, 6, 742, 0, 0, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #2688 = VISTRF { 2687, 2, 1, 6, 743, 0, 1, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2687 = VISTRBS { 2686, 3, 1, 6, 742, 0, 0, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #2686 = VISTRB { 2685, 4, 1, 6, 742, 0, 1, SystemZImpOpBase + 0, 1458, 0, 0x0ULL }, // Inst #2685 = VISTR { 2684, 3, 1, 6, 533, 0, 0, SystemZImpOpBase + 0, 1531, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #2684 = VGMH { 2683, 3, 1, 6, 533, 0, 0, SystemZImpOpBase + 0, 1531, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #2683 = VGMG { 2682, 3, 1, 6, 533, 0, 0, SystemZImpOpBase + 0, 1531, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #2682 = VGMF { 2681, 3, 1, 6, 533, 0, 0, SystemZImpOpBase + 0, 1531, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #2681 = VGMB { 2680, 4, 1, 6, 533, 0, 0, SystemZImpOpBase + 0, 1527, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #2680 = VGM { 2679, 3, 1, 6, 589, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2679 = VGFMH { 2678, 3, 1, 6, 589, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2678 = VGFMG { 2677, 3, 1, 6, 589, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2677 = VGFMF { 2676, 3, 1, 6, 589, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2676 = VGFMB { 2675, 4, 1, 6, 588, 0, 0, SystemZImpOpBase + 0, 1449, 0, 0x0ULL }, // Inst #2675 = VGFMAH { 2674, 4, 1, 6, 588, 0, 0, SystemZImpOpBase + 0, 1449, 0, 0x0ULL }, // Inst #2674 = VGFMAG { 2673, 4, 1, 6, 588, 0, 0, SystemZImpOpBase + 0, 1449, 0, 0x0ULL }, // Inst #2673 = VGFMAF { 2672, 4, 1, 6, 588, 0, 0, SystemZImpOpBase + 0, 1449, 0, 0x0ULL }, // Inst #2672 = VGFMAB { 2671, 5, 1, 6, 588, 0, 0, SystemZImpOpBase + 0, 1444, 0, 0x0ULL }, // Inst #2671 = VGFMA { 2670, 4, 1, 6, 587, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2670 = VGFM { 2669, 6, 1, 6, 542, 0, 0, SystemZImpOpBase + 0, 1521, 0|(1ULL<<MCID::MayLoad), 0x100ULL }, // Inst #2669 = VGEG { 2668, 6, 1, 6, 542, 0, 0, SystemZImpOpBase + 0, 1521, 0|(1ULL<<MCID::MayLoad), 0x80ULL }, // Inst #2668 = VGEF { 2667, 2, 1, 6, 532, 0, 0, SystemZImpOpBase + 0, 1519, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #2667 = VGBM { 2666, 3, 1, 6, 682, 0, 1, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #2666 = VFTCISB { 2665, 3, 1, 6, 681, 0, 1, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #2665 = VFTCIDB { 2664, 5, 1, 6, 680, 0, 1, SystemZImpOpBase + 0, 1453, 0, 0x0ULL }, // Inst #2664 = VFTCI { 2663, 3, 1, 6, 687, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2663 = VFSSB { 2662, 2, 1, 6, 708, 1, 0, SystemZImpOpBase + 12, 415, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2662 = VFSQSB { 2661, 2, 1, 6, 706, 1, 0, SystemZImpOpBase + 12, 415, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2661 = VFSQDB { 2660, 4, 1, 6, 705, 1, 0, SystemZImpOpBase + 12, 1458, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2660 = VFSQ { 2659, 3, 1, 6, 685, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2659 = VFSDB { 2658, 5, 1, 6, 684, 1, 0, SystemZImpOpBase + 12, 427, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2658 = VFS { 2657, 3, 1, 6, 669, 0, 0, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #2657 = VFPSOSB { 2656, 3, 1, 6, 668, 0, 0, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #2656 = VFPSODB { 2655, 5, 1, 6, 667, 0, 0, SystemZImpOpBase + 0, 1453, 0, 0x0ULL }, // Inst #2655 = VFPSO { 2654, 4, 1, 6, 697, 1, 0, SystemZImpOpBase + 12, 1449, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2654 = VFNMSSB { 2653, 4, 1, 6, 695, 1, 0, SystemZImpOpBase + 12, 1449, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2653 = VFNMSDB { 2652, 6, 1, 6, 694, 1, 0, SystemZImpOpBase + 12, 1513, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2652 = VFNMS { 2651, 4, 1, 6, 697, 1, 0, SystemZImpOpBase + 12, 1449, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2651 = VFNMASB { 2650, 4, 1, 6, 695, 1, 0, SystemZImpOpBase + 12, 1449, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2650 = VFNMADB { 2649, 6, 1, 6, 694, 1, 0, SystemZImpOpBase + 12, 1513, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2649 = VFNMA { 2648, 4, 1, 6, 697, 1, 0, SystemZImpOpBase + 12, 1449, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2648 = VFMSSB { 2647, 4, 1, 6, 879, 1, 0, SystemZImpOpBase + 12, 1449, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2647 = VFMSDB { 2646, 3, 1, 6, 692, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2646 = VFMSB { 2645, 6, 1, 6, 878, 1, 0, SystemZImpOpBase + 12, 1513, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2645 = VFMS { 2644, 4, 1, 6, 677, 1, 0, SystemZImpOpBase + 12, 1437, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2644 = VFMINSB { 2643, 4, 1, 6, 675, 1, 0, SystemZImpOpBase + 12, 1437, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2643 = VFMINDB { 2642, 6, 1, 6, 674, 1, 0, SystemZImpOpBase + 12, 1507, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2642 = VFMIN { 2641, 3, 1, 6, 690, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2641 = VFMDB { 2640, 4, 1, 6, 677, 1, 0, SystemZImpOpBase + 12, 1437, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2640 = VFMAXSB { 2639, 4, 1, 6, 675, 1, 0, SystemZImpOpBase + 12, 1437, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2639 = VFMAXDB { 2638, 6, 1, 6, 674, 1, 0, SystemZImpOpBase + 12, 1507, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2638 = VFMAX { 2637, 4, 1, 6, 697, 1, 0, SystemZImpOpBase + 12, 1449, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2637 = VFMASB { 2636, 4, 1, 6, 879, 1, 0, SystemZImpOpBase + 12, 1449, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2636 = VFMADB { 2635, 6, 1, 6, 878, 1, 0, SystemZImpOpBase + 12, 1513, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2635 = VFMA { 2634, 5, 1, 6, 867, 1, 0, SystemZImpOpBase + 12, 427, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2634 = VFM { 2633, 4, 1, 6, 658, 1, 0, SystemZImpOpBase + 12, 1458, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2633 = VFLRD { 2632, 5, 1, 6, 657, 1, 0, SystemZImpOpBase + 12, 1453, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2632 = VFLR { 2631, 2, 1, 6, 672, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2631 = VFLPSB { 2630, 2, 1, 6, 671, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2630 = VFLPDB { 2629, 2, 1, 6, 672, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2629 = VFLNSB { 2628, 2, 1, 6, 671, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2628 = VFLNDB { 2627, 2, 1, 6, 658, 1, 0, SystemZImpOpBase + 12, 415, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2627 = VFLLS { 2626, 4, 1, 6, 657, 1, 0, SystemZImpOpBase + 12, 1458, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2626 = VFLL { 2625, 2, 1, 6, 672, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2625 = VFLCSB { 2624, 2, 1, 6, 671, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2624 = VFLCDB { 2623, 3, 1, 6, 722, 1, 1, SystemZImpOpBase + 1, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2623 = VFKHSBS { 2622, 3, 1, 6, 714, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2622 = VFKHSB { 2621, 3, 1, 6, 722, 1, 1, SystemZImpOpBase + 1, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2621 = VFKHESBS { 2620, 3, 1, 6, 714, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2620 = VFKHESB { 2619, 3, 1, 6, 720, 1, 1, SystemZImpOpBase + 1, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2619 = VFKHEDBS { 2618, 3, 1, 6, 711, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2618 = VFKHEDB { 2617, 3, 1, 6, 720, 1, 1, SystemZImpOpBase + 1, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2617 = VFKHDBS { 2616, 3, 1, 6, 711, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2616 = VFKHDB { 2615, 3, 1, 6, 722, 1, 1, SystemZImpOpBase + 1, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2615 = VFKESBS { 2614, 3, 1, 6, 714, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2614 = VFKESB { 2613, 3, 1, 6, 720, 1, 1, SystemZImpOpBase + 1, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2613 = VFKEDBS { 2612, 3, 1, 6, 711, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2612 = VFKEDB { 2611, 4, 1, 6, 664, 1, 0, SystemZImpOpBase + 12, 1458, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2611 = VFISB { 2610, 4, 1, 6, 662, 1, 0, SystemZImpOpBase + 12, 1458, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2610 = VFIDB { 2609, 5, 1, 6, 866, 1, 0, SystemZImpOpBase + 12, 1453, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2609 = VFI { 2608, 3, 1, 6, 741, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2608 = VFENEZHS { 2607, 3, 1, 6, 740, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2607 = VFENEZH { 2606, 3, 1, 6, 741, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2606 = VFENEZFS { 2605, 3, 1, 6, 740, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2605 = VFENEZF { 2604, 3, 1, 6, 741, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2604 = VFENEZBS { 2603, 3, 1, 6, 740, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2603 = VFENEZB { 2602, 3, 1, 6, 741, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2602 = VFENEHS { 2601, 4, 1, 6, 740, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2601 = VFENEH { 2600, 3, 1, 6, 741, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2600 = VFENEFS { 2599, 4, 1, 6, 740, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2599 = VFENEF { 2598, 3, 1, 6, 741, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2598 = VFENEBS { 2597, 4, 1, 6, 740, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2597 = VFENEB { 2596, 5, 1, 6, 740, 0, 1, SystemZImpOpBase + 0, 427, 0, 0x0ULL }, // Inst #2596 = VFENE { 2595, 3, 1, 6, 739, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2595 = VFEEZHS { 2594, 3, 1, 6, 738, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2594 = VFEEZH { 2593, 3, 1, 6, 739, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2593 = VFEEZFS { 2592, 3, 1, 6, 738, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2592 = VFEEZF { 2591, 3, 1, 6, 739, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2591 = VFEEZBS { 2590, 3, 1, 6, 738, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2590 = VFEEZB { 2589, 3, 1, 6, 739, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2589 = VFEEHS { 2588, 4, 1, 6, 738, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2588 = VFEEH { 2587, 3, 1, 6, 739, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2587 = VFEEFS { 2586, 4, 1, 6, 738, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2586 = VFEEF { 2585, 3, 1, 6, 739, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2585 = VFEEBS { 2584, 4, 1, 6, 738, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2584 = VFEEB { 2583, 5, 1, 6, 738, 0, 1, SystemZImpOpBase + 0, 427, 0, 0x0ULL }, // Inst #2583 = VFEE { 2582, 3, 1, 6, 703, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2582 = VFDSB { 2581, 3, 1, 6, 701, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2581 = VFDDB { 2580, 5, 1, 6, 700, 1, 0, SystemZImpOpBase + 12, 427, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2580 = VFD { 2579, 3, 1, 6, 722, 1, 1, SystemZImpOpBase + 1, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2579 = VFCHSBS { 2578, 3, 1, 6, 714, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2578 = VFCHSB { 2577, 3, 1, 6, 722, 1, 1, SystemZImpOpBase + 1, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2577 = VFCHESBS { 2576, 3, 1, 6, 714, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2576 = VFCHESB { 2575, 3, 1, 6, 719, 1, 1, SystemZImpOpBase + 1, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2575 = VFCHEDBS { 2574, 3, 1, 6, 881, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2574 = VFCHEDB { 2573, 6, 1, 6, 710, 1, 0, SystemZImpOpBase + 12, 1507, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2573 = VFCHE { 2572, 3, 1, 6, 719, 1, 1, SystemZImpOpBase + 1, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2572 = VFCHDBS { 2571, 3, 1, 6, 881, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2571 = VFCHDB { 2570, 6, 1, 6, 710, 1, 0, SystemZImpOpBase + 12, 1507, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2570 = VFCH { 2569, 3, 1, 6, 722, 1, 1, SystemZImpOpBase + 1, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2569 = VFCESBS { 2568, 3, 1, 6, 714, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2568 = VFCESB { 2567, 3, 1, 6, 719, 1, 1, SystemZImpOpBase + 1, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2567 = VFCEDBS { 2566, 3, 1, 6, 881, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2566 = VFCEDB { 2565, 6, 1, 6, 710, 1, 0, SystemZImpOpBase + 12, 1507, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2565 = VFCE { 2564, 3, 1, 6, 687, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2564 = VFASB { 2563, 4, 1, 6, 737, 0, 1, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2563 = VFAEZHS { 2562, 4, 1, 6, 736, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2562 = VFAEZH { 2561, 4, 1, 6, 737, 0, 1, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2561 = VFAEZFS { 2560, 4, 1, 6, 736, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2560 = VFAEZF { 2559, 4, 1, 6, 737, 0, 1, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2559 = VFAEZBS { 2558, 4, 1, 6, 736, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2558 = VFAEZB { 2557, 4, 1, 6, 735, 0, 1, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2557 = VFAEHS { 2556, 4, 1, 6, 734, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2556 = VFAEH { 2555, 4, 1, 6, 735, 0, 1, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2555 = VFAEFS { 2554, 4, 1, 6, 734, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2554 = VFAEF { 2553, 4, 1, 6, 735, 0, 1, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2553 = VFAEBS { 2552, 4, 1, 6, 733, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2552 = VFAEB { 2551, 5, 1, 6, 733, 0, 1, SystemZImpOpBase + 0, 427, 0, 0x0ULL }, // Inst #2551 = VFAE { 2550, 3, 1, 6, 685, 1, 0, SystemZImpOpBase + 12, 1441, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2550 = VFADB { 2549, 5, 1, 6, 684, 1, 0, SystemZImpOpBase + 12, 427, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2549 = VFA { 2548, 3, 1, 6, 620, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2548 = VESRLVH { 2547, 3, 1, 6, 620, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2547 = VESRLVG { 2546, 3, 1, 6, 620, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2546 = VESRLVF { 2545, 3, 1, 6, 620, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2545 = VESRLVB { 2544, 4, 1, 6, 620, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2544 = VESRLV { 2543, 4, 1, 6, 619, 0, 0, SystemZImpOpBase + 0, 1503, 0, 0x0ULL }, // Inst #2543 = VESRLH { 2542, 4, 1, 6, 619, 0, 0, SystemZImpOpBase + 0, 1503, 0, 0x0ULL }, // Inst #2542 = VESRLG { 2541, 4, 1, 6, 619, 0, 0, SystemZImpOpBase + 0, 1503, 0, 0x0ULL }, // Inst #2541 = VESRLF { 2540, 4, 1, 6, 619, 0, 0, SystemZImpOpBase + 0, 1503, 0, 0x0ULL }, // Inst #2540 = VESRLB { 2539, 5, 1, 6, 619, 0, 0, SystemZImpOpBase + 0, 1498, 0, 0x0ULL }, // Inst #2539 = VESRL { 2538, 3, 1, 6, 618, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2538 = VESRAVH { 2537, 3, 1, 6, 618, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2537 = VESRAVG { 2536, 3, 1, 6, 618, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2536 = VESRAVF { 2535, 3, 1, 6, 618, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2535 = VESRAVB { 2534, 4, 1, 6, 618, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2534 = VESRAV { 2533, 4, 1, 6, 617, 0, 0, SystemZImpOpBase + 0, 1503, 0, 0x0ULL }, // Inst #2533 = VESRAH { 2532, 4, 1, 6, 617, 0, 0, SystemZImpOpBase + 0, 1503, 0, 0x0ULL }, // Inst #2532 = VESRAG { 2531, 4, 1, 6, 617, 0, 0, SystemZImpOpBase + 0, 1503, 0, 0x0ULL }, // Inst #2531 = VESRAF { 2530, 4, 1, 6, 617, 0, 0, SystemZImpOpBase + 0, 1503, 0, 0x0ULL }, // Inst #2530 = VESRAB { 2529, 5, 1, 6, 617, 0, 0, SystemZImpOpBase + 0, 1498, 0, 0x0ULL }, // Inst #2529 = VESRA { 2528, 3, 1, 6, 616, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2528 = VESLVH { 2527, 3, 1, 6, 616, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2527 = VESLVG { 2526, 3, 1, 6, 616, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2526 = VESLVF { 2525, 3, 1, 6, 616, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2525 = VESLVB { 2524, 4, 1, 6, 616, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2524 = VESLV { 2523, 4, 1, 6, 615, 0, 0, SystemZImpOpBase + 0, 1503, 0, 0x0ULL }, // Inst #2523 = VESLH { 2522, 4, 1, 6, 615, 0, 0, SystemZImpOpBase + 0, 1503, 0, 0x0ULL }, // Inst #2522 = VESLG { 2521, 4, 1, 6, 615, 0, 0, SystemZImpOpBase + 0, 1503, 0, 0x0ULL }, // Inst #2521 = VESLF { 2520, 4, 1, 6, 615, 0, 0, SystemZImpOpBase + 0, 1503, 0, 0x0ULL }, // Inst #2520 = VESLB { 2519, 5, 1, 6, 615, 0, 0, SystemZImpOpBase + 0, 1498, 0, 0x0ULL }, // Inst #2519 = VESL { 2518, 3, 1, 6, 613, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2518 = VERLLVH { 2517, 3, 1, 6, 613, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2517 = VERLLVG { 2516, 3, 1, 6, 613, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2516 = VERLLVF { 2515, 3, 1, 6, 613, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2515 = VERLLVB { 2514, 4, 1, 6, 613, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2514 = VERLLV { 2513, 4, 1, 6, 612, 0, 0, SystemZImpOpBase + 0, 1503, 0, 0x0ULL }, // Inst #2513 = VERLLH { 2512, 4, 1, 6, 612, 0, 0, SystemZImpOpBase + 0, 1503, 0, 0x0ULL }, // Inst #2512 = VERLLG { 2511, 4, 1, 6, 612, 0, 0, SystemZImpOpBase + 0, 1503, 0, 0x0ULL }, // Inst #2511 = VERLLF { 2510, 4, 1, 6, 612, 0, 0, SystemZImpOpBase + 0, 1503, 0, 0x0ULL }, // Inst #2510 = VERLLB { 2509, 5, 1, 6, 612, 0, 0, SystemZImpOpBase + 0, 1498, 0, 0x0ULL }, // Inst #2509 = VERLL { 2508, 5, 1, 6, 614, 0, 0, SystemZImpOpBase + 0, 1493, 0, 0x0ULL }, // Inst #2508 = VERIMH { 2507, 5, 1, 6, 614, 0, 0, SystemZImpOpBase + 0, 1493, 0, 0x0ULL }, // Inst #2507 = VERIMG { 2506, 5, 1, 6, 614, 0, 0, SystemZImpOpBase + 0, 1493, 0, 0x0ULL }, // Inst #2506 = VERIMF { 2505, 5, 1, 6, 614, 0, 0, SystemZImpOpBase + 0, 1493, 0, 0x0ULL }, // Inst #2505 = VERIMB { 2504, 6, 1, 6, 614, 0, 0, SystemZImpOpBase + 0, 1487, 0, 0x0ULL }, // Inst #2504 = VERIM { 2503, 2, 0, 6, 634, 0, 1, SystemZImpOpBase + 0, 415, 0|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #2503 = VECLH { 2502, 2, 0, 6, 634, 0, 1, SystemZImpOpBase + 0, 415, 0|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #2502 = VECLG { 2501, 2, 0, 6, 634, 0, 1, SystemZImpOpBase + 0, 415, 0|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #2501 = VECLF { 2500, 2, 0, 6, 634, 0, 1, SystemZImpOpBase + 0, 415, 0|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #2500 = VECLB { 2499, 3, 0, 6, 634, 0, 1, SystemZImpOpBase + 0, 1462, 0|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #2499 = VECL { 2498, 2, 0, 6, 633, 0, 1, SystemZImpOpBase + 0, 415, 0|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #2498 = VECH { 2497, 2, 0, 6, 633, 0, 1, SystemZImpOpBase + 0, 415, 0|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #2497 = VECG { 2496, 2, 0, 6, 633, 0, 1, SystemZImpOpBase + 0, 415, 0|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #2496 = VECF { 2495, 2, 0, 6, 633, 0, 1, SystemZImpOpBase + 0, 415, 0|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #2495 = VECB { 2494, 3, 0, 6, 633, 0, 1, SystemZImpOpBase + 0, 1462, 0|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #2494 = VEC { 2493, 5, 1, 6, 760, 0, 1, SystemZImpOpBase + 0, 427, 0, 0x0ULL }, // Inst #2493 = VDP { 2492, 4, 1, 6, 757, 0, 1, SystemZImpOpBase + 0, 1483, 0, 0x0ULL }, // Inst #2492 = VCVDG { 2491, 4, 1, 6, 757, 0, 1, SystemZImpOpBase + 0, 1479, 0, 0x0ULL }, // Inst #2491 = VCVD { 2490, 4, 1, 6, 756, 0, 1, SystemZImpOpBase + 0, 1475, 0, 0x0ULL }, // Inst #2490 = VCVBOpt { 2489, 4, 1, 6, 756, 0, 1, SystemZImpOpBase + 0, 1471, 0, 0x0ULL }, // Inst #2489 = VCVBGOpt { 2488, 3, 1, 6, 868, 0, 1, SystemZImpOpBase + 0, 1468, 0, 0x0ULL }, // Inst #2488 = VCVBG { 2487, 3, 1, 6, 868, 0, 1, SystemZImpOpBase + 0, 1465, 0, 0x0ULL }, // Inst #2487 = VCVB { 2486, 2, 1, 6, 585, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2486 = VCTZH { 2485, 2, 1, 6, 585, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2485 = VCTZG { 2484, 2, 1, 6, 585, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2484 = VCTZF { 2483, 2, 1, 6, 585, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2483 = VCTZB { 2482, 3, 1, 6, 585, 0, 0, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #2482 = VCTZ { 2481, 4, 1, 6, 767, 0, 0, SystemZImpOpBase + 0, 1437, 0, 0x0ULL }, // Inst #2481 = VCSPH { 2480, 5, 1, 6, 648, 1, 0, SystemZImpOpBase + 12, 1453, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2480 = VCSFP { 2479, 5, 1, 6, 752, 1, 0, SystemZImpOpBase + 12, 427, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2479 = VCRNF { 2478, 3, 0, 6, 764, 0, 1, SystemZImpOpBase + 0, 1462, 0|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #2478 = VCP { 2477, 4, 1, 6, 752, 1, 0, SystemZImpOpBase + 12, 1458, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2477 = VCNF { 2476, 2, 1, 6, 584, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2476 = VCLZH { 2475, 2, 1, 6, 584, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2475 = VCLZG { 2474, 2, 1, 6, 584, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2474 = VCLZF { 2473, 3, 1, 6, 768, 0, 1, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #2473 = VCLZDP { 2472, 2, 1, 6, 584, 0, 0, SystemZImpOpBase + 0, 415, 0, 0x0ULL }, // Inst #2472 = VCLZB { 2471, 3, 1, 6, 584, 0, 0, SystemZImpOpBase + 0, 1462, 0, 0x0ULL }, // Inst #2471 = VCLZ { 2470, 4, 1, 6, 650, 1, 0, SystemZImpOpBase + 12, 1458, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2470 = VCLGDB { 2469, 5, 1, 6, 649, 1, 0, SystemZImpOpBase + 12, 1453, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2469 = VCLGD { 2468, 5, 1, 6, 648, 1, 0, SystemZImpOpBase + 12, 1453, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2468 = VCLFP { 2467, 4, 1, 6, 751, 1, 0, SystemZImpOpBase + 12, 1458, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2467 = VCLFNL { 2466, 4, 1, 6, 751, 1, 0, SystemZImpOpBase + 12, 1458, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2466 = VCLFNH { 2465, 4, 1, 6, 652, 1, 0, SystemZImpOpBase + 12, 1458, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2465 = VCLFEB { 2464, 3, 1, 6, 583, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2464 = VCKSM { 2463, 3, 1, 6, 640, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2463 = VCHLHS { 2462, 3, 1, 6, 639, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2462 = VCHLH { 2461, 3, 1, 6, 640, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2461 = VCHLGS { 2460, 3, 1, 6, 639, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2460 = VCHLG { 2459, 3, 1, 6, 640, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2459 = VCHLFS { 2458, 3, 1, 6, 639, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2458 = VCHLF { 2457, 3, 1, 6, 640, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2457 = VCHLBS { 2456, 3, 1, 6, 639, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2456 = VCHLB { 2455, 5, 1, 6, 639, 0, 1, SystemZImpOpBase + 0, 427, 0, 0x0ULL }, // Inst #2455 = VCHL { 2454, 3, 1, 6, 638, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2454 = VCHHS { 2453, 3, 1, 6, 637, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2453 = VCHH { 2452, 3, 1, 6, 638, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2452 = VCHGS { 2451, 3, 1, 6, 637, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2451 = VCHG { 2450, 3, 1, 6, 638, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2450 = VCHFS { 2449, 3, 1, 6, 637, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2449 = VCHF { 2448, 3, 1, 6, 638, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2448 = VCHBS { 2447, 3, 1, 6, 637, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2447 = VCHB { 2446, 5, 1, 6, 637, 0, 1, SystemZImpOpBase + 0, 427, 0, 0x0ULL }, // Inst #2446 = VCH { 2445, 4, 1, 6, 650, 1, 0, SystemZImpOpBase + 12, 1458, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2445 = VCGDB { 2444, 5, 1, 6, 649, 1, 0, SystemZImpOpBase + 12, 1453, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2444 = VCGD { 2443, 5, 1, 6, 642, 1, 0, SystemZImpOpBase + 12, 1453, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2443 = VCFPS { 2442, 5, 1, 6, 642, 1, 0, SystemZImpOpBase + 12, 1453, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2442 = VCFPL { 2441, 4, 1, 6, 750, 1, 0, SystemZImpOpBase + 12, 1458, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2441 = VCFN { 2440, 4, 1, 6, 652, 1, 0, SystemZImpOpBase + 12, 1458, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2440 = VCFEB { 2439, 3, 1, 6, 636, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2439 = VCEQHS { 2438, 3, 1, 6, 635, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2438 = VCEQH { 2437, 3, 1, 6, 636, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2437 = VCEQGS { 2436, 3, 1, 6, 635, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2436 = VCEQG { 2435, 3, 1, 6, 636, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2435 = VCEQFS { 2434, 3, 1, 6, 635, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2434 = VCEQF { 2433, 3, 1, 6, 636, 0, 1, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2433 = VCEQBS { 2432, 3, 1, 6, 635, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2432 = VCEQB { 2431, 5, 1, 6, 635, 0, 1, SystemZImpOpBase + 0, 427, 0, 0x0ULL }, // Inst #2431 = VCEQ { 2430, 4, 1, 6, 646, 1, 0, SystemZImpOpBase + 12, 1458, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2430 = VCELFB { 2429, 4, 1, 6, 646, 1, 0, SystemZImpOpBase + 12, 1458, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2429 = VCEFB { 2428, 4, 1, 6, 644, 1, 0, SystemZImpOpBase + 12, 1458, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2428 = VCDLGB { 2427, 5, 1, 6, 643, 1, 0, SystemZImpOpBase + 12, 1453, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2427 = VCDLG { 2426, 4, 1, 6, 644, 1, 0, SystemZImpOpBase + 12, 1458, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2426 = VCDGB { 2425, 5, 1, 6, 643, 1, 0, SystemZImpOpBase + 12, 1453, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2425 = VCDG { 2424, 3, 1, 6, 564, 0, 0, SystemZImpOpBase + 0, 1441, 0, 0x0ULL }, // Inst #2424 = VBPERM { 2423, 3, 1, 6, 580, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2423 = VAVGLH { 2422, 3, 1, 6, 580, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2422 = VAVGLG { 2421, 3, 1, 6, 580, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2421 = VAVGLF { 2420, 3, 1, 6, 580, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2420 = VAVGLB { 2419, 4, 1, 6, 580, 0, 0, SystemZImpOpBase + 0, 1437, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2419 = VAVGL { 2418, 3, 1, 6, 579, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2418 = VAVGH { 2417, 3, 1, 6, 579, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2417 = VAVGG { 2416, 3, 1, 6, 579, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2416 = VAVGF { 2415, 3, 1, 6, 579, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2415 = VAVGB { 2414, 4, 1, 6, 579, 0, 0, SystemZImpOpBase + 0, 1437, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2414 = VAVG { 2413, 3, 1, 6, 577, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2413 = VAQ { 2412, 5, 1, 6, 758, 0, 1, SystemZImpOpBase + 0, 427, 0, 0x0ULL }, // Inst #2412 = VAP { 2411, 3, 1, 6, 577, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2411 = VAH { 2410, 3, 1, 6, 577, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2410 = VAG { 2409, 3, 1, 6, 577, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2409 = VAF { 2408, 4, 1, 6, 577, 0, 0, SystemZImpOpBase + 0, 1449, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2408 = VACQ { 2407, 3, 1, 6, 578, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2407 = VACCQ { 2406, 3, 1, 6, 578, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2406 = VACCH { 2405, 3, 1, 6, 578, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2405 = VACCG { 2404, 3, 1, 6, 578, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2404 = VACCF { 2403, 4, 1, 6, 578, 0, 0, SystemZImpOpBase + 0, 1449, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2403 = VACCCQ { 2402, 5, 1, 6, 578, 0, 0, SystemZImpOpBase + 0, 1444, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2402 = VACCC { 2401, 3, 1, 6, 578, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2401 = VACCB { 2400, 4, 1, 6, 578, 0, 0, SystemZImpOpBase + 0, 1437, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2400 = VACC { 2399, 5, 1, 6, 577, 0, 0, SystemZImpOpBase + 0, 1444, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2399 = VAC { 2398, 3, 1, 6, 577, 0, 0, SystemZImpOpBase + 0, 1441, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2398 = VAB { 2397, 4, 1, 6, 577, 0, 0, SystemZImpOpBase + 0, 1437, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2397 = VA { 2396, 0, 0, 2, 334, 6, 6, SystemZImpOpBase + 90, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2396 = UPT { 2395, 5, 0, 6, 303, 0, 1, SystemZImpOpBase + 0, 789, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2395 = UNPKU { 2394, 5, 0, 6, 303, 0, 1, SystemZImpOpBase + 0, 789, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2394 = UNPKA { 2393, 6, 0, 6, 304, 0, 0, SystemZImpOpBase + 0, 544, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2393 = UNPK { 2392, 2, 0, 4, 856, 1, 1, SystemZImpOpBase + 41, 675, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2392 = TSCH { 2391, 2, 0, 4, 274, 0, 1, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20ULL }, // Inst #2391 = TS { 2390, 4, 2, 4, 288, 2, 1, SystemZImpOpBase + 43, 1421, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2390 = TRTTOpt { 2389, 5, 2, 4, 288, 2, 1, SystemZImpOpBase + 43, 1425, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2389 = TRTT { 2388, 3, 2, 4, 287, 1, 1, SystemZImpOpBase + 88, 1434, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2388 = TRTREOpt { 2387, 4, 2, 4, 287, 1, 1, SystemZImpOpBase + 88, 1430, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2387 = TRTRE { 2386, 5, 0, 6, 285, 0, 3, SystemZImpOpBase + 85, 789, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2386 = TRTR { 2385, 4, 2, 4, 288, 2, 1, SystemZImpOpBase + 43, 1421, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2385 = TRTOOpt { 2384, 5, 2, 4, 288, 2, 1, SystemZImpOpBase + 43, 1425, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2384 = TRTO { 2383, 3, 2, 4, 287, 1, 1, SystemZImpOpBase + 88, 1434, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2383 = TRTEOpt { 2382, 4, 2, 4, 287, 1, 1, SystemZImpOpBase + 88, 1430, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2382 = TRTE { 2381, 5, 0, 6, 284, 0, 3, SystemZImpOpBase + 85, 789, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2381 = TRT { 2380, 4, 2, 4, 288, 2, 1, SystemZImpOpBase + 43, 1421, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2380 = TROTOpt { 2379, 5, 2, 4, 288, 2, 1, SystemZImpOpBase + 43, 1425, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2379 = TROT { 2378, 4, 2, 4, 288, 2, 1, SystemZImpOpBase + 43, 1421, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2378 = TROOOpt { 2377, 5, 2, 4, 288, 2, 1, SystemZImpOpBase + 43, 1425, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2377 = TROO { 2376, 4, 2, 4, 286, 1, 0, SystemZImpOpBase + 55, 1421, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2376 = TRE { 2375, 2, 0, 4, 845, 0, 0, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2375 = TRAP4 { 2374, 0, 0, 2, 845, 0, 0, SystemZImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2374 = TRAP2 { 2373, 4, 0, 6, 844, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2373 = TRACG { 2372, 4, 0, 4, 844, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2372 = TRACE { 2371, 5, 0, 6, 283, 0, 0, SystemZImpOpBase + 0, 789, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2371 = TR { 2370, 4, 0, 6, 809, 0, 1, SystemZImpOpBase + 0, 1108, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2370 = TPROT { 2369, 2, 0, 4, 883, 0, 1, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2369 = TPI { 2368, 2, 1, 4, 860, 0, 1, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2368 = TPEI { 2367, 3, 0, 6, 310, 0, 1, SystemZImpOpBase + 0, 1418, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2367 = TP { 2366, 3, 0, 6, 257, 0, 1, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x4ULL }, // Inst #2366 = TMY { 2365, 2, 0, 4, 262, 0, 1, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #2365 = TMLL { 2364, 2, 0, 4, 261, 0, 1, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #2364 = TMLH { 2363, 2, 0, 4, 260, 0, 1, SystemZImpOpBase + 0, 776, 0|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #2363 = TMHL { 2362, 2, 0, 4, 259, 0, 1, SystemZImpOpBase + 0, 776, 0|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #2362 = TMHH { 2361, 3, 0, 4, 257, 0, 1, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2361 = TM { 2360, 2, 1, 4, 427, 0, 1, SystemZImpOpBase + 0, 631, 0, 0x0ULL }, // Inst #2360 = THDR { 2359, 2, 1, 4, 427, 0, 1, SystemZImpOpBase + 0, 1121, 0, 0x0ULL }, // Inst #2359 = THDER { 2358, 0, 0, 4, 324, 0, 1, SystemZImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2358 = TEND { 2357, 4, 0, 6, 525, 0, 1, SystemZImpOpBase + 0, 347, 0, 0x8ULL }, // Inst #2357 = TDGXT { 2356, 4, 0, 6, 524, 0, 1, SystemZImpOpBase + 0, 655, 0, 0x8ULL }, // Inst #2356 = TDGET { 2355, 4, 0, 6, 895, 0, 1, SystemZImpOpBase + 0, 627, 0, 0x8ULL }, // Inst #2355 = TDGDT { 2354, 4, 0, 6, 525, 0, 1, SystemZImpOpBase + 0, 347, 0, 0x8ULL }, // Inst #2354 = TDCXT { 2353, 4, 0, 6, 524, 0, 1, SystemZImpOpBase + 0, 655, 0, 0x8ULL }, // Inst #2353 = TDCET { 2352, 4, 0, 6, 895, 0, 1, SystemZImpOpBase + 0, 627, 0, 0x8ULL }, // Inst #2352 = TDCDT { 2351, 4, 0, 6, 406, 0, 1, SystemZImpOpBase + 0, 347, 0, 0x3008ULL }, // Inst #2351 = TCXB { 2350, 4, 0, 6, 405, 0, 1, SystemZImpOpBase + 0, 655, 0, 0x3008ULL }, // Inst #2350 = TCEB { 2349, 4, 0, 6, 405, 0, 1, SystemZImpOpBase + 0, 627, 0, 0x3008ULL }, // Inst #2349 = TCDB { 2348, 3, 0, 6, 323, 0, 1, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2348 = TBEGINC { 2347, 3, 0, 6, 323, 0, 1, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2347 = TBEGIN { 2346, 3, 1, 4, 428, 0, 1, SystemZImpOpBase + 0, 1415, 0, 0x0ULL }, // Inst #2346 = TBEDR { 2345, 3, 1, 4, 428, 0, 1, SystemZImpOpBase + 0, 946, 0, 0x0ULL }, // Inst #2345 = TBDR { 2344, 2, 0, 4, 795, 1, 2, SystemZImpOpBase + 68, 563, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2344 = TB { 2343, 2, 0, 4, 821, 0, 1, SystemZImpOpBase + 0, 1354, 0, 0x0ULL }, // Inst #2343 = TAR { 2342, 0, 0, 2, 319, 0, 1, SystemZImpOpBase + 0, 1, 0, 0x0ULL }, // Inst #2342 = TAM { 2341, 2, 0, 4, 325, 0, 0, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2341 = TABORT { 2340, 5, 1, 6, 129, 0, 1, SystemZImpOpBase + 0, 487, 0|(1ULL<<MCID::MayLoad), 0x223c8cULL }, // Inst #2340 = SY { 2339, 4, 1, 4, 507, 1, 1, SystemZImpOpBase + 1, 556, 0, 0x0ULL }, // Inst #2339 = SXTRA { 2338, 3, 1, 4, 507, 1, 1, SystemZImpOpBase + 1, 553, 0, 0x0ULL }, // Inst #2338 = SXTR { 2337, 3, 1, 2, 443, 0, 1, SystemZImpOpBase + 0, 550, 0, 0x0ULL }, // Inst #2337 = SXR { 2336, 3, 1, 4, 386, 1, 1, SystemZImpOpBase + 1, 550, 0|(1ULL<<MCID::MayRaiseFPException), 0x3fc00ULL }, // Inst #2336 = SXBR { 2335, 3, 1, 2, 442, 0, 1, SystemZImpOpBase + 0, 497, 0, 0x0ULL }, // Inst #2335 = SWR { 2334, 5, 1, 4, 441, 0, 1, SystemZImpOpBase + 0, 492, 0|(1ULL<<MCID::MayLoad), 0x108ULL }, // Inst #2334 = SW { 2333, 1, 0, 2, 841, 0, 1, SystemZImpOpBase + 0, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2333 = SVC { 2332, 3, 1, 2, 442, 0, 1, SystemZImpOpBase + 0, 512, 0, 0x0ULL }, // Inst #2332 = SUR { 2331, 5, 1, 4, 441, 0, 1, SystemZImpOpBase + 0, 507, 0|(1ULL<<MCID::MayLoad), 0x88ULL }, // Inst #2331 = SU { 2330, 4, 0, 6, 48, 0, 0, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::MayStore), 0x8eULL }, // Inst #2330 = STY { 2329, 2, 0, 4, 808, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2329 = STURG { 2328, 2, 0, 4, 808, 0, 0, SystemZImpOpBase + 0, 933, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2328 = STURA { 2327, 2, 0, 4, 834, 2, 2, SystemZImpOpBase + 81, 675, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2327 = STSI { 2326, 2, 0, 4, 856, 1, 1, SystemZImpOpBase + 41, 675, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2326 = STSCH { 2325, 4, 0, 6, 84, 0, 0, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::MayStore), 0x4cULL }, // Inst #2325 = STRVH { 2324, 4, 0, 6, 84, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x10cULL }, // Inst #2324 = STRVG { 2323, 4, 0, 6, 84, 0, 0, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::MayStore), 0x8cULL }, // Inst #2323 = STRV { 2322, 2, 0, 6, 48, 0, 0, SystemZImpOpBase + 0, 765, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2322 = STRL { 2321, 4, 0, 6, 806, 0, 0, SystemZImpOpBase + 0, 1108, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2321 = STRAG { 2320, 2, 0, 4, 786, 0, 0, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #2320 = STPX { 2319, 2, 0, 4, 831, 0, 0, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #2319 = STPT { 2318, 4, 0, 6, 281, 0, 0, SystemZImpOpBase + 0, 306, 0|(1ULL<<MCID::MayStore), 0x20cULL }, // Inst #2318 = STPQ { 2317, 3, 0, 4, 778, 0, 0, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2317 = STOSM { 2316, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::MayStore), 0x104ULL }, // Inst #2316 = STOCGAsmZ { 2315, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::MayStore), 0x104ULL }, // Inst #2315 = STOCGAsmP { 2314, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::MayStore), 0x104ULL }, // Inst #2314 = STOCGAsmO { 2313, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::MayStore), 0x104ULL }, // Inst #2313 = STOCGAsmNZ { 2312, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::MayStore), 0x104ULL }, // Inst #2312 = STOCGAsmNP { 2311, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::MayStore), 0x104ULL }, // Inst #2311 = STOCGAsmNO { 2310, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::MayStore), 0x104ULL }, // Inst #2310 = STOCGAsmNM { 2309, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::MayStore), 0x104ULL }, // Inst #2309 = STOCGAsmNLH { 2308, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::MayStore), 0x104ULL }, // Inst #2308 = STOCGAsmNLE { 2307, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::MayStore), 0x104ULL }, // Inst #2307 = STOCGAsmNL { 2306, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::MayStore), 0x104ULL }, // Inst #2306 = STOCGAsmNHE { 2305, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::MayStore), 0x104ULL }, // Inst #2305 = STOCGAsmNH { 2304, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::MayStore), 0x104ULL }, // Inst #2304 = STOCGAsmNE { 2303, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::MayStore), 0x104ULL }, // Inst #2303 = STOCGAsmM { 2302, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::MayStore), 0x104ULL }, // Inst #2302 = STOCGAsmLH { 2301, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::MayStore), 0x104ULL }, // Inst #2301 = STOCGAsmLE { 2300, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::MayStore), 0x104ULL }, // Inst #2300 = STOCGAsmL { 2299, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::MayStore), 0x104ULL }, // Inst #2299 = STOCGAsmHE { 2298, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::MayStore), 0x104ULL }, // Inst #2298 = STOCGAsmH { 2297, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::MayStore), 0x104ULL }, // Inst #2297 = STOCGAsmE { 2296, 4, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 804, 0|(1ULL<<MCID::MayStore), 0x104ULL }, // Inst #2296 = STOCGAsm { 2295, 5, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 1410, 0|(1ULL<<MCID::MayStore), 0x80104ULL }, // Inst #2295 = STOCG { 2294, 3, 0, 6, 54, 1, 0, SystemZImpOpBase + 0, 1407, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2294 = STOCFHAsmZ { 2293, 3, 0, 6, 54, 1, 0, SystemZImpOpBase + 0, 1407, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2293 = STOCFHAsmP { 2292, 3, 0, 6, 54, 1, 0, SystemZImpOpBase + 0, 1407, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2292 = STOCFHAsmO { 2291, 3, 0, 6, 54, 1, 0, SystemZImpOpBase + 0, 1407, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2291 = STOCFHAsmNZ { 2290, 3, 0, 6, 54, 1, 0, SystemZImpOpBase + 0, 1407, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2290 = STOCFHAsmNP { 2289, 3, 0, 6, 54, 1, 0, SystemZImpOpBase + 0, 1407, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2289 = STOCFHAsmNO { 2288, 3, 0, 6, 54, 1, 0, SystemZImpOpBase + 0, 1407, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2288 = STOCFHAsmNM { 2287, 3, 0, 6, 54, 1, 0, SystemZImpOpBase + 0, 1407, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2287 = STOCFHAsmNLH { 2286, 3, 0, 6, 54, 1, 0, SystemZImpOpBase + 0, 1407, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2286 = STOCFHAsmNLE { 2285, 3, 0, 6, 54, 1, 0, SystemZImpOpBase + 0, 1407, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2285 = STOCFHAsmNL { 2284, 3, 0, 6, 54, 1, 0, SystemZImpOpBase + 0, 1407, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2284 = STOCFHAsmNHE { 2283, 3, 0, 6, 54, 1, 0, SystemZImpOpBase + 0, 1407, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2283 = STOCFHAsmNH { 2282, 3, 0, 6, 54, 1, 0, SystemZImpOpBase + 0, 1407, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2282 = STOCFHAsmNE { 2281, 3, 0, 6, 54, 1, 0, SystemZImpOpBase + 0, 1407, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2281 = STOCFHAsmM { 2280, 3, 0, 6, 54, 1, 0, SystemZImpOpBase + 0, 1407, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2280 = STOCFHAsmLH { 2279, 3, 0, 6, 54, 1, 0, SystemZImpOpBase + 0, 1407, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2279 = STOCFHAsmLE { 2278, 3, 0, 6, 54, 1, 0, SystemZImpOpBase + 0, 1407, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2278 = STOCFHAsmL { 2277, 3, 0, 6, 54, 1, 0, SystemZImpOpBase + 0, 1407, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2277 = STOCFHAsmHE { 2276, 3, 0, 6, 54, 1, 0, SystemZImpOpBase + 0, 1407, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2276 = STOCFHAsmH { 2275, 3, 0, 6, 54, 1, 0, SystemZImpOpBase + 0, 1407, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2275 = STOCFHAsmE { 2274, 4, 0, 6, 54, 1, 0, SystemZImpOpBase + 0, 1403, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2274 = STOCFHAsm { 2273, 5, 0, 6, 54, 1, 0, SystemZImpOpBase + 0, 1398, 0|(1ULL<<MCID::MayStore), 0x80084ULL }, // Inst #2273 = STOCFH { 2272, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2272 = STOCAsmZ { 2271, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2271 = STOCAsmP { 2270, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2270 = STOCAsmO { 2269, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2269 = STOCAsmNZ { 2268, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2268 = STOCAsmNP { 2267, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2267 = STOCAsmNO { 2266, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2266 = STOCAsmNM { 2265, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2265 = STOCAsmNLH { 2264, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2264 = STOCAsmNLE { 2263, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2263 = STOCAsmNL { 2262, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2262 = STOCAsmNHE { 2261, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2261 = STOCAsmNH { 2260, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2260 = STOCAsmNE { 2259, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2259 = STOCAsmM { 2258, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2258 = STOCAsmLH { 2257, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2257 = STOCAsmLE { 2256, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2256 = STOCAsmL { 2255, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2255 = STOCAsmHE { 2254, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2254 = STOCAsmH { 2253, 3, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2253 = STOCAsmE { 2252, 4, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 837, 0|(1ULL<<MCID::MayStore), 0x84ULL }, // Inst #2252 = STOCAsm { 2251, 5, 0, 6, 886, 1, 0, SystemZImpOpBase + 0, 1393, 0|(1ULL<<MCID::MayStore), 0x80084ULL }, // Inst #2251 = STOC { 2250, 3, 0, 4, 778, 0, 0, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2250 = STNSM { 2249, 4, 0, 6, 81, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #2249 = STMY { 2248, 4, 0, 6, 81, 0, 0, SystemZImpOpBase + 0, 1142, 0|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #2248 = STMH { 2247, 4, 0, 6, 81, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #2247 = STMG { 2246, 4, 0, 4, 81, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2246 = STM { 2245, 2, 0, 4, 833, 0, 0, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #2245 = STIDP { 2244, 4, 0, 6, 77, 0, 0, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::MayStore), 0x4cULL }, // Inst #2244 = STHY { 2243, 2, 0, 6, 77, 0, 0, SystemZImpOpBase + 0, 765, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2243 = STHRL { 2242, 4, 0, 6, 77, 0, 0, SystemZImpOpBase + 0, 757, 0|(1ULL<<MCID::MayStore), 0x4cULL }, // Inst #2242 = STHH { 2241, 4, 0, 4, 77, 0, 0, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::MayStore), 0x48ULL }, // Inst #2241 = STH { 2240, 4, 0, 6, 296, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xcULL }, // Inst #2240 = STGSC { 2239, 2, 0, 6, 46, 0, 0, SystemZImpOpBase + 0, 716, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2239 = STGRL { 2238, 4, 0, 6, 46, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x10eULL }, // Inst #2238 = STG { 2237, 2, 0, 4, 408, 1, 0, SystemZImpOpBase + 12, 675, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #2237 = STFPC { 2236, 2, 0, 4, 835, 1, 2, SystemZImpOpBase + 68, 675, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2236 = STFLE { 2235, 2, 0, 4, 835, 0, 0, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #2235 = STFL { 2234, 4, 0, 6, 48, 0, 0, SystemZImpOpBase + 0, 757, 0|(1ULL<<MCID::MayStore), 0x8eULL }, // Inst #2234 = STFH { 2233, 4, 0, 6, 354, 0, 0, SystemZImpOpBase + 0, 655, 0|(1ULL<<MCID::MayStore), 0x8eULL }, // Inst #2233 = STEY { 2232, 4, 0, 4, 354, 0, 0, SystemZImpOpBase + 0, 655, 0|(1ULL<<MCID::MayStore), 0x8aULL }, // Inst #2232 = STE { 2231, 4, 0, 6, 354, 0, 0, SystemZImpOpBase + 0, 627, 0|(1ULL<<MCID::MayStore), 0x10eULL }, // Inst #2231 = STDY { 2230, 4, 0, 4, 354, 0, 0, SystemZImpOpBase + 0, 627, 0|(1ULL<<MCID::MayStore), 0x10aULL }, // Inst #2230 = STD { 2229, 4, 0, 6, 76, 0, 0, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::MayStore), 0x2cULL }, // Inst #2229 = STCY { 2228, 4, 0, 4, 782, 0, 0, SystemZImpOpBase + 0, 1117, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2228 = STCTL { 2227, 4, 0, 6, 782, 0, 0, SystemZImpOpBase + 0, 1117, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2227 = STCTG { 2226, 2, 0, 4, 859, 0, 1, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2226 = STCRW { 2225, 2, 0, 4, 859, 0, 0, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2225 = STCPS { 2224, 4, 0, 6, 78, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #2224 = STCMY { 2223, 4, 0, 6, 78, 0, 0, SystemZImpOpBase + 0, 811, 0|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #2223 = STCMH { 2222, 4, 0, 4, 78, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2222 = STCM { 2221, 2, 0, 4, 828, 0, 1, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #2221 = STCKF { 2220, 2, 0, 4, 829, 0, 1, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #2220 = STCKE { 2219, 2, 0, 4, 830, 0, 0, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #2219 = STCKC { 2218, 2, 0, 4, 828, 0, 1, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #2218 = STCK { 2217, 4, 0, 6, 76, 0, 0, SystemZImpOpBase + 0, 757, 0|(1ULL<<MCID::MayStore), 0x2cULL }, // Inst #2217 = STCH { 2216, 4, 0, 4, 76, 0, 0, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::MayStore), 0x28ULL }, // Inst #2216 = STC { 2215, 2, 0, 4, 788, 0, 0, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #2215 = STBEAR { 2214, 2, 0, 4, 832, 0, 0, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #2214 = STAP { 2213, 4, 0, 6, 315, 0, 0, SystemZImpOpBase + 0, 1104, 0|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #2213 = STAMY { 2212, 4, 0, 4, 315, 0, 0, SystemZImpOpBase + 0, 1104, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2212 = STAM { 2211, 4, 0, 4, 48, 0, 0, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::MayStore), 0x8aULL }, // Inst #2211 = ST { 2210, 2, 0, 4, 777, 0, 0, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x20ULL }, // Inst #2210 = SSM { 2209, 2, 0, 4, 791, 0, 1, SystemZImpOpBase + 0, 933, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2209 = SSKEOpt { 2208, 3, 0, 4, 791, 0, 1, SystemZImpOpBase + 0, 1390, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2208 = SSKE { 2207, 2, 0, 4, 856, 1, 1, SystemZImpOpBase + 41, 675, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2207 = SSCH { 2206, 1, 0, 4, 784, 0, 0, SystemZImpOpBase + 0, 935, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2206 = SSAR { 2205, 1, 0, 4, 784, 0, 0, SystemZImpOpBase + 0, 302, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2205 = SSAIR { 2204, 5, 1, 6, 517, 0, 0, SystemZImpOpBase + 0, 1377, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #2204 = SRXT { 2203, 4, 2, 4, 331, 1, 1, SystemZImpOpBase + 35, 833, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2203 = SRSTU { 2202, 4, 2, 4, 331, 1, 1, SystemZImpOpBase + 35, 833, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2202 = SRST { 2201, 6, 0, 6, 308, 0, 1, SystemZImpOpBase + 0, 1384, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2201 = SRP { 2200, 2, 0, 4, 413, 1, 1, SystemZImpOpBase + 79, 1382, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2200 = SRNMT { 2199, 2, 0, 4, 413, 1, 1, SystemZImpOpBase + 79, 1382, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2199 = SRNMB { 2198, 2, 0, 4, 413, 1, 1, SystemZImpOpBase + 79, 1382, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2198 = SRNM { 2197, 4, 1, 6, 209, 0, 0, SystemZImpOpBase + 0, 1350, 0, 0x4ULL }, // Inst #2197 = SRLK { 2196, 4, 1, 6, 209, 0, 0, SystemZImpOpBase + 0, 929, 0, 0x4ULL }, // Inst #2196 = SRLG { 2195, 4, 1, 4, 209, 0, 0, SystemZImpOpBase + 0, 1369, 0, 0x0ULL }, // Inst #2195 = SRL { 2194, 3, 1, 4, 137, 0, 1, SystemZImpOpBase + 0, 541, 0, 0x223c00ULL }, // Inst #2194 = SRK { 2193, 5, 1, 6, 516, 0, 0, SystemZImpOpBase + 0, 156, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #2193 = SRDT { 2192, 4, 1, 4, 212, 0, 0, SystemZImpOpBase + 0, 1373, 0, 0x0ULL }, // Inst #2192 = SRDL { 2191, 4, 1, 4, 212, 0, 1, SystemZImpOpBase + 0, 1373, 0, 0x3b800ULL }, // Inst #2191 = SRDA { 2190, 4, 1, 6, 210, 0, 1, SystemZImpOpBase + 0, 1350, 0, 0x3b804ULL }, // Inst #2190 = SRAK { 2189, 4, 1, 6, 210, 0, 1, SystemZImpOpBase + 0, 929, 0, 0x3b804ULL }, // Inst #2189 = SRAG { 2188, 4, 1, 4, 210, 0, 1, SystemZImpOpBase + 0, 1369, 0, 0x3b800ULL }, // Inst #2188 = SRA { 2187, 3, 1, 2, 137, 0, 1, SystemZImpOpBase + 0, 538, 0, 0x223c00ULL }, // Inst #2187 = SR { 2186, 2, 1, 4, 435, 0, 0, SystemZImpOpBase + 0, 673, 0, 0x0ULL }, // Inst #2186 = SQXR { 2185, 2, 1, 4, 378, 1, 0, SystemZImpOpBase + 12, 673, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2185 = SQXBR { 2184, 2, 1, 4, 433, 0, 0, SystemZImpOpBase + 0, 659, 0, 0x0ULL }, // Inst #2184 = SQER { 2183, 2, 1, 4, 376, 1, 0, SystemZImpOpBase + 12, 659, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2183 = SQEBR { 2182, 4, 1, 6, 375, 1, 0, SystemZImpOpBase + 12, 655, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayRaiseFPException), 0x88ULL }, // Inst #2182 = SQEB { 2181, 4, 1, 6, 432, 0, 0, SystemZImpOpBase + 0, 655, 0|(1ULL<<MCID::MayLoad), 0x88ULL }, // Inst #2181 = SQE { 2180, 2, 1, 4, 434, 0, 0, SystemZImpOpBase + 0, 631, 0, 0x0ULL }, // Inst #2180 = SQDR { 2179, 2, 1, 4, 377, 1, 0, SystemZImpOpBase + 12, 631, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2179 = SQDBR { 2178, 4, 1, 6, 375, 1, 0, SystemZImpOpBase + 12, 627, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayRaiseFPException), 0x108ULL }, // Inst #2178 = SQDB { 2177, 4, 1, 6, 432, 0, 0, SystemZImpOpBase + 0, 627, 0|(1ULL<<MCID::MayLoad), 0x108ULL }, // Inst #2177 = SQD { 2176, 2, 0, 4, 786, 0, 0, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #2176 = SPX { 2175, 2, 0, 4, 827, 0, 0, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #2175 = SPT { 2174, 1, 0, 2, 317, 0, 1, SystemZImpOpBase + 0, 935, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2174 = SPM { 2173, 2, 0, 4, 776, 0, 0, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2173 = SPKA { 2172, 2, 0, 4, 854, 0, 1, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2172 = SPCTR { 2171, 6, 0, 6, 305, 0, 1, SystemZImpOpBase + 0, 544, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2171 = SP { 2170, 4, 2, 4, 337, 2, 1, SystemZImpOpBase + 43, 794, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2170 = SORTL { 2169, 5, 1, 6, 133, 0, 1, SystemZImpOpBase + 0, 487, 0|(1ULL<<MCID::MayLoad), 0x101c8cULL }, // Inst #2169 = SLY { 2168, 5, 1, 6, 517, 0, 0, SystemZImpOpBase + 0, 1377, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #2168 = SLXT { 2167, 3, 1, 4, 136, 0, 1, SystemZImpOpBase + 0, 541, 0, 0x101c00ULL }, // Inst #2167 = SLRK { 2166, 3, 1, 2, 136, 0, 1, SystemZImpOpBase + 0, 538, 0, 0x101c00ULL }, // Inst #2166 = SLR { 2165, 4, 1, 6, 208, 0, 0, SystemZImpOpBase + 0, 1350, 0, 0x4ULL }, // Inst #2165 = SLLK { 2164, 4, 1, 6, 208, 0, 0, SystemZImpOpBase + 0, 929, 0, 0x4ULL }, // Inst #2164 = SLLG { 2163, 4, 1, 4, 208, 0, 0, SystemZImpOpBase + 0, 1369, 0, 0x0ULL }, // Inst #2163 = SLL { 2162, 3, 1, 4, 139, 0, 1, SystemZImpOpBase + 0, 532, 0, 0x101c00ULL }, // Inst #2162 = SLHHLR { 2161, 3, 1, 4, 138, 0, 1, SystemZImpOpBase + 0, 529, 0, 0x101c00ULL }, // Inst #2161 = SLHHHR { 2160, 3, 1, 4, 135, 0, 1, SystemZImpOpBase + 0, 382, 0, 0x101c00ULL }, // Inst #2160 = SLGRK { 2159, 3, 1, 4, 135, 0, 1, SystemZImpOpBase + 0, 526, 0, 0x101c00ULL }, // Inst #2159 = SLGR { 2158, 3, 1, 4, 134, 0, 1, SystemZImpOpBase + 0, 523, 0, 0x101c00ULL }, // Inst #2158 = SLGFR { 2157, 3, 1, 6, 134, 0, 1, SystemZImpOpBase + 0, 303, 0, 0x101c00ULL }, // Inst #2157 = SLGFI { 2156, 5, 1, 6, 133, 0, 1, SystemZImpOpBase + 0, 518, 0|(1ULL<<MCID::MayLoad), 0x101c8cULL }, // Inst #2156 = SLGF { 2155, 5, 1, 6, 133, 0, 1, SystemZImpOpBase + 0, 518, 0|(1ULL<<MCID::MayLoad), 0x101d0cULL }, // Inst #2155 = SLG { 2154, 3, 1, 6, 132, 0, 1, SystemZImpOpBase + 0, 515, 0, 0x101c00ULL }, // Inst #2154 = SLFI { 2153, 5, 1, 6, 516, 0, 0, SystemZImpOpBase + 0, 156, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #2153 = SLDT { 2152, 4, 1, 4, 212, 0, 0, SystemZImpOpBase + 0, 1373, 0, 0x0ULL }, // Inst #2152 = SLDL { 2151, 4, 1, 4, 212, 0, 1, SystemZImpOpBase + 0, 1373, 0, 0x0ULL }, // Inst #2151 = SLDA { 2150, 3, 1, 4, 141, 1, 1, SystemZImpOpBase + 26, 538, 0, 0x103c00ULL }, // Inst #2150 = SLBR { 2149, 3, 1, 4, 141, 1, 1, SystemZImpOpBase + 26, 526, 0, 0x103c00ULL }, // Inst #2149 = SLBGR { 2148, 5, 1, 6, 140, 1, 1, SystemZImpOpBase + 26, 518, 0|(1ULL<<MCID::MayLoad), 0x103d0cULL }, // Inst #2148 = SLBG { 2147, 5, 1, 6, 140, 1, 1, SystemZImpOpBase + 26, 487, 0|(1ULL<<MCID::MayLoad), 0x103c8cULL }, // Inst #2147 = SLB { 2146, 4, 1, 6, 211, 0, 1, SystemZImpOpBase + 0, 1350, 0, 0x4ULL }, // Inst #2146 = SLAK { 2145, 4, 1, 6, 211, 0, 1, SystemZImpOpBase + 0, 929, 0, 0x4ULL }, // Inst #2145 = SLAG { 2144, 4, 1, 4, 211, 0, 1, SystemZImpOpBase + 0, 1369, 0, 0x0ULL }, // Inst #2144 = SLA { 2143, 5, 1, 4, 133, 0, 1, SystemZImpOpBase + 0, 487, 0|(1ULL<<MCID::MayLoad), 0x101c88ULL }, // Inst #2143 = SL { 2142, 4, 0, 4, 846, 0, 1, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2142 = SIGP { 2141, 2, 0, 4, 846, 4, 1, SystemZImpOpBase + 74, 675, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2141 = SIGA { 2140, 2, 0, 4, 847, 0, 1, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2140 = SIE { 2139, 5, 1, 6, 130, 0, 1, SystemZImpOpBase + 0, 487, 0|(1ULL<<MCID::MayLoad), 0x223c4cULL }, // Inst #2139 = SHY { 2138, 3, 1, 4, 139, 0, 1, SystemZImpOpBase + 0, 532, 0, 0x223c00ULL }, // Inst #2138 = SHHLR { 2137, 3, 1, 4, 138, 0, 1, SystemZImpOpBase + 0, 529, 0, 0x223c00ULL }, // Inst #2137 = SHHHR { 2136, 5, 1, 4, 130, 0, 1, SystemZImpOpBase + 0, 487, 0|(1ULL<<MCID::MayLoad), 0x223c48ULL }, // Inst #2136 = SH { 2135, 3, 1, 4, 131, 0, 1, SystemZImpOpBase + 0, 382, 0, 0x223c00ULL }, // Inst #2135 = SGRK { 2134, 3, 1, 4, 131, 0, 1, SystemZImpOpBase + 0, 526, 0, 0x223c00ULL }, // Inst #2134 = SGR { 2133, 5, 1, 6, 142, 0, 1, SystemZImpOpBase + 0, 518, 0|(1ULL<<MCID::MayLoad), 0x223c4cULL }, // Inst #2133 = SGH { 2132, 3, 1, 4, 143, 0, 1, SystemZImpOpBase + 0, 523, 0, 0x223c00ULL }, // Inst #2132 = SGFR { 2131, 5, 1, 6, 870, 0, 1, SystemZImpOpBase + 0, 518, 0|(1ULL<<MCID::MayLoad), 0x223c8cULL }, // Inst #2131 = SGF { 2130, 5, 1, 6, 129, 0, 1, SystemZImpOpBase + 0, 518, 0|(1ULL<<MCID::MayLoad), 0x223d0cULL }, // Inst #2130 = SG { 2129, 1, 0, 4, 409, 0, 1, SystemZImpOpBase + 12, 935, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2129 = SFPC { 2128, 1, 0, 4, 411, 0, 1, SystemZImpOpBase + 12, 935, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2128 = SFASR { 2127, 3, 1, 2, 442, 0, 1, SystemZImpOpBase + 0, 512, 0, 0x0ULL }, // Inst #2127 = SER { 2126, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 541, 0, 0x0ULL }, // Inst #2126 = SELRAsmZ { 2125, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 541, 0, 0x0ULL }, // Inst #2125 = SELRAsmP { 2124, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 541, 0, 0x0ULL }, // Inst #2124 = SELRAsmO { 2123, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 541, 0, 0x0ULL }, // Inst #2123 = SELRAsmNZ { 2122, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 541, 0, 0x0ULL }, // Inst #2122 = SELRAsmNP { 2121, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 541, 0, 0x0ULL }, // Inst #2121 = SELRAsmNO { 2120, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 541, 0, 0x0ULL }, // Inst #2120 = SELRAsmNM { 2119, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 541, 0, 0x0ULL }, // Inst #2119 = SELRAsmNLH { 2118, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 541, 0, 0x0ULL }, // Inst #2118 = SELRAsmNLE { 2117, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 541, 0, 0x0ULL }, // Inst #2117 = SELRAsmNL { 2116, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 541, 0, 0x0ULL }, // Inst #2116 = SELRAsmNHE { 2115, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 541, 0, 0x0ULL }, // Inst #2115 = SELRAsmNH { 2114, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 541, 0, 0x0ULL }, // Inst #2114 = SELRAsmNE { 2113, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 541, 0, 0x0ULL }, // Inst #2113 = SELRAsmM { 2112, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 541, 0, 0x0ULL }, // Inst #2112 = SELRAsmLH { 2111, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 541, 0, 0x0ULL }, // Inst #2111 = SELRAsmLE { 2110, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 541, 0, 0x0ULL }, // Inst #2110 = SELRAsmL { 2109, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 541, 0, 0x0ULL }, // Inst #2109 = SELRAsmHE { 2108, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 541, 0, 0x0ULL }, // Inst #2108 = SELRAsmH { 2107, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 541, 0, 0x0ULL }, // Inst #2107 = SELRAsmE { 2106, 4, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 1365, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2106 = SELRAsm { 2105, 5, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 432, 0|(1ULL<<MCID::Commutable), 0x80000ULL }, // Inst #2105 = SELR { 2104, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2104 = SELGRAsmZ { 2103, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2103 = SELGRAsmP { 2102, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2102 = SELGRAsmO { 2101, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2101 = SELGRAsmNZ { 2100, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2100 = SELGRAsmNP { 2099, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2099 = SELGRAsmNO { 2098, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2098 = SELGRAsmNM { 2097, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2097 = SELGRAsmNLH { 2096, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2096 = SELGRAsmNLE { 2095, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2095 = SELGRAsmNL { 2094, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2094 = SELGRAsmNHE { 2093, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2093 = SELGRAsmNH { 2092, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2092 = SELGRAsmNE { 2091, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2091 = SELGRAsmM { 2090, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2090 = SELGRAsmLH { 2089, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2089 = SELGRAsmLE { 2088, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2088 = SELGRAsmL { 2087, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2087 = SELGRAsmHE { 2086, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2086 = SELGRAsmH { 2085, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2085 = SELGRAsmE { 2084, 4, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 977, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2084 = SELGRAsm { 2083, 5, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 437, 0|(1ULL<<MCID::Commutable), 0x80000ULL }, // Inst #2083 = SELGR { 2082, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 529, 0, 0x0ULL }, // Inst #2082 = SELFHRAsmZ { 2081, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 529, 0, 0x0ULL }, // Inst #2081 = SELFHRAsmP { 2080, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 529, 0, 0x0ULL }, // Inst #2080 = SELFHRAsmO { 2079, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 529, 0, 0x0ULL }, // Inst #2079 = SELFHRAsmNZ { 2078, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 529, 0, 0x0ULL }, // Inst #2078 = SELFHRAsmNP { 2077, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 529, 0, 0x0ULL }, // Inst #2077 = SELFHRAsmNO { 2076, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 529, 0, 0x0ULL }, // Inst #2076 = SELFHRAsmNM { 2075, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 529, 0, 0x0ULL }, // Inst #2075 = SELFHRAsmNLH { 2074, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 529, 0, 0x0ULL }, // Inst #2074 = SELFHRAsmNLE { 2073, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 529, 0, 0x0ULL }, // Inst #2073 = SELFHRAsmNL { 2072, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 529, 0, 0x0ULL }, // Inst #2072 = SELFHRAsmNHE { 2071, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 529, 0, 0x0ULL }, // Inst #2071 = SELFHRAsmNH { 2070, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 529, 0, 0x0ULL }, // Inst #2070 = SELFHRAsmNE { 2069, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 529, 0, 0x0ULL }, // Inst #2069 = SELFHRAsmM { 2068, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 529, 0, 0x0ULL }, // Inst #2068 = SELFHRAsmLH { 2067, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 529, 0, 0x0ULL }, // Inst #2067 = SELFHRAsmLE { 2066, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 529, 0, 0x0ULL }, // Inst #2066 = SELFHRAsmL { 2065, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 529, 0, 0x0ULL }, // Inst #2065 = SELFHRAsmHE { 2064, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 529, 0, 0x0ULL }, // Inst #2064 = SELFHRAsmH { 2063, 3, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 529, 0, 0x0ULL }, // Inst #2063 = SELFHRAsmE { 2062, 4, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 1361, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2062 = SELFHRAsm { 2061, 5, 1, 4, 56, 1, 0, SystemZImpOpBase + 0, 1356, 0|(1ULL<<MCID::Commutable), 0x80000ULL }, // Inst #2061 = SELFHR { 2060, 3, 1, 4, 385, 1, 1, SystemZImpOpBase + 1, 512, 0|(1ULL<<MCID::MayRaiseFPException), 0x3fc00ULL }, // Inst #2060 = SEBR { 2059, 5, 1, 6, 384, 1, 1, SystemZImpOpBase + 1, 507, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayRaiseFPException), 0x3fc88ULL }, // Inst #2059 = SEB { 2058, 5, 1, 4, 441, 0, 1, SystemZImpOpBase + 0, 507, 0|(1ULL<<MCID::MayLoad), 0x88ULL }, // Inst #2058 = SE { 2057, 4, 1, 4, 506, 1, 1, SystemZImpOpBase + 1, 503, 0, 0x0ULL }, // Inst #2057 = SDTRA { 2056, 3, 1, 4, 506, 1, 1, SystemZImpOpBase + 1, 500, 0, 0x0ULL }, // Inst #2056 = SDTR { 2055, 3, 1, 2, 442, 0, 1, SystemZImpOpBase + 0, 497, 0, 0x0ULL }, // Inst #2055 = SDR { 2054, 3, 1, 4, 385, 1, 1, SystemZImpOpBase + 1, 497, 0|(1ULL<<MCID::MayRaiseFPException), 0x3fc00ULL }, // Inst #2054 = SDBR { 2053, 5, 1, 6, 384, 1, 1, SystemZImpOpBase + 1, 492, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayRaiseFPException), 0x3fd08ULL }, // Inst #2053 = SDB { 2052, 5, 1, 4, 441, 0, 1, SystemZImpOpBase + 0, 492, 0|(1ULL<<MCID::MayLoad), 0x108ULL }, // Inst #2052 = SD { 2051, 0, 0, 2, 897, 1, 0, SystemZImpOpBase + 55, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2051 = SCKPF { 2050, 2, 0, 4, 826, 0, 0, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #2050 = SCKC { 2049, 2, 0, 4, 896, 0, 1, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #2049 = SCK { 2048, 0, 0, 4, 858, 2, 0, SystemZImpOpBase + 72, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2048 = SCHM { 2047, 2, 0, 4, 854, 0, 1, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2047 = SCCTR { 2046, 2, 1, 4, 312, 0, 0, SystemZImpOpBase + 0, 1354, 0, 0x0ULL }, // Inst #2046 = SAR { 2045, 0, 0, 2, 320, 0, 0, SystemZImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2045 = SAM64 { 2044, 0, 0, 2, 320, 0, 0, SystemZImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2044 = SAM31 { 2043, 0, 0, 2, 320, 0, 0, SystemZImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2043 = SAM24 { 2042, 0, 0, 4, 861, 1, 0, SystemZImpOpBase + 71, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2042 = SAL { 2041, 2, 0, 4, 780, 0, 0, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2041 = SACF { 2040, 2, 0, 4, 780, 0, 0, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2040 = SAC { 2039, 5, 1, 4, 129, 0, 1, SystemZImpOpBase + 0, 487, 0|(1ULL<<MCID::MayLoad), 0x223c88ULL }, // Inst #2039 = S { 2038, 6, 1, 6, 218, 0, 1, SystemZImpOpBase + 0, 1332, 0, 0x0ULL }, // Inst #2038 = RXSBG { 2037, 0, 0, 4, 855, 1, 1, SystemZImpOpBase + 41, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2037 = RSCH { 2036, 5, 2, 4, 515, 1, 0, SystemZImpOpBase + 12, 1327, 0, 0x0ULL }, // Inst #2036 = RRXTR { 2035, 5, 2, 4, 514, 1, 0, SystemZImpOpBase + 12, 914, 0, 0x0ULL }, // Inst #2035 = RRDTR { 2034, 2, 1, 4, 792, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2034 = RRBM { 2033, 2, 0, 4, 792, 0, 1, SystemZImpOpBase + 0, 933, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2033 = RRBE { 2032, 2, 0, 4, 819, 0, 1, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2032 = RP { 2031, 6, 1, 6, 218, 0, 1, SystemZImpOpBase + 0, 1332, 0, 0x0ULL }, // Inst #2031 = ROSBG { 2030, 6, 1, 6, 218, 0, 1, SystemZImpOpBase + 0, 1332, 0, 0x0ULL }, // Inst #2030 = RNSBG { 2029, 4, 1, 6, 213, 0, 0, SystemZImpOpBase + 0, 929, 0, 0x4ULL }, // Inst #2029 = RLLG { 2028, 4, 1, 6, 213, 0, 0, SystemZImpOpBase + 0, 1350, 0, 0x4ULL }, // Inst #2028 = RLL { 2027, 6, 1, 6, 215, 0, 0, SystemZImpOpBase + 0, 1344, 0, 0x0ULL }, // Inst #2027 = RISBLG { 2026, 6, 1, 6, 214, 0, 0, SystemZImpOpBase + 0, 1338, 0, 0x0ULL }, // Inst #2026 = RISBHG { 2025, 6, 1, 6, 898, 0, 1, SystemZImpOpBase + 0, 1332, 0, 0x3b800ULL }, // Inst #2025 = RISBGZ { 2024, 6, 1, 6, 216, 0, 0, SystemZImpOpBase + 0, 1332, 0, 0x0ULL }, // Inst #2024 = RISBGNZ { 2023, 6, 1, 6, 216, 0, 0, SystemZImpOpBase + 0, 1332, 0, 0x0ULL }, // Inst #2023 = RISBGN { 2022, 6, 1, 6, 898, 0, 1, SystemZImpOpBase + 0, 403, 0, 0x0ULL }, // Inst #2022 = RISBG32 { 2021, 6, 1, 6, 898, 0, 1, SystemZImpOpBase + 0, 1332, 0, 0x3b800ULL }, // Inst #2021 = RISBG { 2020, 3, 0, 4, 800, 0, 0, SystemZImpOpBase + 0, 382, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2020 = RDPOpt { 2019, 4, 0, 4, 800, 0, 0, SystemZImpOpBase + 0, 977, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2019 = RDP { 2018, 0, 0, 4, 857, 1, 1, SystemZImpOpBase + 41, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2018 = RCHP { 2017, 2, 0, 4, 853, 0, 0, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2017 = QSI { 2016, 2, 0, 4, 840, 1, 2, SystemZImpOpBase + 68, 675, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2016 = QPACI { 2015, 2, 0, 4, 853, 0, 0, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2015 = QCTRI { 2014, 5, 2, 4, 513, 1, 0, SystemZImpOpBase + 12, 1327, 0, 0x0ULL }, // Inst #2014 = QAXTR { 2013, 5, 2, 4, 512, 1, 0, SystemZImpOpBase + 12, 914, 0, 0x0ULL }, // Inst #2013 = QADTR { 2012, 0, 0, 4, 802, 0, 0, SystemZImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2012 = PTLB { 2011, 2, 0, 4, 818, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2011 = PTI { 2010, 0, 0, 2, 825, 2, 1, SystemZImpOpBase + 43, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2010 = PTFF { 2009, 2, 1, 4, 838, 0, 0, SystemZImpOpBase + 0, 1325, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2009 = PTF { 2008, 2, 0, 4, 818, 0, 0, SystemZImpOpBase + 0, 933, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2008 = PT { 2007, 4, 2, 4, 293, 2, 1, SystemZImpOpBase + 43, 794, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2007 = PRNO { 2006, 0, 0, 2, 817, 0, 1, SystemZImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2006 = PR { 2005, 4, 2, 4, 872, 2, 1, SystemZImpOpBase + 43, 794, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2005 = PPNO { 2004, 3, 0, 4, 328, 0, 0, SystemZImpOpBase + 0, 223, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2004 = PPA { 2003, 3, 1, 4, 330, 0, 1, SystemZImpOpBase + 0, 223, 0, 0x0ULL }, // Inst #2003 = POPCNTOpt { 2002, 2, 1, 4, 865, 0, 1, SystemZImpOpBase + 0, 563, 0, 0x0ULL }, // Inst #2002 = POPCNT { 2001, 6, 0, 6, 279, 2, 1, SystemZImpOpBase + 43, 1319, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2001 = PLO { 2000, 5, 0, 6, 302, 0, 0, SystemZImpOpBase + 0, 1314, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2000 = PKU { 1999, 5, 0, 6, 302, 0, 0, SystemZImpOpBase + 0, 1314, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1999 = PKA { 1998, 2, 0, 4, 797, 0, 1, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1998 = PGOUT { 1997, 2, 0, 4, 796, 0, 1, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1997 = PGIN { 1996, 0, 0, 2, 497, 3, 3, SystemZImpOpBase + 62, 1, 0, 0x0ULL }, // Inst #1996 = PFPO { 1995, 3, 1, 4, 794, 0, 0, SystemZImpOpBase + 0, 1311, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1995 = PFMF { 1994, 2, 0, 6, 264, 0, 0, SystemZImpOpBase + 0, 594, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1994 = PFDRL { 1993, 4, 0, 6, 264, 0, 0, SystemZImpOpBase + 0, 572, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #1993 = PFD { 1992, 0, 0, 4, 839, 2, 0, SystemZImpOpBase + 60, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1992 = PCKMO { 1991, 0, 0, 4, 889, 2, 1, SystemZImpOpBase + 43, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1991 = PCC { 1990, 2, 0, 4, 816, 0, 0, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1990 = PC { 1989, 0, 0, 4, 815, 0, 0, SystemZImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1989 = PALB { 1988, 6, 0, 6, 302, 0, 0, SystemZImpOpBase + 0, 544, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1988 = PACK { 1987, 5, 1, 6, 156, 0, 1, SystemZImpOpBase + 0, 487, 0|(1ULL<<MCID::MayLoad), 0x2308cULL }, // Inst #1987 = OY { 1986, 3, 1, 4, 166, 0, 1, SystemZImpOpBase + 0, 541, 0|(1ULL<<MCID::Commutable), 0x23000ULL }, // Inst #1986 = ORK { 1985, 3, 1, 2, 166, 0, 1, SystemZImpOpBase + 0, 538, 0|(1ULL<<MCID::Commutable), 0x23000ULL }, // Inst #1985 = OR { 1984, 3, 0, 6, 158, 0, 1, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #1984 = OIY { 1983, 3, 1, 4, 165, 0, 1, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1983 = OILL { 1982, 3, 1, 4, 164, 0, 1, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1982 = OILH { 1981, 3, 1, 6, 163, 0, 1, SystemZImpOpBase + 0, 515, 0, 0x23000ULL }, // Inst #1981 = OILF { 1980, 3, 1, 4, 162, 0, 1, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1980 = OIHL { 1979, 3, 1, 4, 161, 0, 1, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1979 = OIHH { 1978, 3, 1, 6, 160, 0, 1, SystemZImpOpBase + 0, 535, 0, 0x23000ULL }, // Inst #1978 = OIHF { 1977, 3, 0, 4, 158, 0, 1, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1977 = OI { 1976, 3, 1, 4, 157, 0, 1, SystemZImpOpBase + 0, 382, 0|(1ULL<<MCID::Commutable), 0x23000ULL }, // Inst #1976 = OGRK { 1975, 3, 1, 4, 157, 0, 1, SystemZImpOpBase + 0, 526, 0|(1ULL<<MCID::Commutable), 0x23000ULL }, // Inst #1975 = OGR { 1974, 5, 1, 6, 156, 0, 1, SystemZImpOpBase + 0, 518, 0|(1ULL<<MCID::MayLoad), 0x2310cULL }, // Inst #1974 = OG { 1973, 3, 1, 4, 177, 0, 1, SystemZImpOpBase + 0, 541, 0, 0x23000ULL }, // Inst #1973 = OCRK { 1972, 3, 1, 4, 177, 0, 1, SystemZImpOpBase + 0, 382, 0, 0x23000ULL }, // Inst #1972 = OCGRK { 1971, 5, 0, 6, 167, 0, 1, SystemZImpOpBase + 0, 789, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1971 = OC { 1970, 5, 1, 4, 156, 0, 1, SystemZImpOpBase + 0, 487, 0|(1ULL<<MCID::MayLoad), 0x23088ULL }, // Inst #1970 = O { 1969, 5, 1, 6, 144, 0, 1, SystemZImpOpBase + 0, 487, 0|(1ULL<<MCID::MayLoad), 0x2308cULL }, // Inst #1969 = NY { 1968, 3, 1, 4, 181, 0, 1, SystemZImpOpBase + 0, 541, 0|(1ULL<<MCID::Commutable), 0x23000ULL }, // Inst #1968 = NXRK { 1967, 3, 1, 4, 181, 0, 1, SystemZImpOpBase + 0, 382, 0|(1ULL<<MCID::Commutable), 0x23000ULL }, // Inst #1967 = NXGRK { 1966, 4, 0, 6, 327, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x10cULL }, // Inst #1966 = NTSTG { 1965, 3, 1, 4, 154, 0, 1, SystemZImpOpBase + 0, 541, 0|(1ULL<<MCID::Commutable), 0x23000ULL }, // Inst #1965 = NRK { 1964, 3, 1, 2, 154, 0, 1, SystemZImpOpBase + 0, 538, 0|(1ULL<<MCID::Commutable), 0x23000ULL }, // Inst #1964 = NR { 1963, 3, 1, 4, 180, 0, 1, SystemZImpOpBase + 0, 541, 0|(1ULL<<MCID::Commutable), 0x23000ULL }, // Inst #1963 = NOTR { 1962, 3, 1, 4, 180, 0, 1, SystemZImpOpBase + 0, 382, 0|(1ULL<<MCID::Commutable), 0x23000ULL }, // Inst #1962 = NOTGR { 1961, 3, 1, 4, 179, 0, 1, SystemZImpOpBase + 0, 541, 0|(1ULL<<MCID::Commutable), 0x23000ULL }, // Inst #1961 = NORK { 1960, 0, 0, 4, 0, 0, 0, SystemZImpOpBase + 0, 1, 0, 0x8ULL }, // Inst #1960 = NOP_bare { 1959, 1, 0, 2, 862, 0, 0, SystemZImpOpBase + 0, 302, 0, 0x0ULL }, // Inst #1959 = NOPR { 1958, 3, 0, 4, 862, 0, 0, SystemZImpOpBase + 0, 560, 0, 0x8ULL }, // Inst #1958 = NOP { 1957, 3, 1, 4, 179, 0, 1, SystemZImpOpBase + 0, 382, 0|(1ULL<<MCID::Commutable), 0x23000ULL }, // Inst #1957 = NOGRK { 1956, 3, 1, 4, 178, 0, 1, SystemZImpOpBase + 0, 541, 0|(1ULL<<MCID::Commutable), 0x23000ULL }, // Inst #1956 = NNRK { 1955, 0, 0, 4, 339, 2, 2, SystemZImpOpBase + 56, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1955 = NNPA { 1954, 3, 1, 4, 178, 0, 1, SystemZImpOpBase + 0, 382, 0|(1ULL<<MCID::Commutable), 0x23000ULL }, // Inst #1954 = NNGRK { 1953, 3, 0, 6, 147, 0, 1, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #1953 = NIY { 1952, 3, 1, 4, 153, 0, 1, SystemZImpOpBase + 0, 515, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL }, // Inst #1952 = NILL { 1951, 3, 1, 4, 152, 0, 1, SystemZImpOpBase + 0, 515, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL }, // Inst #1951 = NILH { 1950, 3, 1, 6, 151, 0, 1, SystemZImpOpBase + 0, 515, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x23000ULL }, // Inst #1950 = NILF { 1949, 3, 1, 4, 150, 0, 1, SystemZImpOpBase + 0, 535, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL }, // Inst #1949 = NIHL { 1948, 3, 1, 4, 149, 0, 1, SystemZImpOpBase + 0, 535, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL }, // Inst #1948 = NIHH { 1947, 3, 1, 6, 148, 0, 1, SystemZImpOpBase + 0, 535, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x23000ULL }, // Inst #1947 = NIHF { 1946, 2, 0, 4, 267, 0, 0, SystemZImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1946 = NIAI { 1945, 3, 0, 4, 147, 0, 1, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1945 = NI { 1944, 3, 1, 4, 145, 0, 1, SystemZImpOpBase + 0, 382, 0|(1ULL<<MCID::Commutable), 0x23000ULL }, // Inst #1944 = NGRK { 1943, 3, 1, 4, 145, 0, 1, SystemZImpOpBase + 0, 526, 0|(1ULL<<MCID::Commutable), 0x23000ULL }, // Inst #1943 = NGR { 1942, 5, 1, 6, 144, 0, 1, SystemZImpOpBase + 0, 518, 0|(1ULL<<MCID::MayLoad), 0x2310cULL }, // Inst #1942 = NG { 1941, 3, 1, 4, 176, 0, 1, SystemZImpOpBase + 0, 541, 0, 0x23000ULL }, // Inst #1941 = NCRK { 1940, 3, 1, 4, 176, 0, 1, SystemZImpOpBase + 0, 382, 0, 0x23000ULL }, // Inst #1940 = NCGRK { 1939, 5, 0, 6, 155, 0, 1, SystemZImpOpBase + 0, 789, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1939 = NC { 1938, 5, 1, 4, 144, 0, 1, SystemZImpOpBase + 0, 487, 0|(1ULL<<MCID::MayLoad), 0x23088ULL }, // Inst #1938 = N { 1937, 3, 1, 4, 451, 0, 0, SystemZImpOpBase + 0, 1308, 0, 0x0ULL }, // Inst #1937 = MYR { 1936, 3, 1, 4, 452, 0, 0, SystemZImpOpBase + 0, 500, 0, 0x0ULL }, // Inst #1936 = MYLR { 1935, 5, 1, 6, 450, 0, 0, SystemZImpOpBase + 0, 156, 0|(1ULL<<MCID::MayLoad), 0x108ULL }, // Inst #1935 = MYL { 1934, 3, 1, 4, 452, 0, 0, SystemZImpOpBase + 0, 500, 0, 0x0ULL }, // Inst #1934 = MYHR { 1933, 5, 1, 6, 450, 0, 0, SystemZImpOpBase + 0, 156, 0|(1ULL<<MCID::MayLoad), 0x108ULL }, // Inst #1933 = MYH { 1932, 5, 1, 6, 449, 0, 0, SystemZImpOpBase + 0, 1303, 0|(1ULL<<MCID::MayLoad), 0x108ULL }, // Inst #1932 = MY { 1931, 4, 1, 4, 509, 1, 0, SystemZImpOpBase + 12, 556, 0, 0x0ULL }, // Inst #1931 = MXTRA { 1930, 3, 1, 4, 509, 1, 0, SystemZImpOpBase + 12, 553, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #1930 = MXTR { 1929, 3, 1, 2, 448, 0, 0, SystemZImpOpBase + 0, 550, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #1929 = MXR { 1928, 3, 1, 2, 447, 0, 0, SystemZImpOpBase + 0, 1300, 0, 0x0ULL }, // Inst #1928 = MXDR { 1927, 3, 1, 4, 390, 1, 0, SystemZImpOpBase + 12, 1300, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1927 = MXDBR { 1926, 5, 1, 6, 389, 1, 0, SystemZImpOpBase + 12, 1295, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayRaiseFPException), 0x108ULL }, // Inst #1926 = MXDB { 1925, 5, 1, 4, 446, 0, 0, SystemZImpOpBase + 0, 1295, 0|(1ULL<<MCID::MayLoad), 0x108ULL }, // Inst #1925 = MXD { 1924, 3, 1, 4, 391, 1, 0, SystemZImpOpBase + 12, 550, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #1924 = MXBR { 1923, 5, 0, 6, 301, 0, 0, SystemZImpOpBase + 0, 789, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1923 = MVZ { 1922, 4, 2, 4, 49, 1, 1, SystemZImpOpBase + 35, 833, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1922 = MVST { 1921, 2, 0, 4, 813, 1, 1, SystemZImpOpBase + 35, 563, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1921 = MVPG { 1920, 6, 0, 6, 301, 0, 0, SystemZImpOpBase + 0, 544, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1920 = MVO { 1919, 5, 0, 6, 301, 0, 0, SystemZImpOpBase + 0, 789, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1919 = MVN { 1918, 3, 0, 6, 25, 0, 0, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #1918 = MVIY { 1917, 3, 0, 4, 25, 0, 0, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1917 = MVI { 1916, 3, 0, 6, 24, 0, 0, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1916 = MVHI { 1915, 3, 0, 6, 24, 0, 0, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1915 = MVHHI { 1914, 3, 0, 6, 24, 0, 0, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1914 = MVGHI { 1913, 4, 0, 6, 811, 2, 0, SystemZImpOpBase + 53, 1108, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1913 = MVCSK { 1912, 6, 0, 6, 810, 0, 1, SystemZImpOpBase + 0, 1289, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1912 = MVCS { 1911, 4, 0, 6, 28, 1, 0, SystemZImpOpBase + 55, 1108, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1911 = MVCRL { 1910, 6, 0, 6, 810, 0, 1, SystemZImpOpBase + 0, 1289, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1910 = MVCP { 1909, 5, 0, 6, 812, 1, 0, SystemZImpOpBase + 55, 873, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1909 = MVCOS { 1908, 6, 2, 6, 27, 0, 1, SystemZImpOpBase + 0, 798, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #1908 = MVCLU { 1907, 6, 2, 4, 27, 0, 1, SystemZImpOpBase + 0, 798, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1907 = MVCLE { 1906, 4, 2, 2, 27, 0, 1, SystemZImpOpBase + 0, 794, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1906 = MVCL { 1905, 6, 0, 6, 810, 0, 1, SystemZImpOpBase + 0, 1289, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1905 = MVCK { 1904, 5, 0, 6, 85, 0, 0, SystemZImpOpBase + 0, 789, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1904 = MVCIN { 1903, 4, 0, 6, 811, 2, 0, SystemZImpOpBase + 53, 1108, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1903 = MVCDK { 1902, 5, 0, 6, 26, 0, 0, SystemZImpOpBase + 0, 789, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1902 = MVC { 1901, 5, 1, 6, 182, 0, 0, SystemZImpOpBase + 0, 487, 0|(1ULL<<MCID::MayLoad), 0x8cULL }, // Inst #1901 = MSY { 1900, 1, 0, 4, 824, 0, 0, SystemZImpOpBase + 0, 1288, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1900 = MSTA { 1899, 3, 1, 4, 199, 0, 1, SystemZImpOpBase + 0, 541, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #1899 = MSRKC { 1898, 3, 1, 4, 183, 0, 0, SystemZImpOpBase + 0, 538, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #1898 = MSR { 1897, 3, 1, 4, 200, 0, 1, SystemZImpOpBase + 0, 382, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #1897 = MSGRKC { 1896, 3, 1, 4, 185, 0, 0, SystemZImpOpBase + 0, 526, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #1896 = MSGR { 1895, 3, 1, 4, 186, 0, 0, SystemZImpOpBase + 0, 523, 0, 0x0ULL }, // Inst #1895 = MSGFR { 1894, 3, 1, 6, 186, 0, 0, SystemZImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #1894 = MSGFI { 1893, 5, 1, 6, 182, 0, 0, SystemZImpOpBase + 0, 518, 0|(1ULL<<MCID::MayLoad), 0x8cULL }, // Inst #1893 = MSGF { 1892, 5, 1, 6, 198, 0, 1, SystemZImpOpBase + 0, 518, 0|(1ULL<<MCID::MayLoad), 0x10cULL }, // Inst #1892 = MSGC { 1891, 5, 1, 6, 184, 0, 0, SystemZImpOpBase + 0, 518, 0|(1ULL<<MCID::MayLoad), 0x10cULL }, // Inst #1891 = MSG { 1890, 3, 1, 6, 183, 0, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1890 = MSFI { 1889, 4, 1, 4, 454, 0, 0, SystemZImpOpBase + 0, 1281, 0, 0x0ULL }, // Inst #1889 = MSER { 1888, 4, 1, 4, 393, 1, 0, SystemZImpOpBase + 12, 1281, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1888 = MSEBR { 1887, 6, 1, 6, 392, 1, 0, SystemZImpOpBase + 12, 1275, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayRaiseFPException), 0x88ULL }, // Inst #1887 = MSEB { 1886, 6, 1, 6, 453, 0, 0, SystemZImpOpBase + 0, 1275, 0|(1ULL<<MCID::MayLoad), 0x88ULL }, // Inst #1886 = MSE { 1885, 4, 1, 4, 454, 0, 0, SystemZImpOpBase + 0, 1271, 0, 0x0ULL }, // Inst #1885 = MSDR { 1884, 4, 1, 4, 395, 1, 0, SystemZImpOpBase + 12, 1271, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1884 = MSDBR { 1883, 6, 1, 6, 394, 1, 0, SystemZImpOpBase + 12, 1265, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayRaiseFPException), 0x108ULL }, // Inst #1883 = MSDB { 1882, 6, 1, 6, 453, 0, 0, SystemZImpOpBase + 0, 1265, 0|(1ULL<<MCID::MayLoad), 0x108ULL }, // Inst #1882 = MSD { 1881, 2, 0, 4, 856, 1, 1, SystemZImpOpBase + 41, 675, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1881 = MSCH { 1880, 5, 1, 6, 197, 0, 1, SystemZImpOpBase + 0, 487, 0|(1ULL<<MCID::MayLoad), 0x8cULL }, // Inst #1880 = MSC { 1879, 5, 1, 4, 182, 0, 0, SystemZImpOpBase + 0, 487, 0|(1ULL<<MCID::MayLoad), 0x88ULL }, // Inst #1879 = MS { 1878, 3, 1, 2, 192, 0, 0, SystemZImpOpBase + 0, 924, 0, 0x0ULL }, // Inst #1878 = MR { 1877, 6, 0, 6, 306, 0, 0, SystemZImpOpBase + 0, 544, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1877 = MP { 1876, 3, 1, 4, 192, 0, 0, SystemZImpOpBase + 0, 924, 0, 0x0ULL }, // Inst #1876 = MLR { 1875, 3, 1, 4, 188, 0, 0, SystemZImpOpBase + 0, 870, 0, 0x0ULL }, // Inst #1875 = MLGR { 1874, 5, 1, 6, 187, 0, 0, SystemZImpOpBase + 0, 904, 0|(1ULL<<MCID::MayLoad), 0x10cULL }, // Inst #1874 = MLG { 1873, 5, 1, 6, 193, 0, 0, SystemZImpOpBase + 0, 904, 0|(1ULL<<MCID::MayLoad), 0x8cULL }, // Inst #1873 = ML { 1872, 5, 1, 6, 191, 0, 0, SystemZImpOpBase + 0, 487, 0|(1ULL<<MCID::MayLoad), 0x4cULL }, // Inst #1872 = MHY { 1871, 3, 1, 4, 190, 0, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1871 = MHI { 1870, 5, 1, 4, 191, 0, 0, SystemZImpOpBase + 0, 487, 0|(1ULL<<MCID::MayLoad), 0x48ULL }, // Inst #1870 = MH { 1869, 3, 1, 4, 196, 0, 0, SystemZImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1869 = MGRK { 1868, 3, 1, 4, 189, 0, 0, SystemZImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #1868 = MGHI { 1867, 5, 1, 6, 194, 0, 0, SystemZImpOpBase + 0, 518, 0|(1ULL<<MCID::MayLoad), 0x4cULL }, // Inst #1867 = MGH { 1866, 5, 1, 6, 195, 0, 0, SystemZImpOpBase + 0, 904, 0|(1ULL<<MCID::MayLoad), 0x10cULL }, // Inst #1866 = MG { 1865, 5, 1, 6, 193, 0, 0, SystemZImpOpBase + 0, 904, 0|(1ULL<<MCID::MayLoad), 0x8cULL }, // Inst #1865 = MFY { 1864, 3, 1, 2, 445, 0, 0, SystemZImpOpBase + 0, 1285, 0, 0x0ULL }, // Inst #1864 = MER { 1863, 3, 1, 4, 892, 0, 0, SystemZImpOpBase + 0, 512, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #1863 = MEER { 1862, 3, 1, 4, 388, 1, 0, SystemZImpOpBase + 12, 512, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #1862 = MEEBR { 1861, 5, 1, 6, 387, 1, 0, SystemZImpOpBase + 12, 507, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayRaiseFPException), 0x88ULL }, // Inst #1861 = MEEB { 1860, 5, 1, 6, 891, 0, 0, SystemZImpOpBase + 0, 507, 0|(1ULL<<MCID::MayLoad), 0x88ULL }, // Inst #1860 = MEE { 1859, 5, 1, 4, 444, 0, 0, SystemZImpOpBase + 0, 492, 0|(1ULL<<MCID::MayLoad), 0x88ULL }, // Inst #1859 = ME { 1858, 4, 1, 4, 508, 1, 0, SystemZImpOpBase + 12, 503, 0, 0x0ULL }, // Inst #1858 = MDTRA { 1857, 3, 1, 4, 508, 1, 0, SystemZImpOpBase + 12, 500, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #1857 = MDTR { 1856, 3, 1, 2, 892, 0, 0, SystemZImpOpBase + 0, 497, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #1856 = MDR { 1855, 3, 1, 2, 445, 0, 0, SystemZImpOpBase + 0, 1285, 0, 0x0ULL }, // Inst #1855 = MDER { 1854, 3, 1, 4, 388, 1, 0, SystemZImpOpBase + 12, 1285, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1854 = MDEBR { 1853, 5, 1, 6, 387, 1, 0, SystemZImpOpBase + 12, 492, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayRaiseFPException), 0x88ULL }, // Inst #1853 = MDEB { 1852, 5, 1, 4, 444, 0, 0, SystemZImpOpBase + 0, 492, 0|(1ULL<<MCID::MayLoad), 0x88ULL }, // Inst #1852 = MDE { 1851, 3, 1, 4, 388, 1, 0, SystemZImpOpBase + 12, 497, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #1851 = MDBR { 1850, 5, 1, 6, 387, 1, 0, SystemZImpOpBase + 12, 492, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayRaiseFPException), 0x108ULL }, // Inst #1850 = MDB { 1849, 5, 1, 4, 891, 0, 0, SystemZImpOpBase + 0, 492, 0|(1ULL<<MCID::MayLoad), 0x108ULL }, // Inst #1849 = MD { 1848, 3, 0, 4, 842, 0, 0, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1848 = MC { 1847, 4, 1, 4, 457, 0, 0, SystemZImpOpBase + 0, 1271, 0, 0x0ULL }, // Inst #1847 = MAYR { 1846, 4, 1, 4, 458, 0, 0, SystemZImpOpBase + 0, 1271, 0, 0x0ULL }, // Inst #1846 = MAYLR { 1845, 6, 1, 6, 456, 0, 0, SystemZImpOpBase + 0, 1265, 0|(1ULL<<MCID::MayLoad), 0x108ULL }, // Inst #1845 = MAYL { 1844, 4, 1, 4, 458, 0, 0, SystemZImpOpBase + 0, 1271, 0, 0x0ULL }, // Inst #1844 = MAYHR { 1843, 6, 1, 6, 456, 0, 0, SystemZImpOpBase + 0, 1265, 0|(1ULL<<MCID::MayLoad), 0x108ULL }, // Inst #1843 = MAYH { 1842, 6, 1, 6, 455, 0, 0, SystemZImpOpBase + 0, 1265, 0|(1ULL<<MCID::MayLoad), 0x108ULL }, // Inst #1842 = MAY { 1841, 4, 1, 4, 454, 0, 0, SystemZImpOpBase + 0, 1281, 0, 0x0ULL }, // Inst #1841 = MAER { 1840, 4, 1, 4, 393, 1, 0, SystemZImpOpBase + 12, 1281, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1840 = MAEBR { 1839, 6, 1, 6, 392, 1, 0, SystemZImpOpBase + 12, 1275, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayRaiseFPException), 0x88ULL }, // Inst #1839 = MAEB { 1838, 6, 1, 6, 453, 0, 0, SystemZImpOpBase + 0, 1275, 0|(1ULL<<MCID::MayLoad), 0x88ULL }, // Inst #1838 = MAE { 1837, 4, 1, 4, 454, 0, 0, SystemZImpOpBase + 0, 1271, 0, 0x0ULL }, // Inst #1837 = MADR { 1836, 4, 1, 4, 395, 1, 0, SystemZImpOpBase + 12, 1271, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1836 = MADBR { 1835, 6, 1, 6, 394, 1, 0, SystemZImpOpBase + 12, 1265, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayRaiseFPException), 0x108ULL }, // Inst #1835 = MADB { 1834, 6, 1, 6, 453, 0, 0, SystemZImpOpBase + 0, 1265, 0|(1ULL<<MCID::MayLoad), 0x108ULL }, // Inst #1834 = MAD { 1833, 5, 1, 4, 193, 0, 0, SystemZImpOpBase + 0, 904, 0|(1ULL<<MCID::MayLoad), 0x88ULL }, // Inst #1833 = M { 1832, 1, 1, 4, 343, 0, 0, SystemZImpOpBase + 0, 346, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1832 = LZXR { 1831, 4, 1, 6, 42, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x10cULL }, // Inst #1831 = LZRG { 1830, 4, 1, 6, 42, 0, 0, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::MayLoad), 0x8cULL }, // Inst #1830 = LZRF { 1829, 1, 1, 4, 342, 0, 0, SystemZImpOpBase + 0, 345, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1829 = LZER { 1828, 1, 1, 4, 342, 0, 0, SystemZImpOpBase + 0, 344, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1828 = LZDR { 1827, 4, 1, 6, 33, 0, 0, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x8dULL }, // Inst #1827 = LY { 1826, 2, 1, 4, 347, 0, 0, SystemZImpOpBase + 0, 673, 0, 0x0ULL }, // Inst #1826 = LXR { 1825, 2, 1, 4, 422, 0, 0, SystemZImpOpBase + 0, 1263, 0, 0x0ULL }, // Inst #1825 = LXER { 1824, 2, 1, 4, 361, 1, 0, SystemZImpOpBase + 12, 1263, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1824 = LXEBR { 1823, 4, 1, 6, 360, 1, 0, SystemZImpOpBase + 12, 347, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayRaiseFPException), 0x88ULL }, // Inst #1823 = LXEB { 1822, 4, 1, 6, 421, 0, 0, SystemZImpOpBase + 0, 347, 0|(1ULL<<MCID::MayLoad), 0x88ULL }, // Inst #1822 = LXE { 1821, 3, 1, 4, 472, 1, 0, SystemZImpOpBase + 12, 1260, 0, 0x0ULL }, // Inst #1821 = LXDTR { 1820, 2, 1, 4, 422, 0, 0, SystemZImpOpBase + 0, 1258, 0, 0x0ULL }, // Inst #1820 = LXDR { 1819, 2, 1, 4, 361, 1, 0, SystemZImpOpBase + 12, 1258, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1819 = LXDBR { 1818, 4, 1, 6, 360, 1, 0, SystemZImpOpBase + 12, 347, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayRaiseFPException), 0x108ULL }, // Inst #1818 = LXDB { 1817, 4, 1, 6, 421, 0, 0, SystemZImpOpBase + 0, 347, 0|(1ULL<<MCID::MayLoad), 0x108ULL }, // Inst #1817 = LXD { 1816, 2, 1, 4, 807, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1816 = LURAG { 1815, 2, 1, 4, 807, 0, 0, SystemZImpOpBase + 0, 933, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1815 = LURA { 1814, 2, 1, 4, 468, 1, 1, SystemZImpOpBase + 1, 673, 0, 0x0ULL }, // Inst #1814 = LTXTR { 1813, 2, 1, 4, 415, 0, 1, SystemZImpOpBase + 0, 673, 0, 0x0ULL }, // Inst #1813 = LTXR { 1812, 2, 1, 4, 349, 1, 1, SystemZImpOpBase + 1, 673, 0|(1ULL<<MCID::MayRaiseFPException), 0x3fc00ULL }, // Inst #1812 = LTXBR { 1811, 2, 1, 2, 45, 0, 1, SystemZImpOpBase + 0, 815, 0, 0x3b800ULL }, // Inst #1811 = LTR { 1810, 2, 1, 4, 45, 0, 1, SystemZImpOpBase + 0, 563, 0, 0x3b800ULL }, // Inst #1810 = LTGR { 1809, 2, 1, 4, 60, 0, 1, SystemZImpOpBase + 0, 714, 0, 0x3b800ULL }, // Inst #1809 = LTGFR { 1808, 4, 1, 6, 59, 0, 1, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x3b88cULL }, // Inst #1808 = LTGF { 1807, 4, 1, 6, 44, 0, 1, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x3b90cULL }, // Inst #1807 = LTG { 1806, 2, 1, 2, 414, 0, 1, SystemZImpOpBase + 0, 659, 0, 0x0ULL }, // Inst #1806 = LTER { 1805, 2, 1, 4, 348, 1, 1, SystemZImpOpBase + 1, 659, 0|(1ULL<<MCID::MayRaiseFPException), 0x3fc00ULL }, // Inst #1805 = LTEBR { 1804, 2, 1, 4, 467, 1, 1, SystemZImpOpBase + 1, 631, 0, 0x0ULL }, // Inst #1804 = LTDTR { 1803, 2, 1, 2, 414, 0, 1, SystemZImpOpBase + 0, 631, 0, 0x0ULL }, // Inst #1803 = LTDR { 1802, 2, 1, 4, 348, 1, 1, SystemZImpOpBase + 1, 631, 0|(1ULL<<MCID::MayRaiseFPException), 0x3fc00ULL }, // Inst #1802 = LTDBR { 1801, 4, 1, 6, 44, 0, 1, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::MayLoad), 0x3b88cULL }, // Inst #1801 = LT { 1800, 2, 0, 4, 852, 0, 1, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1800 = LSCTL { 1799, 2, 1, 4, 82, 0, 0, SystemZImpOpBase + 0, 815, 0, 0x0ULL }, // Inst #1799 = LRVR { 1798, 4, 1, 6, 83, 0, 0, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::MayLoad), 0x4cULL }, // Inst #1798 = LRVH { 1797, 2, 1, 4, 82, 0, 0, SystemZImpOpBase + 0, 563, 0, 0x0ULL }, // Inst #1797 = LRVGR { 1796, 4, 1, 6, 83, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x10cULL }, // Inst #1796 = LRVG { 1795, 4, 1, 6, 83, 0, 0, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::MayLoad), 0x8cULL }, // Inst #1795 = LRV { 1794, 2, 1, 6, 33, 0, 0, SystemZImpOpBase + 0, 765, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1794 = LRL { 1793, 2, 1, 2, 416, 0, 0, SystemZImpOpBase + 0, 1128, 0, 0x0ULL }, // Inst #1793 = LRER { 1792, 2, 1, 2, 418, 0, 0, SystemZImpOpBase + 0, 1126, 0, 0x0ULL }, // Inst #1792 = LRDR { 1791, 4, 1, 6, 805, 0, 1, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xcULL }, // Inst #1791 = LRAY { 1790, 4, 1, 6, 805, 0, 1, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xcULL }, // Inst #1790 = LRAG { 1789, 4, 1, 4, 805, 0, 1, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL }, // Inst #1789 = LRA { 1788, 2, 1, 2, 41, 0, 0, SystemZImpOpBase + 0, 815, 0, 0x0ULL }, // Inst #1788 = LR { 1787, 2, 1, 4, 430, 0, 1, SystemZImpOpBase + 0, 673, 0, 0x0ULL }, // Inst #1787 = LPXR { 1786, 2, 1, 4, 374, 0, 1, SystemZImpOpBase + 0, 673, 0, 0x3fc00ULL }, // Inst #1786 = LPXBR { 1785, 5, 2, 4, 804, 0, 1, SystemZImpOpBase + 0, 1253, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1785 = LPTEA { 1784, 2, 0, 6, 774, 0, 1, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x204ULL }, // Inst #1784 = LPSWEY { 1783, 2, 0, 4, 863, 0, 1, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1783 = LPSWE { 1782, 2, 0, 4, 863, 0, 1, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1782 = LPSW { 1781, 2, 1, 2, 88, 0, 1, SystemZImpOpBase + 0, 815, 0, 0x23c00ULL }, // Inst #1781 = LPR { 1780, 4, 1, 6, 280, 0, 0, SystemZImpOpBase + 0, 306, 0|(1ULL<<MCID::MayLoad), 0x20cULL }, // Inst #1780 = LPQ { 1779, 2, 0, 4, 848, 0, 0, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1779 = LPP { 1778, 2, 1, 4, 88, 0, 1, SystemZImpOpBase + 0, 563, 0, 0x23c00ULL }, // Inst #1778 = LPGR { 1777, 2, 1, 4, 89, 0, 1, SystemZImpOpBase + 0, 714, 0, 0x3b800ULL }, // Inst #1777 = LPGFR { 1776, 2, 1, 2, 429, 0, 1, SystemZImpOpBase + 0, 659, 0, 0x0ULL }, // Inst #1776 = LPER { 1775, 2, 1, 4, 372, 0, 1, SystemZImpOpBase + 0, 659, 0, 0x3fc00ULL }, // Inst #1775 = LPEBR { 1774, 2, 1, 2, 429, 0, 1, SystemZImpOpBase + 0, 631, 0, 0x0ULL }, // Inst #1774 = LPDR { 1773, 5, 1, 6, 282, 0, 1, SystemZImpOpBase + 0, 1248, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1773 = LPDG { 1772, 2, 1, 4, 373, 0, 0, SystemZImpOpBase + 0, 659, 0, 0x0ULL }, // Inst #1772 = LPDFR_32 { 1771, 2, 1, 4, 373, 0, 0, SystemZImpOpBase + 0, 631, 0, 0x0ULL }, // Inst #1771 = LPDFR { 1770, 2, 1, 4, 372, 0, 1, SystemZImpOpBase + 0, 631, 0, 0x3fc00ULL }, // Inst #1770 = LPDBR { 1769, 5, 1, 6, 282, 0, 1, SystemZImpOpBase + 0, 1248, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1769 = LPD { 1768, 2, 0, 4, 852, 0, 1, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1768 = LPCTL { 1767, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #1767 = LOCRAsmZ { 1766, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #1766 = LOCRAsmP { 1765, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #1765 = LOCRAsmO { 1764, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #1764 = LOCRAsmNZ { 1763, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #1763 = LOCRAsmNP { 1762, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #1762 = LOCRAsmNO { 1761, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #1761 = LOCRAsmNM { 1760, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #1760 = LOCRAsmNLH { 1759, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #1759 = LOCRAsmNLE { 1758, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #1758 = LOCRAsmNL { 1757, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #1757 = LOCRAsmNHE { 1756, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #1756 = LOCRAsmNH { 1755, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #1755 = LOCRAsmNE { 1754, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #1754 = LOCRAsmM { 1753, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #1753 = LOCRAsmLH { 1752, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #1752 = LOCRAsmLE { 1751, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #1751 = LOCRAsmL { 1750, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #1750 = LOCRAsmHE { 1749, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #1749 = LOCRAsmH { 1748, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 538, 0, 0x0ULL }, // Inst #1748 = LOCRAsmE { 1747, 4, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 1244, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #1747 = LOCRAsm { 1746, 5, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 1239, 0|(1ULL<<MCID::Commutable), 0x80000ULL }, // Inst #1746 = LOCR { 1745, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1745 = LOCHIAsmZ { 1744, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1744 = LOCHIAsmP { 1743, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1743 = LOCHIAsmO { 1742, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1742 = LOCHIAsmNZ { 1741, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1741 = LOCHIAsmNP { 1740, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1740 = LOCHIAsmNO { 1739, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1739 = LOCHIAsmNM { 1738, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1738 = LOCHIAsmNLH { 1737, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1737 = LOCHIAsmNLE { 1736, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1736 = LOCHIAsmNL { 1735, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1735 = LOCHIAsmNHE { 1734, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1734 = LOCHIAsmNH { 1733, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1733 = LOCHIAsmNE { 1732, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1732 = LOCHIAsmM { 1731, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1731 = LOCHIAsmLH { 1730, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1730 = LOCHIAsmLE { 1729, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1729 = LOCHIAsmL { 1728, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1728 = LOCHIAsmHE { 1727, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1727 = LOCHIAsmH { 1726, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1726 = LOCHIAsmE { 1725, 4, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 1235, 0, 0x0ULL }, // Inst #1725 = LOCHIAsm { 1724, 5, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 1230, 0, 0x80000ULL }, // Inst #1724 = LOCHI { 1723, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1723 = LOCHHIAsmZ { 1722, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1722 = LOCHHIAsmP { 1721, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1721 = LOCHHIAsmO { 1720, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1720 = LOCHHIAsmNZ { 1719, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1719 = LOCHHIAsmNP { 1718, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1718 = LOCHHIAsmNO { 1717, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1717 = LOCHHIAsmNM { 1716, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1716 = LOCHHIAsmNLH { 1715, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1715 = LOCHHIAsmNLE { 1714, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1714 = LOCHHIAsmNL { 1713, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1713 = LOCHHIAsmNHE { 1712, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1712 = LOCHHIAsmNH { 1711, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1711 = LOCHHIAsmNE { 1710, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1710 = LOCHHIAsmM { 1709, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1709 = LOCHHIAsmLH { 1708, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1708 = LOCHHIAsmLE { 1707, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1707 = LOCHHIAsmL { 1706, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1706 = LOCHHIAsmHE { 1705, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1705 = LOCHHIAsmH { 1704, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1704 = LOCHHIAsmE { 1703, 4, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 1226, 0, 0x0ULL }, // Inst #1703 = LOCHHIAsm { 1702, 5, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 1221, 0, 0x80000ULL }, // Inst #1702 = LOCHHI { 1701, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #1701 = LOCGRAsmZ { 1700, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #1700 = LOCGRAsmP { 1699, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #1699 = LOCGRAsmO { 1698, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #1698 = LOCGRAsmNZ { 1697, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #1697 = LOCGRAsmNP { 1696, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #1696 = LOCGRAsmNO { 1695, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #1695 = LOCGRAsmNM { 1694, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #1694 = LOCGRAsmNLH { 1693, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #1693 = LOCGRAsmNLE { 1692, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #1692 = LOCGRAsmNL { 1691, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #1691 = LOCGRAsmNHE { 1690, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #1690 = LOCGRAsmNH { 1689, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #1689 = LOCGRAsmNE { 1688, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #1688 = LOCGRAsmM { 1687, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #1687 = LOCGRAsmLH { 1686, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #1686 = LOCGRAsmLE { 1685, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #1685 = LOCGRAsmL { 1684, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #1684 = LOCGRAsmHE { 1683, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #1683 = LOCGRAsmH { 1682, 3, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 526, 0, 0x0ULL }, // Inst #1682 = LOCGRAsmE { 1681, 4, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 1217, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #1681 = LOCGRAsm { 1680, 5, 1, 4, 884, 1, 0, SystemZImpOpBase + 0, 1212, 0|(1ULL<<MCID::Commutable), 0x80000ULL }, // Inst #1680 = LOCGR { 1679, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #1679 = LOCGHIAsmZ { 1678, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #1678 = LOCGHIAsmP { 1677, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #1677 = LOCGHIAsmO { 1676, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #1676 = LOCGHIAsmNZ { 1675, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #1675 = LOCGHIAsmNP { 1674, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #1674 = LOCGHIAsmNO { 1673, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #1673 = LOCGHIAsmNM { 1672, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #1672 = LOCGHIAsmNLH { 1671, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #1671 = LOCGHIAsmNLE { 1670, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #1670 = LOCGHIAsmNL { 1669, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #1669 = LOCGHIAsmNHE { 1668, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #1668 = LOCGHIAsmNH { 1667, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #1667 = LOCGHIAsmNE { 1666, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #1666 = LOCGHIAsmM { 1665, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #1665 = LOCGHIAsmLH { 1664, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #1664 = LOCGHIAsmLE { 1663, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #1663 = LOCGHIAsmL { 1662, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #1662 = LOCGHIAsmHE { 1661, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #1661 = LOCGHIAsmH { 1660, 3, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #1660 = LOCGHIAsmE { 1659, 4, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 1208, 0, 0x0ULL }, // Inst #1659 = LOCGHIAsm { 1658, 5, 1, 6, 52, 1, 0, SystemZImpOpBase + 0, 1203, 0, 0x80000ULL }, // Inst #1658 = LOCGHI { 1657, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1199, 0|(1ULL<<MCID::MayLoad), 0x104ULL }, // Inst #1657 = LOCGAsmZ { 1656, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1199, 0|(1ULL<<MCID::MayLoad), 0x104ULL }, // Inst #1656 = LOCGAsmP { 1655, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1199, 0|(1ULL<<MCID::MayLoad), 0x104ULL }, // Inst #1655 = LOCGAsmO { 1654, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1199, 0|(1ULL<<MCID::MayLoad), 0x104ULL }, // Inst #1654 = LOCGAsmNZ { 1653, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1199, 0|(1ULL<<MCID::MayLoad), 0x104ULL }, // Inst #1653 = LOCGAsmNP { 1652, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1199, 0|(1ULL<<MCID::MayLoad), 0x104ULL }, // Inst #1652 = LOCGAsmNO { 1651, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1199, 0|(1ULL<<MCID::MayLoad), 0x104ULL }, // Inst #1651 = LOCGAsmNM { 1650, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1199, 0|(1ULL<<MCID::MayLoad), 0x104ULL }, // Inst #1650 = LOCGAsmNLH { 1649, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1199, 0|(1ULL<<MCID::MayLoad), 0x104ULL }, // Inst #1649 = LOCGAsmNLE { 1648, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1199, 0|(1ULL<<MCID::MayLoad), 0x104ULL }, // Inst #1648 = LOCGAsmNL { 1647, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1199, 0|(1ULL<<MCID::MayLoad), 0x104ULL }, // Inst #1647 = LOCGAsmNHE { 1646, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1199, 0|(1ULL<<MCID::MayLoad), 0x104ULL }, // Inst #1646 = LOCGAsmNH { 1645, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1199, 0|(1ULL<<MCID::MayLoad), 0x104ULL }, // Inst #1645 = LOCGAsmNE { 1644, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1199, 0|(1ULL<<MCID::MayLoad), 0x104ULL }, // Inst #1644 = LOCGAsmM { 1643, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1199, 0|(1ULL<<MCID::MayLoad), 0x104ULL }, // Inst #1643 = LOCGAsmLH { 1642, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1199, 0|(1ULL<<MCID::MayLoad), 0x104ULL }, // Inst #1642 = LOCGAsmLE { 1641, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1199, 0|(1ULL<<MCID::MayLoad), 0x104ULL }, // Inst #1641 = LOCGAsmL { 1640, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1199, 0|(1ULL<<MCID::MayLoad), 0x104ULL }, // Inst #1640 = LOCGAsmHE { 1639, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1199, 0|(1ULL<<MCID::MayLoad), 0x104ULL }, // Inst #1639 = LOCGAsmH { 1638, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1199, 0|(1ULL<<MCID::MayLoad), 0x104ULL }, // Inst #1638 = LOCGAsmE { 1637, 5, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1194, 0|(1ULL<<MCID::MayLoad), 0x104ULL }, // Inst #1637 = LOCGAsm { 1636, 6, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1188, 0|(1ULL<<MCID::MayLoad), 0x80104ULL }, // Inst #1636 = LOCG { 1635, 3, 1, 4, 51, 1, 0, SystemZImpOpBase + 0, 1185, 0, 0x0ULL }, // Inst #1635 = LOCFHRAsmZ { 1634, 3, 1, 4, 51, 1, 0, SystemZImpOpBase + 0, 1185, 0, 0x0ULL }, // Inst #1634 = LOCFHRAsmP { 1633, 3, 1, 4, 51, 1, 0, SystemZImpOpBase + 0, 1185, 0, 0x0ULL }, // Inst #1633 = LOCFHRAsmO { 1632, 3, 1, 4, 51, 1, 0, SystemZImpOpBase + 0, 1185, 0, 0x0ULL }, // Inst #1632 = LOCFHRAsmNZ { 1631, 3, 1, 4, 51, 1, 0, SystemZImpOpBase + 0, 1185, 0, 0x0ULL }, // Inst #1631 = LOCFHRAsmNP { 1630, 3, 1, 4, 51, 1, 0, SystemZImpOpBase + 0, 1185, 0, 0x0ULL }, // Inst #1630 = LOCFHRAsmNO { 1629, 3, 1, 4, 51, 1, 0, SystemZImpOpBase + 0, 1185, 0, 0x0ULL }, // Inst #1629 = LOCFHRAsmNM { 1628, 3, 1, 4, 51, 1, 0, SystemZImpOpBase + 0, 1185, 0, 0x0ULL }, // Inst #1628 = LOCFHRAsmNLH { 1627, 3, 1, 4, 51, 1, 0, SystemZImpOpBase + 0, 1185, 0, 0x0ULL }, // Inst #1627 = LOCFHRAsmNLE { 1626, 3, 1, 4, 51, 1, 0, SystemZImpOpBase + 0, 1185, 0, 0x0ULL }, // Inst #1626 = LOCFHRAsmNL { 1625, 3, 1, 4, 51, 1, 0, SystemZImpOpBase + 0, 1185, 0, 0x0ULL }, // Inst #1625 = LOCFHRAsmNHE { 1624, 3, 1, 4, 51, 1, 0, SystemZImpOpBase + 0, 1185, 0, 0x0ULL }, // Inst #1624 = LOCFHRAsmNH { 1623, 3, 1, 4, 51, 1, 0, SystemZImpOpBase + 0, 1185, 0, 0x0ULL }, // Inst #1623 = LOCFHRAsmNE { 1622, 3, 1, 4, 51, 1, 0, SystemZImpOpBase + 0, 1185, 0, 0x0ULL }, // Inst #1622 = LOCFHRAsmM { 1621, 3, 1, 4, 51, 1, 0, SystemZImpOpBase + 0, 1185, 0, 0x0ULL }, // Inst #1621 = LOCFHRAsmLH { 1620, 3, 1, 4, 51, 1, 0, SystemZImpOpBase + 0, 1185, 0, 0x0ULL }, // Inst #1620 = LOCFHRAsmLE { 1619, 3, 1, 4, 51, 1, 0, SystemZImpOpBase + 0, 1185, 0, 0x0ULL }, // Inst #1619 = LOCFHRAsmL { 1618, 3, 1, 4, 51, 1, 0, SystemZImpOpBase + 0, 1185, 0, 0x0ULL }, // Inst #1618 = LOCFHRAsmHE { 1617, 3, 1, 4, 51, 1, 0, SystemZImpOpBase + 0, 1185, 0, 0x0ULL }, // Inst #1617 = LOCFHRAsmH { 1616, 3, 1, 4, 51, 1, 0, SystemZImpOpBase + 0, 1185, 0, 0x0ULL }, // Inst #1616 = LOCFHRAsmE { 1615, 4, 1, 4, 51, 1, 0, SystemZImpOpBase + 0, 1181, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #1615 = LOCFHRAsm { 1614, 5, 1, 4, 51, 1, 0, SystemZImpOpBase + 0, 1176, 0|(1ULL<<MCID::Commutable), 0x80000ULL }, // Inst #1614 = LOCFHR { 1613, 4, 1, 6, 53, 1, 0, SystemZImpOpBase + 0, 1172, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1613 = LOCFHAsmZ { 1612, 4, 1, 6, 53, 1, 0, SystemZImpOpBase + 0, 1172, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1612 = LOCFHAsmP { 1611, 4, 1, 6, 53, 1, 0, SystemZImpOpBase + 0, 1172, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1611 = LOCFHAsmO { 1610, 4, 1, 6, 53, 1, 0, SystemZImpOpBase + 0, 1172, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1610 = LOCFHAsmNZ { 1609, 4, 1, 6, 53, 1, 0, SystemZImpOpBase + 0, 1172, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1609 = LOCFHAsmNP { 1608, 4, 1, 6, 53, 1, 0, SystemZImpOpBase + 0, 1172, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1608 = LOCFHAsmNO { 1607, 4, 1, 6, 53, 1, 0, SystemZImpOpBase + 0, 1172, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1607 = LOCFHAsmNM { 1606, 4, 1, 6, 53, 1, 0, SystemZImpOpBase + 0, 1172, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1606 = LOCFHAsmNLH { 1605, 4, 1, 6, 53, 1, 0, SystemZImpOpBase + 0, 1172, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1605 = LOCFHAsmNLE { 1604, 4, 1, 6, 53, 1, 0, SystemZImpOpBase + 0, 1172, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1604 = LOCFHAsmNL { 1603, 4, 1, 6, 53, 1, 0, SystemZImpOpBase + 0, 1172, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1603 = LOCFHAsmNHE { 1602, 4, 1, 6, 53, 1, 0, SystemZImpOpBase + 0, 1172, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1602 = LOCFHAsmNH { 1601, 4, 1, 6, 53, 1, 0, SystemZImpOpBase + 0, 1172, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1601 = LOCFHAsmNE { 1600, 4, 1, 6, 53, 1, 0, SystemZImpOpBase + 0, 1172, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1600 = LOCFHAsmM { 1599, 4, 1, 6, 53, 1, 0, SystemZImpOpBase + 0, 1172, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1599 = LOCFHAsmLH { 1598, 4, 1, 6, 53, 1, 0, SystemZImpOpBase + 0, 1172, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1598 = LOCFHAsmLE { 1597, 4, 1, 6, 53, 1, 0, SystemZImpOpBase + 0, 1172, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1597 = LOCFHAsmL { 1596, 4, 1, 6, 53, 1, 0, SystemZImpOpBase + 0, 1172, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1596 = LOCFHAsmHE { 1595, 4, 1, 6, 53, 1, 0, SystemZImpOpBase + 0, 1172, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1595 = LOCFHAsmH { 1594, 4, 1, 6, 53, 1, 0, SystemZImpOpBase + 0, 1172, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1594 = LOCFHAsmE { 1593, 5, 1, 6, 53, 1, 0, SystemZImpOpBase + 0, 1167, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1593 = LOCFHAsm { 1592, 6, 1, 6, 53, 1, 0, SystemZImpOpBase + 0, 1161, 0|(1ULL<<MCID::MayLoad), 0x80084ULL }, // Inst #1592 = LOCFH { 1591, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1157, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1591 = LOCAsmZ { 1590, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1157, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1590 = LOCAsmP { 1589, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1157, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1589 = LOCAsmO { 1588, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1157, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1588 = LOCAsmNZ { 1587, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1157, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1587 = LOCAsmNP { 1586, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1157, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1586 = LOCAsmNO { 1585, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1157, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1585 = LOCAsmNM { 1584, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1157, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1584 = LOCAsmNLH { 1583, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1157, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1583 = LOCAsmNLE { 1582, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1157, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1582 = LOCAsmNL { 1581, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1157, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1581 = LOCAsmNHE { 1580, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1157, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1580 = LOCAsmNH { 1579, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1157, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1579 = LOCAsmNE { 1578, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1157, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1578 = LOCAsmM { 1577, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1157, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1577 = LOCAsmLH { 1576, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1157, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1576 = LOCAsmLE { 1575, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1157, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1575 = LOCAsmL { 1574, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1157, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1574 = LOCAsmHE { 1573, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1157, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1573 = LOCAsmH { 1572, 4, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1157, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1572 = LOCAsmE { 1571, 5, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1152, 0|(1ULL<<MCID::MayLoad), 0x84ULL }, // Inst #1571 = LOCAsm { 1570, 6, 1, 6, 885, 1, 0, SystemZImpOpBase + 0, 1146, 0|(1ULL<<MCID::MayLoad), 0x80084ULL }, // Inst #1570 = LOC { 1569, 2, 1, 4, 430, 0, 1, SystemZImpOpBase + 0, 673, 0, 0x0ULL }, // Inst #1569 = LNXR { 1568, 2, 1, 4, 374, 0, 1, SystemZImpOpBase + 0, 673, 0, 0x3fc00ULL }, // Inst #1568 = LNXBR { 1567, 2, 1, 2, 90, 0, 1, SystemZImpOpBase + 0, 815, 0, 0x23c00ULL }, // Inst #1567 = LNR { 1566, 2, 1, 4, 90, 0, 1, SystemZImpOpBase + 0, 563, 0, 0x23c00ULL }, // Inst #1566 = LNGR { 1565, 2, 1, 4, 89, 0, 1, SystemZImpOpBase + 0, 714, 0, 0x3b800ULL }, // Inst #1565 = LNGFR { 1564, 2, 1, 2, 429, 0, 1, SystemZImpOpBase + 0, 659, 0, 0x0ULL }, // Inst #1564 = LNER { 1563, 2, 1, 4, 372, 0, 1, SystemZImpOpBase + 0, 659, 0, 0x3fc00ULL }, // Inst #1563 = LNEBR { 1562, 2, 1, 2, 429, 0, 1, SystemZImpOpBase + 0, 631, 0, 0x0ULL }, // Inst #1562 = LNDR { 1561, 2, 1, 4, 373, 0, 0, SystemZImpOpBase + 0, 659, 0, 0x0ULL }, // Inst #1561 = LNDFR_32 { 1560, 2, 1, 4, 373, 0, 0, SystemZImpOpBase + 0, 631, 0, 0x0ULL }, // Inst #1560 = LNDFR { 1559, 2, 1, 4, 372, 0, 1, SystemZImpOpBase + 0, 631, 0, 0x3fc00ULL }, // Inst #1559 = LNDBR { 1558, 4, 2, 6, 79, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::MayLoad), 0x4ULL }, // Inst #1558 = LMY { 1557, 4, 2, 6, 79, 0, 0, SystemZImpOpBase + 0, 1142, 0|(1ULL<<MCID::MayLoad), 0x4ULL }, // Inst #1557 = LMH { 1556, 4, 2, 6, 79, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::MayLoad), 0x4ULL }, // Inst #1556 = LMG { 1555, 6, 2, 6, 80, 0, 0, SystemZImpOpBase + 0, 1136, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1555 = LMD { 1554, 4, 2, 4, 79, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1554 = LM { 1553, 4, 1, 6, 74, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x8cULL }, // Inst #1553 = LLZRGF { 1552, 2, 1, 4, 38, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1552 = LLILL { 1551, 2, 1, 4, 38, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1551 = LLILH { 1550, 2, 1, 6, 38, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1550 = LLILF { 1549, 2, 1, 4, 37, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1549 = LLIHL { 1548, 2, 1, 4, 37, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1548 = LLIHH { 1547, 2, 1, 6, 37, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1547 = LLIHF { 1546, 2, 1, 6, 72, 0, 0, SystemZImpOpBase + 0, 765, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1546 = LLHRL { 1545, 2, 1, 4, 67, 0, 0, SystemZImpOpBase + 0, 815, 0, 0x0ULL }, // Inst #1545 = LLHR { 1544, 4, 1, 6, 71, 0, 0, SystemZImpOpBase + 0, 757, 0|(1ULL<<MCID::MayLoad), 0x4cULL }, // Inst #1544 = LLHH { 1543, 4, 1, 6, 70, 0, 0, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::MayLoad), 0x4cULL }, // Inst #1543 = LLH { 1542, 2, 1, 4, 68, 0, 0, SystemZImpOpBase + 0, 563, 0, 0x0ULL }, // Inst #1542 = LLGTR { 1541, 4, 1, 6, 75, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x8cULL }, // Inst #1541 = LLGTAT { 1540, 4, 1, 6, 73, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x8cULL }, // Inst #1540 = LLGT { 1539, 2, 1, 6, 73, 0, 0, SystemZImpOpBase + 0, 716, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1539 = LLGHRL { 1538, 2, 1, 4, 68, 0, 0, SystemZImpOpBase + 0, 563, 0, 0x0ULL }, // Inst #1538 = LLGHR { 1537, 4, 1, 6, 73, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x4cULL }, // Inst #1537 = LLGH { 1536, 4, 1, 6, 295, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x8cULL }, // Inst #1536 = LLGFSG { 1535, 2, 1, 6, 73, 0, 0, SystemZImpOpBase + 0, 716, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1535 = LLGFRL { 1534, 2, 1, 4, 68, 0, 0, SystemZImpOpBase + 0, 714, 0, 0x0ULL }, // Inst #1534 = LLGFR { 1533, 4, 1, 6, 75, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x8cULL }, // Inst #1533 = LLGFAT { 1532, 4, 1, 6, 73, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x8cULL }, // Inst #1532 = LLGF { 1531, 2, 1, 4, 68, 0, 0, SystemZImpOpBase + 0, 563, 0, 0x0ULL }, // Inst #1531 = LLGCR { 1530, 4, 1, 6, 73, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x2cULL }, // Inst #1530 = LLGC { 1529, 2, 1, 4, 66, 0, 0, SystemZImpOpBase + 0, 815, 0, 0x0ULL }, // Inst #1529 = LLCR { 1528, 4, 1, 6, 71, 0, 0, SystemZImpOpBase + 0, 757, 0|(1ULL<<MCID::MayLoad), 0x2cULL }, // Inst #1528 = LLCH { 1527, 4, 1, 6, 69, 0, 0, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::MayLoad), 0x2cULL }, // Inst #1527 = LLC { 1526, 4, 1, 6, 62, 0, 0, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::MayLoad), 0x4cULL }, // Inst #1526 = LHY { 1525, 2, 1, 6, 63, 0, 0, SystemZImpOpBase + 0, 765, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1525 = LHRL { 1524, 2, 1, 4, 57, 0, 0, SystemZImpOpBase + 0, 815, 0, 0x0ULL }, // Inst #1524 = LHR { 1523, 2, 1, 4, 40, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1523 = LHI { 1522, 4, 1, 6, 63, 0, 0, SystemZImpOpBase + 0, 757, 0|(1ULL<<MCID::MayLoad), 0x4cULL }, // Inst #1522 = LHH { 1521, 4, 1, 4, 62, 0, 0, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::MayLoad), 0x48ULL }, // Inst #1521 = LH { 1520, 4, 0, 6, 296, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0xcULL }, // Inst #1520 = LGSC { 1519, 2, 1, 6, 35, 0, 0, SystemZImpOpBase + 0, 716, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1519 = LGRL { 1518, 2, 1, 4, 57, 0, 0, SystemZImpOpBase + 0, 563, 0, 0x0ULL }, // Inst #1518 = LGR { 1517, 2, 1, 6, 65, 0, 0, SystemZImpOpBase + 0, 716, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1517 = LGHRL { 1516, 2, 1, 4, 58, 0, 0, SystemZImpOpBase + 0, 563, 0, 0x0ULL }, // Inst #1516 = LGHR { 1515, 2, 1, 4, 39, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1515 = LGHI { 1514, 4, 1, 6, 64, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x4cULL }, // Inst #1514 = LGH { 1513, 4, 1, 6, 294, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x10cULL }, // Inst #1513 = LGG { 1512, 2, 1, 6, 65, 0, 0, SystemZImpOpBase + 0, 716, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1512 = LGFRL { 1511, 2, 1, 4, 58, 0, 0, SystemZImpOpBase + 0, 714, 0, 0x0ULL }, // Inst #1511 = LGFR { 1510, 2, 1, 6, 39, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1510 = LGFI { 1509, 4, 1, 6, 64, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x8cULL }, // Inst #1509 = LGF { 1508, 2, 1, 4, 346, 0, 0, SystemZImpOpBase + 0, 886, 0|(1ULL<<MCID::Bitcast), 0x0ULL }, // Inst #1508 = LGDR { 1507, 2, 1, 4, 58, 0, 0, SystemZImpOpBase + 0, 563, 0, 0x0ULL }, // Inst #1507 = LGBR { 1506, 4, 1, 6, 64, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x2cULL }, // Inst #1506 = LGB { 1505, 4, 1, 6, 43, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x10cULL }, // Inst #1505 = LGAT { 1504, 4, 1, 6, 35, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x10dULL }, // Inst #1504 = LG { 1503, 2, 0, 4, 410, 0, 1, SystemZImpOpBase + 12, 675, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1503 = LFPC { 1502, 4, 1, 6, 43, 0, 0, SystemZImpOpBase + 0, 757, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x8cULL }, // Inst #1502 = LFHAT { 1501, 4, 1, 6, 33, 0, 0, SystemZImpOpBase + 0, 757, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x8dULL }, // Inst #1501 = LFH { 1500, 2, 0, 4, 412, 0, 1, SystemZImpOpBase + 12, 675, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1500 = LFAS { 1499, 4, 1, 6, 351, 0, 0, SystemZImpOpBase + 0, 655, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x8dULL }, // Inst #1499 = LEY { 1498, 2, 1, 4, 417, 0, 0, SystemZImpOpBase + 0, 1134, 0, 0x0ULL }, // Inst #1498 = LEXR { 1497, 4, 1, 4, 357, 1, 0, SystemZImpOpBase + 12, 963, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1497 = LEXBRA { 1496, 2, 1, 4, 357, 1, 0, SystemZImpOpBase + 12, 673, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1496 = LEXBR { 1495, 2, 1, 2, 344, 0, 0, SystemZImpOpBase + 0, 659, 0, 0x0ULL }, // Inst #1495 = LER { 1494, 4, 1, 4, 469, 1, 0, SystemZImpOpBase + 12, 1130, 0, 0x0ULL }, // Inst #1494 = LEDTR { 1493, 2, 1, 2, 416, 0, 0, SystemZImpOpBase + 0, 1128, 0, 0x0ULL }, // Inst #1493 = LEDR { 1492, 4, 1, 4, 356, 1, 0, SystemZImpOpBase + 12, 1130, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1492 = LEDBRA { 1491, 2, 1, 4, 356, 1, 0, SystemZImpOpBase + 12, 1128, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1491 = LEDBR { 1490, 4, 1, 4, 351, 0, 0, SystemZImpOpBase + 0, 655, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x89ULL }, // Inst #1490 = LE { 1489, 4, 1, 6, 352, 0, 0, SystemZImpOpBase + 0, 627, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x10dULL }, // Inst #1489 = LDY { 1488, 4, 1, 4, 470, 1, 0, SystemZImpOpBase + 12, 963, 0, 0x0ULL }, // Inst #1488 = LDXTR { 1487, 2, 1, 2, 418, 0, 0, SystemZImpOpBase + 0, 1126, 0, 0x0ULL }, // Inst #1487 = LDXR { 1486, 4, 1, 4, 357, 1, 0, SystemZImpOpBase + 12, 963, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1486 = LDXBRA { 1485, 2, 1, 4, 357, 1, 0, SystemZImpOpBase + 12, 673, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1485 = LDXBR { 1484, 2, 1, 2, 345, 0, 0, SystemZImpOpBase + 0, 659, 0, 0x0ULL }, // Inst #1484 = LDR32 { 1483, 2, 1, 2, 345, 0, 0, SystemZImpOpBase + 0, 631, 0, 0x0ULL }, // Inst #1483 = LDR { 1482, 2, 1, 4, 345, 0, 0, SystemZImpOpBase + 0, 639, 0|(1ULL<<MCID::Bitcast), 0x0ULL }, // Inst #1482 = LDGR { 1481, 3, 1, 4, 471, 1, 0, SystemZImpOpBase + 12, 1123, 0, 0x0ULL }, // Inst #1481 = LDETR { 1480, 2, 1, 4, 420, 0, 0, SystemZImpOpBase + 0, 1121, 0, 0x0ULL }, // Inst #1480 = LDER { 1479, 2, 1, 4, 359, 1, 0, SystemZImpOpBase + 12, 1121, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1479 = LDEBR { 1478, 4, 1, 6, 358, 1, 0, SystemZImpOpBase + 12, 627, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayRaiseFPException), 0x88ULL }, // Inst #1478 = LDEB { 1477, 4, 1, 6, 352, 0, 0, SystemZImpOpBase + 0, 655, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x89ULL }, // Inst #1477 = LDE32 { 1476, 4, 1, 6, 419, 0, 0, SystemZImpOpBase + 0, 627, 0|(1ULL<<MCID::MayLoad), 0x88ULL }, // Inst #1476 = LDE { 1475, 4, 1, 4, 352, 0, 0, SystemZImpOpBase + 0, 627, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x109ULL }, // Inst #1475 = LD { 1474, 2, 1, 4, 430, 0, 1, SystemZImpOpBase + 0, 673, 0, 0x0ULL }, // Inst #1474 = LCXR { 1473, 2, 1, 4, 374, 0, 1, SystemZImpOpBase + 0, 673, 0, 0x3fc00ULL }, // Inst #1473 = LCXBR { 1472, 4, 2, 6, 781, 0, 0, SystemZImpOpBase + 0, 1117, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1472 = LCTLG { 1471, 4, 2, 4, 781, 0, 0, SystemZImpOpBase + 0, 1117, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1471 = LCTL { 1470, 2, 1, 2, 91, 0, 1, SystemZImpOpBase + 0, 815, 0, 0x23c00ULL }, // Inst #1470 = LCR { 1469, 2, 1, 4, 91, 0, 1, SystemZImpOpBase + 0, 563, 0, 0x23c00ULL }, // Inst #1469 = LCGR { 1468, 2, 1, 4, 92, 0, 1, SystemZImpOpBase + 0, 714, 0, 0x3b800ULL }, // Inst #1468 = LCGFR { 1467, 2, 1, 2, 429, 0, 1, SystemZImpOpBase + 0, 659, 0, 0x0ULL }, // Inst #1467 = LCER { 1466, 2, 1, 4, 372, 0, 1, SystemZImpOpBase + 0, 659, 0, 0x3fc00ULL }, // Inst #1466 = LCEBR { 1465, 2, 1, 2, 429, 0, 1, SystemZImpOpBase + 0, 631, 0, 0x0ULL }, // Inst #1465 = LCDR { 1464, 2, 1, 4, 373, 0, 0, SystemZImpOpBase + 0, 659, 0, 0x0ULL }, // Inst #1464 = LCDFR_32 { 1463, 2, 1, 4, 373, 0, 0, SystemZImpOpBase + 0, 631, 0, 0x0ULL }, // Inst #1463 = LCDFR { 1462, 2, 1, 4, 372, 0, 1, SystemZImpOpBase + 0, 631, 0, 0x3fc00ULL }, // Inst #1462 = LCDBR { 1461, 2, 0, 4, 851, 0, 1, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1461 = LCCTL { 1460, 5, 1, 6, 34, 0, 1, SystemZImpOpBase + 0, 1112, 0, 0x8ULL }, // Inst #1460 = LCBB { 1459, 2, 1, 4, 57, 0, 0, SystemZImpOpBase + 0, 815, 0, 0x0ULL }, // Inst #1459 = LBR { 1458, 4, 1, 6, 61, 0, 0, SystemZImpOpBase + 0, 757, 0|(1ULL<<MCID::MayLoad), 0x2cULL }, // Inst #1458 = LBH { 1457, 2, 0, 4, 787, 0, 0, SystemZImpOpBase + 0, 675, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1457 = LBEAR { 1456, 4, 1, 6, 61, 0, 0, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::MayLoad), 0x2cULL }, // Inst #1456 = LB { 1455, 4, 1, 6, 86, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0xcULL }, // Inst #1455 = LAY { 1454, 4, 1, 6, 273, 0, 1, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #1454 = LAXG { 1453, 4, 1, 6, 273, 0, 1, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #1453 = LAX { 1452, 4, 1, 6, 43, 0, 0, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x8cULL }, // Inst #1452 = LAT { 1451, 4, 0, 6, 814, 0, 1, SystemZImpOpBase + 0, 1108, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1451 = LASP { 1450, 2, 1, 6, 86, 0, 0, SystemZImpOpBase + 0, 716, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1450 = LARL { 1449, 4, 1, 6, 272, 0, 1, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #1449 = LAOG { 1448, 4, 1, 6, 272, 0, 1, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #1448 = LAO { 1447, 4, 1, 6, 271, 0, 1, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #1447 = LANG { 1446, 4, 1, 6, 271, 0, 1, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #1446 = LAN { 1445, 4, 2, 6, 314, 0, 0, SystemZImpOpBase + 0, 1104, 0|(1ULL<<MCID::MayLoad), 0x4ULL }, // Inst #1445 = LAMY { 1444, 4, 2, 4, 314, 0, 0, SystemZImpOpBase + 0, 1104, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1444 = LAM { 1443, 4, 1, 6, 313, 0, 0, SystemZImpOpBase + 0, 161, 0, 0xcULL }, // Inst #1443 = LAEY { 1442, 4, 1, 4, 313, 0, 0, SystemZImpOpBase + 0, 161, 0, 0x8ULL }, // Inst #1442 = LAE { 1441, 4, 1, 6, 270, 0, 1, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #1441 = LAALG { 1440, 4, 1, 6, 270, 0, 1, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #1440 = LAAL { 1439, 4, 1, 6, 269, 0, 1, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #1439 = LAAG { 1438, 4, 1, 6, 269, 0, 1, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #1438 = LAA { 1437, 4, 1, 4, 86, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x8ULL }, // Inst #1437 = LA { 1436, 4, 1, 4, 33, 0, 0, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x89ULL }, // Inst #1436 = L { 1435, 2, 0, 4, 521, 1, 1, SystemZImpOpBase + 1, 673, 0|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #1435 = KXTR { 1434, 2, 0, 4, 404, 1, 1, SystemZImpOpBase + 1, 673, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x3c00ULL }, // Inst #1434 = KXBR { 1433, 4, 2, 4, 871, 2, 1, SystemZImpOpBase + 43, 794, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1433 = KMO { 1432, 4, 2, 4, 871, 2, 1, SystemZImpOpBase + 43, 794, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1432 = KMF { 1431, 6, 3, 4, 871, 2, 1, SystemZImpOpBase + 43, 1098, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1431 = KMCTR { 1430, 4, 2, 4, 871, 2, 1, SystemZImpOpBase + 43, 794, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1430 = KMC { 1429, 3, 1, 4, 864, 2, 1, SystemZImpOpBase + 43, 1095, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1429 = KMAC { 1428, 6, 3, 4, 291, 2, 1, SystemZImpOpBase + 43, 1098, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1428 = KMA { 1427, 4, 2, 4, 871, 2, 1, SystemZImpOpBase + 43, 794, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1427 = KM { 1426, 3, 1, 4, 864, 2, 1, SystemZImpOpBase + 43, 1095, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1426 = KLMD { 1425, 3, 1, 4, 864, 2, 1, SystemZImpOpBase + 43, 1095, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1425 = KIMD { 1424, 2, 0, 4, 403, 1, 1, SystemZImpOpBase + 1, 659, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x3c00ULL }, // Inst #1424 = KEBR { 1423, 4, 0, 6, 402, 1, 1, SystemZImpOpBase + 1, 655, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayRaiseFPException), 0x3c88ULL }, // Inst #1423 = KEB { 1422, 2, 0, 4, 520, 1, 1, SystemZImpOpBase + 1, 631, 0|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #1422 = KDTR { 1421, 3, 1, 4, 292, 2, 1, SystemZImpOpBase + 43, 1095, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1421 = KDSA { 1420, 2, 0, 4, 403, 1, 1, SystemZImpOpBase + 1, 631, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x3c00ULL }, // Inst #1420 = KDBR { 1419, 4, 0, 6, 402, 1, 1, SystemZImpOpBase + 1, 627, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayRaiseFPException), 0x3d08ULL }, // Inst #1419 = KDB { 1418, 1, 0, 6, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1418 = JGAsmZ { 1417, 1, 0, 6, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1417 = JGAsmP { 1416, 1, 0, 6, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1416 = JGAsmO { 1415, 1, 0, 6, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1415 = JGAsmNZ { 1414, 1, 0, 6, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1414 = JGAsmNP { 1413, 1, 0, 6, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1413 = JGAsmNO { 1412, 1, 0, 6, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1412 = JGAsmNM { 1411, 1, 0, 6, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1411 = JGAsmNLH { 1410, 1, 0, 6, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1410 = JGAsmNLE { 1409, 1, 0, 6, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1409 = JGAsmNL { 1408, 1, 0, 6, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1408 = JGAsmNHE { 1407, 1, 0, 6, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1407 = JGAsmNH { 1406, 1, 0, 6, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1406 = JGAsmNE { 1405, 1, 0, 6, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1405 = JGAsmM { 1404, 1, 0, 6, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1404 = JGAsmLH { 1403, 1, 0, 6, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1403 = JGAsmLE { 1402, 1, 0, 6, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1402 = JGAsmL { 1401, 1, 0, 6, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1401 = JGAsmHE { 1400, 1, 0, 6, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1400 = JGAsmH { 1399, 1, 0, 6, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1399 = JGAsmE { 1398, 1, 0, 6, 3, 0, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1398 = JG { 1397, 1, 0, 4, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1397 = JAsmZ { 1396, 1, 0, 4, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1396 = JAsmP { 1395, 1, 0, 4, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1395 = JAsmO { 1394, 1, 0, 4, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1394 = JAsmNZ { 1393, 1, 0, 4, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1393 = JAsmNP { 1392, 1, 0, 4, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1392 = JAsmNO { 1391, 1, 0, 4, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1391 = JAsmNM { 1390, 1, 0, 4, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1390 = JAsmNLH { 1389, 1, 0, 4, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1389 = JAsmNLE { 1388, 1, 0, 4, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1388 = JAsmNL { 1387, 1, 0, 4, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1387 = JAsmNHE { 1386, 1, 0, 4, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1386 = JAsmNH { 1385, 1, 0, 4, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1385 = JAsmNE { 1384, 1, 0, 4, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1384 = JAsmM { 1383, 1, 0, 4, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1383 = JAsmLH { 1382, 1, 0, 4, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1382 = JAsmLE { 1381, 1, 0, 4, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1381 = JAsmL { 1380, 1, 0, 4, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1380 = JAsmHE { 1379, 1, 0, 4, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1379 = JAsmH { 1378, 1, 0, 4, 3, 1, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1378 = JAsmE { 1377, 1, 0, 4, 3, 0, 0, SystemZImpOpBase + 0, 262, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1377 = J { 1376, 5, 0, 6, 341, 0, 0, SystemZImpOpBase + 0, 1090, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1376 = InsnVSI { 1375, 6, 0, 6, 341, 0, 0, SystemZImpOpBase + 0, 1084, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1375 = InsnVRX { 1374, 6, 0, 6, 341, 0, 0, SystemZImpOpBase + 0, 1078, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1374 = InsnVRV { 1373, 6, 0, 6, 341, 0, 0, SystemZImpOpBase + 0, 1072, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1373 = InsnVRS { 1372, 7, 0, 6, 341, 0, 0, SystemZImpOpBase + 0, 1065, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1372 = InsnVRR { 1371, 6, 0, 6, 341, 0, 0, SystemZImpOpBase + 0, 1059, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1371 = InsnVRI { 1370, 6, 0, 6, 341, 0, 0, SystemZImpOpBase + 0, 1053, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1370 = InsnSSF { 1369, 5, 0, 6, 341, 0, 0, SystemZImpOpBase + 0, 1048, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1369 = InsnSSE { 1368, 7, 0, 6, 341, 0, 0, SystemZImpOpBase + 0, 1041, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1368 = InsnSS { 1367, 4, 0, 6, 341, 0, 0, SystemZImpOpBase + 0, 1037, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1367 = InsnSIY { 1366, 4, 0, 6, 341, 0, 0, SystemZImpOpBase + 0, 1037, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1366 = InsnSIL { 1365, 4, 0, 4, 341, 0, 0, SystemZImpOpBase + 0, 1037, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1365 = InsnSI { 1364, 3, 0, 4, 341, 0, 0, SystemZImpOpBase + 0, 1034, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1364 = InsnS { 1363, 5, 0, 6, 341, 0, 0, SystemZImpOpBase + 0, 1023, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xcULL }, // Inst #1363 = InsnRXY { 1362, 6, 0, 6, 341, 0, 0, SystemZImpOpBase + 0, 1028, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL }, // Inst #1362 = InsnRXF { 1361, 5, 0, 6, 341, 0, 0, SystemZImpOpBase + 0, 1023, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL }, // Inst #1361 = InsnRXE { 1360, 5, 0, 4, 341, 0, 0, SystemZImpOpBase + 0, 1023, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL }, // Inst #1360 = InsnRX { 1359, 5, 0, 6, 341, 0, 0, SystemZImpOpBase + 0, 1018, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1359 = InsnRSY { 1358, 4, 0, 4, 341, 0, 0, SystemZImpOpBase + 0, 991, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1358 = InsnRSI { 1357, 5, 0, 6, 341, 0, 0, SystemZImpOpBase + 0, 1018, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1357 = InsnRSE { 1356, 5, 0, 4, 341, 0, 0, SystemZImpOpBase + 0, 1018, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1356 = InsnRS { 1355, 6, 0, 6, 341, 0, 0, SystemZImpOpBase + 0, 1012, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1355 = InsnRRS { 1354, 5, 0, 4, 341, 0, 0, SystemZImpOpBase + 0, 1007, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1354 = InsnRRF { 1353, 3, 0, 4, 341, 0, 0, SystemZImpOpBase + 0, 1004, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1353 = InsnRRE { 1352, 3, 0, 2, 341, 0, 0, SystemZImpOpBase + 0, 1004, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1352 = InsnRR { 1351, 6, 0, 6, 341, 0, 0, SystemZImpOpBase + 0, 998, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1351 = InsnRIS { 1350, 3, 0, 6, 341, 0, 0, SystemZImpOpBase + 0, 988, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1350 = InsnRILU { 1349, 3, 0, 6, 341, 0, 0, SystemZImpOpBase + 0, 995, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1349 = InsnRIL { 1348, 4, 0, 6, 341, 0, 0, SystemZImpOpBase + 0, 991, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1348 = InsnRIE { 1347, 3, 0, 4, 341, 0, 0, SystemZImpOpBase + 0, 988, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1347 = InsnRI { 1346, 1, 0, 2, 341, 0, 0, SystemZImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1346 = InsnE { 1345, 3, 1, 4, 790, 0, 0, SystemZImpOpBase + 0, 581, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1345 = IVSK { 1344, 3, 1, 4, 789, 0, 0, SystemZImpOpBase + 0, 581, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1344 = ISKE { 1343, 2, 1, 4, 793, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1343 = IRBM { 1342, 2, 0, 4, 798, 0, 0, SystemZImpOpBase + 0, 714, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1342 = IPTEOptOpt { 1341, 3, 0, 4, 798, 0, 0, SystemZImpOpBase + 0, 985, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1341 = IPTEOpt { 1340, 4, 0, 4, 798, 0, 0, SystemZImpOpBase + 0, 981, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1340 = IPTE { 1339, 1, 1, 4, 316, 1, 0, SystemZImpOpBase + 0, 935, 0, 0x0ULL }, // Inst #1339 = IPM { 1338, 0, 0, 4, 775, 1, 1, SystemZImpOpBase + 51, 1, 0, 0x0ULL }, // Inst #1338 = IPK { 1337, 3, 1, 4, 102, 0, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1337 = IILL { 1336, 3, 1, 4, 101, 0, 0, SystemZImpOpBase + 0, 515, 0, 0x0ULL }, // Inst #1336 = IILH { 1335, 2, 1, 6, 100, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1335 = IILF { 1334, 3, 1, 4, 99, 0, 0, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1334 = IIHL { 1333, 3, 1, 4, 98, 0, 0, SystemZImpOpBase + 0, 535, 0, 0x0ULL }, // Inst #1333 = IIHH { 1332, 2, 1, 6, 97, 0, 0, SystemZImpOpBase + 0, 776, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1332 = IIHF { 1331, 3, 1, 4, 519, 0, 0, SystemZImpOpBase + 0, 553, 0, 0x0ULL }, // Inst #1331 = IEXTR { 1330, 3, 1, 4, 518, 0, 0, SystemZImpOpBase + 0, 500, 0, 0x0ULL }, // Inst #1330 = IEDTR { 1329, 3, 0, 4, 799, 0, 0, SystemZImpOpBase + 0, 382, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1329 = IDTEOpt { 1328, 4, 0, 4, 799, 0, 0, SystemZImpOpBase + 0, 977, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1328 = IDTE { 1327, 5, 1, 6, 93, 0, 0, SystemZImpOpBase + 0, 518, 0|(1ULL<<MCID::MayLoad), 0x2cULL }, // Inst #1327 = ICY { 1326, 5, 1, 6, 95, 0, 1, SystemZImpOpBase + 0, 967, 0|(1ULL<<MCID::MayLoad), 0x4ULL }, // Inst #1326 = ICMY { 1325, 5, 1, 6, 95, 0, 1, SystemZImpOpBase + 0, 972, 0|(1ULL<<MCID::MayLoad), 0x4ULL }, // Inst #1325 = ICMH { 1324, 5, 1, 4, 95, 0, 1, SystemZImpOpBase + 0, 967, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1324 = ICM { 1323, 5, 1, 6, 94, 0, 0, SystemZImpOpBase + 0, 487, 0|(1ULL<<MCID::MayLoad), 0x2cULL }, // Inst #1323 = IC32Y { 1322, 5, 1, 4, 94, 0, 0, SystemZImpOpBase + 0, 487, 0|(1ULL<<MCID::MayLoad), 0x28ULL }, // Inst #1322 = IC32 { 1321, 5, 1, 4, 93, 0, 0, SystemZImpOpBase + 0, 518, 0|(1ULL<<MCID::MayLoad), 0x28ULL }, // Inst #1321 = IC { 1320, 1, 1, 4, 779, 0, 0, SystemZImpOpBase + 0, 935, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1320 = IAC { 1319, 0, 0, 4, 855, 1, 1, SystemZImpOpBase + 41, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1319 = HSCH { 1318, 2, 1, 2, 431, 0, 0, SystemZImpOpBase + 0, 659, 0, 0x0ULL }, // Inst #1318 = HER { 1317, 2, 1, 2, 431, 0, 0, SystemZImpOpBase + 0, 631, 0, 0x0ULL }, // Inst #1317 = HDR { 1316, 2, 1, 4, 329, 0, 1, SystemZImpOpBase + 0, 170, 0, 0x0ULL }, // Inst #1316 = FLOGR { 1315, 4, 1, 4, 499, 1, 0, SystemZImpOpBase + 12, 963, 0, 0x0ULL }, // Inst #1315 = FIXTR { 1314, 2, 1, 4, 437, 0, 0, SystemZImpOpBase + 0, 673, 0, 0x0ULL }, // Inst #1314 = FIXR { 1313, 4, 1, 4, 380, 1, 0, SystemZImpOpBase + 12, 963, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1313 = FIXBRA { 1312, 3, 1, 4, 380, 1, 0, SystemZImpOpBase + 12, 960, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1312 = FIXBR { 1311, 2, 1, 4, 436, 0, 0, SystemZImpOpBase + 0, 659, 0, 0x0ULL }, // Inst #1311 = FIER { 1310, 4, 1, 4, 379, 1, 0, SystemZImpOpBase + 12, 956, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1310 = FIEBRA { 1309, 3, 1, 4, 379, 1, 0, SystemZImpOpBase + 12, 953, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1309 = FIEBR { 1308, 4, 1, 4, 498, 1, 0, SystemZImpOpBase + 12, 949, 0, 0x0ULL }, // Inst #1308 = FIDTR { 1307, 2, 1, 4, 436, 0, 0, SystemZImpOpBase + 0, 631, 0, 0x0ULL }, // Inst #1307 = FIDR { 1306, 4, 1, 4, 379, 1, 0, SystemZImpOpBase + 12, 949, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1306 = FIDBRA { 1305, 3, 1, 4, 379, 1, 0, SystemZImpOpBase + 12, 946, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1305 = FIDBR { 1304, 2, 0, 6, 340, 0, 0, SystemZImpOpBase + 0, 944, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1304 = EXRL { 1303, 4, 0, 4, 340, 0, 0, SystemZImpOpBase + 0, 940, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL }, // Inst #1303 = EX { 1302, 1, 1, 4, 326, 0, 0, SystemZImpOpBase + 0, 935, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1302 = ETND { 1301, 2, 1, 4, 503, 0, 0, SystemZImpOpBase + 0, 673, 0, 0x0ULL }, // Inst #1301 = ESXTR { 1300, 2, 1, 4, 824, 0, 1, SystemZImpOpBase + 0, 938, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1300 = ESTA { 1299, 2, 1, 4, 785, 0, 0, SystemZImpOpBase + 0, 936, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1299 = ESEA { 1298, 2, 1, 4, 502, 0, 0, SystemZImpOpBase + 0, 631, 0, 0x0ULL }, // Inst #1298 = ESDTR { 1297, 1, 1, 4, 783, 0, 0, SystemZImpOpBase + 0, 935, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1297 = ESAR { 1296, 1, 1, 4, 783, 0, 0, SystemZImpOpBase + 0, 302, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1296 = ESAIR { 1295, 2, 0, 4, 823, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1295 = EREGG { 1294, 2, 0, 4, 823, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1294 = EREG { 1293, 2, 2, 4, 773, 1, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1293 = EPSW { 1292, 2, 1, 4, 850, 0, 1, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1292 = EPCTR { 1291, 1, 1, 4, 783, 0, 0, SystemZImpOpBase + 0, 935, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1291 = EPAR { 1290, 1, 1, 4, 783, 0, 0, SystemZImpOpBase + 0, 302, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1290 = EPAIR { 1289, 1, 1, 4, 407, 1, 0, SystemZImpOpBase + 12, 935, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1289 = EFPC { 1288, 2, 1, 4, 501, 0, 0, SystemZImpOpBase + 0, 673, 0, 0x0ULL }, // Inst #1288 = EEXTR { 1287, 2, 1, 4, 500, 0, 0, SystemZImpOpBase + 0, 631, 0, 0x0ULL }, // Inst #1287 = EEDTR { 1286, 5, 0, 6, 311, 0, 1, SystemZImpOpBase + 0, 789, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1286 = EDMK { 1285, 5, 0, 6, 311, 0, 1, SystemZImpOpBase + 0, 789, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1285 = ED { 1284, 5, 0, 6, 837, 0, 2, SystemZImpOpBase + 49, 873, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1284 = ECTG { 1283, 2, 1, 4, 849, 0, 1, SystemZImpOpBase + 0, 933, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1283 = ECPGA { 1282, 2, 1, 4, 850, 0, 1, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1282 = ECCTR { 1281, 4, 1, 6, 836, 0, 0, SystemZImpOpBase + 0, 929, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1281 = ECAG { 1280, 2, 1, 4, 312, 0, 0, SystemZImpOpBase + 0, 927, 0, 0x0ULL }, // Inst #1280 = EAR { 1279, 4, 1, 4, 511, 1, 0, SystemZImpOpBase + 12, 556, 0, 0x0ULL }, // Inst #1279 = DXTRA { 1278, 3, 1, 4, 511, 1, 0, SystemZImpOpBase + 12, 553, 0, 0x0ULL }, // Inst #1278 = DXTR { 1277, 3, 1, 4, 463, 0, 0, SystemZImpOpBase + 0, 550, 0, 0x0ULL }, // Inst #1277 = DXR { 1276, 3, 1, 4, 400, 1, 0, SystemZImpOpBase + 12, 550, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1276 = DXBR { 1275, 3, 1, 4, 203, 0, 0, SystemZImpOpBase + 0, 870, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1275 = DSGR { 1274, 3, 1, 4, 203, 0, 0, SystemZImpOpBase + 0, 924, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1274 = DSGFR { 1273, 5, 1, 6, 204, 0, 0, SystemZImpOpBase + 0, 904, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x8cULL }, // Inst #1273 = DSGF { 1272, 5, 1, 6, 204, 0, 0, SystemZImpOpBase + 0, 904, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x10cULL }, // Inst #1272 = DSG { 1271, 3, 1, 2, 201, 0, 0, SystemZImpOpBase + 0, 924, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1271 = DR { 1270, 6, 0, 6, 307, 0, 0, SystemZImpOpBase + 0, 544, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1270 = DP { 1269, 3, 1, 4, 205, 0, 0, SystemZImpOpBase + 0, 924, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1269 = DLR { 1268, 3, 1, 4, 206, 0, 0, SystemZImpOpBase + 0, 870, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1268 = DLGR { 1267, 5, 1, 6, 207, 0, 0, SystemZImpOpBase + 0, 904, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x10cULL }, // Inst #1267 = DLG { 1266, 5, 1, 6, 207, 0, 0, SystemZImpOpBase + 0, 904, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x8cULL }, // Inst #1266 = DL { 1265, 5, 2, 4, 401, 1, 1, SystemZImpOpBase + 1, 919, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1265 = DIEBR { 1264, 5, 2, 4, 401, 1, 1, SystemZImpOpBase + 1, 914, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1264 = DIDBR { 1263, 4, 0, 4, 843, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1263 = DIAG { 1262, 5, 2, 4, 338, 2, 1, SystemZImpOpBase + 43, 909, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1262 = DFLTCC { 1261, 3, 1, 2, 461, 0, 0, SystemZImpOpBase + 0, 512, 0, 0x0ULL }, // Inst #1261 = DER { 1260, 3, 1, 4, 398, 1, 0, SystemZImpOpBase + 12, 512, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1260 = DEBR { 1259, 5, 1, 6, 396, 1, 0, SystemZImpOpBase + 12, 507, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayRaiseFPException), 0x88ULL }, // Inst #1259 = DEB { 1258, 5, 1, 4, 459, 0, 0, SystemZImpOpBase + 0, 507, 0|(1ULL<<MCID::MayLoad), 0x88ULL }, // Inst #1258 = DE { 1257, 4, 1, 4, 510, 1, 0, SystemZImpOpBase + 12, 503, 0, 0x0ULL }, // Inst #1257 = DDTRA { 1256, 3, 1, 4, 510, 1, 0, SystemZImpOpBase + 12, 500, 0, 0x0ULL }, // Inst #1256 = DDTR { 1255, 3, 1, 2, 462, 0, 0, SystemZImpOpBase + 0, 497, 0, 0x0ULL }, // Inst #1255 = DDR { 1254, 3, 1, 4, 399, 1, 0, SystemZImpOpBase + 12, 497, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1254 = DDBR { 1253, 5, 1, 6, 397, 1, 0, SystemZImpOpBase + 12, 492, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayRaiseFPException), 0x108ULL }, // Inst #1253 = DDB { 1252, 5, 1, 4, 460, 0, 0, SystemZImpOpBase + 0, 492, 0|(1ULL<<MCID::MayLoad), 0x108ULL }, // Inst #1252 = DD { 1251, 5, 1, 4, 202, 0, 0, SystemZImpOpBase + 0, 904, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x88ULL }, // Inst #1251 = D { 1250, 5, 0, 6, 492, 0, 0, SystemZImpOpBase + 0, 853, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1250 = CZXT { 1249, 5, 0, 6, 491, 0, 0, SystemZImpOpBase + 0, 645, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1249 = CZDT { 1248, 4, 0, 6, 219, 0, 1, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x388cULL }, // Inst #1248 = CY { 1247, 5, 1, 6, 490, 0, 0, SystemZImpOpBase + 0, 853, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1247 = CXZT { 1246, 2, 1, 4, 486, 0, 0, SystemZImpOpBase + 0, 902, 0, 0x0ULL }, // Inst #1246 = CXUTR { 1245, 2, 0, 4, 521, 1, 1, SystemZImpOpBase + 1, 673, 0|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #1245 = CXTR { 1244, 2, 1, 4, 486, 0, 0, SystemZImpOpBase + 0, 902, 0, 0x0ULL }, // Inst #1244 = CXSTR { 1243, 2, 0, 4, 466, 0, 1, SystemZImpOpBase + 0, 673, 0|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #1243 = CXR { 1242, 5, 1, 6, 494, 0, 0, SystemZImpOpBase + 0, 853, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1242 = CXPT { 1241, 4, 1, 4, 480, 1, 0, SystemZImpOpBase + 12, 898, 0, 0x0ULL }, // Inst #1241 = CXLGTR { 1240, 4, 1, 4, 365, 1, 0, SystemZImpOpBase + 12, 898, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1240 = CXLGBR { 1239, 4, 1, 4, 479, 1, 0, SystemZImpOpBase + 12, 892, 0, 0x0ULL }, // Inst #1239 = CXLFTR { 1238, 4, 1, 4, 365, 1, 0, SystemZImpOpBase + 12, 892, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1238 = CXLFBR { 1237, 4, 1, 4, 476, 1, 0, SystemZImpOpBase + 12, 898, 0, 0x0ULL }, // Inst #1237 = CXGTRA { 1236, 2, 1, 4, 476, 1, 0, SystemZImpOpBase + 12, 896, 0, 0x0ULL }, // Inst #1236 = CXGTR { 1235, 2, 1, 4, 424, 0, 0, SystemZImpOpBase + 0, 896, 0, 0x0ULL }, // Inst #1235 = CXGR { 1234, 4, 1, 4, 363, 1, 0, SystemZImpOpBase + 12, 898, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1234 = CXGBRA { 1233, 2, 1, 4, 363, 1, 0, SystemZImpOpBase + 12, 896, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1233 = CXGBR { 1232, 4, 1, 4, 475, 1, 0, SystemZImpOpBase + 12, 892, 0, 0x0ULL }, // Inst #1232 = CXFTR { 1231, 2, 1, 4, 424, 0, 0, SystemZImpOpBase + 0, 890, 0, 0x0ULL }, // Inst #1231 = CXFR { 1230, 4, 1, 4, 363, 1, 0, SystemZImpOpBase + 12, 892, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1230 = CXFBRA { 1229, 2, 1, 4, 363, 1, 0, SystemZImpOpBase + 12, 890, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1229 = CXFBR { 1228, 2, 0, 4, 404, 1, 1, SystemZImpOpBase + 1, 673, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x3c00ULL }, // Inst #1228 = CXBR { 1227, 4, 0, 6, 300, 0, 0, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::MayStore), 0x8cULL }, // Inst #1227 = CVDY { 1226, 4, 0, 6, 299, 0, 0, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x10cULL }, // Inst #1226 = CVDG { 1225, 4, 0, 4, 300, 0, 0, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::MayStore), 0x88ULL }, // Inst #1225 = CVD { 1224, 5, 1, 6, 298, 0, 0, SystemZImpOpBase + 0, 487, 0|(1ULL<<MCID::MayLoad), 0x8cULL }, // Inst #1224 = CVBY { 1223, 5, 1, 6, 297, 0, 0, SystemZImpOpBase + 0, 518, 0|(1ULL<<MCID::MayLoad), 0x10cULL }, // Inst #1223 = CVBG { 1222, 5, 1, 4, 298, 0, 0, SystemZImpOpBase + 0, 487, 0|(1ULL<<MCID::MayLoad), 0x88ULL }, // Inst #1222 = CVB { 1221, 2, 1, 4, 488, 0, 0, SystemZImpOpBase + 0, 888, 0, 0x0ULL }, // Inst #1221 = CUXTR { 1220, 4, 2, 4, 290, 0, 1, SystemZImpOpBase + 0, 794, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1220 = CUUTFOpt { 1219, 5, 2, 4, 290, 0, 1, SystemZImpOpBase + 0, 881, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1219 = CUUTF { 1218, 4, 2, 4, 290, 0, 1, SystemZImpOpBase + 0, 794, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1218 = CUTFUOpt { 1217, 5, 2, 4, 290, 0, 1, SystemZImpOpBase + 0, 881, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1217 = CUTFU { 1216, 4, 2, 4, 332, 2, 1, SystemZImpOpBase + 46, 794, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1216 = CUSE { 1215, 2, 1, 4, 487, 0, 0, SystemZImpOpBase + 0, 886, 0, 0x0ULL }, // Inst #1215 = CUDTR { 1214, 4, 2, 4, 289, 0, 1, SystemZImpOpBase + 0, 794, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1214 = CU42 { 1213, 4, 2, 4, 289, 0, 1, SystemZImpOpBase + 0, 794, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1213 = CU41 { 1212, 4, 2, 4, 289, 0, 1, SystemZImpOpBase + 0, 794, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1212 = CU24Opt { 1211, 5, 2, 4, 289, 0, 1, SystemZImpOpBase + 0, 881, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1211 = CU24 { 1210, 4, 2, 4, 289, 0, 1, SystemZImpOpBase + 0, 794, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1210 = CU21Opt { 1209, 5, 2, 4, 289, 0, 1, SystemZImpOpBase + 0, 881, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1209 = CU21 { 1208, 4, 2, 4, 289, 0, 1, SystemZImpOpBase + 0, 794, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1208 = CU14Opt { 1207, 5, 2, 4, 289, 0, 1, SystemZImpOpBase + 0, 881, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1207 = CU14 { 1206, 4, 2, 4, 289, 0, 1, SystemZImpOpBase + 0, 794, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1206 = CU12Opt { 1205, 5, 2, 4, 289, 0, 1, SystemZImpOpBase + 0, 881, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1205 = CU12 { 1204, 5, 1, 6, 275, 0, 1, SystemZImpOpBase + 0, 613, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #1204 = CSY { 1203, 3, 1, 4, 488, 0, 0, SystemZImpOpBase + 0, 878, 0, 0x0ULL }, // Inst #1203 = CSXTR { 1202, 5, 0, 6, 278, 2, 1, SystemZImpOpBase + 43, 873, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1202 = CSST { 1201, 3, 1, 4, 803, 0, 1, SystemZImpOpBase + 0, 870, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1201 = CSPG { 1200, 3, 1, 4, 803, 0, 1, SystemZImpOpBase + 0, 870, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1200 = CSP { 1199, 5, 1, 6, 275, 0, 1, SystemZImpOpBase + 0, 618, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #1199 = CSG { 1198, 3, 1, 4, 487, 0, 0, SystemZImpOpBase + 0, 867, 0, 0x0ULL }, // Inst #1198 = CSDTR { 1197, 0, 0, 4, 855, 1, 1, SystemZImpOpBase + 41, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1197 = CSCH { 1196, 5, 1, 4, 275, 0, 1, SystemZImpOpBase + 0, 613, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1196 = CS { 1195, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1195 = CRTAsmNLH { 1194, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1194 = CRTAsmNLE { 1193, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1193 = CRTAsmNL { 1192, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1192 = CRTAsmNHE { 1191, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1191 = CRTAsmNH { 1190, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1190 = CRTAsmNE { 1189, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1189 = CRTAsmLH { 1188, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1188 = CRTAsmLE { 1187, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1187 = CRTAsmL { 1186, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1186 = CRTAsmHE { 1185, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1185 = CRTAsmH { 1184, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1184 = CRTAsmE { 1183, 3, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 251, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1183 = CRTAsm { 1182, 3, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 251, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1182 = CRT { 1181, 2, 0, 6, 220, 0, 1, SystemZImpOpBase + 0, 765, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL }, // Inst #1181 = CRL { 1180, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1180 = CRJAsmNLH { 1179, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1179 = CRJAsmNLE { 1178, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1178 = CRJAsmNL { 1177, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1177 = CRJAsmNHE { 1176, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1176 = CRJAsmNH { 1175, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1175 = CRJAsmNE { 1174, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1174 = CRJAsmLH { 1173, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1173 = CRJAsmLE { 1172, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1172 = CRJAsmL { 1171, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1171 = CRJAsmHE { 1170, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1170 = CRJAsmH { 1169, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1169 = CRJAsmE { 1168, 4, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 826, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1168 = CRJAsm { 1167, 4, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 826, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1167 = CRJ { 1166, 3, 0, 4, 801, 0, 1, SystemZImpOpBase + 0, 864, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1166 = CRDTEOpt { 1165, 4, 0, 4, 801, 0, 1, SystemZImpOpBase + 0, 860, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1165 = CRDTE { 1164, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1164 = CRBAsmNLH { 1163, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1163 = CRBAsmNLE { 1162, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1162 = CRBAsmNL { 1161, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1161 = CRBAsmNHE { 1160, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1160 = CRBAsmNH { 1159, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1159 = CRBAsmNE { 1158, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1158 = CRBAsmLH { 1157, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1157 = CRBAsmLE { 1156, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1156 = CRBAsmL { 1155, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1155 = CRBAsmHE { 1154, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1154 = CRBAsmH { 1153, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1153 = CRBAsmE { 1152, 5, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 817, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1152 = CRBAsm { 1151, 5, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 817, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1151 = CRB { 1150, 2, 0, 2, 224, 0, 1, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::Compare), 0x3800ULL }, // Inst #1150 = CR { 1149, 2, 1, 4, 312, 0, 0, SystemZImpOpBase + 0, 858, 0, 0x0ULL }, // Inst #1149 = CPYA { 1148, 5, 0, 6, 496, 0, 0, SystemZImpOpBase + 0, 853, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1148 = CPXT { 1147, 3, 1, 4, 350, 0, 0, SystemZImpOpBase + 0, 850, 0, 0x0ULL }, // Inst #1147 = CPSDRss { 1146, 3, 1, 4, 350, 0, 0, SystemZImpOpBase + 0, 847, 0, 0x0ULL }, // Inst #1146 = CPSDRsd { 1145, 3, 1, 4, 350, 0, 0, SystemZImpOpBase + 0, 844, 0, 0x0ULL }, // Inst #1145 = CPSDRds { 1144, 3, 1, 4, 350, 0, 0, SystemZImpOpBase + 0, 500, 0, 0x0ULL }, // Inst #1144 = CPSDRdd { 1143, 5, 0, 6, 495, 0, 0, SystemZImpOpBase + 0, 645, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1143 = CPDT { 1142, 6, 0, 6, 309, 0, 1, SystemZImpOpBase + 0, 544, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1142 = CP { 1141, 4, 2, 4, 336, 2, 2, SystemZImpOpBase + 37, 794, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1141 = CMPSC { 1140, 4, 0, 6, 228, 0, 1, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x10388cULL }, // Inst #1140 = CLY { 1139, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1139 = CLTAsmNLH { 1138, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1138 = CLTAsmNLE { 1137, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1137 = CLTAsmNL { 1136, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1136 = CLTAsmNHE { 1135, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1135 = CLTAsmNH { 1134, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1134 = CLTAsmNE { 1133, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1133 = CLTAsmLH { 1132, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1132 = CLTAsmLE { 1131, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1131 = CLTAsmL { 1130, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1130 = CLTAsmHE { 1129, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1129 = CLTAsmH { 1128, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 841, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1128 = CLTAsmE { 1127, 4, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 837, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1127 = CLTAsm { 1126, 4, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 837, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1126 = CLT { 1125, 4, 2, 4, 256, 1, 1, SystemZImpOpBase + 35, 833, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1125 = CLST { 1124, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1124 = CLRTAsmNLH { 1123, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1123 = CLRTAsmNLE { 1122, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1122 = CLRTAsmNL { 1121, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1121 = CLRTAsmNHE { 1120, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1120 = CLRTAsmNH { 1119, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1119 = CLRTAsmNE { 1118, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1118 = CLRTAsmLH { 1117, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1117 = CLRTAsmLE { 1116, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1116 = CLRTAsmL { 1115, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1115 = CLRTAsmHE { 1114, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1114 = CLRTAsmH { 1113, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1113 = CLRTAsmE { 1112, 3, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 251, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1112 = CLRTAsm { 1111, 3, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 251, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1111 = CLRT { 1110, 2, 0, 6, 243, 0, 1, SystemZImpOpBase + 0, 765, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103800ULL }, // Inst #1110 = CLRL { 1109, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1109 = CLRJAsmNLH { 1108, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1108 = CLRJAsmNLE { 1107, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1107 = CLRJAsmNL { 1106, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1106 = CLRJAsmNHE { 1105, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1105 = CLRJAsmNH { 1104, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1104 = CLRJAsmNE { 1103, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1103 = CLRJAsmLH { 1102, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1102 = CLRJAsmLE { 1101, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1101 = CLRJAsmL { 1100, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1100 = CLRJAsmHE { 1099, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1099 = CLRJAsmH { 1098, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 830, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1098 = CLRJAsmE { 1097, 4, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 826, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1097 = CLRJAsm { 1096, 4, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 826, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1096 = CLRJ { 1095, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1095 = CLRBAsmNLH { 1094, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1094 = CLRBAsmNLE { 1093, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1093 = CLRBAsmNL { 1092, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1092 = CLRBAsmNHE { 1091, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1091 = CLRBAsmNH { 1090, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1090 = CLRBAsmNE { 1089, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1089 = CLRBAsmLH { 1088, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1088 = CLRBAsmLE { 1087, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1087 = CLRBAsmL { 1086, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1086 = CLRBAsmHE { 1085, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1085 = CLRBAsmH { 1084, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 822, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1084 = CLRBAsmE { 1083, 5, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 817, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1083 = CLRBAsm { 1082, 5, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 817, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1082 = CLRB { 1081, 2, 0, 2, 242, 0, 1, SystemZImpOpBase + 0, 815, 0|(1ULL<<MCID::Compare), 0x103800ULL }, // Inst #1081 = CLR { 1080, 4, 0, 6, 263, 0, 1, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::MayLoad), 0x4ULL }, // Inst #1080 = CLMY { 1079, 4, 0, 6, 263, 0, 1, SystemZImpOpBase + 0, 811, 0|(1ULL<<MCID::MayLoad), 0x4ULL }, // Inst #1079 = CLMH { 1078, 4, 0, 4, 263, 0, 1, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1078 = CLM { 1077, 3, 0, 6, 241, 0, 1, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103804ULL }, // Inst #1077 = CLIY { 1076, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1076 = CLIJAsmNLH { 1075, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1075 = CLIJAsmNLE { 1074, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1074 = CLIJAsmNL { 1073, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1073 = CLIJAsmNHE { 1072, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1072 = CLIJAsmNH { 1071, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1071 = CLIJAsmNE { 1070, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1070 = CLIJAsmLH { 1069, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1069 = CLIJAsmLE { 1068, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1068 = CLIJAsmL { 1067, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1067 = CLIJAsmHE { 1066, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1066 = CLIJAsmH { 1065, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1065 = CLIJAsmE { 1064, 4, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 778, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1064 = CLIJAsm { 1063, 4, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 778, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1063 = CLIJ { 1062, 2, 0, 6, 240, 0, 1, SystemZImpOpBase + 0, 776, 0|(1ULL<<MCID::Compare), 0x103800ULL }, // Inst #1062 = CLIH { 1061, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1061 = CLIBAsmNLH { 1060, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1060 = CLIBAsmNLE { 1059, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1059 = CLIBAsmNL { 1058, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1058 = CLIBAsmNHE { 1057, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1057 = CLIBAsmNH { 1056, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1056 = CLIBAsmNE { 1055, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1055 = CLIBAsmLH { 1054, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1054 = CLIBAsmLE { 1053, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1053 = CLIBAsmL { 1052, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1052 = CLIBAsmHE { 1051, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1051 = CLIBAsmH { 1050, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1050 = CLIBAsmE { 1049, 5, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 767, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1049 = CLIBAsm { 1048, 5, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 767, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1048 = CLIB { 1047, 3, 0, 4, 241, 0, 1, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103800ULL }, // Inst #1047 = CLI { 1046, 2, 0, 6, 239, 0, 1, SystemZImpOpBase + 0, 765, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103800ULL }, // Inst #1046 = CLHRL { 1045, 2, 0, 4, 245, 0, 1, SystemZImpOpBase + 0, 763, 0|(1ULL<<MCID::Compare), 0x103800ULL }, // Inst #1045 = CLHLR { 1044, 3, 0, 6, 239, 0, 1, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103800ULL }, // Inst #1044 = CLHHSI { 1043, 2, 0, 4, 244, 0, 1, SystemZImpOpBase + 0, 761, 0|(1ULL<<MCID::Compare), 0x103800ULL }, // Inst #1043 = CLHHR { 1042, 4, 0, 6, 238, 0, 1, SystemZImpOpBase + 0, 757, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x10388cULL }, // Inst #1042 = CLHF { 1041, 4, 1, 4, 484, 1, 1, SystemZImpOpBase + 1, 753, 0, 0x0ULL }, // Inst #1041 = CLGXTR { 1040, 4, 1, 4, 371, 1, 1, SystemZImpOpBase + 1, 753, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #1040 = CLGXBR { 1039, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1039 = CLGTAsmNLH { 1038, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1038 = CLGTAsmNLE { 1037, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1037 = CLGTAsmNL { 1036, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1036 = CLGTAsmNHE { 1035, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1035 = CLGTAsmNH { 1034, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1034 = CLGTAsmNE { 1033, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1033 = CLGTAsmLH { 1032, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1032 = CLGTAsmLE { 1031, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1031 = CLGTAsmL { 1030, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1030 = CLGTAsmHE { 1029, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1029 = CLGTAsmH { 1028, 3, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 808, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1028 = CLGTAsmE { 1027, 4, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 804, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1027 = CLGTAsm { 1026, 4, 0, 6, 17, 0, 0, SystemZImpOpBase + 0, 804, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1026 = CLGT { 1025, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1025 = CLGRTAsmNLH { 1024, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1024 = CLGRTAsmNLE { 1023, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1023 = CLGRTAsmNL { 1022, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1022 = CLGRTAsmNHE { 1021, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1021 = CLGRTAsmNH { 1020, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1020 = CLGRTAsmNE { 1019, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1019 = CLGRTAsmLH { 1018, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1018 = CLGRTAsmLE { 1017, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1017 = CLGRTAsmL { 1016, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1016 = CLGRTAsmHE { 1015, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1015 = CLGRTAsmH { 1014, 2, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1014 = CLGRTAsmE { 1013, 3, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 223, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1013 = CLGRTAsm { 1012, 3, 0, 4, 15, 0, 0, SystemZImpOpBase + 0, 223, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1012 = CLGRT { 1011, 2, 0, 6, 237, 0, 1, SystemZImpOpBase + 0, 716, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103800ULL }, // Inst #1011 = CLGRL { 1010, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1010 = CLGRJAsmNLH { 1009, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1009 = CLGRJAsmNLE { 1008, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1008 = CLGRJAsmNL { 1007, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1007 = CLGRJAsmNHE { 1006, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1006 = CLGRJAsmNH { 1005, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1005 = CLGRJAsmNE { 1004, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1004 = CLGRJAsmLH { 1003, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1003 = CLGRJAsmLE { 1002, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1002 = CLGRJAsmL { 1001, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1001 = CLGRJAsmHE { 1000, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1000 = CLGRJAsmH { 999, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #999 = CLGRJAsmE { 998, 4, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 743, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #998 = CLGRJAsm { 997, 4, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 743, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #997 = CLGRJ { 996, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #996 = CLGRBAsmNLH { 995, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #995 = CLGRBAsmNLE { 994, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #994 = CLGRBAsmNL { 993, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #993 = CLGRBAsmNHE { 992, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #992 = CLGRBAsmNH { 991, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #991 = CLGRBAsmNE { 990, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #990 = CLGRBAsmLH { 989, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #989 = CLGRBAsmLE { 988, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #988 = CLGRBAsmL { 987, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #987 = CLGRBAsmHE { 986, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #986 = CLGRBAsmH { 985, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #985 = CLGRBAsmE { 984, 5, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 734, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #984 = CLGRBAsm { 983, 5, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 734, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #983 = CLGRB { 982, 2, 0, 4, 236, 0, 1, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::Compare), 0x103800ULL }, // Inst #982 = CLGR { 981, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #981 = CLGITAsmNLH { 980, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #980 = CLGITAsmNLE { 979, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #979 = CLGITAsmNL { 978, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #978 = CLGITAsmNHE { 977, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #977 = CLGITAsmNH { 976, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #976 = CLGITAsmNE { 975, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #975 = CLGITAsmLH { 974, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #974 = CLGITAsmLE { 973, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #973 = CLGITAsmL { 972, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #972 = CLGITAsmHE { 971, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #971 = CLGITAsmH { 970, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #970 = CLGITAsmE { 969, 3, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #969 = CLGITAsm { 968, 3, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #968 = CLGIT { 967, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #967 = CLGIJAsmNLH { 966, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #966 = CLGIJAsmNLE { 965, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #965 = CLGIJAsmNL { 964, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #964 = CLGIJAsmNHE { 963, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #963 = CLGIJAsmNH { 962, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #962 = CLGIJAsmNE { 961, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #961 = CLGIJAsmLH { 960, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #960 = CLGIJAsmLE { 959, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #959 = CLGIJAsmL { 958, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #958 = CLGIJAsmHE { 957, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #957 = CLGIJAsmH { 956, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #956 = CLGIJAsmE { 955, 4, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 727, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #955 = CLGIJAsm { 954, 4, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 727, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #954 = CLGIJ { 953, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #953 = CLGIBAsmNLH { 952, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #952 = CLGIBAsmNLE { 951, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #951 = CLGIBAsmNL { 950, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #950 = CLGIBAsmNHE { 949, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #949 = CLGIBAsmNH { 948, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #948 = CLGIBAsmNE { 947, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #947 = CLGIBAsmLH { 946, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #946 = CLGIBAsmLE { 945, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #945 = CLGIBAsmL { 944, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #944 = CLGIBAsmHE { 943, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #943 = CLGIBAsmH { 942, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #942 = CLGIBAsmE { 941, 5, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 718, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #941 = CLGIBAsm { 940, 5, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 718, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #940 = CLGIB { 939, 3, 0, 6, 232, 0, 1, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103800ULL }, // Inst #939 = CLGHSI { 938, 2, 0, 6, 232, 0, 1, SystemZImpOpBase + 0, 716, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103800ULL }, // Inst #938 = CLGHRL { 937, 2, 0, 6, 234, 0, 1, SystemZImpOpBase + 0, 716, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103800ULL }, // Inst #937 = CLGFRL { 936, 2, 0, 4, 235, 0, 1, SystemZImpOpBase + 0, 714, 0|(1ULL<<MCID::Compare), 0x103800ULL }, // Inst #936 = CLGFR { 935, 2, 0, 6, 235, 0, 1, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::Compare), 0x103800ULL }, // Inst #935 = CLGFI { 934, 4, 0, 6, 233, 0, 1, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x10388cULL }, // Inst #934 = CLGF { 933, 4, 1, 4, 370, 1, 1, SystemZImpOpBase + 1, 710, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #933 = CLGEBR { 932, 4, 1, 4, 483, 1, 1, SystemZImpOpBase + 1, 703, 0, 0x0ULL }, // Inst #932 = CLGDTR { 931, 4, 1, 4, 370, 1, 1, SystemZImpOpBase + 1, 703, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #931 = CLGDBR { 930, 4, 0, 6, 231, 0, 1, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x10390cULL }, // Inst #930 = CLG { 929, 4, 1, 4, 484, 1, 1, SystemZImpOpBase + 1, 696, 0, 0x0ULL }, // Inst #929 = CLFXTR { 928, 4, 1, 4, 371, 1, 1, SystemZImpOpBase + 1, 696, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #928 = CLFXBR { 927, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #927 = CLFITAsmNLH { 926, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #926 = CLFITAsmNLE { 925, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #925 = CLFITAsmNL { 924, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #924 = CLFITAsmNHE { 923, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #923 = CLFITAsmNH { 922, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #922 = CLFITAsmNE { 921, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #921 = CLFITAsmLH { 920, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #920 = CLFITAsmLE { 919, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #919 = CLFITAsmL { 918, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #918 = CLFITAsmHE { 917, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #917 = CLFITAsmH { 916, 2, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #916 = CLFITAsmE { 915, 3, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 230, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #915 = CLFITAsm { 914, 3, 0, 6, 16, 0, 0, SystemZImpOpBase + 0, 230, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #914 = CLFIT { 913, 2, 0, 6, 230, 0, 1, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::Compare), 0x103800ULL }, // Inst #913 = CLFI { 912, 3, 0, 6, 229, 0, 1, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103800ULL }, // Inst #912 = CLFHSI { 911, 4, 1, 4, 368, 1, 1, SystemZImpOpBase + 1, 687, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #911 = CLFEBR { 910, 4, 1, 4, 483, 1, 1, SystemZImpOpBase + 1, 680, 0, 0x0ULL }, // Inst #910 = CLFDTR { 909, 4, 1, 4, 369, 1, 1, SystemZImpOpBase + 1, 680, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #909 = CLFDBR { 908, 6, 2, 6, 255, 0, 1, SystemZImpOpBase + 0, 798, 0|(1ULL<<MCID::MayLoad), 0x4ULL }, // Inst #908 = CLCLU { 907, 6, 2, 4, 255, 0, 1, SystemZImpOpBase + 0, 798, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #907 = CLCLE { 906, 4, 2, 2, 255, 0, 1, SystemZImpOpBase + 0, 794, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #906 = CLCL { 905, 5, 0, 6, 254, 0, 1, SystemZImpOpBase + 0, 789, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #905 = CLC { 904, 4, 0, 4, 228, 0, 1, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103888ULL }, // Inst #904 = CL { 903, 4, 2, 4, 335, 0, 1, SystemZImpOpBase + 0, 785, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #903 = CKSM { 902, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #902 = CITAsmNLH { 901, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #901 = CITAsmNLE { 900, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #900 = CITAsmNL { 899, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #899 = CITAsmNHE { 898, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #898 = CITAsmNH { 897, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #897 = CITAsmNE { 896, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #896 = CITAsmLH { 895, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #895 = CITAsmLE { 894, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #894 = CITAsmL { 893, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #893 = CITAsmHE { 892, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #892 = CITAsmH { 891, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #891 = CITAsmE { 890, 3, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 230, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #890 = CITAsm { 889, 3, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 230, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #889 = CIT { 888, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #888 = CIJAsmNLH { 887, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #887 = CIJAsmNLE { 886, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #886 = CIJAsmNL { 885, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #885 = CIJAsmNHE { 884, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #884 = CIJAsmNH { 883, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #883 = CIJAsmNE { 882, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #882 = CIJAsmLH { 881, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #881 = CIJAsmLE { 880, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #880 = CIJAsmL { 879, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #879 = CIJAsmHE { 878, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #878 = CIJAsmH { 877, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 782, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #877 = CIJAsmE { 876, 4, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 778, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #876 = CIJAsm { 875, 4, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 778, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #875 = CIJ { 874, 2, 0, 6, 225, 0, 1, SystemZImpOpBase + 0, 776, 0|(1ULL<<MCID::Compare), 0x3800ULL }, // Inst #874 = CIH { 873, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #873 = CIBAsmNLH { 872, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #872 = CIBAsmNLE { 871, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #871 = CIBAsmNL { 870, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #870 = CIBAsmNHE { 869, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #869 = CIBAsmNH { 868, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #868 = CIBAsmNE { 867, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #867 = CIBAsmLH { 866, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #866 = CIBAsmLE { 865, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #865 = CIBAsmL { 864, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #864 = CIBAsmHE { 863, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #863 = CIBAsmH { 862, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 772, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #862 = CIBAsmE { 861, 5, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 767, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #861 = CIBAsm { 860, 5, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 767, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #860 = CIB { 859, 4, 0, 6, 246, 0, 1, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x384cULL }, // Inst #859 = CHY { 858, 3, 0, 6, 227, 0, 1, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL }, // Inst #858 = CHSI { 857, 2, 0, 6, 247, 0, 1, SystemZImpOpBase + 0, 765, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL }, // Inst #857 = CHRL { 856, 2, 0, 4, 245, 0, 1, SystemZImpOpBase + 0, 763, 0|(1ULL<<MCID::Compare), 0x3800ULL }, // Inst #856 = CHLR { 855, 2, 0, 4, 221, 0, 1, SystemZImpOpBase + 0, 691, 0|(1ULL<<MCID::Compare), 0x3800ULL }, // Inst #855 = CHI { 854, 3, 0, 6, 250, 0, 1, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL }, // Inst #854 = CHHSI { 853, 2, 0, 4, 244, 0, 1, SystemZImpOpBase + 0, 761, 0|(1ULL<<MCID::Compare), 0x3800ULL }, // Inst #853 = CHHR { 852, 4, 0, 6, 226, 0, 1, SystemZImpOpBase + 0, 757, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x388cULL }, // Inst #852 = CHF { 851, 4, 0, 4, 246, 0, 1, SystemZImpOpBase + 0, 623, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3848ULL }, // Inst #851 = CH { 850, 4, 1, 4, 482, 1, 1, SystemZImpOpBase + 1, 753, 0, 0x0ULL }, // Inst #850 = CGXTRA { 849, 3, 1, 4, 482, 1, 1, SystemZImpOpBase + 1, 750, 0, 0x0ULL }, // Inst #849 = CGXTR { 848, 3, 1, 4, 426, 0, 1, SystemZImpOpBase + 0, 750, 0, 0x0ULL }, // Inst #848 = CGXR { 847, 4, 1, 4, 367, 1, 1, SystemZImpOpBase + 1, 753, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #847 = CGXBRA { 846, 3, 1, 4, 367, 1, 1, SystemZImpOpBase + 1, 750, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #846 = CGXBR { 845, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #845 = CGRTAsmNLH { 844, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #844 = CGRTAsmNLE { 843, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #843 = CGRTAsmNL { 842, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #842 = CGRTAsmNHE { 841, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #841 = CGRTAsmNH { 840, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #840 = CGRTAsmNE { 839, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #839 = CGRTAsmLH { 838, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #838 = CGRTAsmLE { 837, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #837 = CGRTAsmL { 836, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #836 = CGRTAsmHE { 835, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #835 = CGRTAsmH { 834, 2, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #834 = CGRTAsmE { 833, 3, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 223, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #833 = CGRTAsm { 832, 3, 0, 4, 14, 0, 0, SystemZImpOpBase + 0, 223, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #832 = CGRT { 831, 2, 0, 6, 223, 0, 1, SystemZImpOpBase + 0, 716, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL }, // Inst #831 = CGRL { 830, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #830 = CGRJAsmNLH { 829, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #829 = CGRJAsmNLE { 828, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #828 = CGRJAsmNL { 827, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #827 = CGRJAsmNHE { 826, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #826 = CGRJAsmNH { 825, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #825 = CGRJAsmNE { 824, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #824 = CGRJAsmLH { 823, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #823 = CGRJAsmLE { 822, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #822 = CGRJAsmL { 821, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #821 = CGRJAsmHE { 820, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #820 = CGRJAsmH { 819, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 747, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #819 = CGRJAsmE { 818, 4, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 743, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #818 = CGRJAsm { 817, 4, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 743, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #817 = CGRJ { 816, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #816 = CGRBAsmNLH { 815, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #815 = CGRBAsmNLE { 814, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #814 = CGRBAsmNL { 813, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #813 = CGRBAsmNHE { 812, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #812 = CGRBAsmNH { 811, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #811 = CGRBAsmNE { 810, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #810 = CGRBAsmLH { 809, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #809 = CGRBAsmLE { 808, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #808 = CGRBAsmL { 807, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #807 = CGRBAsmHE { 806, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #806 = CGRBAsmH { 805, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 739, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #805 = CGRBAsmE { 804, 5, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 734, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #804 = CGRBAsm { 803, 5, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 734, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #803 = CGRB { 802, 2, 0, 4, 224, 0, 1, SystemZImpOpBase + 0, 563, 0|(1ULL<<MCID::Compare), 0x3800ULL }, // Inst #802 = CGR { 801, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #801 = CGITAsmNLH { 800, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #800 = CGITAsmNLE { 799, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #799 = CGITAsmNL { 798, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #798 = CGITAsmNHE { 797, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #797 = CGITAsmNH { 796, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #796 = CGITAsmNE { 795, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #795 = CGITAsmLH { 794, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #794 = CGITAsmLE { 793, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #793 = CGITAsmL { 792, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #792 = CGITAsmHE { 791, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #791 = CGITAsmH { 790, 2, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #790 = CGITAsmE { 789, 3, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #789 = CGITAsm { 788, 3, 0, 6, 14, 0, 0, SystemZImpOpBase + 0, 216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #788 = CGIT { 787, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #787 = CGIJAsmNLH { 786, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #786 = CGIJAsmNLE { 785, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #785 = CGIJAsmNL { 784, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #784 = CGIJAsmNHE { 783, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #783 = CGIJAsmNH { 782, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #782 = CGIJAsmNE { 781, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #781 = CGIJAsmLH { 780, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #780 = CGIJAsmLE { 779, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #779 = CGIJAsmL { 778, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #778 = CGIJAsmHE { 777, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #777 = CGIJAsmH { 776, 3, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 731, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #776 = CGIJAsmE { 775, 4, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 727, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #775 = CGIJAsm { 774, 4, 0, 6, 11, 0, 1, SystemZImpOpBase + 0, 727, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #774 = CGIJ { 773, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #773 = CGIBAsmNLH { 772, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #772 = CGIBAsmNLE { 771, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #771 = CGIBAsmNL { 770, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #770 = CGIBAsmNHE { 769, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #769 = CGIBAsmNH { 768, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #768 = CGIBAsmNE { 767, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #767 = CGIBAsmLH { 766, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #766 = CGIBAsmLE { 765, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #765 = CGIBAsmL { 764, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #764 = CGIBAsmHE { 763, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #763 = CGIBAsmH { 762, 4, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 723, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #762 = CGIBAsmE { 761, 5, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 718, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #761 = CGIBAsm { 760, 5, 0, 6, 12, 0, 0, SystemZImpOpBase + 0, 718, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #760 = CGIB { 759, 3, 0, 6, 223, 0, 1, SystemZImpOpBase + 0, 467, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL }, // Inst #759 = CGHSI { 758, 2, 0, 6, 249, 0, 1, SystemZImpOpBase + 0, 716, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL }, // Inst #758 = CGHRL { 757, 2, 0, 4, 222, 0, 1, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::Compare), 0x3800ULL }, // Inst #757 = CGHI { 756, 4, 0, 6, 248, 0, 1, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x384cULL }, // Inst #756 = CGH { 755, 2, 0, 6, 252, 0, 1, SystemZImpOpBase + 0, 716, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL }, // Inst #755 = CGFRL { 754, 2, 0, 4, 253, 0, 1, SystemZImpOpBase + 0, 714, 0|(1ULL<<MCID::Compare), 0x3800ULL }, // Inst #754 = CGFR { 753, 2, 0, 6, 222, 0, 1, SystemZImpOpBase + 0, 470, 0|(1ULL<<MCID::Compare), 0x3800ULL }, // Inst #753 = CGFI { 752, 4, 0, 6, 251, 0, 1, SystemZImpOpBase + 0, 161, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x388cULL }, // Inst #752 = CGF { 751, 3, 1, 4, 425, 0, 1, SystemZImpOpBase + 0, 707, 0, 0x0ULL }, // Inst #751 = CGER { 750, 4, 1, 4, 366, 1, 1, SystemZImpOpBase + 1, 710, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #750 = CGEBRA { 749, 3, 1, 4, 366, 1, 1, SystemZImpOpBase + 1, 707, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #749 = CGEBR { 748, 4, 1, 4, 481, 1, 1, SystemZImpOpBase + 1, 703, 0, 0x0ULL }, // Inst #748 = CGDTRA { 747, 3, 1, 4, 481, 1,<TRUNCATED>#ifdef __GNUC__#pragma GCC diagnostic push#pragma GCC diagnostic ignored "-Woverlength-strings"#endif#ifdef __GNUC__#pragma GCC diagnostic pop#endif#endif // GET_INSTRINFO_MC_DESC#ifdef GET_INSTRINFO_HEADER#undef GET_INSTRINFO_HEADER#endif // GET_INSTRINFO_HEADER#ifdef GET_INSTRINFO_HELPER_DECLS#undef GET_INSTRINFO_HELPER_DECLS#endif // GET_INSTRINFO_HELPER_DECLS#ifdef GET_INSTRINFO_HELPERS#undef GET_INSTRINFO_HELPERS#endif // GET_INSTRINFO_HELPERS#ifdef GET_INSTRINFO_CTOR_DTOR#undef GET_INSTRINFO_CTOR_DTOR#endif // GET_INSTRINFO_CTOR_DTOR#ifdef GET_INSTRINFO_OPERAND_ENUM#undef GET_INSTRINFO_OPERAND_ENUM#endif //GET_INSTRINFO_OPERAND_ENUM#ifdef GET_INSTRINFO_NAMED_OPS#undef GET_INSTRINFO_NAMED_OPS#endif //GET_INSTRINFO_NAMED_OPS#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM#undef GET_INSTRINFO_OPERAND_TYPES_ENUM#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM#ifdef GET_INSTRINFO_OPERAND_TYPE#undef GET_INSTRINFO_OPERAND_TYPE#endif // GET_INSTRINFO_OPERAND_TYPE#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE#undef GET_INSTRINFO_MEM_OPERAND_SIZE#endif // GET_INSTRINFO_MEM_OPERAND_SIZE#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP#ifdef GET_INSTRINFO_MC_HELPER_DECLS#undef GET_INSTRINFO_MC_HELPER_DECLSclass MCInstclass FeatureBitsetvoid verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features)#endif // GET_INSTRINFO_MC_HELPER_DECLS#ifdef GET_INSTRINFO_MC_HELPERS#undef GET_INSTRINFO_MC_HELPERS#endif // GET_GENISTRINFO_MC_HELPERS#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\ defined(GET_AVAILABLE_OPCODE_CHECKER)#define GET_COMPUTE_FEATURES#endif#ifdef GET_COMPUTE_FEATURES#undef GET_COMPUTE_FEATURES#endif // GET_COMPUTE_FEATURES#ifdef GET_AVAILABLE_OPCODE_CHECKER#undef GET_AVAILABLE_OPCODE_CHECKER#endif // GET_AVAILABLE_OPCODE_CHECKER#ifdef ENABLE_INSTR_PREDICATE_VERIFIER#undef ENABLE_INSTR_PREDICATE_VERIFIER#include <sstream>#ifndef NDEBUG#endif // NDEBUG#ifndef NDEBUG#endif // NDEBUG#endif // ENABLE_INSTR_PREDICATE_VERIFIER#ifdef GET_INSTRMAP_INFO#undef GET_INSTRMAP_INFO#endif // GET_INSTRMAP_INFO
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