Codebase Browser
llvm
Go to App

llvm/lib/Target/SystemZ/SystemZGenAsmWriter.inc 

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Assembly Writer Source Fragment                                            *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|* From: SystemZ.td                                                           *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

/// getMnemonic - This method is automatically generated by tablegen
/// from the instruction set description.
std::pair<const char *, uint64_t> SystemZInstPrinter::getMnemonic(const MCInst *MI) { … }
/// printInstruction - This method is automatically generated by tablegen
/// from the instruction set description.
LLVM_NO_PROFILE_INSTRUMENT_FUNCTION
void SystemZInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O) { … }


/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description.  This returns the assembler name
/// for the specified register.
const char *SystemZInstPrinter::getRegisterName(MCRegister Reg) { … }

#ifdef PRINT_ALIAS_INSTR
#undef PRINT_ALIAS_INSTR

bool SystemZInstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS) {
  static const PatternsForOpcode OpToPatterns[] = {
    {SystemZ::IILF, 0, 1 },
    {SystemZ::LLILF, 1, 1 },
    {SystemZ::LLILL, 2, 1 },
    {SystemZ::VFAE, 3, 1 },
    {SystemZ::VFAEB, 4, 1 },
    {SystemZ::VFAEBS, 5, 1 },
    {SystemZ::VFAEF, 6, 1 },
    {SystemZ::VFAEFS, 7, 1 },
    {SystemZ::VFAEH, 8, 1 },
    {SystemZ::VFAEHS, 9, 1 },
    {SystemZ::VFAEZB, 10, 1 },
    {SystemZ::VFAEZBS, 11, 1 },
    {SystemZ::VFAEZF, 12, 1 },
    {SystemZ::VFAEZFS, 13, 1 },
    {SystemZ::VFAEZH, 14, 1 },
    {SystemZ::VFAEZHS, 15, 1 },
    {SystemZ::VFEE, 16, 1 },
    {SystemZ::VFEEB, 17, 1 },
    {SystemZ::VFEEF, 18, 1 },
    {SystemZ::VFEEH, 19, 1 },
    {SystemZ::VFENE, 20, 1 },
    {SystemZ::VFENEB, 21, 1 },
    {SystemZ::VFENEF, 22, 1 },
    {SystemZ::VFENEH, 23, 1 },
    {SystemZ::VISTR, 24, 1 },
    {SystemZ::VISTRB, 25, 1 },
    {SystemZ::VISTRF, 26, 1 },
    {SystemZ::VISTRH, 27, 1 },
    {SystemZ::VSTRC, 28, 1 },
    {SystemZ::VSTRCB, 29, 1 },
    {SystemZ::VSTRCBS, 30, 1 },
    {SystemZ::VSTRCF, 31, 1 },
    {SystemZ::VSTRCFS, 32, 1 },
    {SystemZ::VSTRCH, 33, 1 },
    {SystemZ::VSTRCHS, 34, 1 },
    {SystemZ::VSTRCZB, 35, 1 },
    {SystemZ::VSTRCZBS, 36, 1 },
    {SystemZ::VSTRCZF, 37, 1 },
    {SystemZ::VSTRCZFS, 38, 1 },
    {SystemZ::VSTRCZH, 39, 1 },
    {SystemZ::VSTRCZHS, 40, 1 },
    {SystemZ::VSTRS, 41, 1 },
    {SystemZ::VSTRSB, 42, 1 },
    {SystemZ::VSTRSF, 43, 1 },
    {SystemZ::VSTRSH, 44, 1 },
  };

  static const AliasPattern Patterns[] = {
    // SystemZ::IILF - 0
    {0, 0, 2, 1 },
    // SystemZ::LLILF - 1
    {13, 1, 2, 1 },
    // SystemZ::LLILL - 2
    {28, 2, 2, 1 },
    // SystemZ::VFAE - 3
    {43, 3, 5, 5 },
    // SystemZ::VFAEB - 4
    {65, 8, 4, 4 },
    // SystemZ::VFAEBS - 5
    {82, 12, 4, 4 },
    // SystemZ::VFAEF - 6
    {100, 16, 4, 4 },
    // SystemZ::VFAEFS - 7
    {117, 20, 4, 4 },
    // SystemZ::VFAEH - 8
    {135, 24, 4, 4 },
    // SystemZ::VFAEHS - 9
    {152, 28, 4, 4 },
    // SystemZ::VFAEZB - 10
    {170, 32, 4, 4 },
    // SystemZ::VFAEZBS - 11
    {188, 36, 4, 4 },
    // SystemZ::VFAEZF - 12
    {207, 40, 4, 4 },
    // SystemZ::VFAEZFS - 13
    {225, 44, 4, 4 },
    // SystemZ::VFAEZH - 14
    {244, 48, 4, 4 },
    // SystemZ::VFAEZHS - 15
    {262, 52, 4, 4 },
    // SystemZ::VFEE - 16
    {281, 56, 5, 5 },
    // SystemZ::VFEEB - 17
    {303, 61, 4, 4 },
    // SystemZ::VFEEF - 18
    {320, 65, 4, 4 },
    // SystemZ::VFEEH - 19
    {337, 69, 4, 4 },
    // SystemZ::VFENE - 20
    {354, 73, 5, 5 },
    // SystemZ::VFENEB - 21
    {377, 78, 4, 4 },
    // SystemZ::VFENEF - 22
    {395, 82, 4, 4 },
    // SystemZ::VFENEH - 23
    {413, 86, 4, 4 },
    // SystemZ::VISTR - 24
    {431, 90, 4, 4 },
    // SystemZ::VISTRB - 25
    {450, 94, 3, 3 },
    // SystemZ::VISTRF - 26
    {464, 97, 3, 3 },
    // SystemZ::VISTRH - 27
    {478, 100, 3, 3 },
    // SystemZ::VSTRC - 28
    {492, 103, 6, 6 },
    // SystemZ::VSTRCB - 29
    {519, 109, 5, 5 },
    // SystemZ::VSTRCBS - 30
    {541, 114, 5, 5 },
    // SystemZ::VSTRCF - 31
    {564, 119, 5, 5 },
    // SystemZ::VSTRCFS - 32
    {586, 124, 5, 5 },
    // SystemZ::VSTRCH - 33
    {609, 129, 5, 5 },
    // SystemZ::VSTRCHS - 34
    {631, 134, 5, 5 },
    // SystemZ::VSTRCZB - 35
    {654, 139, 5, 5 },
    // SystemZ::VSTRCZBS - 36
    {677, 144, 5, 5 },
    // SystemZ::VSTRCZF - 37
    {701, 149, 5, 5 },
    // SystemZ::VSTRCZFS - 38
    {724, 154, 5, 5 },
    // SystemZ::VSTRCZH - 39
    {748, 159, 5, 5 },
    // SystemZ::VSTRCZHS - 40
    {771, 164, 5, 5 },
    // SystemZ::VSTRS - 41
    {795, 169, 6, 6 },
    // SystemZ::VSTRSB - 42
    {822, 175, 5, 5 },
    // SystemZ::VSTRSF - 43
    {844, 180, 5, 5 },
    // SystemZ::VSTRSH - 44
    {866, 185, 5, 5 },
  };

  static const AliasPatternCond Conds[] = {
    // (IILF GR32:$R1, uimm32:$RI1) - 0
    {AliasPatternCond::K_RegClass, SystemZ::GR32BitRegClassID},
    // (LLILF GR64:$R1, imm64lf32:$RI1) - 1
    {AliasPatternCond::K_RegClass, SystemZ::GR64BitRegClassID},
    // (LLILL GR64:$R1, imm64ll16:$RI1) - 2
    {AliasPatternCond::K_RegClass, SystemZ::GR64BitRegClassID},
    // (VFAE VR128:$V1, VR128:$V2, VR128:$V3, imm32zx4:$M4, 0) - 3
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VFAEB VR128:$V1, VR128:$V2, VR128:$V3, 0) - 8
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VFAEBS VR128:$V1, VR128:$V2, VR128:$V3, 0) - 12
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VFAEF VR128:$V1, VR128:$V2, VR128:$V3, 0) - 16
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VFAEFS VR128:$V1, VR128:$V2, VR128:$V3, 0) - 20
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VFAEH VR128:$V1, VR128:$V2, VR128:$V3, 0) - 24
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VFAEHS VR128:$V1, VR128:$V2, VR128:$V3, 0) - 28
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VFAEZB VR128:$V1, VR128:$V2, VR128:$V3, 0) - 32
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VFAEZBS VR128:$V1, VR128:$V2, VR128:$V3, 0) - 36
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VFAEZF VR128:$V1, VR128:$V2, VR128:$V3, 0) - 40
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VFAEZFS VR128:$V1, VR128:$V2, VR128:$V3, 0) - 44
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VFAEZH VR128:$V1, VR128:$V2, VR128:$V3, 0) - 48
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VFAEZHS VR128:$V1, VR128:$V2, VR128:$V3, 0) - 52
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VFEE VR128:$V1, VR128:$V2, VR128:$V3, imm32zx4:$M4, 0) - 56
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VFEEB VR128:$V1, VR128:$V2, VR128:$V3, 0) - 61
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VFEEF VR128:$V1, VR128:$V2, VR128:$V3, 0) - 65
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VFEEH VR128:$V1, VR128:$V2, VR128:$V3, 0) - 69
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VFENE VR128:$V1, VR128:$V2, VR128:$V3, imm32zx4:$M4, 0) - 73
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VFENEB VR128:$V1, VR128:$V2, VR128:$V3, 0) - 78
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VFENEF VR128:$V1, VR128:$V2, VR128:$V3, 0) - 82
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VFENEH VR128:$V1, VR128:$V2, VR128:$V3, 0) - 86
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VISTR VR128:$V1, VR128:$V2, imm32zx4:$M3, 0) - 90
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VISTRB VR128:$V1, VR128:$V2, 0) - 94
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VISTRF VR128:$V1, VR128:$V2, 0) - 97
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VISTRH VR128:$V1, VR128:$V2, 0) - 100
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VSTRC VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4_timm:$M5, 0) - 103
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VSTRCB VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 109
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VSTRCBS VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 114
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VSTRCF VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 119
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VSTRCFS VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 124
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VSTRCH VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 129
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VSTRCHS VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 134
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VSTRCZB VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 139
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VSTRCZBS VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 144
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VSTRCZF VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 149
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VSTRCZFS VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 154
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VSTRCZH VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 159
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VSTRCZHS VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 164
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VSTRS VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, 0) - 169
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VSTRSB VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 175
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VSTRSF VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 180
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (VSTRSH VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 185
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_RegClass, SystemZ::VR128BitRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
  };

  static const char AsmStrings[] =
    /* 0 */ "lfi	$\x01, $\xFF\x02\x01\0"
    /* 13 */ "llgfi	$\x01, $\xFF\x02\x01\0"
    /* 28 */ "llghi	$\x01, $\xFF\x02\x02\0"
    /* 43 */ "vfae	$\x01, $\x02, $\x03, $\xFF\x04\x03\0"
    /* 65 */ "vfaeb	$\x01, $\x02, $\x03\0"
    /* 82 */ "vfaebs	$\x01, $\x02, $\x03\0"
    /* 100 */ "vfaef	$\x01, $\x02, $\x03\0"
    /* 117 */ "vfaefs	$\x01, $\x02, $\x03\0"
    /* 135 */ "vfaeh	$\x01, $\x02, $\x03\0"
    /* 152 */ "vfaehs	$\x01, $\x02, $\x03\0"
    /* 170 */ "vfaezb	$\x01, $\x02, $\x03\0"
    /* 188 */ "vfaezbs	$\x01, $\x02, $\x03\0"
    /* 207 */ "vfaezf	$\x01, $\x02, $\x03\0"
    /* 225 */ "vfaezfs	$\x01, $\x02, $\x03\0"
    /* 244 */ "vfaezh	$\x01, $\x02, $\x03\0"
    /* 262 */ "vfaezhs	$\x01, $\x02, $\x03\0"
    /* 281 */ "vfee	$\x01, $\x02, $\x03, $\xFF\x04\x03\0"
    /* 303 */ "vfeeb	$\x01, $\x02, $\x03\0"
    /* 320 */ "vfeef	$\x01, $\x02, $\x03\0"
    /* 337 */ "vfeeh	$\x01, $\x02, $\x03\0"
    /* 354 */ "vfene	$\x01, $\x02, $\x03, $\xFF\x04\x03\0"
    /* 377 */ "vfeneb	$\x01, $\x02, $\x03\0"
    /* 395 */ "vfenef	$\x01, $\x02, $\x03\0"
    /* 413 */ "vfeneh	$\x01, $\x02, $\x03\0"
    /* 431 */ "vistr	$\x01, $\x02, $\xFF\x03\x03\0"
    /* 450 */ "vistrb	$\x01, $\x02\0"
    /* 464 */ "vistrf	$\x01, $\x02\0"
    /* 478 */ "vistrh	$\x01, $\x02\0"
    /* 492 */ "vstrc	$\x01, $\x02, $\x03, $\x04, $\xFF\x05\x03\0"
    /* 519 */ "vstrcb	$\x01, $\x02, $\x03, $\x04\0"
    /* 541 */ "vstrcbs	$\x01, $\x02, $\x03, $\x04\0"
    /* 564 */ "vstrcf	$\x01, $\x02, $\x03, $\x04\0"
    /* 586 */ "vstrcfs	$\x01, $\x02, $\x03, $\x04\0"
    /* 609 */ "vstrch	$\x01, $\x02, $\x03, $\x04\0"
    /* 631 */ "vstrchs	$\x01, $\x02, $\x03, $\x04\0"
    /* 654 */ "vstrczb	$\x01, $\x02, $\x03, $\x04\0"
    /* 677 */ "vstrczbs	$\x01, $\x02, $\x03, $\x04\0"
    /* 701 */ "vstrczf	$\x01, $\x02, $\x03, $\x04\0"
    /* 724 */ "vstrczfs	$\x01, $\x02, $\x03, $\x04\0"
    /* 748 */ "vstrczh	$\x01, $\x02, $\x03, $\x04\0"
    /* 771 */ "vstrczhs	$\x01, $\x02, $\x03, $\x04\0"
    /* 795 */ "vstrs	$\x01, $\x02, $\x03, $\x04, $\xFF\x05\x03\0"
    /* 822 */ "vstrsb	$\x01, $\x02, $\x03, $\x04\0"
    /* 844 */ "vstrsf	$\x01, $\x02, $\x03, $\x04\0"
    /* 866 */ "vstrsh	$\x01, $\x02, $\x03, $\x04\0"
  ;

#ifndef NDEBUG
  static struct SortCheck {
    SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {
      assert(std::is_sorted(
                 OpToPatterns.begin(), OpToPatterns.end(),
                 [](const PatternsForOpcode &L, const PatternsForOpcode &R) {
                   return L.Opcode < R.Opcode;
                 }) &&
             "tablegen failed to sort opcode patterns");
    }
  } sortCheckVar(OpToPatterns);
#endif

  AliasMatchingData M {
    ArrayRef(OpToPatterns),
    ArrayRef(Patterns),
    ArrayRef(Conds),
    StringRef(AsmStrings, std::size(AsmStrings)),
    nullptr,
  };
  const char *AsmString = matchAliasPatterns(MI, nullptr, M);
  if (!AsmString) return false;

  unsigned I = 0;
  while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
         AsmString[I] != '$' && AsmString[I] != '\0')
    ++I;
  OS << '\t' << StringRef(AsmString, I);
  if (AsmString[I] != '\0') {
    if (AsmString[I] == ' ' || AsmString[I] == '\t') {
      OS << '\t';
      ++I;
    }
    do {
      if (AsmString[I] == '$') {
        ++I;
        if (AsmString[I] == (char)0xff) {
          ++I;
          int OpIdx = AsmString[I++] - 1;
          int PrintMethodIdx = AsmString[I++] - 1;
          printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, OS);
        } else
          printOperand(MI, unsigned(AsmString[I++]) - 1, OS);
      } else {
        OS << AsmString[I++];
      }
    } while (AsmString[I] != '\0');
  }

  return true;
}

void SystemZInstPrinter::printCustomAliasOperand(
         const MCInst *MI, uint64_t Address, unsigned OpIdx,
         unsigned PrintMethodIdx,
         raw_ostream &OS) {
  switch (PrintMethodIdx) {
  default:
    llvm_unreachable("Unknown PrintMethod kind");
    break;
  case 0:
    printU32ImmOperand(MI, OpIdx, OS);
    break;
  case 1:
    printU16ImmOperand(MI, OpIdx, OS);
    break;
  case 2:
    printU4ImmOperand(MI, OpIdx, OS);
    break;
  }
}

#endif // PRINT_ALIAS_INSTR