llvm/lib/Target/XCore/XCoreGenInstrInfo.inc

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Instruction Enum Values and Descriptors                             *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
namespace llvm {

namespace XCore {
  enum { … };

} // end namespace XCore
} // end namespace llvm
#endif // GET_INSTRINFO_ENUM

#ifdef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_SCHED_ENUM
namespace llvm {

namespace XCore {
namespace Sched {
  enum {
    NoInstrModel	= 0,
    SCHED_LIST_END = 1
  };
} // end namespace Sched
} // end namespace XCore
} // end namespace llvm
#endif // GET_INSTRINFO_SCHED_ENUM

#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
namespace llvm {

struct XCoreInstrTable {
  MCInstrDesc Insts[526];
  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
  MCOperandInfo OperandInfo[213];
  static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
  MCPhysReg ImplicitOps[11];
};

} // end namespace llvm
#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)

#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC
namespace llvm {

static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
static constexpr unsigned XCoreImpOpBase = sizeof XCoreInstrTable::OperandInfo / (sizeof(MCPhysReg));

extern const XCoreInstrTable XCoreDescs = {
  {
    { 525,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	205,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #525 = ZEXT_rus
    { 524,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	170,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #524 = ZEXT_2r
    { 523,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #523 = XOR_l3r
    { 522,	0,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #522 = WAITEU_0R
    { 521,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #521 = WAITET_1R
    { 520,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #520 = WAITEF_1R
    { 519,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #519 = TSTART_1R
    { 518,	3,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	210,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #518 = TSETR_3r
    { 517,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	208,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #517 = TSETMR_2r
    { 516,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #516 = TESTWCT_2r
    { 515,	2,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #515 = TESTLCL_l2r
    { 514,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #514 = TESTCT_2r
    { 513,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #513 = SYNCR_1r
    { 512,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #512 = SUB_3r
    { 511,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #511 = SUB_2rus
    { 510,	3,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #510 = STW_l3r
    { 509,	3,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #509 = STW_2rus
    { 508,	2,	0,	2,	0,	1,	0,	XCoreImpOpBase + 10,	191,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #508 = STWSP_ru6
    { 507,	2,	0,	4,	0,	1,	0,	XCoreImpOpBase + 10,	191,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #507 = STWSP_lru6
    { 506,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	191,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #506 = STWDP_ru6
    { 505,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	191,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #505 = STWDP_lru6
    { 504,	0,	0,	2,	0,	1,	0,	XCoreImpOpBase + 10,	1,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #504 = STSSR_0R
    { 503,	0,	0,	2,	0,	1,	0,	XCoreImpOpBase + 10,	1,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #503 = STSPC_0R
    { 502,	0,	0,	2,	0,	1,	0,	XCoreImpOpBase + 10,	1,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #502 = STSED_0R
    { 501,	0,	0,	2,	0,	1,	0,	XCoreImpOpBase + 10,	1,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #501 = STET_0R
    { 500,	3,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #500 = ST8_l3r
    { 499,	3,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #499 = ST16_l3r
    { 498,	0,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #498 = SSYNC_0r
    { 497,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #497 = SHR_3r
    { 496,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #496 = SHR_2rus
    { 495,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #495 = SHL_3r
    { 494,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #494 = SHL_2rus
    { 493,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	205,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #493 = SEXT_rus
    { 492,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	170,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #492 = SEXT_2r
    { 491,	1,	0,	2,	0,	1,	0,	XCoreImpOpBase + 9,	156,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #491 = SETV_1r
    { 490,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #490 = SETTW_l2r
    { 489,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #489 = SETSR_u6
    { 488,	1,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #488 = SETSR_lu6
    { 487,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #487 = SETSR_branch_u6
    { 486,	1,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #486 = SETSR_branch_lu6
    { 485,	1,	0,	2,	0,	0,	1,	XCoreImpOpBase + 10,	156,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #485 = SETSP_1r
    { 484,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #484 = SETRDY_l2r
    { 483,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #483 = SETPT_2r
    { 482,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #482 = SETPS_l2r
    { 481,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #481 = SETPSC_2r
    { 480,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #480 = SETN_l2r
    { 479,	0,	0,	2,	0,	1,	0,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #479 = SETKEP_0R
    { 478,	1,	0,	2,	0,	1,	0,	XCoreImpOpBase + 9,	156,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #478 = SETEV_1r
    { 477,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #477 = SETD_2r
    { 476,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #476 = SETDP_1r
    { 475,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	175,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #475 = SETC_ru6
    { 474,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	175,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #474 = SETC_lru6
    { 473,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #473 = SETC_l2r
    { 472,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #472 = SETCP_1r
    { 471,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #471 = SETCLK_l2r
    { 470,	1,	0,	2,	0,	1,	1,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #470 = RETSP_u6
    { 469,	1,	0,	4,	0,	1,	1,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #469 = RETSP_lu6
    { 468,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #468 = REMU_l3r
    { 467,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #467 = REMS_l3r
    { 466,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #466 = PEEK_2r
    { 465,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #465 = OUT_2r
    { 464,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #464 = OUTT_2r
    { 463,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	170,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #463 = OUTSHR_2r
    { 462,	3,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #462 = OUTPW_l2rus
    { 461,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	175,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #461 = OUTCT_rus
    { 460,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #460 = OUTCT_2r
    { 459,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #459 = OR_3r
    { 458,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #458 = NOT
    { 457,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #457 = NEG
    { 456,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #456 = MUL_l3r
    { 455,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #455 = MSYNC_1r
    { 454,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	175,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #454 = MKMSK_rus
    { 453,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #453 = MKMSK_2r
    { 452,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #452 = MJOIN_1r
    { 451,	6,	2,	4,	0,	0,	0,	XCoreImpOpBase + 0,	199,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #451 = MACCU_l4r
    { 450,	6,	2,	4,	0,	0,	0,	XCoreImpOpBase + 0,	199,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #450 = MACCS_l4r
    { 449,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #449 = LSU_3r
    { 448,	5,	2,	4,	0,	0,	0,	XCoreImpOpBase + 0,	186,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #448 = LSUB_l5r
    { 447,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #447 = LSS_3r
    { 446,	6,	2,	4,	0,	0,	0,	XCoreImpOpBase + 0,	193,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #446 = LMUL_l6r
    { 445,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #445 = LDW_3r
    { 444,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #444 = LDW_2rus
    { 443,	2,	1,	2,	0,	1,	0,	XCoreImpOpBase + 10,	191,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #443 = LDWSP_ru6
    { 442,	2,	1,	4,	0,	1,	0,	XCoreImpOpBase + 10,	191,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #442 = LDWSP_lru6
    { 441,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	191,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #441 = LDWDP_ru6
    { 440,	2,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	191,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #440 = LDWDP_lru6
    { 439,	1,	0,	2,	0,	0,	1,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #439 = LDWCP_u10
    { 438,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	191,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #438 = LDWCP_ru6
    { 437,	1,	0,	4,	0,	0,	1,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #437 = LDWCP_lu10
    { 436,	2,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	191,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #436 = LDWCP_lru6
    { 435,	0,	0,	2,	0,	1,	0,	XCoreImpOpBase + 10,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #435 = LDSSR_0R
    { 434,	0,	0,	2,	0,	1,	0,	XCoreImpOpBase + 10,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #434 = LDSPC_0R
    { 433,	0,	0,	2,	0,	1,	0,	XCoreImpOpBase + 10,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #433 = LDSED_0R
    { 432,	5,	2,	4,	0,	0,	0,	XCoreImpOpBase + 0,	186,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #432 = LDIVU_l5r
    { 431,	0,	0,	2,	0,	1,	0,	XCoreImpOpBase + 10,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #431 = LDET_0R
    { 430,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	191,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #430 = LDC_ru6
    { 429,	2,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	191,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #429 = LDC_lru6
    { 428,	2,	1,	2,	0,	1,	0,	XCoreImpOpBase + 10,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #428 = LDAWSP_ru6
    { 427,	2,	1,	4,	0,	1,	0,	XCoreImpOpBase + 10,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #427 = LDAWSP_lru6
    { 426,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #426 = LDAWF_l3r
    { 425,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #425 = LDAWF_l2rus
    { 424,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	191,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #424 = LDAWDP_ru6
    { 423,	2,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	191,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #423 = LDAWDP_lru6
    { 422,	1,	0,	2,	0,	0,	1,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #422 = LDAWCP_u6
    { 421,	1,	0,	4,	0,	0,	1,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #421 = LDAWCP_lu6
    { 420,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #420 = LDAWB_l3r
    { 419,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #419 = LDAWB_l2rus
    { 418,	1,	0,	2,	0,	0,	1,	XCoreImpOpBase + 9,	0,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #418 = LDAPF_u10
    { 417,	1,	0,	4,	0,	0,	1,	XCoreImpOpBase + 9,	0,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #417 = LDAPF_lu10_ba
    { 416,	1,	0,	4,	0,	0,	1,	XCoreImpOpBase + 9,	0,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #416 = LDAPF_lu10
    { 415,	1,	0,	2,	0,	0,	1,	XCoreImpOpBase + 9,	0,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #415 = LDAPB_u10
    { 414,	1,	0,	4,	0,	0,	1,	XCoreImpOpBase + 9,	0,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #414 = LDAPB_lu10
    { 413,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #413 = LDA16F_l3r
    { 412,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #412 = LDA16B_l3r
    { 411,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #411 = LD8U_3r
    { 410,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #410 = LD16S_3r
    { 409,	5,	2,	4,	0,	0,	0,	XCoreImpOpBase + 0,	186,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #409 = LADD_l5r
    { 408,	0,	0,	2,	0,	0,	1,	XCoreImpOpBase + 10,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #408 = KRET_0R
    { 407,	1,	0,	2,	0,	1,	1,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #407 = KRESTSP_u6
    { 406,	1,	0,	4,	0,	1,	1,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #406 = KRESTSP_lu6
    { 405,	1,	0,	2,	0,	1,	1,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #405 = KENTSP_u6
    { 404,	1,	0,	4,	0,	1,	1,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #404 = KENTSP_lu6
    { 403,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #403 = KCALL_u6
    { 402,	1,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #402 = KCALL_lu6
    { 401,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #401 = KCALL_1r
    { 400,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #400 = IN_2r
    { 399,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #399 = INT_2r
    { 398,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	170,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #398 = INSHR_2r
    { 397,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #397 = INPW_l2rus
    { 396,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #396 = INITSP_2r
    { 395,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #395 = INITPC_2r
    { 394,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #394 = INITLR_l2r
    { 393,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #393 = INITDP_2r
    { 392,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #392 = INITCP_2r
    { 391,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #391 = INCT_2r
    { 390,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #390 = GETTS_2r
    { 389,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #389 = GETST_2r
    { 388,	1,	0,	2,	0,	0,	1,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #388 = GETSR_u6
    { 387,	1,	0,	4,	0,	0,	1,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #387 = GETSR_lu6
    { 386,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	175,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #386 = GETR_rus
    { 385,	2,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #385 = GETPS_l2r
    { 384,	2,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #384 = GETN_l2r
    { 383,	0,	0,	2,	0,	0,	1,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #383 = GETKSP_0R
    { 382,	0,	0,	2,	0,	0,	1,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #382 = GETKEP_0R
    { 381,	0,	0,	2,	0,	0,	1,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #381 = GETID_0R
    { 380,	0,	0,	2,	0,	0,	1,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #380 = GETET_0R
    { 379,	0,	0,	2,	0,	0,	1,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #379 = GETED_0R
    { 378,	2,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #378 = GETD_l2r
    { 377,	0,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #377 = FREET_0R
    { 376,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #376 = FREER_1r
    { 375,	1,	0,	2,	0,	1,	1,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #375 = EXTSP_u6
    { 374,	1,	0,	4,	0,	1,	1,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #374 = EXTSP_lu6
    { 373,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #373 = EXTDP_u6
    { 372,	1,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #372 = EXTDP_lu6
    { 371,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #371 = EQ_3r
    { 370,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #370 = EQ_2rus
    { 369,	1,	0,	2,	0,	1,	1,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #369 = ENTSP_u6
    { 368,	1,	0,	4,	0,	1,	1,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #368 = ENTSP_lu6
    { 367,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #367 = ENDIN_2r
    { 366,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #366 = EEU_1r
    { 365,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #365 = EET_2r
    { 364,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #364 = EEF_2r
    { 363,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #363 = EDU_1r
    { 362,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #362 = ECALLT_1r
    { 361,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #361 = ECALLF_1r
    { 360,	0,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #360 = DRET_0R
    { 359,	0,	0,	2,	0,	0,	1,	XCoreImpOpBase + 10,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #359 = DRESTSP_0R
    { 358,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #358 = DIVU_l3r
    { 357,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #357 = DIVS_l3r
    { 356,	1,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #356 = DGETREG_1r
    { 355,	0,	0,	2,	0,	1,	1,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #355 = DENTSP_0R
    { 354,	0,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #354 = DCALL_0R
    { 353,	4,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	182,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #353 = CRC_l3r
    { 352,	5,	2,	4,	0,	0,	0,	XCoreImpOpBase + 0,	177,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #352 = CRC8_l4r
    { 351,	2,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #351 = CLZ_l2r
    { 350,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #350 = CLRSR_u6
    { 349,	1,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #349 = CLRSR_lu6
    { 348,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #348 = CLRSR_branch_u6
    { 347,	1,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #347 = CLRSR_branch_lu6
    { 346,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #346 = CLRPT_1R
    { 345,	0,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #345 = CLRE_0R
    { 344,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	175,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #344 = CHKCT_rus
    { 343,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #343 = CHKCT_2r
    { 342,	2,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #342 = BYTEREV_l2r
    { 341,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #341 = BRU_1r
    { 340,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #340 = BRFU_u6
    { 339,	1,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #339 = BRFU_lu6
    { 338,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	173,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #338 = BRFT_ru6
    { 337,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	173,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #337 = BRFT_lru6
    { 336,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	173,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #336 = BRFF_ru6
    { 335,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	173,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #335 = BRFF_lru6
    { 334,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #334 = BRBU_u6
    { 333,	1,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #333 = BRBU_lu6
    { 332,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	173,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #332 = BRBT_ru6
    { 331,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	173,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #331 = BRBT_lru6
    { 330,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	173,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #330 = BRBF_ru6
    { 329,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	173,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #329 = BRBF_lru6
    { 328,	1,	0,	2,	0,	1,	6,	XCoreImpOpBase + 2,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #328 = BLRF_u10
    { 327,	1,	0,	4,	0,	1,	6,	XCoreImpOpBase + 2,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #327 = BLRF_lu10
    { 326,	1,	0,	2,	0,	1,	6,	XCoreImpOpBase + 2,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #326 = BLRB_u10
    { 325,	1,	0,	4,	0,	1,	6,	XCoreImpOpBase + 2,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #325 = BLRB_lu10
    { 324,	1,	0,	2,	0,	1,	6,	XCoreImpOpBase + 2,	156,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #324 = BLA_1r
    { 323,	1,	0,	2,	0,	1,	0,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #323 = BLAT_u6
    { 322,	1,	0,	4,	0,	1,	0,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #322 = BLAT_lu6
    { 321,	1,	0,	2,	0,	1,	6,	XCoreImpOpBase + 2,	1,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #321 = BLACP_u10
    { 320,	1,	0,	4,	0,	1,	6,	XCoreImpOpBase + 2,	1,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #320 = BLACP_lu10
    { 319,	2,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #319 = BITREV_l2r
    { 318,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #318 = BAU_1r
    { 317,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #317 = ASHR_l3r
    { 316,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #316 = ASHR_l2rus
    { 315,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #315 = AND_3r
    { 314,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	170,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #314 = ANDNOT_2r
    { 313,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #313 = ADD_3r
    { 312,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #312 = ADD_2rus
    { 311,	3,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	157,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #311 = STWFI
    { 310,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	160,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #310 = SELECT_CC
    { 309,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	157,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #309 = LDWFI
    { 308,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	157,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #308 = LDAWFI
    { 307,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #307 = FRAME_TO_ARGS_OFFSET
    { 306,	2,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #306 = EH_RETURN
    { 305,	2,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #305 = BR_JT32
    { 304,	2,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #304 = BR_JT
    { 303,	2,	0,	0,	0,	1,	1,	XCoreImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #303 = ADJCALLSTACKUP
    { 302,	2,	0,	0,	0,	1,	1,	XCoreImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #302 = ADJCALLSTACKDOWN
    { 301,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #301 = G_UBFX
    { 300,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #300 = G_SBFX
    { 299,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #299 = G_VECREDUCE_UMIN
    { 298,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #298 = G_VECREDUCE_UMAX
    { 297,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #297 = G_VECREDUCE_SMIN
    { 296,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #296 = G_VECREDUCE_SMAX
    { 295,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #295 = G_VECREDUCE_XOR
    { 294,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #294 = G_VECREDUCE_OR
    { 293,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #293 = G_VECREDUCE_AND
    { 292,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #292 = G_VECREDUCE_MUL
    { 291,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #291 = G_VECREDUCE_ADD
    { 290,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #290 = G_VECREDUCE_FMINIMUM
    { 289,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #289 = G_VECREDUCE_FMAXIMUM
    { 288,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #288 = G_VECREDUCE_FMIN
    { 287,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #287 = G_VECREDUCE_FMAX
    { 286,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #286 = G_VECREDUCE_FMUL
    { 285,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #285 = G_VECREDUCE_FADD
    { 284,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #284 = G_VECREDUCE_SEQ_FMUL
    { 283,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #283 = G_VECREDUCE_SEQ_FADD
    { 282,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #282 = G_UBSANTRAP
    { 281,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #281 = G_DEBUGTRAP
    { 280,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #280 = G_TRAP
    { 279,	3,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #279 = G_BZERO
    { 278,	4,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #278 = G_MEMSET
    { 277,	4,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #277 = G_MEMMOVE
    { 276,	3,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #276 = G_MEMCPY_INLINE
    { 275,	4,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #275 = G_MEMCPY
    { 274,	2,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	142,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #274 = G_WRITE_REGISTER
    { 273,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #273 = G_READ_REGISTER
    { 272,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #272 = G_STRICT_FLDEXP
    { 271,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #271 = G_STRICT_FSQRT
    { 270,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #270 = G_STRICT_FMA
    { 269,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #269 = G_STRICT_FREM
    { 268,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #268 = G_STRICT_FDIV
    { 267,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #267 = G_STRICT_FMUL
    { 266,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #266 = G_STRICT_FSUB
    { 265,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #265 = G_STRICT_FADD
    { 264,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #264 = G_STACKRESTORE
    { 263,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #263 = G_STACKSAVE
    { 262,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #262 = G_DYN_STACKALLOC
    { 261,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #261 = G_JUMP_TABLE
    { 260,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #260 = G_BLOCK_ADDR
    { 259,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #259 = G_ADDRSPACE_CAST
    { 258,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #258 = G_FNEARBYINT
    { 257,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #257 = G_FRINT
    { 256,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #256 = G_FFLOOR
    { 255,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #255 = G_FSQRT
    { 254,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #254 = G_FTANH
    { 253,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #253 = G_FSINH
    { 252,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #252 = G_FCOSH
    { 251,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #251 = G_FATAN2
    { 250,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #250 = G_FATAN
    { 249,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #249 = G_FASIN
    { 248,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #248 = G_FACOS
    { 247,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #247 = G_FTAN
    { 246,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #246 = G_FSIN
    { 245,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #245 = G_FCOS
    { 244,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #244 = G_FCEIL
    { 243,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #243 = G_BITREVERSE
    { 242,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #242 = G_BSWAP
    { 241,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #241 = G_CTPOP
    { 240,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #240 = G_CTLZ_ZERO_UNDEF
    { 239,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #239 = G_CTLZ
    { 238,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #238 = G_CTTZ_ZERO_UNDEF
    { 237,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #237 = G_CTTZ
    { 236,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	138,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #236 = G_VECTOR_COMPRESS
    { 235,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #235 = G_SPLAT_VECTOR
    { 234,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	134,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #234 = G_SHUFFLE_VECTOR
    { 233,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #233 = G_EXTRACT_VECTOR_ELT
    { 232,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	127,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #232 = G_INSERT_VECTOR_ELT
    { 231,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #231 = G_EXTRACT_SUBVECTOR
    { 230,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #230 = G_INSERT_SUBVECTOR
    { 229,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #229 = G_VSCALE
    { 228,	3,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	124,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #228 = G_BRJT
    { 227,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #227 = G_BR
    { 226,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #226 = G_LLROUND
    { 225,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #225 = G_LROUND
    { 224,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #224 = G_ABS
    { 223,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #223 = G_UMAX
    { 222,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #222 = G_UMIN
    { 221,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #221 = G_SMAX
    { 220,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #220 = G_SMIN
    { 219,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #219 = G_PTRMASK
    { 218,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #218 = G_PTR_ADD
    { 217,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #217 = G_RESET_FPMODE
    { 216,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #216 = G_SET_FPMODE
    { 215,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #215 = G_GET_FPMODE
    { 214,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #214 = G_RESET_FPENV
    { 213,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #213 = G_SET_FPENV
    { 212,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #212 = G_GET_FPENV
    { 211,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #211 = G_FMAXIMUM
    { 210,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #210 = G_FMINIMUM
    { 209,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #209 = G_FMAXNUM_IEEE
    { 208,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #208 = G_FMINNUM_IEEE
    { 207,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #207 = G_FMAXNUM
    { 206,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #206 = G_FMINNUM
    { 205,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #205 = G_FCANONICALIZE
    { 204,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #204 = G_IS_FPCLASS
    { 203,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #203 = G_FCOPYSIGN
    { 202,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #202 = G_FABS
    { 201,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #201 = G_FPTOUI_SAT
    { 200,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #200 = G_FPTOSI_SAT
    { 199,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #199 = G_UITOFP
    { 198,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #198 = G_SITOFP
    { 197,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #197 = G_FPTOUI
    { 196,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #196 = G_FPTOSI
    { 195,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #195 = G_FPTRUNC
    { 194,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #194 = G_FPEXT
    { 193,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #193 = G_FNEG
    { 192,	3,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #192 = G_FFREXP
    { 191,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #191 = G_FLDEXP
    { 190,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #190 = G_FLOG10
    { 189,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #189 = G_FLOG2
    { 188,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #188 = G_FLOG
    { 187,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #187 = G_FEXP10
    { 186,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #186 = G_FEXP2
    { 185,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #185 = G_FEXP
    { 184,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #184 = G_FPOWI
    { 183,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #183 = G_FPOW
    { 182,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #182 = G_FREM
    { 181,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #181 = G_FDIV
    { 180,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #180 = G_FMAD
    { 179,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #179 = G_FMA
    { 178,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #178 = G_FMUL
    { 177,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #177 = G_FSUB
    { 176,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #176 = G_FADD
    { 175,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #175 = G_UDIVFIXSAT
    { 174,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #174 = G_SDIVFIXSAT
    { 173,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #173 = G_UDIVFIX
    { 172,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #172 = G_SDIVFIX
    { 171,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #171 = G_UMULFIXSAT
    { 170,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #170 = G_SMULFIXSAT
    { 169,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #169 = G_UMULFIX
    { 168,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #168 = G_SMULFIX
    { 167,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #167 = G_SSHLSAT
    { 166,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #166 = G_USHLSAT
    { 165,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #165 = G_SSUBSAT
    { 164,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #164 = G_USUBSAT
    { 163,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #163 = G_SADDSAT
    { 162,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #162 = G_UADDSAT
    { 161,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #161 = G_SMULH
    { 160,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #160 = G_UMULH
    { 159,	4,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #159 = G_SMULO
    { 158,	4,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #158 = G_UMULO
    { 157,	5,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #157 = G_SSUBE
    { 156,	4,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #156 = G_SSUBO
    { 155,	5,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #155 = G_SADDE
    { 154,	4,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #154 = G_SADDO
    { 153,	5,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #153 = G_USUBE
    { 152,	4,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #152 = G_USUBO
    { 151,	5,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #151 = G_UADDE
    { 150,	4,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #150 = G_UADDO
    { 149,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #149 = G_SELECT
    { 148,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #148 = G_UCMP
    { 147,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #147 = G_SCMP
    { 146,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #146 = G_FCMP
    { 145,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #145 = G_ICMP
    { 144,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #144 = G_ROTL
    { 143,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #143 = G_ROTR
    { 142,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #142 = G_FSHR
    { 141,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #141 = G_FSHL
    { 140,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #140 = G_ASHR
    { 139,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #139 = G_LSHR
    { 138,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #138 = G_SHL
    { 137,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #137 = G_ZEXT
    { 136,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #136 = G_SEXT_INREG
    { 135,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #135 = G_SEXT
    { 134,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #134 = G_VAARG
    { 133,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #133 = G_VASTART
    { 132,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #132 = G_FCONSTANT
    { 131,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #131 = G_CONSTANT
    { 130,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #130 = G_TRUNC
    { 129,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #129 = G_ANYEXT
    { 128,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #128 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
    { 127,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #127 = G_INTRINSIC_CONVERGENT
    { 126,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #126 = G_INTRINSIC_W_SIDE_EFFECTS
    { 125,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #125 = G_INTRINSIC
    { 124,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #124 = G_INVOKE_REGION_START
    { 123,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #123 = G_BRINDIRECT
    { 122,	2,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #122 = G_BRCOND
    { 121,	4,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	94,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #121 = G_PREFETCH
    { 120,	2,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	21,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #120 = G_FENCE
    { 119,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #119 = G_ATOMICRMW_USUB_SAT
    { 118,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #118 = G_ATOMICRMW_USUB_COND
    { 117,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #117 = G_ATOMICRMW_UDEC_WRAP
    { 116,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #116 = G_ATOMICRMW_UINC_WRAP
    { 115,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #115 = G_ATOMICRMW_FMIN
    { 114,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #114 = G_ATOMICRMW_FMAX
    { 113,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #113 = G_ATOMICRMW_FSUB
    { 112,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #112 = G_ATOMICRMW_FADD
    { 111,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #111 = G_ATOMICRMW_UMIN
    { 110,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #110 = G_ATOMICRMW_UMAX
    { 109,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #109 = G_ATOMICRMW_MIN
    { 108,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #108 = G_ATOMICRMW_MAX
    { 107,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #107 = G_ATOMICRMW_XOR
    { 106,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #106 = G_ATOMICRMW_OR
    { 105,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #105 = G_ATOMICRMW_NAND
    { 104,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #104 = G_ATOMICRMW_AND
    { 103,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #103 = G_ATOMICRMW_SUB
    { 102,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #102 = G_ATOMICRMW_ADD
    { 101,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #101 = G_ATOMICRMW_XCHG
    { 100,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #100 = G_ATOMIC_CMPXCHG
    { 99,	5,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	82,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #99 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
    { 98,	5,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	77,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #98 = G_INDEXED_STORE
    { 97,	2,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #97 = G_STORE
    { 96,	5,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #96 = G_INDEXED_ZEXTLOAD
    { 95,	5,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #95 = G_INDEXED_SEXTLOAD
    { 94,	5,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #94 = G_INDEXED_LOAD
    { 93,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #93 = G_ZEXTLOAD
    { 92,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #92 = G_SEXTLOAD
    { 91,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #91 = G_LOAD
    { 90,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #90 = G_READSTEADYCOUNTER
    { 89,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #89 = G_READCYCLECOUNTER
    { 88,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #88 = G_INTRINSIC_ROUNDEVEN
    { 87,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #87 = G_INTRINSIC_LLRINT
    { 86,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #86 = G_INTRINSIC_LRINT
    { 85,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #85 = G_INTRINSIC_ROUND
    { 84,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #84 = G_INTRINSIC_TRUNC
    { 83,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #83 = G_INTRINSIC_FPTRUNC_ROUND
    { 82,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #82 = G_CONSTANT_FOLD_BARRIER
    { 81,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #81 = G_FREEZE
    { 80,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #80 = G_BITCAST
    { 79,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #79 = G_INTTOPTR
    { 78,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #78 = G_PTRTOINT
    { 77,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #77 = G_CONCAT_VECTORS
    { 76,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #76 = G_BUILD_VECTOR_TRUNC
    { 75,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #75 = G_BUILD_VECTOR
    { 74,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #74 = G_MERGE_VALUES
    { 73,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #73 = G_INSERT
    { 72,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #72 = G_UNMERGE_VALUES
    { 71,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #71 = G_EXTRACT
    { 70,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #70 = G_CONSTANT_POOL
    { 69,	5,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	53,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #69 = G_PTRAUTH_GLOBAL_VALUE
    { 68,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #68 = G_GLOBAL_VALUE
    { 67,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #67 = G_FRAME_INDEX
    { 66,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #66 = G_PHI
    { 65,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #65 = G_IMPLICIT_DEF
    { 64,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #64 = G_XOR
    { 63,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #63 = G_OR
    { 62,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #62 = G_AND
    { 61,	4,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #61 = G_UDIVREM
    { 60,	4,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #60 = G_SDIVREM
    { 59,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #59 = G_UREM
    { 58,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #58 = G_SREM
    { 57,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #57 = G_UDIV
    { 56,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #56 = G_SDIV
    { 55,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #55 = G_MUL
    { 54,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #54 = G_SUB
    { 53,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #53 = G_ADD
    { 52,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #52 = G_ASSERT_ALIGN
    { 51,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #51 = G_ASSERT_ZEXT
    { 50,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #50 = G_ASSERT_SEXT
    { 49,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #49 = CONVERGENCECTRL_GLUE
    { 48,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #48 = CONVERGENCECTRL_LOOP
    { 47,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #47 = CONVERGENCECTRL_ANCHOR
    { 46,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #46 = CONVERGENCECTRL_ENTRY
    { 45,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #45 = JUMP_TABLE_DEBUG_INFO
    { 44,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #44 = MEMBARRIER
    { 43,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #43 = FAKE_USE
    { 42,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #42 = ICALL_BRANCH_FUNNEL
    { 41,	3,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	37,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #41 = PATCHABLE_TYPED_EVENT_CALL
    { 40,	2,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	35,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #40 = PATCHABLE_EVENT_CALL
    { 39,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #39 = PATCHABLE_TAIL_CALL
    { 38,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #38 = PATCHABLE_FUNCTION_EXIT
    { 37,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #37 = PATCHABLE_RET
    { 36,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #36 = PATCHABLE_FUNCTION_ENTER
    { 35,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #35 = PATCHABLE_OP
    { 34,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #34 = FAULTING_OP
    { 33,	2,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	33,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #33 = LOCAL_ESCAPE
    { 32,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #32 = STATEPOINT
    { 31,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	30,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #31 = PREALLOCATED_ARG
    { 30,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #30 = PREALLOCATED_SETUP
    { 29,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	29,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #29 = LOAD_STACK_GUARD
    { 28,	6,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	23,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #28 = PATCHPOINT
    { 27,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #27 = FENTRY_CALL
    { 26,	2,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #26 = STACKMAP
    { 25,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	19,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #25 = ARITH_FENCE
    { 24,	4,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	15,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #24 = PSEUDO_PROBE
    { 23,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #23 = LIFETIME_END
    { 22,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #22 = LIFETIME_START
    { 21,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #21 = BUNDLE
    { 20,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #20 = COPY
    { 19,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #19 = REG_SEQUENCE
    { 18,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #18 = DBG_LABEL
    { 17,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #17 = DBG_PHI
    { 16,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #16 = DBG_INSTR_REF
    { 15,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #15 = DBG_VALUE_LIST
    { 14,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #14 = DBG_VALUE
    { 13,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #13 = COPY_TO_REGCLASS
    { 12,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #12 = SUBREG_TO_REG
    { 11,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #11 = INIT_UNDEF
    { 10,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #10 = IMPLICIT_DEF
    { 9,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	5,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #9 = INSERT_SUBREG
    { 8,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #8 = EXTRACT_SUBREG
    { 7,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #7 = KILL
    { 6,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #6 = ANNOTATION_LABEL
    { 5,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #5 = GC_LABEL
    { 4,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #4 = EH_LABEL
    { 3,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #3 = CFI_INSTRUCTION
    { 2,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #2 = INLINEASM_BR
    { 1,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1 = INLINEASM
    { 0,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #0 = PHI
  }, {
    /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 1 */
    /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
    /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
    /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 152 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 154 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 156 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 157 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 160 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 164 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 167 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 170 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 173 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 175 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 177 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 182 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 186 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 191 */ { XCore::RRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 193 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 199 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 205 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 208 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 210 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
  }, {
    /* 0 */
    /* 0 */ XCore::SP, XCore::SP,
    /* 2 */ XCore::SP, XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R11, XCore::LR,
    /* 9 */ XCore::R11,
    /* 10 */ XCore::SP,
  }
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char XCoreInstrNameData[] = {
  /* 0 */ "G_FLOG10\0"
  /* 9 */ "G_FEXP10\0"
  /* 18 */ "LDAPB_u10\0"
  /* 28 */ "BLRB_u10\0"
  /* 37 */ "LDAPF_u10\0"
  /* 47 */ "BLRF_u10\0"
  /* 56 */ "BLACP_u10\0"
  /* 66 */ "LDWCP_u10\0"
  /* 76 */ "LDAPB_lu10\0"
  /* 87 */ "BLRB_lu10\0"
  /* 97 */ "LDAPF_lu10\0"
  /* 108 */ "BLRF_lu10\0"
  /* 118 */ "BLACP_lu10\0"
  /* 129 */ "LDWCP_lu10\0"
  /* 140 */ "BR_JT32\0"
  /* 148 */ "G_FLOG2\0"
  /* 156 */ "G_FATAN2\0"
  /* 165 */ "G_FEXP2\0"
  /* 173 */ "KCALL_u6\0"
  /* 182 */ "LDAWCP_u6\0"
  /* 192 */ "EXTDP_u6\0"
  /* 201 */ "RETSP_u6\0"
  /* 210 */ "KENTSP_u6\0"
  /* 220 */ "KRESTSP_u6\0"
  /* 231 */ "EXTSP_u6\0"
  /* 240 */ "CLRSR_u6\0"
  /* 249 */ "GETSR_u6\0"
  /* 258 */ "SETSR_u6\0"
  /* 267 */ "BLAT_u6\0"
  /* 275 */ "BRBU_u6\0"
  /* 283 */ "BRFU_u6\0"
  /* 291 */ "CLRSR_branch_u6\0"
  /* 307 */ "SETSR_branch_u6\0"
  /* 323 */ "KCALL_lu6\0"
  /* 333 */ "LDAWCP_lu6\0"
  /* 344 */ "EXTDP_lu6\0"
  /* 354 */ "RETSP_lu6\0"
  /* 364 */ "KENTSP_lu6\0"
  /* 375 */ "KRESTSP_lu6\0"
  /* 387 */ "EXTSP_lu6\0"
  /* 397 */ "CLRSR_lu6\0"
  /* 407 */ "GETSR_lu6\0"
  /* 417 */ "SETSR_lu6\0"
  /* 427 */ "BLAT_lu6\0"
  /* 436 */ "BRBU_lu6\0"
  /* 445 */ "BRFU_lu6\0"
  /* 454 */ "CLRSR_branch_lu6\0"
  /* 471 */ "SETSR_branch_lu6\0"
  /* 488 */ "LDC_ru6\0"
  /* 496 */ "SETC_ru6\0"
  /* 505 */ "BRBF_ru6\0"
  /* 514 */ "BRFF_ru6\0"
  /* 523 */ "LDWCP_ru6\0"
  /* 533 */ "LDAWDP_ru6\0"
  /* 544 */ "LDWDP_ru6\0"
  /* 554 */ "STWDP_ru6\0"
  /* 564 */ "LDAWSP_ru6\0"
  /* 575 */ "LDWSP_ru6\0"
  /* 585 */ "STWSP_ru6\0"
  /* 595 */ "BRBT_ru6\0"
  /* 604 */ "BRFT_ru6\0"
  /* 613 */ "LDC_lru6\0"
  /* 622 */ "SETC_lru6\0"
  /* 632 */ "BRBF_lru6\0"
  /* 642 */ "BRFF_lru6\0"
  /* 652 */ "LDWCP_lru6\0"
  /* 663 */ "LDAWDP_lru6\0"
  /* 675 */ "LDWDP_lru6\0"
  /* 686 */ "STWDP_lru6\0"
  /* 697 */ "LDAWSP_lru6\0"
  /* 709 */ "LDWSP_lru6\0"
  /* 720 */ "STWSP_lru6\0"
  /* 731 */ "BRBT_lru6\0"
  /* 741 */ "BRFT_lru6\0"
  /* 751 */ "G_FMA\0"
  /* 757 */ "G_STRICT_FMA\0"
  /* 770 */ "G_FSUB\0"
  /* 777 */ "G_STRICT_FSUB\0"
  /* 791 */ "G_ATOMICRMW_FSUB\0"
  /* 808 */ "G_SUB\0"
  /* 814 */ "G_ATOMICRMW_SUB\0"
  /* 830 */ "SELECT_CC\0"
  /* 840 */ "G_INTRINSIC\0"
  /* 852 */ "G_FPTRUNC\0"
  /* 862 */ "G_INTRINSIC_TRUNC\0"
  /* 880 */ "G_TRUNC\0"
  /* 888 */ "G_BUILD_VECTOR_TRUNC\0"
  /* 909 */ "G_DYN_STACKALLOC\0"
  /* 926 */ "G_FMAD\0"
  /* 933 */ "G_INDEXED_SEXTLOAD\0"
  /* 952 */ "G_SEXTLOAD\0"
  /* 963 */ "G_INDEXED_ZEXTLOAD\0"
  /* 982 */ "G_ZEXTLOAD\0"
  /* 993 */ "G_INDEXED_LOAD\0"
  /* 1008 */ "G_LOAD\0"
  /* 1015 */ "G_VECREDUCE_FADD\0"
  /* 1032 */ "G_FADD\0"
  /* 1039 */ "G_VECREDUCE_SEQ_FADD\0"
  /* 1060 */ "G_STRICT_FADD\0"
  /* 1074 */ "G_ATOMICRMW_FADD\0"
  /* 1091 */ "G_VECREDUCE_ADD\0"
  /* 1107 */ "G_ADD\0"
  /* 1113 */ "G_PTR_ADD\0"
  /* 1123 */ "G_ATOMICRMW_ADD\0"
  /* 1139 */ "G_ATOMICRMW_NAND\0"
  /* 1156 */ "G_VECREDUCE_AND\0"
  /* 1172 */ "G_AND\0"
  /* 1178 */ "G_ATOMICRMW_AND\0"
  /* 1194 */ "LIFETIME_END\0"
  /* 1207 */ "G_BRCOND\0"
  /* 1216 */ "G_ATOMICRMW_USUB_COND\0"
  /* 1238 */ "G_LLROUND\0"
  /* 1248 */ "G_LROUND\0"
  /* 1257 */ "G_INTRINSIC_ROUND\0"
  /* 1275 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
  /* 1301 */ "LOAD_STACK_GUARD\0"
  /* 1318 */ "PSEUDO_PROBE\0"
  /* 1331 */ "G_SSUBE\0"
  /* 1339 */ "G_USUBE\0"
  /* 1347 */ "G_FENCE\0"
  /* 1355 */ "ARITH_FENCE\0"
  /* 1367 */ "REG_SEQUENCE\0"
  /* 1380 */ "G_SADDE\0"
  /* 1388 */ "G_UADDE\0"
  /* 1396 */ "G_GET_FPMODE\0"
  /* 1409 */ "G_RESET_FPMODE\0"
  /* 1424 */ "G_SET_FPMODE\0"
  /* 1437 */ "G_FMINNUM_IEEE\0"
  /* 1452 */ "G_FMAXNUM_IEEE\0"
  /* 1467 */ "G_VSCALE\0"
  /* 1476 */ "G_JUMP_TABLE\0"
  /* 1489 */ "BUNDLE\0"
  /* 1496 */ "G_MEMCPY_INLINE\0"
  /* 1512 */ "LOCAL_ESCAPE\0"
  /* 1525 */ "G_STACKRESTORE\0"
  /* 1540 */ "G_INDEXED_STORE\0"
  /* 1556 */ "G_STORE\0"
  /* 1564 */ "G_BITREVERSE\0"
  /* 1577 */ "FAKE_USE\0"
  /* 1586 */ "DBG_VALUE\0"
  /* 1596 */ "G_GLOBAL_VALUE\0"
  /* 1611 */ "G_PTRAUTH_GLOBAL_VALUE\0"
  /* 1634 */ "CONVERGENCECTRL_GLUE\0"
  /* 1655 */ "G_STACKSAVE\0"
  /* 1667 */ "G_MEMMOVE\0"
  /* 1677 */ "G_FREEZE\0"
  /* 1686 */ "G_FCANONICALIZE\0"
  /* 1702 */ "G_CTLZ_ZERO_UNDEF\0"
  /* 1720 */ "G_CTTZ_ZERO_UNDEF\0"
  /* 1738 */ "INIT_UNDEF\0"
  /* 1749 */ "G_IMPLICIT_DEF\0"
  /* 1764 */ "DBG_INSTR_REF\0"
  /* 1778 */ "G_FNEG\0"
  /* 1785 */ "EXTRACT_SUBREG\0"
  /* 1800 */ "INSERT_SUBREG\0"
  /* 1814 */ "G_SEXT_INREG\0"
  /* 1827 */ "SUBREG_TO_REG\0"
  /* 1841 */ "G_ATOMIC_CMPXCHG\0"
  /* 1858 */ "G_ATOMICRMW_XCHG\0"
  /* 1875 */ "G_FLOG\0"
  /* 1882 */ "G_VAARG\0"
  /* 1890 */ "PREALLOCATED_ARG\0"
  /* 1907 */ "G_PREFETCH\0"
  /* 1918 */ "G_SMULH\0"
  /* 1926 */ "G_UMULH\0"
  /* 1934 */ "G_FTANH\0"
  /* 1942 */ "G_FSINH\0"
  /* 1950 */ "G_FCOSH\0"
  /* 1958 */ "LDAWFI\0"
  /* 1965 */ "LDWFI\0"
  /* 1971 */ "STWFI\0"
  /* 1977 */ "DBG_PHI\0"
  /* 1985 */ "G_FPTOSI\0"
  /* 1994 */ "G_FPTOUI\0"
  /* 2003 */ "G_FPOWI\0"
  /* 2011 */ "G_PTRMASK\0"
  /* 2021 */ "GC_LABEL\0"
  /* 2030 */ "DBG_LABEL\0"
  /* 2040 */ "EH_LABEL\0"
  /* 2049 */ "ANNOTATION_LABEL\0"
  /* 2066 */ "ICALL_BRANCH_FUNNEL\0"
  /* 2086 */ "G_FSHL\0"
  /* 2093 */ "G_SHL\0"
  /* 2099 */ "G_FCEIL\0"
  /* 2107 */ "PATCHABLE_TAIL_CALL\0"
  /* 2127 */ "PATCHABLE_TYPED_EVENT_CALL\0"
  /* 2154 */ "PATCHABLE_EVENT_CALL\0"
  /* 2175 */ "FENTRY_CALL\0"
  /* 2187 */ "KILL\0"
  /* 2192 */ "G_CONSTANT_POOL\0"
  /* 2208 */ "G_ROTL\0"
  /* 2215 */ "G_VECREDUCE_FMUL\0"
  /* 2232 */ "G_FMUL\0"
  /* 2239 */ "G_VECREDUCE_SEQ_FMUL\0"
  /* 2260 */ "G_STRICT_FMUL\0"
  /* 2274 */ "G_VECREDUCE_MUL\0"
  /* 2290 */ "G_MUL\0"
  /* 2296 */ "G_FREM\0"
  /* 2303 */ "G_STRICT_FREM\0"
  /* 2317 */ "G_SREM\0"
  /* 2324 */ "G_UREM\0"
  /* 2331 */ "G_SDIVREM\0"
  /* 2341 */ "G_UDIVREM\0"
  /* 2351 */ "INLINEASM\0"
  /* 2361 */ "G_VECREDUCE_FMINIMUM\0"
  /* 2382 */ "G_FMINIMUM\0"
  /* 2393 */ "G_VECREDUCE_FMAXIMUM\0"
  /* 2414 */ "G_FMAXIMUM\0"
  /* 2425 */ "G_FMINNUM\0"
  /* 2435 */ "G_FMAXNUM\0"
  /* 2445 */ "G_FATAN\0"
  /* 2453 */ "G_FTAN\0"
  /* 2460 */ "G_INTRINSIC_ROUNDEVEN\0"
  /* 2482 */ "G_ASSERT_ALIGN\0"
  /* 2497 */ "G_FCOPYSIGN\0"
  /* 2509 */ "G_VECREDUCE_FMIN\0"
  /* 2526 */ "G_ATOMICRMW_FMIN\0"
  /* 2543 */ "G_VECREDUCE_SMIN\0"
  /* 2560 */ "G_SMIN\0"
  /* 2567 */ "G_VECREDUCE_UMIN\0"
  /* 2584 */ "G_UMIN\0"
  /* 2591 */ "G_ATOMICRMW_UMIN\0"
  /* 2608 */ "G_ATOMICRMW_MIN\0"
  /* 2624 */ "G_FASIN\0"
  /* 2632 */ "G_FSIN\0"
  /* 2639 */ "CFI_INSTRUCTION\0"
  /* 2655 */ "EH_RETURN\0"
  /* 2665 */ "ADJCALLSTACKDOWN\0"
  /* 2682 */ "G_SSUBO\0"
  /* 2690 */ "G_USUBO\0"
  /* 2698 */ "G_SADDO\0"
  /* 2706 */ "G_UADDO\0"
  /* 2714 */ "JUMP_TABLE_DEBUG_INFO\0"
  /* 2736 */ "G_SMULO\0"
  /* 2744 */ "G_UMULO\0"
  /* 2752 */ "G_BZERO\0"
  /* 2760 */ "STACKMAP\0"
  /* 2769 */ "G_DEBUGTRAP\0"
  /* 2781 */ "G_UBSANTRAP\0"
  /* 2793 */ "G_TRAP\0"
  /* 2800 */ "G_ATOMICRMW_UDEC_WRAP\0"
  /* 2822 */ "G_ATOMICRMW_UINC_WRAP\0"
  /* 2844 */ "G_BSWAP\0"
  /* 2852 */ "G_SITOFP\0"
  /* 2861 */ "G_UITOFP\0"
  /* 2870 */ "G_FCMP\0"
  /* 2877 */ "G_ICMP\0"
  /* 2884 */ "G_SCMP\0"
  /* 2891 */ "G_UCMP\0"
  /* 2898 */ "CONVERGENCECTRL_LOOP\0"
  /* 2919 */ "G_CTPOP\0"
  /* 2927 */ "PATCHABLE_OP\0"
  /* 2940 */ "FAULTING_OP\0"
  /* 2952 */ "ADJCALLSTACKUP\0"
  /* 2967 */ "PREALLOCATED_SETUP\0"
  /* 2986 */ "G_FLDEXP\0"
  /* 2995 */ "G_STRICT_FLDEXP\0"
  /* 3011 */ "G_FEXP\0"
  /* 3018 */ "G_FFREXP\0"
  /* 3027 */ "LDSPC_0R\0"
  /* 3036 */ "STSPC_0R\0"
  /* 3045 */ "LDSED_0R\0"
  /* 3054 */ "STSED_0R\0"
  /* 3063 */ "GETED_0R\0"
  /* 3072 */ "GETID_0R\0"
  /* 3081 */ "CLRE_0R\0"
  /* 3089 */ "DCALL_0R\0"
  /* 3098 */ "GETKEP_0R\0"
  /* 3108 */ "SETKEP_0R\0"
  /* 3118 */ "GETKSP_0R\0"
  /* 3128 */ "DENTSP_0R\0"
  /* 3138 */ "DRESTSP_0R\0"
  /* 3149 */ "LDSSR_0R\0"
  /* 3158 */ "STSSR_0R\0"
  /* 3167 */ "LDET_0R\0"
  /* 3175 */ "FREET_0R\0"
  /* 3184 */ "DRET_0R\0"
  /* 3192 */ "KRET_0R\0"
  /* 3200 */ "GETET_0R\0"
  /* 3209 */ "STET_0R\0"
  /* 3217 */ "WAITEU_0R\0"
  /* 3227 */ "WAITEF_1R\0"
  /* 3237 */ "WAITET_1R\0"
  /* 3247 */ "CLRPT_1R\0"
  /* 3256 */ "TSTART_1R\0"
  /* 3266 */ "G_BR\0"
  /* 3271 */ "INLINEASM_BR\0"
  /* 3284 */ "G_BLOCK_ADDR\0"
  /* 3297 */ "MEMBARRIER\0"
  /* 3308 */ "G_CONSTANT_FOLD_BARRIER\0"
  /* 3332 */ "PATCHABLE_FUNCTION_ENTER\0"
  /* 3357 */ "G_READCYCLECOUNTER\0"
  /* 3376 */ "G_READSTEADYCOUNTER\0"
  /* 3396 */ "G_READ_REGISTER\0"
  /* 3412 */ "G_WRITE_REGISTER\0"
  /* 3429 */ "G_ASHR\0"
  /* 3436 */ "G_FSHR\0"
  /* 3443 */ "G_LSHR\0"
  /* 3450 */ "CONVERGENCECTRL_ANCHOR\0"
  /* 3473 */ "G_FFLOOR\0"
  /* 3482 */ "G_EXTRACT_SUBVECTOR\0"
  /* 3502 */ "G_INSERT_SUBVECTOR\0"
  /* 3521 */ "G_BUILD_VECTOR\0"
  /* 3536 */ "G_SHUFFLE_VECTOR\0"
  /* 3553 */ "G_SPLAT_VECTOR\0"
  /* 3568 */ "G_VECREDUCE_XOR\0"
  /* 3584 */ "G_XOR\0"
  /* 3590 */ "G_ATOMICRMW_XOR\0"
  /* 3606 */ "G_VECREDUCE_OR\0"
  /* 3621 */ "G_OR\0"
  /* 3626 */ "G_ATOMICRMW_OR\0"
  /* 3641 */ "G_ROTR\0"
  /* 3648 */ "G_INTTOPTR\0"
  /* 3659 */ "G_FABS\0"
  /* 3666 */ "G_ABS\0"
  /* 3672 */ "G_UNMERGE_VALUES\0"
  /* 3689 */ "G_MERGE_VALUES\0"
  /* 3704 */ "G_FACOS\0"
  /* 3712 */ "G_FCOS\0"
  /* 3719 */ "G_CONCAT_VECTORS\0"
  /* 3736 */ "COPY_TO_REGCLASS\0"
  /* 3753 */ "G_IS_FPCLASS\0"
  /* 3766 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
  /* 3796 */ "G_VECTOR_COMPRESS\0"
  /* 3814 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
  /* 3841 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
  /* 3879 */ "G_SSUBSAT\0"
  /* 3889 */ "G_USUBSAT\0"
  /* 3899 */ "G_SADDSAT\0"
  /* 3909 */ "G_UADDSAT\0"
  /* 3919 */ "G_SSHLSAT\0"
  /* 3929 */ "G_USHLSAT\0"
  /* 3939 */ "G_SMULFIXSAT\0"
  /* 3952 */ "G_UMULFIXSAT\0"
  /* 3965 */ "G_SDIVFIXSAT\0"
  /* 3978 */ "G_UDIVFIXSAT\0"
  /* 3991 */ "G_ATOMICRMW_USUB_SAT\0"
  /* 4012 */ "G_FPTOSI_SAT\0"
  /* 4025 */ "G_FPTOUI_SAT\0"
  /* 4038 */ "G_EXTRACT\0"
  /* 4048 */ "G_SELECT\0"
  /* 4057 */ "G_BRINDIRECT\0"
  /* 4070 */ "PATCHABLE_RET\0"
  /* 4084 */ "FRAME_TO_ARGS_OFFSET\0"
  /* 4105 */ "G_MEMSET\0"
  /* 4114 */ "PATCHABLE_FUNCTION_EXIT\0"
  /* 4138 */ "G_BRJT\0"
  /* 4145 */ "BR_JT\0"
  /* 4151 */ "G_EXTRACT_VECTOR_ELT\0"
  /* 4172 */ "G_INSERT_VECTOR_ELT\0"
  /* 4192 */ "G_FCONSTANT\0"
  /* 4204 */ "G_CONSTANT\0"
  /* 4215 */ "G_INTRINSIC_CONVERGENT\0"
  /* 4238 */ "STATEPOINT\0"
  /* 4249 */ "PATCHPOINT\0"
  /* 4260 */ "G_PTRTOINT\0"
  /* 4271 */ "G_FRINT\0"
  /* 4279 */ "G_INTRINSIC_LLRINT\0"
  /* 4298 */ "G_INTRINSIC_LRINT\0"
  /* 4316 */ "G_FNEARBYINT\0"
  /* 4329 */ "NOT\0"
  /* 4333 */ "G_VASTART\0"
  /* 4343 */ "LIFETIME_START\0"
  /* 4358 */ "G_INVOKE_REGION_START\0"
  /* 4380 */ "G_INSERT\0"
  /* 4389 */ "G_FSQRT\0"
  /* 4397 */ "G_STRICT_FSQRT\0"
  /* 4412 */ "G_BITCAST\0"
  /* 4422 */ "G_ADDRSPACE_CAST\0"
  /* 4439 */ "DBG_VALUE_LIST\0"
  /* 4454 */ "G_FPEXT\0"
  /* 4462 */ "G_SEXT\0"
  /* 4469 */ "G_ASSERT_SEXT\0"
  /* 4483 */ "G_ANYEXT\0"
  /* 4492 */ "G_ZEXT\0"
  /* 4499 */ "G_ASSERT_ZEXT\0"
  /* 4513 */ "G_FDIV\0"
  /* 4520 */ "G_STRICT_FDIV\0"
  /* 4534 */ "G_SDIV\0"
  /* 4541 */ "G_UDIV\0"
  /* 4548 */ "G_GET_FPENV\0"
  /* 4560 */ "G_RESET_FPENV\0"
  /* 4574 */ "G_SET_FPENV\0"
  /* 4586 */ "G_FPOW\0"
  /* 4593 */ "G_VECREDUCE_FMAX\0"
  /* 4610 */ "G_ATOMICRMW_FMAX\0"
  /* 4627 */ "G_VECREDUCE_SMAX\0"
  /* 4644 */ "G_SMAX\0"
  /* 4651 */ "G_VECREDUCE_UMAX\0"
  /* 4668 */ "G_UMAX\0"
  /* 4675 */ "G_ATOMICRMW_UMAX\0"
  /* 4692 */ "G_ATOMICRMW_MAX\0"
  /* 4708 */ "G_FRAME_INDEX\0"
  /* 4722 */ "G_SBFX\0"
  /* 4729 */ "G_UBFX\0"
  /* 4736 */ "G_SMULFIX\0"
  /* 4746 */ "G_UMULFIX\0"
  /* 4756 */ "G_SDIVFIX\0"
  /* 4766 */ "G_UDIVFIX\0"
  /* 4776 */ "G_MEMCPY\0"
  /* 4785 */ "COPY\0"
  /* 4790 */ "CONVERGENCECTRL_ENTRY\0"
  /* 4812 */ "G_CTLZ\0"
  /* 4819 */ "G_CTTZ\0"
  /* 4826 */ "LDAPF_lu10_ba\0"
  /* 4840 */ "SSYNC_0r\0"
  /* 4849 */ "BLA_1r\0"
  /* 4856 */ "MSYNC_1r\0"
  /* 4865 */ "ECALLF_1r\0"
  /* 4875 */ "DGETREG_1r\0"
  /* 4886 */ "KCALL_1r\0"
  /* 4895 */ "MJOIN_1r\0"
  /* 4904 */ "SETCP_1r\0"
  /* 4913 */ "SETDP_1r\0"
  /* 4922 */ "SETSP_1r\0"
  /* 4931 */ "SYNCR_1r\0"
  /* 4940 */ "FREER_1r\0"
  /* 4949 */ "ECALLT_1r\0"
  /* 4959 */ "BAU_1r\0"
  /* 4966 */ "EDU_1r\0"
  /* 4973 */ "EEU_1r\0"
  /* 4980 */ "BRU_1r\0"
  /* 4987 */ "SETEV_1r\0"
  /* 4996 */ "SETV_1r\0"
  /* 5004 */ "INITPC_2r\0"
  /* 5014 */ "SETPSC_2r\0"
  /* 5024 */ "SETD_2r\0"
  /* 5032 */ "EEF_2r\0"
  /* 5039 */ "PEEK_2r\0"
  /* 5047 */ "MKMSK_2r\0"
  /* 5056 */ "ENDIN_2r\0"
  /* 5065 */ "INITCP_2r\0"
  /* 5075 */ "INITDP_2r\0"
  /* 5085 */ "INITSP_2r\0"
  /* 5095 */ "INSHR_2r\0"
  /* 5104 */ "OUTSHR_2r\0"
  /* 5114 */ "TSETMR_2r\0"
  /* 5124 */ "GETTS_2r\0"
  /* 5133 */ "CHKCT_2r\0"
  /* 5142 */ "INCT_2r\0"
  /* 5150 */ "TESTCT_2r\0"
  /* 5160 */ "OUTCT_2r\0"
  /* 5169 */ "TESTWCT_2r\0"
  /* 5180 */ "EET_2r\0"
  /* 5187 */ "INT_2r\0"
  /* 5194 */ "ANDNOT_2r\0"
  /* 5204 */ "SETPT_2r\0"
  /* 5213 */ "GETST_2r\0"
  /* 5222 */ "OUTT_2r\0"
  /* 5230 */ "OUT_2r\0"
  /* 5237 */ "SEXT_2r\0"
  /* 5245 */ "ZEXT_2r\0"
  /* 5253 */ "SETC_l2r\0"
  /* 5262 */ "GETD_l2r\0"
  /* 5271 */ "SETCLK_l2r\0"
  /* 5282 */ "TESTLCL_l2r\0"
  /* 5294 */ "GETN_l2r\0"
  /* 5303 */ "SETN_l2r\0"
  /* 5312 */ "INITLR_l2r\0"
  /* 5323 */ "GETPS_l2r\0"
  /* 5333 */ "SETPS_l2r\0"
  /* 5343 */ "BYTEREV_l2r\0"
  /* 5355 */ "BITREV_l2r\0"
  /* 5366 */ "SETTW_l2r\0"
  /* 5376 */ "SETRDY_l2r\0"
  /* 5387 */ "CLZ_l2r\0"
  /* 5395 */ "SUB_3r\0"
  /* 5402 */ "ADD_3r\0"
  /* 5409 */ "AND_3r\0"
  /* 5416 */ "SHL_3r\0"
  /* 5423 */ "EQ_3r\0"
  /* 5429 */ "SHR_3r\0"
  /* 5436 */ "OR_3r\0"
  /* 5442 */ "TSETR_3r\0"
  /* 5451 */ "LD16S_3r\0"
  /* 5460 */ "LSS_3r\0"
  /* 5467 */ "LD8U_3r\0"
  /* 5475 */ "LSU_3r\0"
  /* 5482 */ "LDW_3r\0"
  /* 5489 */ "ST16_l3r\0"
  /* 5498 */ "ST8_l3r\0"
  /* 5506 */ "LDA16B_l3r\0"
  /* 5517 */ "LDAWB_l3r\0"
  /* 5527 */ "CRC_l3r\0"
  /* 5535 */ "LDA16F_l3r\0"
  /* 5546 */ "LDAWF_l3r\0"
  /* 5556 */ "MUL_l3r\0"
  /* 5564 */ "ASHR_l3r\0"
  /* 5573 */ "XOR_l3r\0"
  /* 5581 */ "REMS_l3r\0"
  /* 5590 */ "DIVS_l3r\0"
  /* 5599 */ "REMU_l3r\0"
  /* 5608 */ "DIVU_l3r\0"
  /* 5617 */ "STW_l3r\0"
  /* 5625 */ "CRC8_l4r\0"
  /* 5634 */ "MACCS_l4r\0"
  /* 5644 */ "MACCU_l4r\0"
  /* 5654 */ "LSUB_l5r\0"
  /* 5663 */ "LADD_l5r\0"
  /* 5672 */ "LDIVU_l5r\0"
  /* 5682 */ "LMUL_l6r\0"
  /* 5691 */ "SUB_2rus\0"
  /* 5700 */ "ADD_2rus\0"
  /* 5709 */ "SHL_2rus\0"
  /* 5718 */ "EQ_2rus\0"
  /* 5726 */ "SHR_2rus\0"
  /* 5735 */ "LDW_2rus\0"
  /* 5744 */ "STW_2rus\0"
  /* 5753 */ "LDAWB_l2rus\0"
  /* 5765 */ "LDAWF_l2rus\0"
  /* 5777 */ "ASHR_l2rus\0"
  /* 5788 */ "INPW_l2rus\0"
  /* 5799 */ "OUTPW_l2rus\0"
  /* 5811 */ "MKMSK_rus\0"
  /* 5821 */ "GETR_rus\0"
  /* 5830 */ "CHKCT_rus\0"
  /* 5840 */ "OUTCT_rus\0"
  /* 5850 */ "SEXT_rus\0"
  /* 5859 */ "ZEXT_rus\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const unsigned XCoreInstrNameIndices[] = {
    1981U, 2351U, 3271U, 2639U, 2040U, 2021U, 2049U, 2187U, 
    1785U, 1800U, 1751U, 1738U, 1827U, 3736U, 1586U, 4439U, 
    1764U, 1977U, 2030U, 1367U, 4785U, 1489U, 4343U, 1194U, 
    1318U, 1355U, 2760U, 2175U, 4249U, 1301U, 2967U, 1890U, 
    4238U, 1512U, 2940U, 2927U, 3332U, 4070U, 4114U, 2107U, 
    2154U, 2127U, 2066U, 1577U, 3297U, 2714U, 4790U, 3450U, 
    2898U, 1634U, 4469U, 4499U, 2482U, 1107U, 808U, 2290U, 
    4534U, 4541U, 2317U, 2324U, 2331U, 2341U, 1172U, 3621U, 
    3584U, 1749U, 1979U, 4708U, 1596U, 1611U, 2192U, 4038U, 
    3672U, 4380U, 3689U, 3521U, 888U, 3719U, 4260U, 3648U, 
    4412U, 1677U, 3308U, 1275U, 862U, 1257U, 4298U, 4279U, 
    2460U, 3357U, 3376U, 1008U, 952U, 982U, 993U, 933U, 
    963U, 1556U, 1540U, 3766U, 1841U, 1858U, 1123U, 814U, 
    1178U, 1139U, 3626U, 3590U, 4692U, 2608U, 4675U, 2591U, 
    1074U, 791U, 4610U, 2526U, 2822U, 2800U, 1216U, 3991U, 
    1347U, 1907U, 1207U, 4057U, 4358U, 840U, 3814U, 4215U, 
    3841U, 4483U, 880U, 4204U, 4192U, 4333U, 1882U, 4462U, 
    1814U, 4492U, 2093U, 3443U, 3429U, 2086U, 3436U, 3641U, 
    2208U, 2877U, 2870U, 2884U, 2891U, 4048U, 2706U, 1388U, 
    2690U, 1339U, 2698U, 1380U, 2682U, 1331U, 2744U, 2736U, 
    1926U, 1918U, 3909U, 3899U, 3889U, 3879U, 3929U, 3919U, 
    4736U, 4746U, 3939U, 3952U, 4756U, 4766U, 3965U, 3978U, 
    1032U, 770U, 2232U, 751U, 926U, 4513U, 2296U, 4586U, 
    2003U, 3011U, 165U, 9U, 1875U, 148U, 0U, 2986U, 
    3018U, 1778U, 4454U, 852U, 1985U, 1994U, 2852U, 2861U, 
    4012U, 4025U, 3659U, 2497U, 3753U, 1686U, 2425U, 2435U, 
    1437U, 1452U, 2382U, 2414U, 4548U, 4574U, 4560U, 1396U, 
    1424U, 1409U, 1113U, 2011U, 2560U, 4644U, 2584U, 4668U, 
    3666U, 1248U, 1238U, 3266U, 4138U, 1467U, 3502U, 3482U, 
    4172U, 4151U, 3536U, 3553U, 3796U, 4819U, 1720U, 4812U, 
    1702U, 2919U, 2844U, 1564U, 2099U, 3712U, 2632U, 2453U, 
    3704U, 2624U, 2445U, 156U, 1950U, 1942U, 1934U, 4389U, 
    3473U, 4271U, 4316U, 4422U, 3284U, 1476U, 909U, 1655U, 
    1525U, 1060U, 777U, 2260U, 4520U, 2303U, 757U, 4397U, 
    2995U, 3396U, 3412U, 4776U, 1496U, 1667U, 4105U, 2752U, 
    2793U, 2769U, 2781U, 1039U, 2239U, 1015U, 2215U, 4593U, 
    2509U, 2393U, 2361U, 1091U, 2274U, 1156U, 3606U, 3568U, 
    4627U, 2543U, 4651U, 2567U, 4722U, 4729U, 2665U, 2952U, 
    4145U, 140U, 2655U, 4084U, 1958U, 1965U, 830U, 1971U, 
    5700U, 5402U, 5194U, 5409U, 5777U, 5564U, 4959U, 5355U, 
    118U, 56U, 427U, 267U, 4849U, 87U, 28U, 108U, 
    47U, 632U, 505U, 731U, 595U, 436U, 275U, 642U, 
    514U, 741U, 604U, 445U, 283U, 4980U, 5343U, 5133U, 
    5830U, 3081U, 3247U, 454U, 291U, 397U, 240U, 5387U, 
    5625U, 5527U, 3089U, 3128U, 4875U, 5590U, 5608U, 3138U, 
    3184U, 4865U, 4949U, 4966U, 5032U, 5180U, 4973U, 5056U, 
    365U, 211U, 5718U, 5423U, 344U, 192U, 387U, 231U, 
    4940U, 3175U, 5262U, 3063U, 3200U, 3072U, 3098U, 3118U, 
    5294U, 5323U, 5821U, 407U, 249U, 5213U, 5124U, 5142U, 
    5065U, 5075U, 5312U, 5004U, 5085U, 5788U, 5095U, 5187U, 
    5059U, 4886U, 323U, 173U, 364U, 210U, 375U, 220U, 
    3192U, 5663U, 5451U, 5467U, 5506U, 5535U, 76U, 18U, 
    97U, 4826U, 37U, 5753U, 5517U, 333U, 182U, 663U, 
    533U, 5765U, 5546U, 697U, 564U, 613U, 488U, 3167U, 
    5672U, 3045U, 3027U, 3149U, 652U, 129U, 523U, 66U, 
    675U, 544U, 709U, 575U, 5735U, 5482U, 5682U, 5460U, 
    5654U, 5475U, 5634U, 5644U, 4895U, 5047U, 5811U, 4856U, 
    5556U, 1781U, 4329U, 5436U, 5160U, 5840U, 5799U, 5104U, 
    5222U, 5230U, 5039U, 5581U, 5599U, 354U, 201U, 5271U, 
    4904U, 5253U, 622U, 496U, 4913U, 5024U, 4987U, 3108U, 
    5303U, 5014U, 5333U, 5204U, 5376U, 4922U, 471U, 307U, 
    417U, 258U, 5366U, 4996U, 5237U, 5850U, 5709U, 5416U, 
    5726U, 5429U, 4840U, 5489U, 5498U, 3209U, 3054U, 3036U, 
    3158U, 686U, 554U, 720U, 585U, 5744U, 5617U, 5691U, 
    5395U, 4931U, 5150U, 5282U, 5169U, 5114U, 5442U, 3256U, 
    3227U, 3237U, 3217U, 5573U, 5245U, 5859U, 
};

static inline void InitXCoreMCInstrInfo(MCInstrInfo *II) {
  II->InitMCInstrInfo(XCoreDescs.Insts, XCoreInstrNameIndices, XCoreInstrNameData, nullptr, nullptr, 526);
}

} // end namespace llvm
#endif // GET_INSTRINFO_MC_DESC

#ifdef GET_INSTRINFO_HEADER
#undef GET_INSTRINFO_HEADER
namespace llvm {
struct XCoreGenInstrInfo : public TargetInstrInfo {
  explicit XCoreGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
  ~XCoreGenInstrInfo() override = default;

};
} // end namespace llvm
#endif // GET_INSTRINFO_HEADER

#ifdef GET_INSTRINFO_HELPER_DECLS
#undef GET_INSTRINFO_HELPER_DECLS


#endif // GET_INSTRINFO_HELPER_DECLS

#ifdef GET_INSTRINFO_HELPERS
#undef GET_INSTRINFO_HELPERS

#endif // GET_INSTRINFO_HELPERS

#ifdef GET_INSTRINFO_CTOR_DTOR
#undef GET_INSTRINFO_CTOR_DTOR
namespace llvm {
extern const XCoreInstrTable XCoreDescs;
extern const unsigned XCoreInstrNameIndices[];
extern const char XCoreInstrNameData[];
XCoreGenInstrInfo::XCoreGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
  InitMCInstrInfo(XCoreDescs.Insts, XCoreInstrNameIndices, XCoreInstrNameData, nullptr, nullptr, 526);
}
} // end namespace llvm
#endif // GET_INSTRINFO_CTOR_DTOR

#ifdef GET_INSTRINFO_OPERAND_ENUM
#undef GET_INSTRINFO_OPERAND_ENUM
namespace llvm {
namespace XCore {
namespace OpName {
enum {
  OPERAND_LAST
};
} // end namespace OpName
} // end namespace XCore
} // end namespace llvm
#endif //GET_INSTRINFO_OPERAND_ENUM

#ifdef GET_INSTRINFO_NAMED_OPS
#undef GET_INSTRINFO_NAMED_OPS
namespace llvm {
namespace XCore {
LLVM_READONLY
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
  return -1;
}
} // end namespace XCore
} // end namespace llvm
#endif //GET_INSTRINFO_NAMED_OPS

#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
namespace llvm {
namespace XCore {
namespace OpTypes {
enum OperandType {
  InlineJT = 0,
  InlineJT32 = 1,
  MEMii = 2,
  brtarget = 3,
  brtarget_neg = 4,
  f32imm = 5,
  f64imm = 6,
  i1imm = 7,
  i8imm = 8,
  i16imm = 9,
  i32imm = 10,
  i64imm = 11,
  pcrel_imm = 12,
  pcrel_imm_neg = 13,
  ptype0 = 14,
  ptype1 = 15,
  ptype2 = 16,
  ptype3 = 17,
  ptype4 = 18,
  ptype5 = 19,
  type0 = 20,
  type1 = 21,
  type2 = 22,
  type3 = 23,
  type4 = 24,
  type5 = 25,
  untyped_imm_0 = 26,
  GRRegs = 27,
  RRegs = 28,
  OPERAND_TYPE_LIST_END
};
} // end namespace OpTypes
} // end namespace XCore
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM

#ifdef GET_INSTRINFO_OPERAND_TYPE
#undef GET_INSTRINFO_OPERAND_TYPE
namespace llvm {
namespace XCore {
LLVM_READONLY
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
  static const uint16_t Offsets[] = {
    /* PHI */
    0,
    /* INLINEASM */
    1,
    /* INLINEASM_BR */
    1,
    /* CFI_INSTRUCTION */
    1,
    /* EH_LABEL */
    2,
    /* GC_LABEL */
    3,
    /* ANNOTATION_LABEL */
    4,
    /* KILL */
    5,
    /* EXTRACT_SUBREG */
    5,
    /* INSERT_SUBREG */
    8,
    /* IMPLICIT_DEF */
    12,
    /* INIT_UNDEF */
    13,
    /* SUBREG_TO_REG */
    14,
    /* COPY_TO_REGCLASS */
    18,
    /* DBG_VALUE */
    21,
    /* DBG_VALUE_LIST */
    21,
    /* DBG_INSTR_REF */
    21,
    /* DBG_PHI */
    21,
    /* DBG_LABEL */
    21,
    /* REG_SEQUENCE */
    22,
    /* COPY */
    24,
    /* BUNDLE */
    26,
    /* LIFETIME_START */
    26,
    /* LIFETIME_END */
    27,
    /* PSEUDO_PROBE */
    28,
    /* ARITH_FENCE */
    32,
    /* STACKMAP */
    34,
    /* FENTRY_CALL */
    36,
    /* PATCHPOINT */
    36,
    /* LOAD_STACK_GUARD */
    42,
    /* PREALLOCATED_SETUP */
    43,
    /* PREALLOCATED_ARG */
    44,
    /* STATEPOINT */
    47,
    /* LOCAL_ESCAPE */
    47,
    /* FAULTING_OP */
    49,
    /* PATCHABLE_OP */
    50,
    /* PATCHABLE_FUNCTION_ENTER */
    50,
    /* PATCHABLE_RET */
    50,
    /* PATCHABLE_FUNCTION_EXIT */
    50,
    /* PATCHABLE_TAIL_CALL */
    50,
    /* PATCHABLE_EVENT_CALL */
    50,
    /* PATCHABLE_TYPED_EVENT_CALL */
    52,
    /* ICALL_BRANCH_FUNNEL */
    55,
    /* FAKE_USE */
    55,
    /* MEMBARRIER */
    55,
    /* JUMP_TABLE_DEBUG_INFO */
    55,
    /* CONVERGENCECTRL_ENTRY */
    56,
    /* CONVERGENCECTRL_ANCHOR */
    57,
    /* CONVERGENCECTRL_LOOP */
    58,
    /* CONVERGENCECTRL_GLUE */
    60,
    /* G_ASSERT_SEXT */
    61,
    /* G_ASSERT_ZEXT */
    64,
    /* G_ASSERT_ALIGN */
    67,
    /* G_ADD */
    70,
    /* G_SUB */
    73,
    /* G_MUL */
    76,
    /* G_SDIV */
    79,
    /* G_UDIV */
    82,
    /* G_SREM */
    85,
    /* G_UREM */
    88,
    /* G_SDIVREM */
    91,
    /* G_UDIVREM */
    95,
    /* G_AND */
    99,
    /* G_OR */
    102,
    /* G_XOR */
    105,
    /* G_IMPLICIT_DEF */
    108,
    /* G_PHI */
    109,
    /* G_FRAME_INDEX */
    110,
    /* G_GLOBAL_VALUE */
    112,
    /* G_PTRAUTH_GLOBAL_VALUE */
    114,
    /* G_CONSTANT_POOL */
    119,
    /* G_EXTRACT */
    121,
    /* G_UNMERGE_VALUES */
    124,
    /* G_INSERT */
    126,
    /* G_MERGE_VALUES */
    130,
    /* G_BUILD_VECTOR */
    132,
    /* G_BUILD_VECTOR_TRUNC */
    134,
    /* G_CONCAT_VECTORS */
    136,
    /* G_PTRTOINT */
    138,
    /* G_INTTOPTR */
    140,
    /* G_BITCAST */
    142,
    /* G_FREEZE */
    144,
    /* G_CONSTANT_FOLD_BARRIER */
    146,
    /* G_INTRINSIC_FPTRUNC_ROUND */
    148,
    /* G_INTRINSIC_TRUNC */
    151,
    /* G_INTRINSIC_ROUND */
    153,
    /* G_INTRINSIC_LRINT */
    155,
    /* G_INTRINSIC_LLRINT */
    157,
    /* G_INTRINSIC_ROUNDEVEN */
    159,
    /* G_READCYCLECOUNTER */
    161,
    /* G_READSTEADYCOUNTER */
    162,
    /* G_LOAD */
    163,
    /* G_SEXTLOAD */
    165,
    /* G_ZEXTLOAD */
    167,
    /* G_INDEXED_LOAD */
    169,
    /* G_INDEXED_SEXTLOAD */
    174,
    /* G_INDEXED_ZEXTLOAD */
    179,
    /* G_STORE */
    184,
    /* G_INDEXED_STORE */
    186,
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    191,
    /* G_ATOMIC_CMPXCHG */
    196,
    /* G_ATOMICRMW_XCHG */
    200,
    /* G_ATOMICRMW_ADD */
    203,
    /* G_ATOMICRMW_SUB */
    206,
    /* G_ATOMICRMW_AND */
    209,
    /* G_ATOMICRMW_NAND */
    212,
    /* G_ATOMICRMW_OR */
    215,
    /* G_ATOMICRMW_XOR */
    218,
    /* G_ATOMICRMW_MAX */
    221,
    /* G_ATOMICRMW_MIN */
    224,
    /* G_ATOMICRMW_UMAX */
    227,
    /* G_ATOMICRMW_UMIN */
    230,
    /* G_ATOMICRMW_FADD */
    233,
    /* G_ATOMICRMW_FSUB */
    236,
    /* G_ATOMICRMW_FMAX */
    239,
    /* G_ATOMICRMW_FMIN */
    242,
    /* G_ATOMICRMW_UINC_WRAP */
    245,
    /* G_ATOMICRMW_UDEC_WRAP */
    248,
    /* G_ATOMICRMW_USUB_COND */
    251,
    /* G_ATOMICRMW_USUB_SAT */
    254,
    /* G_FENCE */
    257,
    /* G_PREFETCH */
    259,
    /* G_BRCOND */
    263,
    /* G_BRINDIRECT */
    265,
    /* G_INVOKE_REGION_START */
    266,
    /* G_INTRINSIC */
    266,
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    267,
    /* G_INTRINSIC_CONVERGENT */
    268,
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    269,
    /* G_ANYEXT */
    270,
    /* G_TRUNC */
    272,
    /* G_CONSTANT */
    274,
    /* G_FCONSTANT */
    276,
    /* G_VASTART */
    278,
    /* G_VAARG */
    279,
    /* G_SEXT */
    282,
    /* G_SEXT_INREG */
    284,
    /* G_ZEXT */
    287,
    /* G_SHL */
    289,
    /* G_LSHR */
    292,
    /* G_ASHR */
    295,
    /* G_FSHL */
    298,
    /* G_FSHR */
    302,
    /* G_ROTR */
    306,
    /* G_ROTL */
    309,
    /* G_ICMP */
    312,
    /* G_FCMP */
    316,
    /* G_SCMP */
    320,
    /* G_UCMP */
    323,
    /* G_SELECT */
    326,
    /* G_UADDO */
    330,
    /* G_UADDE */
    334,
    /* G_USUBO */
    339,
    /* G_USUBE */
    343,
    /* G_SADDO */
    348,
    /* G_SADDE */
    352,
    /* G_SSUBO */
    357,
    /* G_SSUBE */
    361,
    /* G_UMULO */
    366,
    /* G_SMULO */
    370,
    /* G_UMULH */
    374,
    /* G_SMULH */
    377,
    /* G_UADDSAT */
    380,
    /* G_SADDSAT */
    383,
    /* G_USUBSAT */
    386,
    /* G_SSUBSAT */
    389,
    /* G_USHLSAT */
    392,
    /* G_SSHLSAT */
    395,
    /* G_SMULFIX */
    398,
    /* G_UMULFIX */
    402,
    /* G_SMULFIXSAT */
    406,
    /* G_UMULFIXSAT */
    410,
    /* G_SDIVFIX */
    414,
    /* G_UDIVFIX */
    418,
    /* G_SDIVFIXSAT */
    422,
    /* G_UDIVFIXSAT */
    426,
    /* G_FADD */
    430,
    /* G_FSUB */
    433,
    /* G_FMUL */
    436,
    /* G_FMA */
    439,
    /* G_FMAD */
    443,
    /* G_FDIV */
    447,
    /* G_FREM */
    450,
    /* G_FPOW */
    453,
    /* G_FPOWI */
    456,
    /* G_FEXP */
    459,
    /* G_FEXP2 */
    461,
    /* G_FEXP10 */
    463,
    /* G_FLOG */
    465,
    /* G_FLOG2 */
    467,
    /* G_FLOG10 */
    469,
    /* G_FLDEXP */
    471,
    /* G_FFREXP */
    474,
    /* G_FNEG */
    477,
    /* G_FPEXT */
    479,
    /* G_FPTRUNC */
    481,
    /* G_FPTOSI */
    483,
    /* G_FPTOUI */
    485,
    /* G_SITOFP */
    487,
    /* G_UITOFP */
    489,
    /* G_FPTOSI_SAT */
    491,
    /* G_FPTOUI_SAT */
    493,
    /* G_FABS */
    495,
    /* G_FCOPYSIGN */
    497,
    /* G_IS_FPCLASS */
    500,
    /* G_FCANONICALIZE */
    503,
    /* G_FMINNUM */
    505,
    /* G_FMAXNUM */
    508,
    /* G_FMINNUM_IEEE */
    511,
    /* G_FMAXNUM_IEEE */
    514,
    /* G_FMINIMUM */
    517,
    /* G_FMAXIMUM */
    520,
    /* G_GET_FPENV */
    523,
    /* G_SET_FPENV */
    524,
    /* G_RESET_FPENV */
    525,
    /* G_GET_FPMODE */
    525,
    /* G_SET_FPMODE */
    526,
    /* G_RESET_FPMODE */
    527,
    /* G_PTR_ADD */
    527,
    /* G_PTRMASK */
    530,
    /* G_SMIN */
    533,
    /* G_SMAX */
    536,
    /* G_UMIN */
    539,
    /* G_UMAX */
    542,
    /* G_ABS */
    545,
    /* G_LROUND */
    547,
    /* G_LLROUND */
    549,
    /* G_BR */
    551,
    /* G_BRJT */
    552,
    /* G_VSCALE */
    555,
    /* G_INSERT_SUBVECTOR */
    557,
    /* G_EXTRACT_SUBVECTOR */
    561,
    /* G_INSERT_VECTOR_ELT */
    564,
    /* G_EXTRACT_VECTOR_ELT */
    568,
    /* G_SHUFFLE_VECTOR */
    571,
    /* G_SPLAT_VECTOR */
    575,
    /* G_VECTOR_COMPRESS */
    577,
    /* G_CTTZ */
    581,
    /* G_CTTZ_ZERO_UNDEF */
    583,
    /* G_CTLZ */
    585,
    /* G_CTLZ_ZERO_UNDEF */
    587,
    /* G_CTPOP */
    589,
    /* G_BSWAP */
    591,
    /* G_BITREVERSE */
    593,
    /* G_FCEIL */
    595,
    /* G_FCOS */
    597,
    /* G_FSIN */
    599,
    /* G_FTAN */
    601,
    /* G_FACOS */
    603,
    /* G_FASIN */
    605,
    /* G_FATAN */
    607,
    /* G_FATAN2 */
    609,
    /* G_FCOSH */
    612,
    /* G_FSINH */
    614,
    /* G_FTANH */
    616,
    /* G_FSQRT */
    618,
    /* G_FFLOOR */
    620,
    /* G_FRINT */
    622,
    /* G_FNEARBYINT */
    624,
    /* G_ADDRSPACE_CAST */
    626,
    /* G_BLOCK_ADDR */
    628,
    /* G_JUMP_TABLE */
    630,
    /* G_DYN_STACKALLOC */
    632,
    /* G_STACKSAVE */
    635,
    /* G_STACKRESTORE */
    636,
    /* G_STRICT_FADD */
    637,
    /* G_STRICT_FSUB */
    640,
    /* G_STRICT_FMUL */
    643,
    /* G_STRICT_FDIV */
    646,
    /* G_STRICT_FREM */
    649,
    /* G_STRICT_FMA */
    652,
    /* G_STRICT_FSQRT */
    656,
    /* G_STRICT_FLDEXP */
    658,
    /* G_READ_REGISTER */
    661,
    /* G_WRITE_REGISTER */
    663,
    /* G_MEMCPY */
    665,
    /* G_MEMCPY_INLINE */
    669,
    /* G_MEMMOVE */
    672,
    /* G_MEMSET */
    676,
    /* G_BZERO */
    680,
    /* G_TRAP */
    683,
    /* G_DEBUGTRAP */
    683,
    /* G_UBSANTRAP */
    683,
    /* G_VECREDUCE_SEQ_FADD */
    684,
    /* G_VECREDUCE_SEQ_FMUL */
    687,
    /* G_VECREDUCE_FADD */
    690,
    /* G_VECREDUCE_FMUL */
    692,
    /* G_VECREDUCE_FMAX */
    694,
    /* G_VECREDUCE_FMIN */
    696,
    /* G_VECREDUCE_FMAXIMUM */
    698,
    /* G_VECREDUCE_FMINIMUM */
    700,
    /* G_VECREDUCE_ADD */
    702,
    /* G_VECREDUCE_MUL */
    704,
    /* G_VECREDUCE_AND */
    706,
    /* G_VECREDUCE_OR */
    708,
    /* G_VECREDUCE_XOR */
    710,
    /* G_VECREDUCE_SMAX */
    712,
    /* G_VECREDUCE_SMIN */
    714,
    /* G_VECREDUCE_UMAX */
    716,
    /* G_VECREDUCE_UMIN */
    718,
    /* G_SBFX */
    720,
    /* G_UBFX */
    724,
    /* ADJCALLSTACKDOWN */
    728,
    /* ADJCALLSTACKUP */
    730,
    /* BR_JT */
    732,
    /* BR_JT32 */
    734,
    /* EH_RETURN */
    736,
    /* FRAME_TO_ARGS_OFFSET */
    738,
    /* LDAWFI */
    739,
    /* LDWFI */
    742,
    /* SELECT_CC */
    745,
    /* STWFI */
    749,
    /* ADD_2rus */
    752,
    /* ADD_3r */
    755,
    /* ANDNOT_2r */
    758,
    /* AND_3r */
    761,
    /* ASHR_l2rus */
    764,
    /* ASHR_l3r */
    767,
    /* BAU_1r */
    770,
    /* BITREV_l2r */
    771,
    /* BLACP_lu10 */
    773,
    /* BLACP_u10 */
    774,
    /* BLAT_lu6 */
    775,
    /* BLAT_u6 */
    776,
    /* BLA_1r */
    777,
    /* BLRB_lu10 */
    778,
    /* BLRB_u10 */
    779,
    /* BLRF_lu10 */
    780,
    /* BLRF_u10 */
    781,
    /* BRBF_lru6 */
    782,
    /* BRBF_ru6 */
    784,
    /* BRBT_lru6 */
    786,
    /* BRBT_ru6 */
    788,
    /* BRBU_lu6 */
    790,
    /* BRBU_u6 */
    791,
    /* BRFF_lru6 */
    792,
    /* BRFF_ru6 */
    794,
    /* BRFT_lru6 */
    796,
    /* BRFT_ru6 */
    798,
    /* BRFU_lu6 */
    800,
    /* BRFU_u6 */
    801,
    /* BRU_1r */
    802,
    /* BYTEREV_l2r */
    803,
    /* CHKCT_2r */
    805,
    /* CHKCT_rus */
    807,
    /* CLRE_0R */
    809,
    /* CLRPT_1R */
    809,
    /* CLRSR_branch_lu6 */
    810,
    /* CLRSR_branch_u6 */
    811,
    /* CLRSR_lu6 */
    812,
    /* CLRSR_u6 */
    813,
    /* CLZ_l2r */
    814,
    /* CRC8_l4r */
    816,
    /* CRC_l3r */
    821,
    /* DCALL_0R */
    825,
    /* DENTSP_0R */
    825,
    /* DGETREG_1r */
    825,
    /* DIVS_l3r */
    826,
    /* DIVU_l3r */
    829,
    /* DRESTSP_0R */
    832,
    /* DRET_0R */
    832,
    /* ECALLF_1r */
    832,
    /* ECALLT_1r */
    833,
    /* EDU_1r */
    834,
    /* EEF_2r */
    835,
    /* EET_2r */
    837,
    /* EEU_1r */
    839,
    /* ENDIN_2r */
    840,
    /* ENTSP_lu6 */
    842,
    /* ENTSP_u6 */
    843,
    /* EQ_2rus */
    844,
    /* EQ_3r */
    847,
    /* EXTDP_lu6 */
    850,
    /* EXTDP_u6 */
    851,
    /* EXTSP_lu6 */
    852,
    /* EXTSP_u6 */
    853,
    /* FREER_1r */
    854,
    /* FREET_0R */
    855,
    /* GETD_l2r */
    855,
    /* GETED_0R */
    857,
    /* GETET_0R */
    857,
    /* GETID_0R */
    857,
    /* GETKEP_0R */
    857,
    /* GETKSP_0R */
    857,
    /* GETN_l2r */
    857,
    /* GETPS_l2r */
    859,
    /* GETR_rus */
    861,
    /* GETSR_lu6 */
    863,
    /* GETSR_u6 */
    864,
    /* GETST_2r */
    865,
    /* GETTS_2r */
    867,
    /* INCT_2r */
    869,
    /* INITCP_2r */
    871,
    /* INITDP_2r */
    873,
    /* INITLR_l2r */
    875,
    /* INITPC_2r */
    877,
    /* INITSP_2r */
    879,
    /* INPW_l2rus */
    881,
    /* INSHR_2r */
    884,
    /* INT_2r */
    887,
    /* IN_2r */
    889,
    /* KCALL_1r */
    891,
    /* KCALL_lu6 */
    892,
    /* KCALL_u6 */
    893,
    /* KENTSP_lu6 */
    894,
    /* KENTSP_u6 */
    895,
    /* KRESTSP_lu6 */
    896,
    /* KRESTSP_u6 */
    897,
    /* KRET_0R */
    898,
    /* LADD_l5r */
    898,
    /* LD16S_3r */
    903,
    /* LD8U_3r */
    906,
    /* LDA16B_l3r */
    909,
    /* LDA16F_l3r */
    912,
    /* LDAPB_lu10 */
    915,
    /* LDAPB_u10 */
    916,
    /* LDAPF_lu10 */
    917,
    /* LDAPF_lu10_ba */
    918,
    /* LDAPF_u10 */
    919,
    /* LDAWB_l2rus */
    920,
    /* LDAWB_l3r */
    923,
    /* LDAWCP_lu6 */
    926,
    /* LDAWCP_u6 */
    927,
    /* LDAWDP_lru6 */
    928,
    /* LDAWDP_ru6 */
    930,
    /* LDAWF_l2rus */
    932,
    /* LDAWF_l3r */
    935,
    /* LDAWSP_lru6 */
    938,
    /* LDAWSP_ru6 */
    940,
    /* LDC_lru6 */
    942,
    /* LDC_ru6 */
    944,
    /* LDET_0R */
    946,
    /* LDIVU_l5r */
    946,
    /* LDSED_0R */
    951,
    /* LDSPC_0R */
    951,
    /* LDSSR_0R */
    951,
    /* LDWCP_lru6 */
    951,
    /* LDWCP_lu10 */
    953,
    /* LDWCP_ru6 */
    954,
    /* LDWCP_u10 */
    956,
    /* LDWDP_lru6 */
    957,
    /* LDWDP_ru6 */
    959,
    /* LDWSP_lru6 */
    961,
    /* LDWSP_ru6 */
    963,
    /* LDW_2rus */
    965,
    /* LDW_3r */
    968,
    /* LMUL_l6r */
    971,
    /* LSS_3r */
    977,
    /* LSUB_l5r */
    980,
    /* LSU_3r */
    985,
    /* MACCS_l4r */
    988,
    /* MACCU_l4r */
    994,
    /* MJOIN_1r */
    1000,
    /* MKMSK_2r */
    1001,
    /* MKMSK_rus */
    1003,
    /* MSYNC_1r */
    1005,
    /* MUL_l3r */
    1006,
    /* NEG */
    1009,
    /* NOT */
    1011,
    /* OR_3r */
    1013,
    /* OUTCT_2r */
    1016,
    /* OUTCT_rus */
    1018,
    /* OUTPW_l2rus */
    1020,
    /* OUTSHR_2r */
    1023,
    /* OUTT_2r */
    1026,
    /* OUT_2r */
    1028,
    /* PEEK_2r */
    1030,
    /* REMS_l3r */
    1032,
    /* REMU_l3r */
    1035,
    /* RETSP_lu6 */
    1038,
    /* RETSP_u6 */
    1039,
    /* SETCLK_l2r */
    1040,
    /* SETCP_1r */
    1042,
    /* SETC_l2r */
    1043,
    /* SETC_lru6 */
    1045,
    /* SETC_ru6 */
    1047,
    /* SETDP_1r */
    1049,
    /* SETD_2r */
    1050,
    /* SETEV_1r */
    1052,
    /* SETKEP_0R */
    1053,
    /* SETN_l2r */
    1053,
    /* SETPSC_2r */
    1055,
    /* SETPS_l2r */
    1057,
    /* SETPT_2r */
    1059,
    /* SETRDY_l2r */
    1061,
    /* SETSP_1r */
    1063,
    /* SETSR_branch_lu6 */
    1064,
    /* SETSR_branch_u6 */
    1065,
    /* SETSR_lu6 */
    1066,
    /* SETSR_u6 */
    1067,
    /* SETTW_l2r */
    1068,
    /* SETV_1r */
    1070,
    /* SEXT_2r */
    1071,
    /* SEXT_rus */
    1074,
    /* SHL_2rus */
    1077,
    /* SHL_3r */
    1080,
    /* SHR_2rus */
    1083,
    /* SHR_3r */
    1086,
    /* SSYNC_0r */
    1089,
    /* ST16_l3r */
    1089,
    /* ST8_l3r */
    1092,
    /* STET_0R */
    1095,
    /* STSED_0R */
    1095,
    /* STSPC_0R */
    1095,
    /* STSSR_0R */
    1095,
    /* STWDP_lru6 */
    1095,
    /* STWDP_ru6 */
    1097,
    /* STWSP_lru6 */
    1099,
    /* STWSP_ru6 */
    1101,
    /* STW_2rus */
    1103,
    /* STW_l3r */
    1106,
    /* SUB_2rus */
    1109,
    /* SUB_3r */
    1112,
    /* SYNCR_1r */
    1115,
    /* TESTCT_2r */
    1116,
    /* TESTLCL_l2r */
    1118,
    /* TESTWCT_2r */
    1120,
    /* TSETMR_2r */
    1122,
    /* TSETR_3r */
    1124,
    /* TSTART_1R */
    1127,
    /* WAITEF_1R */
    1128,
    /* WAITET_1R */
    1129,
    /* WAITEU_0R */
    1130,
    /* XOR_l3r */
    1130,
    /* ZEXT_2r */
    1133,
    /* ZEXT_rus */
    1136,
  };

  using namespace OpTypes;
  static const int8_t OpcodeOperandTypes[] = {
    
    /* PHI */
    -1, 
    /* INLINEASM */
    /* INLINEASM_BR */
    /* CFI_INSTRUCTION */
    i32imm, 
    /* EH_LABEL */
    i32imm, 
    /* GC_LABEL */
    i32imm, 
    /* ANNOTATION_LABEL */
    i32imm, 
    /* KILL */
    /* EXTRACT_SUBREG */
    -1, -1, i32imm, 
    /* INSERT_SUBREG */
    -1, -1, -1, i32imm, 
    /* IMPLICIT_DEF */
    -1, 
    /* INIT_UNDEF */
    -1, 
    /* SUBREG_TO_REG */
    -1, -1, -1, i32imm, 
    /* COPY_TO_REGCLASS */
    -1, -1, i32imm, 
    /* DBG_VALUE */
    /* DBG_VALUE_LIST */
    /* DBG_INSTR_REF */
    /* DBG_PHI */
    /* DBG_LABEL */
    -1, 
    /* REG_SEQUENCE */
    -1, -1, 
    /* COPY */
    -1, -1, 
    /* BUNDLE */
    /* LIFETIME_START */
    i32imm, 
    /* LIFETIME_END */
    i32imm, 
    /* PSEUDO_PROBE */
    i64imm, i64imm, i8imm, i32imm, 
    /* ARITH_FENCE */
    -1, -1, 
    /* STACKMAP */
    i64imm, i32imm, 
    /* FENTRY_CALL */
    /* PATCHPOINT */
    -1, i64imm, i32imm, -1, i32imm, i32imm, 
    /* LOAD_STACK_GUARD */
    -1, 
    /* PREALLOCATED_SETUP */
    i32imm, 
    /* PREALLOCATED_ARG */
    -1, i32imm, i32imm, 
    /* STATEPOINT */
    /* LOCAL_ESCAPE */
    -1, i32imm, 
    /* FAULTING_OP */
    -1, 
    /* PATCHABLE_OP */
    /* PATCHABLE_FUNCTION_ENTER */
    /* PATCHABLE_RET */
    /* PATCHABLE_FUNCTION_EXIT */
    /* PATCHABLE_TAIL_CALL */
    /* PATCHABLE_EVENT_CALL */
    -1, -1, 
    /* PATCHABLE_TYPED_EVENT_CALL */
    -1, -1, -1, 
    /* ICALL_BRANCH_FUNNEL */
    /* FAKE_USE */
    /* MEMBARRIER */
    /* JUMP_TABLE_DEBUG_INFO */
    i64imm, 
    /* CONVERGENCECTRL_ENTRY */
    -1, 
    /* CONVERGENCECTRL_ANCHOR */
    -1, 
    /* CONVERGENCECTRL_LOOP */
    -1, -1, 
    /* CONVERGENCECTRL_GLUE */
    -1, 
    /* G_ASSERT_SEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ZEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ALIGN */
    type0, type0, untyped_imm_0, 
    /* G_ADD */
    type0, type0, type0, 
    /* G_SUB */
    type0, type0, type0, 
    /* G_MUL */
    type0, type0, type0, 
    /* G_SDIV */
    type0, type0, type0, 
    /* G_UDIV */
    type0, type0, type0, 
    /* G_SREM */
    type0, type0, type0, 
    /* G_UREM */
    type0, type0, type0, 
    /* G_SDIVREM */
    type0, type0, type0, type0, 
    /* G_UDIVREM */
    type0, type0, type0, type0, 
    /* G_AND */
    type0, type0, type0, 
    /* G_OR */
    type0, type0, type0, 
    /* G_XOR */
    type0, type0, type0, 
    /* G_IMPLICIT_DEF */
    type0, 
    /* G_PHI */
    type0, 
    /* G_FRAME_INDEX */
    type0, -1, 
    /* G_GLOBAL_VALUE */
    type0, -1, 
    /* G_PTRAUTH_GLOBAL_VALUE */
    type0, -1, i32imm, type1, i64imm, 
    /* G_CONSTANT_POOL */
    type0, -1, 
    /* G_EXTRACT */
    type0, type1, untyped_imm_0, 
    /* G_UNMERGE_VALUES */
    type0, type1, 
    /* G_INSERT */
    type0, type0, type1, untyped_imm_0, 
    /* G_MERGE_VALUES */
    type0, type1, 
    /* G_BUILD_VECTOR */
    type0, type1, 
    /* G_BUILD_VECTOR_TRUNC */
    type0, type1, 
    /* G_CONCAT_VECTORS */
    type0, type1, 
    /* G_PTRTOINT */
    type0, type1, 
    /* G_INTTOPTR */
    type0, type1, 
    /* G_BITCAST */
    type0, type1, 
    /* G_FREEZE */
    type0, type0, 
    /* G_CONSTANT_FOLD_BARRIER */
    type0, type0, 
    /* G_INTRINSIC_FPTRUNC_ROUND */
    type0, type1, i32imm, 
    /* G_INTRINSIC_TRUNC */
    type0, type0, 
    /* G_INTRINSIC_ROUND */
    type0, type0, 
    /* G_INTRINSIC_LRINT */
    type0, type1, 
    /* G_INTRINSIC_LLRINT */
    type0, type1, 
    /* G_INTRINSIC_ROUNDEVEN */
    type0, type0, 
    /* G_READCYCLECOUNTER */
    type0, 
    /* G_READSTEADYCOUNTER */
    type0, 
    /* G_LOAD */
    type0, ptype1, 
    /* G_SEXTLOAD */
    type0, ptype1, 
    /* G_ZEXTLOAD */
    type0, ptype1, 
    /* G_INDEXED_LOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_SEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_ZEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_STORE */
    type0, ptype1, 
    /* G_INDEXED_STORE */
    ptype0, type1, ptype0, ptype2, -1, 
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    type0, type1, type2, type0, type0, 
    /* G_ATOMIC_CMPXCHG */
    type0, ptype1, type0, type0, 
    /* G_ATOMICRMW_XCHG */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_ADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_SUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_AND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_NAND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_OR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_XOR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FSUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UINC_WRAP */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UDEC_WRAP */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_USUB_COND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_USUB_SAT */
    type0, ptype1, type0, 
    /* G_FENCE */
    i32imm, i32imm, 
    /* G_PREFETCH */
    ptype0, i32imm, i32imm, i32imm, 
    /* G_BRCOND */
    type0, -1, 
    /* G_BRINDIRECT */
    type0, 
    /* G_INVOKE_REGION_START */
    /* G_INTRINSIC */
    -1, 
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    -1, 
    /* G_INTRINSIC_CONVERGENT */
    -1, 
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    -1, 
    /* G_ANYEXT */
    type0, type1, 
    /* G_TRUNC */
    type0, type1, 
    /* G_CONSTANT */
    type0, -1, 
    /* G_FCONSTANT */
    type0, -1, 
    /* G_VASTART */
    type0, 
    /* G_VAARG */
    type0, type1, -1, 
    /* G_SEXT */
    type0, type1, 
    /* G_SEXT_INREG */
    type0, type0, untyped_imm_0, 
    /* G_ZEXT */
    type0, type1, 
    /* G_SHL */
    type0, type0, type1, 
    /* G_LSHR */
    type0, type0, type1, 
    /* G_ASHR */
    type0, type0, type1, 
    /* G_FSHL */
    type0, type0, type0, type1, 
    /* G_FSHR */
    type0, type0, type0, type1, 
    /* G_ROTR */
    type0, type0, type1, 
    /* G_ROTL */
    type0, type0, type1, 
    /* G_ICMP */
    type0, -1, type1, type1, 
    /* G_FCMP */
    type0, -1, type1, type1, 
    /* G_SCMP */
    type0, type1, type1, 
    /* G_UCMP */
    type0, type1, type1, 
    /* G_SELECT */
    type0, type1, type0, type0, 
    /* G_UADDO */
    type0, type1, type0, type0, 
    /* G_UADDE */
    type0, type1, type0, type0, type1, 
    /* G_USUBO */
    type0, type1, type0, type0, 
    /* G_USUBE */
    type0, type1, type0, type0, type1, 
    /* G_SADDO */
    type0, type1, type0, type0, 
    /* G_SADDE */
    type0, type1, type0, type0, type1, 
    /* G_SSUBO */
    type0, type1, type0, type0, 
    /* G_SSUBE */
    type0, type1, type0, type0, type1, 
    /* G_UMULO */
    type0, type1, type0, type0, 
    /* G_SMULO */
    type0, type1, type0, type0, 
    /* G_UMULH */
    type0, type0, type0, 
    /* G_SMULH */
    type0, type0, type0, 
    /* G_UADDSAT */
    type0, type0, type0, 
    /* G_SADDSAT */
    type0, type0, type0, 
    /* G_USUBSAT */
    type0, type0, type0, 
    /* G_SSUBSAT */
    type0, type0, type0, 
    /* G_USHLSAT */
    type0, type0, type1, 
    /* G_SSHLSAT */
    type0, type0, type1, 
    /* G_SMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_FADD */
    type0, type0, type0, 
    /* G_FSUB */
    type0, type0, type0, 
    /* G_FMUL */
    type0, type0, type0, 
    /* G_FMA */
    type0, type0, type0, type0, 
    /* G_FMAD */
    type0, type0, type0, type0, 
    /* G_FDIV */
    type0, type0, type0, 
    /* G_FREM */
    type0, type0, type0, 
    /* G_FPOW */
    type0, type0, type0, 
    /* G_FPOWI */
    type0, type0, type1, 
    /* G_FEXP */
    type0, type0, 
    /* G_FEXP2 */
    type0, type0, 
    /* G_FEXP10 */
    type0, type0, 
    /* G_FLOG */
    type0, type0, 
    /* G_FLOG2 */
    type0, type0, 
    /* G_FLOG10 */
    type0, type0, 
    /* G_FLDEXP */
    type0, type0, type1, 
    /* G_FFREXP */
    type0, type1, type0, 
    /* G_FNEG */
    type0, type0, 
    /* G_FPEXT */
    type0, type1, 
    /* G_FPTRUNC */
    type0, type1, 
    /* G_FPTOSI */
    type0, type1, 
    /* G_FPTOUI */
    type0, type1, 
    /* G_SITOFP */
    type0, type1, 
    /* G_UITOFP */
    type0, type1, 
    /* G_FPTOSI_SAT */
    type0, type1, 
    /* G_FPTOUI_SAT */
    type0, type1, 
    /* G_FABS */
    type0, type0, 
    /* G_FCOPYSIGN */
    type0, type0, type1, 
    /* G_IS_FPCLASS */
    type0, type1, -1, 
    /* G_FCANONICALIZE */
    type0, type0, 
    /* G_FMINNUM */
    type0, type0, type0, 
    /* G_FMAXNUM */
    type0, type0, type0, 
    /* G_FMINNUM_IEEE */
    type0, type0, type0, 
    /* G_FMAXNUM_IEEE */
    type0, type0, type0, 
    /* G_FMINIMUM */
    type0, type0, type0, 
    /* G_FMAXIMUM */
    type0, type0, type0, 
    /* G_GET_FPENV */
    type0, 
    /* G_SET_FPENV */
    type0, 
    /* G_RESET_FPENV */
    /* G_GET_FPMODE */
    type0, 
    /* G_SET_FPMODE */
    type0, 
    /* G_RESET_FPMODE */
    /* G_PTR_ADD */
    ptype0, ptype0, type1, 
    /* G_PTRMASK */
    ptype0, ptype0, type1, 
    /* G_SMIN */
    type0, type0, type0, 
    /* G_SMAX */
    type0, type0, type0, 
    /* G_UMIN */
    type0, type0, type0, 
    /* G_UMAX */
    type0, type0, type0, 
    /* G_ABS */
    type0, type0, 
    /* G_LROUND */
    type0, type1, 
    /* G_LLROUND */
    type0, type1, 
    /* G_BR */
    -1, 
    /* G_BRJT */
    ptype0, -1, type1, 
    /* G_VSCALE */
    type0, -1, 
    /* G_INSERT_SUBVECTOR */
    type0, type0, type1, untyped_imm_0, 
    /* G_EXTRACT_SUBVECTOR */
    type0, type1, untyped_imm_0, 
    /* G_INSERT_VECTOR_ELT */
    type0, type0, type1, type2, 
    /* G_EXTRACT_VECTOR_ELT */
    type0, type1, type2, 
    /* G_SHUFFLE_VECTOR */
    type0, type1, type1, -1, 
    /* G_SPLAT_VECTOR */
    type0, type1, 
    /* G_VECTOR_COMPRESS */
    type0, type0, type1, type0, 
    /* G_CTTZ */
    type0, type1, 
    /* G_CTTZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTLZ */
    type0, type1, 
    /* G_CTLZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTPOP */
    type0, type1, 
    /* G_BSWAP */
    type0, type0, 
    /* G_BITREVERSE */
    type0, type0, 
    /* G_FCEIL */
    type0, type0, 
    /* G_FCOS */
    type0, type0, 
    /* G_FSIN */
    type0, type0, 
    /* G_FTAN */
    type0, type0, 
    /* G_FACOS */
    type0, type0, 
    /* G_FASIN */
    type0, type0, 
    /* G_FATAN */
    type0, type0, 
    /* G_FATAN2 */
    type0, type0, type0, 
    /* G_FCOSH */
    type0, type0, 
    /* G_FSINH */
    type0, type0, 
    /* G_FTANH */
    type0, type0, 
    /* G_FSQRT */
    type0, type0, 
    /* G_FFLOOR */
    type0, type0, 
    /* G_FRINT */
    type0, type0, 
    /* G_FNEARBYINT */
    type0, type0, 
    /* G_ADDRSPACE_CAST */
    type0, type1, 
    /* G_BLOCK_ADDR */
    type0, -1, 
    /* G_JUMP_TABLE */
    type0, -1, 
    /* G_DYN_STACKALLOC */
    ptype0, type1, i32imm, 
    /* G_STACKSAVE */
    ptype0, 
    /* G_STACKRESTORE */
    ptype0, 
    /* G_STRICT_FADD */
    type0, type0, type0, 
    /* G_STRICT_FSUB */
    type0, type0, type0, 
    /* G_STRICT_FMUL */
    type0, type0, type0, 
    /* G_STRICT_FDIV */
    type0, type0, type0, 
    /* G_STRICT_FREM */
    type0, type0, type0, 
    /* G_STRICT_FMA */
    type0, type0, type0, type0, 
    /* G_STRICT_FSQRT */
    type0, type0, 
    /* G_STRICT_FLDEXP */
    type0, type0, type1, 
    /* G_READ_REGISTER */
    type0, -1, 
    /* G_WRITE_REGISTER */
    -1, type0, 
    /* G_MEMCPY */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMCPY_INLINE */
    ptype0, ptype1, type2, 
    /* G_MEMMOVE */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMSET */
    ptype0, type1, type2, untyped_imm_0, 
    /* G_BZERO */
    ptype0, type1, untyped_imm_0, 
    /* G_TRAP */
    /* G_DEBUGTRAP */
    /* G_UBSANTRAP */
    i8imm, 
    /* G_VECREDUCE_SEQ_FADD */
    type0, type1, type2, 
    /* G_VECREDUCE_SEQ_FMUL */
    type0, type1, type2, 
    /* G_VECREDUCE_FADD */
    type0, type1, 
    /* G_VECREDUCE_FMUL */
    type0, type1, 
    /* G_VECREDUCE_FMAX */
    type0, type1, 
    /* G_VECREDUCE_FMIN */
    type0, type1, 
    /* G_VECREDUCE_FMAXIMUM */
    type0, type1, 
    /* G_VECREDUCE_FMINIMUM */
    type0, type1, 
    /* G_VECREDUCE_ADD */
    type0, type1, 
    /* G_VECREDUCE_MUL */
    type0, type1, 
    /* G_VECREDUCE_AND */
    type0, type1, 
    /* G_VECREDUCE_OR */
    type0, type1, 
    /* G_VECREDUCE_XOR */
    type0, type1, 
    /* G_VECREDUCE_SMAX */
    type0, type1, 
    /* G_VECREDUCE_SMIN */
    type0, type1, 
    /* G_VECREDUCE_UMAX */
    type0, type1, 
    /* G_VECREDUCE_UMIN */
    type0, type1, 
    /* G_SBFX */
    type0, type0, type1, type1, 
    /* G_UBFX */
    type0, type0, type1, type1, 
    /* ADJCALLSTACKDOWN */
    i32imm, i32imm, 
    /* ADJCALLSTACKUP */
    i32imm, i32imm, 
    /* BR_JT */
    InlineJT, GRRegs, 
    /* BR_JT32 */
    InlineJT32, GRRegs, 
    /* EH_RETURN */
    GRRegs, GRRegs, 
    /* FRAME_TO_ARGS_OFFSET */
    GRRegs, 
    /* LDAWFI */
    GRRegs, i32imm, i32imm, 
    /* LDWFI */
    GRRegs, i32imm, i32imm, 
    /* SELECT_CC */
    GRRegs, GRRegs, GRRegs, GRRegs, 
    /* STWFI */
    GRRegs, i32imm, i32imm, 
    /* ADD_2rus */
    GRRegs, GRRegs, i32imm, 
    /* ADD_3r */
    GRRegs, GRRegs, GRRegs, 
    /* ANDNOT_2r */
    GRRegs, GRRegs, GRRegs, 
    /* AND_3r */
    GRRegs, GRRegs, GRRegs, 
    /* ASHR_l2rus */
    GRRegs, GRRegs, i32imm, 
    /* ASHR_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* BAU_1r */
    GRRegs, 
    /* BITREV_l2r */
    GRRegs, GRRegs, 
    /* BLACP_lu10 */
    i32imm, 
    /* BLACP_u10 */
    i32imm, 
    /* BLAT_lu6 */
    i32imm, 
    /* BLAT_u6 */
    i32imm, 
    /* BLA_1r */
    GRRegs, 
    /* BLRB_lu10 */
    pcrel_imm_neg, 
    /* BLRB_u10 */
    pcrel_imm_neg, 
    /* BLRF_lu10 */
    pcrel_imm, 
    /* BLRF_u10 */
    pcrel_imm, 
    /* BRBF_lru6 */
    GRRegs, brtarget_neg, 
    /* BRBF_ru6 */
    GRRegs, brtarget_neg, 
    /* BRBT_lru6 */
    GRRegs, brtarget_neg, 
    /* BRBT_ru6 */
    GRRegs, brtarget_neg, 
    /* BRBU_lu6 */
    brtarget_neg, 
    /* BRBU_u6 */
    brtarget_neg, 
    /* BRFF_lru6 */
    GRRegs, brtarget, 
    /* BRFF_ru6 */
    GRRegs, brtarget, 
    /* BRFT_lru6 */
    GRRegs, brtarget, 
    /* BRFT_ru6 */
    GRRegs, brtarget, 
    /* BRFU_lu6 */
    brtarget, 
    /* BRFU_u6 */
    brtarget, 
    /* BRU_1r */
    GRRegs, 
    /* BYTEREV_l2r */
    GRRegs, GRRegs, 
    /* CHKCT_2r */
    GRRegs, GRRegs, 
    /* CHKCT_rus */
    GRRegs, i32imm, 
    /* CLRE_0R */
    /* CLRPT_1R */
    GRRegs, 
    /* CLRSR_branch_lu6 */
    i32imm, 
    /* CLRSR_branch_u6 */
    i32imm, 
    /* CLRSR_lu6 */
    i32imm, 
    /* CLRSR_u6 */
    i32imm, 
    /* CLZ_l2r */
    GRRegs, GRRegs, 
    /* CRC8_l4r */
    GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, 
    /* CRC_l3r */
    GRRegs, GRRegs, GRRegs, GRRegs, 
    /* DCALL_0R */
    /* DENTSP_0R */
    /* DGETREG_1r */
    GRRegs, 
    /* DIVS_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* DIVU_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* DRESTSP_0R */
    /* DRET_0R */
    /* ECALLF_1r */
    GRRegs, 
    /* ECALLT_1r */
    GRRegs, 
    /* EDU_1r */
    GRRegs, 
    /* EEF_2r */
    GRRegs, GRRegs, 
    /* EET_2r */
    GRRegs, GRRegs, 
    /* EEU_1r */
    GRRegs, 
    /* ENDIN_2r */
    GRRegs, GRRegs, 
    /* ENTSP_lu6 */
    i32imm, 
    /* ENTSP_u6 */
    i32imm, 
    /* EQ_2rus */
    GRRegs, GRRegs, i32imm, 
    /* EQ_3r */
    GRRegs, GRRegs, GRRegs, 
    /* EXTDP_lu6 */
    i32imm, 
    /* EXTDP_u6 */
    i32imm, 
    /* EXTSP_lu6 */
    i32imm, 
    /* EXTSP_u6 */
    i32imm, 
    /* FREER_1r */
    GRRegs, 
    /* FREET_0R */
    /* GETD_l2r */
    GRRegs, GRRegs, 
    /* GETED_0R */
    /* GETET_0R */
    /* GETID_0R */
    /* GETKEP_0R */
    /* GETKSP_0R */
    /* GETN_l2r */
    GRRegs, GRRegs, 
    /* GETPS_l2r */
    GRRegs, GRRegs, 
    /* GETR_rus */
    GRRegs, i32imm, 
    /* GETSR_lu6 */
    i32imm, 
    /* GETSR_u6 */
    i32imm, 
    /* GETST_2r */
    GRRegs, GRRegs, 
    /* GETTS_2r */
    GRRegs, GRRegs, 
    /* INCT_2r */
    GRRegs, GRRegs, 
    /* INITCP_2r */
    GRRegs, GRRegs, 
    /* INITDP_2r */
    GRRegs, GRRegs, 
    /* INITLR_l2r */
    GRRegs, GRRegs, 
    /* INITPC_2r */
    GRRegs, GRRegs, 
    /* INITSP_2r */
    GRRegs, GRRegs, 
    /* INPW_l2rus */
    GRRegs, GRRegs, i32imm, 
    /* INSHR_2r */
    GRRegs, GRRegs, GRRegs, 
    /* INT_2r */
    GRRegs, GRRegs, 
    /* IN_2r */
    GRRegs, GRRegs, 
    /* KCALL_1r */
    GRRegs, 
    /* KCALL_lu6 */
    i32imm, 
    /* KCALL_u6 */
    i32imm, 
    /* KENTSP_lu6 */
    i32imm, 
    /* KENTSP_u6 */
    i32imm, 
    /* KRESTSP_lu6 */
    i32imm, 
    /* KRESTSP_u6 */
    i32imm, 
    /* KRET_0R */
    /* LADD_l5r */
    GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, 
    /* LD16S_3r */
    GRRegs, GRRegs, GRRegs, 
    /* LD8U_3r */
    GRRegs, GRRegs, GRRegs, 
    /* LDA16B_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* LDA16F_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* LDAPB_lu10 */
    pcrel_imm_neg, 
    /* LDAPB_u10 */
    pcrel_imm_neg, 
    /* LDAPF_lu10 */
    pcrel_imm, 
    /* LDAPF_lu10_ba */
    pcrel_imm, 
    /* LDAPF_u10 */
    pcrel_imm, 
    /* LDAWB_l2rus */
    GRRegs, GRRegs, i32imm, 
    /* LDAWB_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* LDAWCP_lu6 */
    i32imm, 
    /* LDAWCP_u6 */
    i32imm, 
    /* LDAWDP_lru6 */
    RRegs, i32imm, 
    /* LDAWDP_ru6 */
    RRegs, i32imm, 
    /* LDAWF_l2rus */
    GRRegs, GRRegs, i32imm, 
    /* LDAWF_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* LDAWSP_lru6 */
    RRegs, i32imm, 
    /* LDAWSP_ru6 */
    RRegs, i32imm, 
    /* LDC_lru6 */
    RRegs, i32imm, 
    /* LDC_ru6 */
    RRegs, i32imm, 
    /* LDET_0R */
    /* LDIVU_l5r */
    GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, 
    /* LDSED_0R */
    /* LDSPC_0R */
    /* LDSSR_0R */
    /* LDWCP_lru6 */
    RRegs, i32imm, 
    /* LDWCP_lu10 */
    i32imm, 
    /* LDWCP_ru6 */
    RRegs, i32imm, 
    /* LDWCP_u10 */
    i32imm, 
    /* LDWDP_lru6 */
    RRegs, i32imm, 
    /* LDWDP_ru6 */
    RRegs, i32imm, 
    /* LDWSP_lru6 */
    RRegs, i32imm, 
    /* LDWSP_ru6 */
    RRegs, i32imm, 
    /* LDW_2rus */
    GRRegs, GRRegs, i32imm, 
    /* LDW_3r */
    GRRegs, GRRegs, GRRegs, 
    /* LMUL_l6r */
    GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, 
    /* LSS_3r */
    GRRegs, GRRegs, GRRegs, 
    /* LSUB_l5r */
    GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, 
    /* LSU_3r */
    GRRegs, GRRegs, GRRegs, 
    /* MACCS_l4r */
    GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, 
    /* MACCU_l4r */
    GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, 
    /* MJOIN_1r */
    GRRegs, 
    /* MKMSK_2r */
    GRRegs, GRRegs, 
    /* MKMSK_rus */
    GRRegs, i32imm, 
    /* MSYNC_1r */
    GRRegs, 
    /* MUL_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* NEG */
    GRRegs, GRRegs, 
    /* NOT */
    GRRegs, GRRegs, 
    /* OR_3r */
    GRRegs, GRRegs, GRRegs, 
    /* OUTCT_2r */
    GRRegs, GRRegs, 
    /* OUTCT_rus */
    GRRegs, i32imm, 
    /* OUTPW_l2rus */
    GRRegs, GRRegs, i32imm, 
    /* OUTSHR_2r */
    GRRegs, GRRegs, GRRegs, 
    /* OUTT_2r */
    GRRegs, GRRegs, 
    /* OUT_2r */
    GRRegs, GRRegs, 
    /* PEEK_2r */
    GRRegs, GRRegs, 
    /* REMS_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* REMU_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* RETSP_lu6 */
    i32imm, 
    /* RETSP_u6 */
    i32imm, 
    /* SETCLK_l2r */
    GRRegs, GRRegs, 
    /* SETCP_1r */
    GRRegs, 
    /* SETC_l2r */
    GRRegs, GRRegs, 
    /* SETC_lru6 */
    GRRegs, i32imm, 
    /* SETC_ru6 */
    GRRegs, i32imm, 
    /* SETDP_1r */
    GRRegs, 
    /* SETD_2r */
    GRRegs, GRRegs, 
    /* SETEV_1r */
    GRRegs, 
    /* SETKEP_0R */
    /* SETN_l2r */
    GRRegs, GRRegs, 
    /* SETPSC_2r */
    GRRegs, GRRegs, 
    /* SETPS_l2r */
    GRRegs, GRRegs, 
    /* SETPT_2r */
    GRRegs, GRRegs, 
    /* SETRDY_l2r */
    GRRegs, GRRegs, 
    /* SETSP_1r */
    GRRegs, 
    /* SETSR_branch_lu6 */
    i32imm, 
    /* SETSR_branch_u6 */
    i32imm, 
    /* SETSR_lu6 */
    i32imm, 
    /* SETSR_u6 */
    i32imm, 
    /* SETTW_l2r */
    GRRegs, GRRegs, 
    /* SETV_1r */
    GRRegs, 
    /* SEXT_2r */
    GRRegs, GRRegs, GRRegs, 
    /* SEXT_rus */
    GRRegs, GRRegs, i32imm, 
    /* SHL_2rus */
    GRRegs, GRRegs, i32imm, 
    /* SHL_3r */
    GRRegs, GRRegs, GRRegs, 
    /* SHR_2rus */
    GRRegs, GRRegs, i32imm, 
    /* SHR_3r */
    GRRegs, GRRegs, GRRegs, 
    /* SSYNC_0r */
    /* ST16_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* ST8_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* STET_0R */
    /* STSED_0R */
    /* STSPC_0R */
    /* STSSR_0R */
    /* STWDP_lru6 */
    RRegs, i32imm, 
    /* STWDP_ru6 */
    RRegs, i32imm, 
    /* STWSP_lru6 */
    RRegs, i32imm, 
    /* STWSP_ru6 */
    RRegs, i32imm, 
    /* STW_2rus */
    GRRegs, GRRegs, i32imm, 
    /* STW_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* SUB_2rus */
    GRRegs, GRRegs, i32imm, 
    /* SUB_3r */
    GRRegs, GRRegs, GRRegs, 
    /* SYNCR_1r */
    GRRegs, 
    /* TESTCT_2r */
    GRRegs, GRRegs, 
    /* TESTLCL_l2r */
    GRRegs, GRRegs, 
    /* TESTWCT_2r */
    GRRegs, GRRegs, 
    /* TSETMR_2r */
    i32imm, GRRegs, 
    /* TSETR_3r */
    i32imm, GRRegs, GRRegs, 
    /* TSTART_1R */
    GRRegs, 
    /* WAITEF_1R */
    GRRegs, 
    /* WAITET_1R */
    GRRegs, 
    /* WAITEU_0R */
    /* XOR_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* ZEXT_2r */
    GRRegs, GRRegs, GRRegs, 
    /* ZEXT_rus */
    GRRegs, GRRegs, i32imm, 
  };
  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
}
} // end namespace XCore
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPE

#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
#undef GET_INSTRINFO_MEM_OPERAND_SIZE
namespace llvm {
namespace XCore {
LLVM_READONLY
static int getMemOperandSize(int OpType) {
  switch (OpType) {
  default: return 0;
  }
}
} // end namespace XCore
} // end namespace llvm
#endif // GET_INSTRINFO_MEM_OPERAND_SIZE

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
namespace llvm {
namespace XCore {
LLVM_READONLY static unsigned
getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return LogicalOpIdx;
}
LLVM_READONLY static inline unsigned
getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
  auto S = 0U;
  for (auto i = 0U; i < LogicalOpIdx; ++i)
    S += getLogicalOperandSize(Opcode, i);
  return S;
}
} // end namespace XCore
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
namespace llvm {
namespace XCore {
LLVM_READONLY static int
getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return -1;
}
} // end namespace XCore
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP

#ifdef GET_INSTRINFO_MC_HELPER_DECLS
#undef GET_INSTRINFO_MC_HELPER_DECLS

namespace llvm {
class MCInst;
class FeatureBitset;

namespace XCore_MC {

void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);

} // end namespace XCore_MC
} // end namespace llvm

#endif // GET_INSTRINFO_MC_HELPER_DECLS

#ifdef GET_INSTRINFO_MC_HELPERS
#undef GET_INSTRINFO_MC_HELPERS

namespace llvm {
namespace XCore_MC {

} // end namespace XCore_MC
} // end namespace llvm

#endif // GET_GENISTRINFO_MC_HELPERS

#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
    defined(GET_AVAILABLE_OPCODE_CHECKER)
#define GET_COMPUTE_FEATURES
#endif
#ifdef GET_COMPUTE_FEATURES
#undef GET_COMPUTE_FEATURES
namespace llvm {
namespace XCore_MC {

// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
};

inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
  FeatureBitset Features;
  return Features;
}

inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
  enum : uint8_t {
    CEFBS_None,
  };

  static constexpr FeatureBitset FeatureBitsets[] = {
    {}, // CEFBS_None
  };
  static constexpr uint8_t RequiredFeaturesRefs[] = {
    CEFBS_None, // PHI = 0
    CEFBS_None, // INLINEASM = 1
    CEFBS_None, // INLINEASM_BR = 2
    CEFBS_None, // CFI_INSTRUCTION = 3
    CEFBS_None, // EH_LABEL = 4
    CEFBS_None, // GC_LABEL = 5
    CEFBS_None, // ANNOTATION_LABEL = 6
    CEFBS_None, // KILL = 7
    CEFBS_None, // EXTRACT_SUBREG = 8
    CEFBS_None, // INSERT_SUBREG = 9
    CEFBS_None, // IMPLICIT_DEF = 10
    CEFBS_None, // INIT_UNDEF = 11
    CEFBS_None, // SUBREG_TO_REG = 12
    CEFBS_None, // COPY_TO_REGCLASS = 13
    CEFBS_None, // DBG_VALUE = 14
    CEFBS_None, // DBG_VALUE_LIST = 15
    CEFBS_None, // DBG_INSTR_REF = 16
    CEFBS_None, // DBG_PHI = 17
    CEFBS_None, // DBG_LABEL = 18
    CEFBS_None, // REG_SEQUENCE = 19
    CEFBS_None, // COPY = 20
    CEFBS_None, // BUNDLE = 21
    CEFBS_None, // LIFETIME_START = 22
    CEFBS_None, // LIFETIME_END = 23
    CEFBS_None, // PSEUDO_PROBE = 24
    CEFBS_None, // ARITH_FENCE = 25
    CEFBS_None, // STACKMAP = 26
    CEFBS_None, // FENTRY_CALL = 27
    CEFBS_None, // PATCHPOINT = 28
    CEFBS_None, // LOAD_STACK_GUARD = 29
    CEFBS_None, // PREALLOCATED_SETUP = 30
    CEFBS_None, // PREALLOCATED_ARG = 31
    CEFBS_None, // STATEPOINT = 32
    CEFBS_None, // LOCAL_ESCAPE = 33
    CEFBS_None, // FAULTING_OP = 34
    CEFBS_None, // PATCHABLE_OP = 35
    CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 36
    CEFBS_None, // PATCHABLE_RET = 37
    CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 38
    CEFBS_None, // PATCHABLE_TAIL_CALL = 39
    CEFBS_None, // PATCHABLE_EVENT_CALL = 40
    CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 41
    CEFBS_None, // ICALL_BRANCH_FUNNEL = 42
    CEFBS_None, // FAKE_USE = 43
    CEFBS_None, // MEMBARRIER = 44
    CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 45
    CEFBS_None, // CONVERGENCECTRL_ENTRY = 46
    CEFBS_None, // CONVERGENCECTRL_ANCHOR = 47
    CEFBS_None, // CONVERGENCECTRL_LOOP = 48
    CEFBS_None, // CONVERGENCECTRL_GLUE = 49
    CEFBS_None, // G_ASSERT_SEXT = 50
    CEFBS_None, // G_ASSERT_ZEXT = 51
    CEFBS_None, // G_ASSERT_ALIGN = 52
    CEFBS_None, // G_ADD = 53
    CEFBS_None, // G_SUB = 54
    CEFBS_None, // G_MUL = 55
    CEFBS_None, // G_SDIV = 56
    CEFBS_None, // G_UDIV = 57
    CEFBS_None, // G_SREM = 58
    CEFBS_None, // G_UREM = 59
    CEFBS_None, // G_SDIVREM = 60
    CEFBS_None, // G_UDIVREM = 61
    CEFBS_None, // G_AND = 62
    CEFBS_None, // G_OR = 63
    CEFBS_None, // G_XOR = 64
    CEFBS_None, // G_IMPLICIT_DEF = 65
    CEFBS_None, // G_PHI = 66
    CEFBS_None, // G_FRAME_INDEX = 67
    CEFBS_None, // G_GLOBAL_VALUE = 68
    CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 69
    CEFBS_None, // G_CONSTANT_POOL = 70
    CEFBS_None, // G_EXTRACT = 71
    CEFBS_None, // G_UNMERGE_VALUES = 72
    CEFBS_None, // G_INSERT = 73
    CEFBS_None, // G_MERGE_VALUES = 74
    CEFBS_None, // G_BUILD_VECTOR = 75
    CEFBS_None, // G_BUILD_VECTOR_TRUNC = 76
    CEFBS_None, // G_CONCAT_VECTORS = 77
    CEFBS_None, // G_PTRTOINT = 78
    CEFBS_None, // G_INTTOPTR = 79
    CEFBS_None, // G_BITCAST = 80
    CEFBS_None, // G_FREEZE = 81
    CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 82
    CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 83
    CEFBS_None, // G_INTRINSIC_TRUNC = 84
    CEFBS_None, // G_INTRINSIC_ROUND = 85
    CEFBS_None, // G_INTRINSIC_LRINT = 86
    CEFBS_None, // G_INTRINSIC_LLRINT = 87
    CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 88
    CEFBS_None, // G_READCYCLECOUNTER = 89
    CEFBS_None, // G_READSTEADYCOUNTER = 90
    CEFBS_None, // G_LOAD = 91
    CEFBS_None, // G_SEXTLOAD = 92
    CEFBS_None, // G_ZEXTLOAD = 93
    CEFBS_None, // G_INDEXED_LOAD = 94
    CEFBS_None, // G_INDEXED_SEXTLOAD = 95
    CEFBS_None, // G_INDEXED_ZEXTLOAD = 96
    CEFBS_None, // G_STORE = 97
    CEFBS_None, // G_INDEXED_STORE = 98
    CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 99
    CEFBS_None, // G_ATOMIC_CMPXCHG = 100
    CEFBS_None, // G_ATOMICRMW_XCHG = 101
    CEFBS_None, // G_ATOMICRMW_ADD = 102
    CEFBS_None, // G_ATOMICRMW_SUB = 103
    CEFBS_None, // G_ATOMICRMW_AND = 104
    CEFBS_None, // G_ATOMICRMW_NAND = 105
    CEFBS_None, // G_ATOMICRMW_OR = 106
    CEFBS_None, // G_ATOMICRMW_XOR = 107
    CEFBS_None, // G_ATOMICRMW_MAX = 108
    CEFBS_None, // G_ATOMICRMW_MIN = 109
    CEFBS_None, // G_ATOMICRMW_UMAX = 110
    CEFBS_None, // G_ATOMICRMW_UMIN = 111
    CEFBS_None, // G_ATOMICRMW_FADD = 112
    CEFBS_None, // G_ATOMICRMW_FSUB = 113
    CEFBS_None, // G_ATOMICRMW_FMAX = 114
    CEFBS_None, // G_ATOMICRMW_FMIN = 115
    CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 116
    CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 117
    CEFBS_None, // G_ATOMICRMW_USUB_COND = 118
    CEFBS_None, // G_ATOMICRMW_USUB_SAT = 119
    CEFBS_None, // G_FENCE = 120
    CEFBS_None, // G_PREFETCH = 121
    CEFBS_None, // G_BRCOND = 122
    CEFBS_None, // G_BRINDIRECT = 123
    CEFBS_None, // G_INVOKE_REGION_START = 124
    CEFBS_None, // G_INTRINSIC = 125
    CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 126
    CEFBS_None, // G_INTRINSIC_CONVERGENT = 127
    CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 128
    CEFBS_None, // G_ANYEXT = 129
    CEFBS_None, // G_TRUNC = 130
    CEFBS_None, // G_CONSTANT = 131
    CEFBS_None, // G_FCONSTANT = 132
    CEFBS_None, // G_VASTART = 133
    CEFBS_None, // G_VAARG = 134
    CEFBS_None, // G_SEXT = 135
    CEFBS_None, // G_SEXT_INREG = 136
    CEFBS_None, // G_ZEXT = 137
    CEFBS_None, // G_SHL = 138
    CEFBS_None, // G_LSHR = 139
    CEFBS_None, // G_ASHR = 140
    CEFBS_None, // G_FSHL = 141
    CEFBS_None, // G_FSHR = 142
    CEFBS_None, // G_ROTR = 143
    CEFBS_None, // G_ROTL = 144
    CEFBS_None, // G_ICMP = 145
    CEFBS_None, // G_FCMP = 146
    CEFBS_None, // G_SCMP = 147
    CEFBS_None, // G_UCMP = 148
    CEFBS_None, // G_SELECT = 149
    CEFBS_None, // G_UADDO = 150
    CEFBS_None, // G_UADDE = 151
    CEFBS_None, // G_USUBO = 152
    CEFBS_None, // G_USUBE = 153
    CEFBS_None, // G_SADDO = 154
    CEFBS_None, // G_SADDE = 155
    CEFBS_None, // G_SSUBO = 156
    CEFBS_None, // G_SSUBE = 157
    CEFBS_None, // G_UMULO = 158
    CEFBS_None, // G_SMULO = 159
    CEFBS_None, // G_UMULH = 160
    CEFBS_None, // G_SMULH = 161
    CEFBS_None, // G_UADDSAT = 162
    CEFBS_None, // G_SADDSAT = 163
    CEFBS_None, // G_USUBSAT = 164
    CEFBS_None, // G_SSUBSAT = 165
    CEFBS_None, // G_USHLSAT = 166
    CEFBS_None, // G_SSHLSAT = 167
    CEFBS_None, // G_SMULFIX = 168
    CEFBS_None, // G_UMULFIX = 169
    CEFBS_None, // G_SMULFIXSAT = 170
    CEFBS_None, // G_UMULFIXSAT = 171
    CEFBS_None, // G_SDIVFIX = 172
    CEFBS_None, // G_UDIVFIX = 173
    CEFBS_None, // G_SDIVFIXSAT = 174
    CEFBS_None, // G_UDIVFIXSAT = 175
    CEFBS_None, // G_FADD = 176
    CEFBS_None, // G_FSUB = 177
    CEFBS_None, // G_FMUL = 178
    CEFBS_None, // G_FMA = 179
    CEFBS_None, // G_FMAD = 180
    CEFBS_None, // G_FDIV = 181
    CEFBS_None, // G_FREM = 182
    CEFBS_None, // G_FPOW = 183
    CEFBS_None, // G_FPOWI = 184
    CEFBS_None, // G_FEXP = 185
    CEFBS_None, // G_FEXP2 = 186
    CEFBS_None, // G_FEXP10 = 187
    CEFBS_None, // G_FLOG = 188
    CEFBS_None, // G_FLOG2 = 189
    CEFBS_None, // G_FLOG10 = 190
    CEFBS_None, // G_FLDEXP = 191
    CEFBS_None, // G_FFREXP = 192
    CEFBS_None, // G_FNEG = 193
    CEFBS_None, // G_FPEXT = 194
    CEFBS_None, // G_FPTRUNC = 195
    CEFBS_None, // G_FPTOSI = 196
    CEFBS_None, // G_FPTOUI = 197
    CEFBS_None, // G_SITOFP = 198
    CEFBS_None, // G_UITOFP = 199
    CEFBS_None, // G_FPTOSI_SAT = 200
    CEFBS_None, // G_FPTOUI_SAT = 201
    CEFBS_None, // G_FABS = 202
    CEFBS_None, // G_FCOPYSIGN = 203
    CEFBS_None, // G_IS_FPCLASS = 204
    CEFBS_None, // G_FCANONICALIZE = 205
    CEFBS_None, // G_FMINNUM = 206
    CEFBS_None, // G_FMAXNUM = 207
    CEFBS_None, // G_FMINNUM_IEEE = 208
    CEFBS_None, // G_FMAXNUM_IEEE = 209
    CEFBS_None, // G_FMINIMUM = 210
    CEFBS_None, // G_FMAXIMUM = 211
    CEFBS_None, // G_GET_FPENV = 212
    CEFBS_None, // G_SET_FPENV = 213
    CEFBS_None, // G_RESET_FPENV = 214
    CEFBS_None, // G_GET_FPMODE = 215
    CEFBS_None, // G_SET_FPMODE = 216
    CEFBS_None, // G_RESET_FPMODE = 217
    CEFBS_None, // G_PTR_ADD = 218
    CEFBS_None, // G_PTRMASK = 219
    CEFBS_None, // G_SMIN = 220
    CEFBS_None, // G_SMAX = 221
    CEFBS_None, // G_UMIN = 222
    CEFBS_None, // G_UMAX = 223
    CEFBS_None, // G_ABS = 224
    CEFBS_None, // G_LROUND = 225
    CEFBS_None, // G_LLROUND = 226
    CEFBS_None, // G_BR = 227
    CEFBS_None, // G_BRJT = 228
    CEFBS_None, // G_VSCALE = 229
    CEFBS_None, // G_INSERT_SUBVECTOR = 230
    CEFBS_None, // G_EXTRACT_SUBVECTOR = 231
    CEFBS_None, // G_INSERT_VECTOR_ELT = 232
    CEFBS_None, // G_EXTRACT_VECTOR_ELT = 233
    CEFBS_None, // G_SHUFFLE_VECTOR = 234
    CEFBS_None, // G_SPLAT_VECTOR = 235
    CEFBS_None, // G_VECTOR_COMPRESS = 236
    CEFBS_None, // G_CTTZ = 237
    CEFBS_None, // G_CTTZ_ZERO_UNDEF = 238
    CEFBS_None, // G_CTLZ = 239
    CEFBS_None, // G_CTLZ_ZERO_UNDEF = 240
    CEFBS_None, // G_CTPOP = 241
    CEFBS_None, // G_BSWAP = 242
    CEFBS_None, // G_BITREVERSE = 243
    CEFBS_None, // G_FCEIL = 244
    CEFBS_None, // G_FCOS = 245
    CEFBS_None, // G_FSIN = 246
    CEFBS_None, // G_FTAN = 247
    CEFBS_None, // G_FACOS = 248
    CEFBS_None, // G_FASIN = 249
    CEFBS_None, // G_FATAN = 250
    CEFBS_None, // G_FATAN2 = 251
    CEFBS_None, // G_FCOSH = 252
    CEFBS_None, // G_FSINH = 253
    CEFBS_None, // G_FTANH = 254
    CEFBS_None, // G_FSQRT = 255
    CEFBS_None, // G_FFLOOR = 256
    CEFBS_None, // G_FRINT = 257
    CEFBS_None, // G_FNEARBYINT = 258
    CEFBS_None, // G_ADDRSPACE_CAST = 259
    CEFBS_None, // G_BLOCK_ADDR = 260
    CEFBS_None, // G_JUMP_TABLE = 261
    CEFBS_None, // G_DYN_STACKALLOC = 262
    CEFBS_None, // G_STACKSAVE = 263
    CEFBS_None, // G_STACKRESTORE = 264
    CEFBS_None, // G_STRICT_FADD = 265
    CEFBS_None, // G_STRICT_FSUB = 266
    CEFBS_None, // G_STRICT_FMUL = 267
    CEFBS_None, // G_STRICT_FDIV = 268
    CEFBS_None, // G_STRICT_FREM = 269
    CEFBS_None, // G_STRICT_FMA = 270
    CEFBS_None, // G_STRICT_FSQRT = 271
    CEFBS_None, // G_STRICT_FLDEXP = 272
    CEFBS_None, // G_READ_REGISTER = 273
    CEFBS_None, // G_WRITE_REGISTER = 274
    CEFBS_None, // G_MEMCPY = 275
    CEFBS_None, // G_MEMCPY_INLINE = 276
    CEFBS_None, // G_MEMMOVE = 277
    CEFBS_None, // G_MEMSET = 278
    CEFBS_None, // G_BZERO = 279
    CEFBS_None, // G_TRAP = 280
    CEFBS_None, // G_DEBUGTRAP = 281
    CEFBS_None, // G_UBSANTRAP = 282
    CEFBS_None, // G_VECREDUCE_SEQ_FADD = 283
    CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 284
    CEFBS_None, // G_VECREDUCE_FADD = 285
    CEFBS_None, // G_VECREDUCE_FMUL = 286
    CEFBS_None, // G_VECREDUCE_FMAX = 287
    CEFBS_None, // G_VECREDUCE_FMIN = 288
    CEFBS_None, // G_VECREDUCE_FMAXIMUM = 289
    CEFBS_None, // G_VECREDUCE_FMINIMUM = 290
    CEFBS_None, // G_VECREDUCE_ADD = 291
    CEFBS_None, // G_VECREDUCE_MUL = 292
    CEFBS_None, // G_VECREDUCE_AND = 293
    CEFBS_None, // G_VECREDUCE_OR = 294
    CEFBS_None, // G_VECREDUCE_XOR = 295
    CEFBS_None, // G_VECREDUCE_SMAX = 296
    CEFBS_None, // G_VECREDUCE_SMIN = 297
    CEFBS_None, // G_VECREDUCE_UMAX = 298
    CEFBS_None, // G_VECREDUCE_UMIN = 299
    CEFBS_None, // G_SBFX = 300
    CEFBS_None, // G_UBFX = 301
    CEFBS_None, // ADJCALLSTACKDOWN = 302
    CEFBS_None, // ADJCALLSTACKUP = 303
    CEFBS_None, // BR_JT = 304
    CEFBS_None, // BR_JT32 = 305
    CEFBS_None, // EH_RETURN = 306
    CEFBS_None, // FRAME_TO_ARGS_OFFSET = 307
    CEFBS_None, // LDAWFI = 308
    CEFBS_None, // LDWFI = 309
    CEFBS_None, // SELECT_CC = 310
    CEFBS_None, // STWFI = 311
    CEFBS_None, // ADD_2rus = 312
    CEFBS_None, // ADD_3r = 313
    CEFBS_None, // ANDNOT_2r = 314
    CEFBS_None, // AND_3r = 315
    CEFBS_None, // ASHR_l2rus = 316
    CEFBS_None, // ASHR_l3r = 317
    CEFBS_None, // BAU_1r = 318
    CEFBS_None, // BITREV_l2r = 319
    CEFBS_None, // BLACP_lu10 = 320
    CEFBS_None, // BLACP_u10 = 321
    CEFBS_None, // BLAT_lu6 = 322
    CEFBS_None, // BLAT_u6 = 323
    CEFBS_None, // BLA_1r = 324
    CEFBS_None, // BLRB_lu10 = 325
    CEFBS_None, // BLRB_u10 = 326
    CEFBS_None, // BLRF_lu10 = 327
    CEFBS_None, // BLRF_u10 = 328
    CEFBS_None, // BRBF_lru6 = 329
    CEFBS_None, // BRBF_ru6 = 330
    CEFBS_None, // BRBT_lru6 = 331
    CEFBS_None, // BRBT_ru6 = 332
    CEFBS_None, // BRBU_lu6 = 333
    CEFBS_None, // BRBU_u6 = 334
    CEFBS_None, // BRFF_lru6 = 335
    CEFBS_None, // BRFF_ru6 = 336
    CEFBS_None, // BRFT_lru6 = 337
    CEFBS_None, // BRFT_ru6 = 338
    CEFBS_None, // BRFU_lu6 = 339
    CEFBS_None, // BRFU_u6 = 340
    CEFBS_None, // BRU_1r = 341
    CEFBS_None, // BYTEREV_l2r = 342
    CEFBS_None, // CHKCT_2r = 343
    CEFBS_None, // CHKCT_rus = 344
    CEFBS_None, // CLRE_0R = 345
    CEFBS_None, // CLRPT_1R = 346
    CEFBS_None, // CLRSR_branch_lu6 = 347
    CEFBS_None, // CLRSR_branch_u6 = 348
    CEFBS_None, // CLRSR_lu6 = 349
    CEFBS_None, // CLRSR_u6 = 350
    CEFBS_None, // CLZ_l2r = 351
    CEFBS_None, // CRC8_l4r = 352
    CEFBS_None, // CRC_l3r = 353
    CEFBS_None, // DCALL_0R = 354
    CEFBS_None, // DENTSP_0R = 355
    CEFBS_None, // DGETREG_1r = 356
    CEFBS_None, // DIVS_l3r = 357
    CEFBS_None, // DIVU_l3r = 358
    CEFBS_None, // DRESTSP_0R = 359
    CEFBS_None, // DRET_0R = 360
    CEFBS_None, // ECALLF_1r = 361
    CEFBS_None, // ECALLT_1r = 362
    CEFBS_None, // EDU_1r = 363
    CEFBS_None, // EEF_2r = 364
    CEFBS_None, // EET_2r = 365
    CEFBS_None, // EEU_1r = 366
    CEFBS_None, // ENDIN_2r = 367
    CEFBS_None, // ENTSP_lu6 = 368
    CEFBS_None, // ENTSP_u6 = 369
    CEFBS_None, // EQ_2rus = 370
    CEFBS_None, // EQ_3r = 371
    CEFBS_None, // EXTDP_lu6 = 372
    CEFBS_None, // EXTDP_u6 = 373
    CEFBS_None, // EXTSP_lu6 = 374
    CEFBS_None, // EXTSP_u6 = 375
    CEFBS_None, // FREER_1r = 376
    CEFBS_None, // FREET_0R = 377
    CEFBS_None, // GETD_l2r = 378
    CEFBS_None, // GETED_0R = 379
    CEFBS_None, // GETET_0R = 380
    CEFBS_None, // GETID_0R = 381
    CEFBS_None, // GETKEP_0R = 382
    CEFBS_None, // GETKSP_0R = 383
    CEFBS_None, // GETN_l2r = 384
    CEFBS_None, // GETPS_l2r = 385
    CEFBS_None, // GETR_rus = 386
    CEFBS_None, // GETSR_lu6 = 387
    CEFBS_None, // GETSR_u6 = 388
    CEFBS_None, // GETST_2r = 389
    CEFBS_None, // GETTS_2r = 390
    CEFBS_None, // INCT_2r = 391
    CEFBS_None, // INITCP_2r = 392
    CEFBS_None, // INITDP_2r = 393
    CEFBS_None, // INITLR_l2r = 394
    CEFBS_None, // INITPC_2r = 395
    CEFBS_None, // INITSP_2r = 396
    CEFBS_None, // INPW_l2rus = 397
    CEFBS_None, // INSHR_2r = 398
    CEFBS_None, // INT_2r = 399
    CEFBS_None, // IN_2r = 400
    CEFBS_None, // KCALL_1r = 401
    CEFBS_None, // KCALL_lu6 = 402
    CEFBS_None, // KCALL_u6 = 403
    CEFBS_None, // KENTSP_lu6 = 404
    CEFBS_None, // KENTSP_u6 = 405
    CEFBS_None, // KRESTSP_lu6 = 406
    CEFBS_None, // KRESTSP_u6 = 407
    CEFBS_None, // KRET_0R = 408
    CEFBS_None, // LADD_l5r = 409
    CEFBS_None, // LD16S_3r = 410
    CEFBS_None, // LD8U_3r = 411
    CEFBS_None, // LDA16B_l3r = 412
    CEFBS_None, // LDA16F_l3r = 413
    CEFBS_None, // LDAPB_lu10 = 414
    CEFBS_None, // LDAPB_u10 = 415
    CEFBS_None, // LDAPF_lu10 = 416
    CEFBS_None, // LDAPF_lu10_ba = 417
    CEFBS_None, // LDAPF_u10 = 418
    CEFBS_None, // LDAWB_l2rus = 419
    CEFBS_None, // LDAWB_l3r = 420
    CEFBS_None, // LDAWCP_lu6 = 421
    CEFBS_None, // LDAWCP_u6 = 422
    CEFBS_None, // LDAWDP_lru6 = 423
    CEFBS_None, // LDAWDP_ru6 = 424
    CEFBS_None, // LDAWF_l2rus = 425
    CEFBS_None, // LDAWF_l3r = 426
    CEFBS_None, // LDAWSP_lru6 = 427
    CEFBS_None, // LDAWSP_ru6 = 428
    CEFBS_None, // LDC_lru6 = 429
    CEFBS_None, // LDC_ru6 = 430
    CEFBS_None, // LDET_0R = 431
    CEFBS_None, // LDIVU_l5r = 432
    CEFBS_None, // LDSED_0R = 433
    CEFBS_None, // LDSPC_0R = 434
    CEFBS_None, // LDSSR_0R = 435
    CEFBS_None, // LDWCP_lru6 = 436
    CEFBS_None, // LDWCP_lu10 = 437
    CEFBS_None, // LDWCP_ru6 = 438
    CEFBS_None, // LDWCP_u10 = 439
    CEFBS_None, // LDWDP_lru6 = 440
    CEFBS_None, // LDWDP_ru6 = 441
    CEFBS_None, // LDWSP_lru6 = 442
    CEFBS_None, // LDWSP_ru6 = 443
    CEFBS_None, // LDW_2rus = 444
    CEFBS_None, // LDW_3r = 445
    CEFBS_None, // LMUL_l6r = 446
    CEFBS_None, // LSS_3r = 447
    CEFBS_None, // LSUB_l5r = 448
    CEFBS_None, // LSU_3r = 449
    CEFBS_None, // MACCS_l4r = 450
    CEFBS_None, // MACCU_l4r = 451
    CEFBS_None, // MJOIN_1r = 452
    CEFBS_None, // MKMSK_2r = 453
    CEFBS_None, // MKMSK_rus = 454
    CEFBS_None, // MSYNC_1r = 455
    CEFBS_None, // MUL_l3r = 456
    CEFBS_None, // NEG = 457
    CEFBS_None, // NOT = 458
    CEFBS_None, // OR_3r = 459
    CEFBS_None, // OUTCT_2r = 460
    CEFBS_None, // OUTCT_rus = 461
    CEFBS_None, // OUTPW_l2rus = 462
    CEFBS_None, // OUTSHR_2r = 463
    CEFBS_None, // OUTT_2r = 464
    CEFBS_None, // OUT_2r = 465
    CEFBS_None, // PEEK_2r = 466
    CEFBS_None, // REMS_l3r = 467
    CEFBS_None, // REMU_l3r = 468
    CEFBS_None, // RETSP_lu6 = 469
    CEFBS_None, // RETSP_u6 = 470
    CEFBS_None, // SETCLK_l2r = 471
    CEFBS_None, // SETCP_1r = 472
    CEFBS_None, // SETC_l2r = 473
    CEFBS_None, // SETC_lru6 = 474
    CEFBS_None, // SETC_ru6 = 475
    CEFBS_None, // SETDP_1r = 476
    CEFBS_None, // SETD_2r = 477
    CEFBS_None, // SETEV_1r = 478
    CEFBS_None, // SETKEP_0R = 479
    CEFBS_None, // SETN_l2r = 480
    CEFBS_None, // SETPSC_2r = 481
    CEFBS_None, // SETPS_l2r = 482
    CEFBS_None, // SETPT_2r = 483
    CEFBS_None, // SETRDY_l2r = 484
    CEFBS_None, // SETSP_1r = 485
    CEFBS_None, // SETSR_branch_lu6 = 486
    CEFBS_None, // SETSR_branch_u6 = 487
    CEFBS_None, // SETSR_lu6 = 488
    CEFBS_None, // SETSR_u6 = 489
    CEFBS_None, // SETTW_l2r = 490
    CEFBS_None, // SETV_1r = 491
    CEFBS_None, // SEXT_2r = 492
    CEFBS_None, // SEXT_rus = 493
    CEFBS_None, // SHL_2rus = 494
    CEFBS_None, // SHL_3r = 495
    CEFBS_None, // SHR_2rus = 496
    CEFBS_None, // SHR_3r = 497
    CEFBS_None, // SSYNC_0r = 498
    CEFBS_None, // ST16_l3r = 499
    CEFBS_None, // ST8_l3r = 500
    CEFBS_None, // STET_0R = 501
    CEFBS_None, // STSED_0R = 502
    CEFBS_None, // STSPC_0R = 503
    CEFBS_None, // STSSR_0R = 504
    CEFBS_None, // STWDP_lru6 = 505
    CEFBS_None, // STWDP_ru6 = 506
    CEFBS_None, // STWSP_lru6 = 507
    CEFBS_None, // STWSP_ru6 = 508
    CEFBS_None, // STW_2rus = 509
    CEFBS_None, // STW_l3r = 510
    CEFBS_None, // SUB_2rus = 511
    CEFBS_None, // SUB_3r = 512
    CEFBS_None, // SYNCR_1r = 513
    CEFBS_None, // TESTCT_2r = 514
    CEFBS_None, // TESTLCL_l2r = 515
    CEFBS_None, // TESTWCT_2r = 516
    CEFBS_None, // TSETMR_2r = 517
    CEFBS_None, // TSETR_3r = 518
    CEFBS_None, // TSTART_1R = 519
    CEFBS_None, // WAITEF_1R = 520
    CEFBS_None, // WAITET_1R = 521
    CEFBS_None, // WAITEU_0R = 522
    CEFBS_None, // XOR_l3r = 523
    CEFBS_None, // ZEXT_2r = 524
    CEFBS_None, // ZEXT_rus = 525
  };

  assert(Opcode < 526);
  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
}

} // end namespace XCore_MC
} // end namespace llvm
#endif // GET_COMPUTE_FEATURES

#ifdef GET_AVAILABLE_OPCODE_CHECKER
#undef GET_AVAILABLE_OPCODE_CHECKER
namespace llvm {
namespace XCore_MC {
bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  return !MissingFeatures.any();
}
} // end namespace XCore_MC
} // end namespace llvm
#endif // GET_AVAILABLE_OPCODE_CHECKER

#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
#undef ENABLE_INSTR_PREDICATE_VERIFIER
#include <sstream>

namespace llvm {
namespace XCore_MC {

#ifndef NDEBUG
static const char *SubtargetFeatureNames[] = {
  nullptr
};

#endif // NDEBUG

void verifyInstructionPredicates(
    unsigned Opcode, const FeatureBitset &Features) {
#ifndef NDEBUG
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  if (MissingFeatures.any()) {
    std::ostringstream Msg;
    Msg << "Attempting to emit " << &XCoreInstrNameData[XCoreInstrNameIndices[Opcode]]
        << " instruction but the ";
    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
      if (MissingFeatures.test(i))
        Msg << SubtargetFeatureNames[i] << " ";
    Msg << "predicate(s) are not met";
    report_fatal_error(Msg.str().c_str());
  }
#endif // NDEBUG
}
} // end namespace XCore_MC
} // end namespace llvm
#endif // ENABLE_INSTR_PREDICATE_VERIFIER