llvm/llvm/lib/TargetParser/RISCVTargetParser.cpp

//===-- RISCVTargetParser.cpp - Parser for target features ------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file implements a target parser to recognise hardware features
// for RISC-V CPUs.
//
//===----------------------------------------------------------------------===//

#include "llvm/TargetParser/RISCVTargetParser.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/TargetParser/RISCVISAInfo.h"
#include "llvm/TargetParser/Triple.h"

namespace llvm {
namespace RISCV {

enum CPUKind : unsigned { … };

struct CPUInfo { … };

constexpr CPUInfo RISCVCPUInfo[] = …;

static const CPUInfo *getCPUInfoByName(StringRef CPU) { … }

bool hasFastScalarUnalignedAccess(StringRef CPU) { … }

bool hasFastVectorUnalignedAccess(StringRef CPU) { … }

bool parseCPU(StringRef CPU, bool IsRV64) { … }

bool parseTuneCPU(StringRef TuneCPU, bool IsRV64) { … }

StringRef getMArchFromMcpu(StringRef CPU) { … }

void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) { … }

void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) { … }

// This function is currently used by IREE, so it's not dead code.
void getFeaturesForCPU(StringRef CPU,
                       SmallVectorImpl<std::string> &EnabledFeatures,
                       bool NeedPlus) { … }

namespace RISCVExtensionBitmaskTable {
#define GET_RISCVExtensionBitmaskTable_IMPL
#include "llvm/TargetParser/RISCVTargetParserDef.inc"

} // namespace RISCVExtensionBitmaskTable

namespace {
struct LessExtName { … };
} // namespace

} // namespace RISCV

namespace RISCVVType {
// Encode VTYPE into the binary format used by the the VSETVLI instruction which
// is used by our MC layer representation.
//
// Bits | Name       | Description
// -----+------------+------------------------------------------------
// 7    | vma        | Vector mask agnostic
// 6    | vta        | Vector tail agnostic
// 5:3  | vsew[2:0]  | Standard element width (SEW) setting
// 2:0  | vlmul[2:0] | Vector register group multiplier (LMUL) setting
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
                     bool MaskAgnostic) { … }

std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL) { … }

void printVType(unsigned VType, raw_ostream &OS) { … }

unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) { … }

std::optional<RISCVII::VLMUL>
getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW) { … }

} // namespace RISCVVType

} // namespace llvm