llvm/llvm/test/Transforms/PhaseOrdering/X86/pr52289.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -O3 -S < %s | FileCheck %s

target datalayout = "n8:16:32:64"

define i32 @main(i32 %a) {
; CHECK-LABEL: @main(
; CHECK-NEXT:  if.end:
; CHECK-NEXT:    ret i32 0
;
  %inc = add nsw i32 %a, 1
  %and = and i32 %inc, 8
  %conv = trunc i32 %and to i8
  %call = call fastcc i8 @a(i8 %conv, i32 7)
  %conv1 = sext i8 %call to i64
  %call2 = call fastcc i64 @d(i64 %conv1)
  %mul = mul nsw i64 %call2, 20681
  %conv3 = trunc i64 %mul to i16
  %conv4 = sext i16 %conv3 to i32
  %xor = xor i32 %conv4, 1
  %tobool = icmp ne i32 %xor, 0
  br i1 %tobool, label %if.end, label %if.then

if.then:
  call void undef()
  br label %if.end

if.end:
  %call5 = call fastcc i8 @a(i8 0, i32 0)
  ret i32 0
}

define internal fastcc i8 @a(i8 %h, i32 %i) {
  %t0 = zext i8 %h to i32
  %cmp = icmp sgt i32 %t0, %i
  %shl = shl i32 %t0, %i
  %cond = select i1 %cmp, i32 %t0, i32 %shl
  %conv4 = trunc i32 %cond to i8
  ret i8 %conv4
}

define internal fastcc i64 @d(i64 %h) {
  ret i64 %h
}