llvm/llvm/test/Transforms/LoopVectorize/AArch64/cost-no-valid-vplans-built.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -p loop-vectorize -S %s | FileCheck %s

target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128-Fn32"
target triple = "arm64-apple-macosx15.0.0"

define void @test(i32 %N, ptr %dst) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: i32 [[N:%.*]], ptr [[DST:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*]]:
; CHECK-NEXT:    br label %[[LOOP:.*]]
; CHECK:       [[LOOP]]:
; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT:    [[FNEG137:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[FNEG1:%.*]], %[[LOOP]] ]
; CHECK-NEXT:    [[FNEG46:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[FNEG:%.*]], %[[LOOP]] ]
; CHECK-NEXT:    [[FNEG]] = fneg float [[FNEG137]]
; CHECK-NEXT:    [[FNEG1]] = fneg float [[FNEG46]]
; CHECK-NEXT:    [[GEP:%.*]] = getelementptr float, ptr [[DST]], i32 [[IV]]
; CHECK-NEXT:    store float [[FNEG1]], ptr [[GEP]], align 4
; CHECK-NEXT:    [[IV_NEXT]] = add i32 [[IV]], 1
; CHECK-NEXT:    [[EC:%.*]] = icmp eq i32 [[IV]], [[N]]
; CHECK-NEXT:    br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]
; CHECK:       [[EXIT]]:
; CHECK-NEXT:    ret void
;
entry:
  br label %loop

loop:
  %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
  %fneg137 = phi float [ 0.000000e+00, %entry ], [ %fneg1, %loop ]
  %fneg46 = phi float [ 0.000000e+00, %entry ], [ %fneg, %loop ]
  %fneg = fneg float %fneg137
  %fneg1 = fneg float %fneg46
  %gep = getelementptr float, ptr %dst, i32 %iv
  store float %fneg1, ptr %gep
  %iv.next = add i32 %iv, 1
  %ec = icmp eq i32 %iv, %N
  br i1 %ec, label %exit, label %loop

exit:
  ret void
}