# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s
---
name: shrink_scalar_imm_vgpr_v_add_i32_e64_no_carry_out_use
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_no_carry_out_use
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
%0:sreg_32_xm0 = S_MOV_B32 12345
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
S_ENDPGM 0, implicit %2
...
---
name: shrink_vgpr_scalar_imm_v_add_i32_e64_no_carry_out_use
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_add_i32_e64_no_carry_out_use
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
%0:vgpr_32 = IMPLICIT_DEF
%1:sreg_32_xm0 = S_MOV_B32 12345
%2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
S_ENDPGM 0, implicit %2
...
---
name: shrink_scalar_imm_vgpr_v_add_i32_e64_carry_out_use
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_carry_out_use
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
%0:sreg_32_xm0 = S_MOV_B32 12345
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
S_ENDPGM 0, implicit %2
...
---
# This does not shrink because it would violate the constant bus
# restriction. to have an SGPR input and an immediate, so a copy would
# be required.
name: shrink_vector_imm_sgpr_v_add_i32_e64_no_carry_out_use
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: shrink_vector_imm_sgpr_v_add_i32_e64_no_carry_out_use
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec
; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF
; GCN-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[DEF]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]]
%0:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec
%1:sreg_32_xm0 = IMPLICIT_DEF
%2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
S_ENDPGM 0, implicit %2
...
---
name: shrink_sgpr_vector_imm_v_add_i32_e64_no_carry_out_use
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: shrink_sgpr_vector_imm_v_add_i32_e64_no_carry_out_use
; GCN: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec
; GCN-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[V_MOV_B32_e32_]], [[DEF]], 0, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]]
%0:sreg_32_xm0 = IMPLICIT_DEF
%1:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec
%2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
S_ENDPGM 0, implicit %2
...
---
name: shrink_scalar_imm_vgpr_v_add_i32_e64_live_vcc_use
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_live_vcc_use
; GCN: $vcc = S_MOV_B64 -1
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[S_MOV_B32_]], [[DEF]], 0, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]], implicit $vcc
$vcc = S_MOV_B64 -1
%0:sreg_32_xm0 = S_MOV_B32 12345
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
S_ENDPGM 0, implicit %2, implicit $vcc
...
---
name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_use
tracksRegLiveness: true
body: |
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_use
; GCN: bb.0:
; GCN-NEXT: successors: %bb.1(0x80000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: $vcc = S_MOV_B64 -1
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[S_MOV_B32_]], [[DEF]], 0, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
; GCN-NEXT: liveins: $vcc
; GCN-NEXT: {{ $}}
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]], implicit $vcc
bb.0:
successors: %bb.1
$vcc = S_MOV_B64 -1
%0:sreg_32_xm0 = S_MOV_B32 12345
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
bb.1:
liveins: $vcc
S_ENDPGM 0, implicit %2, implicit $vcc
...
---
name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_lo_use
tracksRegLiveness: true
body: |
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_lo_use
; GCN: bb.0:
; GCN-NEXT: successors: %bb.1(0x80000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: $vcc = S_MOV_B64 -1
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[S_MOV_B32_]], [[DEF]], 0, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
; GCN-NEXT: liveins: $vcc_lo
; GCN-NEXT: {{ $}}
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]], implicit $vcc_lo
bb.0:
successors: %bb.1
$vcc = S_MOV_B64 -1
%0:sreg_32_xm0 = S_MOV_B32 12345
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
bb.1:
liveins: $vcc_lo
S_ENDPGM 0, implicit %2, implicit $vcc_lo
...
---
# This is not OK to clobber because vcc_lo has a livein use.
name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc
tracksRegLiveness: true
body: |
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc
; GCN: bb.0:
; GCN-NEXT: successors: %bb.1(0x80000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: $vcc = S_MOV_B64 -1
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
; GCN-NEXT: liveins: $vcc
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[S_MOV_B32_]], [[DEF]], 0, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]], implicit $vcc_lo
bb.0:
successors: %bb.1
$vcc = S_MOV_B64 -1
bb.1:
liveins: $vcc
%0:sreg_32_xm0 = S_MOV_B32 12345
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
S_ENDPGM 0, implicit %2, implicit $vcc_lo
...
---
name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc_hi
tracksRegLiveness: true
body: |
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc_hi
; GCN: bb.0:
; GCN-NEXT: successors: %bb.1(0x80000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: $vcc_hi = S_MOV_B32 -1
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
; GCN-NEXT: successors: %bb.2(0x80000000)
; GCN-NEXT: liveins: $vcc_hi
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[S_MOV_B32_]], [[DEF]], 0, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
; GCN-NEXT: liveins: $vcc_hi
; GCN-NEXT: {{ $}}
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]], implicit $vcc_hi
bb.0:
successors: %bb.1
$vcc_hi = S_MOV_B32 -1
bb.1:
liveins: $vcc_hi
%0:sreg_32_xm0 = S_MOV_B32 12345
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
bb.2:
liveins: $vcc_hi
S_ENDPGM 0, implicit %2, implicit $vcc_hi
...
---
name: shrink_scalar_imm_vgpr_v_sub_i32_e64_no_carry_out_use
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_sub_i32_e64_no_carry_out_use
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[V_SUB_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_SUB_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_SUB_CO_U32_e32_]]
%0:sreg_32_xm0 = S_MOV_B32 12345
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32, %3:sreg_64 = V_SUB_CO_U32_e64 %0, %1, 0, implicit $exec
S_ENDPGM 0, implicit %2
...
---
name: shrink_vgpr_scalar_imm_v_sub_i32_e64_no_carry_out_use
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_sub_i32_e64_no_carry_out_use
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
; GCN-NEXT: [[V_SUBREV_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_SUBREV_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_SUBREV_CO_U32_e32_]]
%0:vgpr_32 = IMPLICIT_DEF
%1:sreg_32_xm0 = S_MOV_B32 12345
%2:vgpr_32, %3:sreg_64 = V_SUB_CO_U32_e64 %0, %1, 0, implicit $exec
S_ENDPGM 0, implicit %2
...
---
name: shrink_scalar_imm_vgpr_v_subrev_i32_e64_no_carry_out_use
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_subrev_i32_e64_no_carry_out_use
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[V_SUBREV_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_SUBREV_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_SUBREV_CO_U32_e32_]]
%0:sreg_32_xm0 = S_MOV_B32 12345
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32, %3:sreg_64 = V_SUBREV_CO_U32_e64 %0, %1, 0, implicit $exec
S_ENDPGM 0, implicit %2
...
---
name: shrink_vgpr_scalar_imm_v_subrev_i32_e64_no_carry_out_use
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_subrev_i32_e64_no_carry_out_use
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
; GCN-NEXT: [[V_SUB_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_SUB_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_SUB_CO_U32_e32_]]
%0:vgpr_32 = IMPLICIT_DEF
%1:sreg_32_xm0 = S_MOV_B32 12345
%2:vgpr_32, %3:sreg_64 = V_SUBREV_CO_U32_e64 %0, %1, 0, implicit $exec
S_ENDPGM 0, implicit %2
...
---
# We know this is OK because vcc isn't live out of the block.
name: shrink_scalar_imm_vgpr_v_add_i32_e64_known_no_liveout
tracksRegLiveness: true
body: |
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_known_no_liveout
; GCN: bb.0:
; GCN-NEXT: successors: %bb.1(0x80000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
bb.0:
successors: %bb.1
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
%0:sreg_32_xm0 = S_MOV_B32 12345
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
S_NOP 0
S_NOP 0
bb.1:
S_ENDPGM 0, implicit %2
...
---
# We know this is OK because vcc isn't live out of the block, even
# though it had a defined but unused. value
name: shrink_scalar_imm_vgpr_v_add_i32_e64_known_no_liveout_dead_vcc_def
tracksRegLiveness: true
body: |
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_known_no_liveout_dead_vcc_def
; GCN: bb.0:
; GCN-NEXT: successors: %bb.1(0x80000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: S_NOP 0, implicit-def $vcc
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
bb.0:
successors: %bb.1
S_NOP 0, implicit-def $vcc
%0:sreg_32_xm0 = S_MOV_B32 12345
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
S_NOP 0
S_NOP 0
bb.1:
S_ENDPGM 0, implicit %2
...
---
# This requires searching through many DBG_VALUE instructions before the insert poitn, which
# should not count against the search limit.
name: vcc_liveness_dbg_value_search_before
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: vcc_liveness_dbg_value_search_before
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
%0:sreg_32_xm0 = S_MOV_B32 12345
%1:vgpr_32 = IMPLICIT_DEF
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
%2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
S_ENDPGM 0, implicit %2
...
---
# This requires searching through many DBG_VALUE instructions after the insert point, which
# should not count against the search limit.
name: vcc_liveness_dbg_value_search_after
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: vcc_liveness_dbg_value_search_after
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
%0:sreg_32_xm0 = S_MOV_B32 12345
%1:vgpr_32 = IMPLICIT_DEF
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
%2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
DBG_VALUE $noreg, 0
$vcc = S_MOV_B64 0
S_ENDPGM 0, implicit %2
...
---
name: shrink_add_kill_flags_src0
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; GCN-LABEL: name: shrink_add_kill_flags_src0
; GCN: liveins: $vgpr0
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 518144, implicit $exec
; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 killed [[V_MOV_B32_e32_]], [[COPY]], implicit-def $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = V_MOV_B32_e32 518144, implicit $exec
%2:vgpr_32, %3:sreg_64_xexec = V_ADD_CO_U32_e64 killed %1, %0, 0, implicit $exec
S_ENDPGM 0, implicit %2
...
---
name: shrink_add_kill_flags_src1
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; GCN-LABEL: name: shrink_add_kill_flags_src1
; GCN: liveins: $vgpr0
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 518144, implicit $exec
; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[V_MOV_B32_e32_]], killed [[COPY]], implicit-def $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = V_MOV_B32_e32 518144, implicit $exec
%2:vgpr_32, %3:sreg_64_xexec = V_ADD_CO_U32_e64 %1, killed %0, 0, implicit $exec
S_ENDPGM 0, implicit %2
...
---
name: shrink_addc_kill_flags_src2
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vcc
; GCN-LABEL: name: shrink_addc_kill_flags_src2
; GCN: liveins: $vgpr0, $vcc
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 518144, implicit $exec
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $vcc
; GCN-NEXT: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADDC_U32_e64 [[V_MOV_B32_e32_]], [[COPY]], [[COPY1]], 0, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADDC_U32_e64_]]
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = V_MOV_B32_e32 518144, implicit $exec
%2:sreg_64_xexec = COPY $vcc
%3:vgpr_32, %4:sreg_64_xexec = V_ADDC_U32_e64 %1, %0, %2, 0, implicit $exec
S_ENDPGM 0, implicit %3
...
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