regbankcombiner-fmed3-minmax-const.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s

---
name: test_min_max_ValK0_K1_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo:
  mode:
    ieee: true
body: |
  bb.1:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_min_max_ValK0_K1_f32
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
    ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_FMED3 [[COPY]], [[COPY1]], [[COPY2]]
    ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)
    %0:vgpr(s32) = COPY $vgpr0
    %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    %7:vgpr(s32) = COPY %2(s32)
    %3:vgpr(s32) = nnan G_FMAXNUM_IEEE %0, %7
    %4:sgpr(s32) = G_FCONSTANT float 4.000000e+00
    %8:vgpr(s32) = COPY %4(s32)
    %5:vgpr(s32) = nnan G_FMINNUM_IEEE %3, %8
    $vgpr0 = COPY %5(s32)
...

---
name: test_min_max_K0Val_K1_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo:
  mode:
    ieee: false
body: |
  bb.1:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_min_max_K0Val_K1_f32
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
    ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_FMED3 [[COPY]], [[COPY1]], [[COPY2]]
    ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)
    %0:vgpr(s32) = COPY $vgpr0
    %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    %7:vgpr(s32) = COPY %2(s32)
    %3:vgpr(s32) = nnan G_FMAXNUM %7, %0
    %4:sgpr(s32) = G_FCONSTANT float 4.000000e+00
    %8:vgpr(s32) = COPY %4(s32)
    %5:vgpr(s32) = nnan G_FMINNUM %3, %8
    $vgpr0 = COPY %5(s32)
...

---
name: test_min_K1max_ValK0_f16
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo:
  mode:
    ieee: true
body: |
  bb.1:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_min_K1max_ValK0_f16
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000
    ; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s16) = G_FCANONICALIZE [[TRUNC]]
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4400
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[C1]](s16)
    ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s16) = G_AMDGPU_FMED3 [[FCANONICALIZE]], [[COPY1]], [[COPY2]]
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_FMED3_]](s16)
    ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
    %2:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s16) = G_TRUNC %2(s32)
    %3:sgpr(s16) = G_FCONSTANT half 0xH4000
    %9:vgpr(s16) = G_FCANONICALIZE %0
    %10:vgpr(s16) = COPY %3(s16)
    %4:vgpr(s16) = G_FMAXNUM_IEEE %9, %10
    %5:sgpr(s16) = G_FCONSTANT half 0xH4400
    %11:vgpr(s16) = COPY %5(s16)
    %6:vgpr(s16) = G_FMINNUM_IEEE %11, %4
    %8:vgpr(s32) = G_ANYEXT %6(s16)
    $vgpr0 = COPY %8(s32)

...

---
name: test_min_K1max_K0Val_f16
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo:
  mode:
    ieee: false
body: |
  bb.1:
    liveins: $vgpr0, $sgpr30_sgpr31

    ; CHECK-LABEL: name: test_min_K1max_K0Val_f16
    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4400
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[C1]](s16)
    ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_FMED3 [[TRUNC]], [[COPY1]], [[COPY2]]
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_FMED3_]](s16)
    ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
    %2:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s16) = G_TRUNC %2(s32)
    %3:sgpr(s16) = G_FCONSTANT half 0xH4000
    %9:vgpr(s16) = COPY %3(s16)
    %4:vgpr(s16) = nnan G_FMAXNUM %9, %0
    %5:sgpr(s16) = G_FCONSTANT half 0xH4400
    %10:vgpr(s16) = COPY %5(s16)
    %6:vgpr(s16) = nnan G_FMINNUM %10, %4
    %8:vgpr(s32) = G_ANYEXT %6(s16)
    $vgpr0 = COPY %8(s32)
...

---
name: test_max_min_ValK1_K0_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo:
  mode:
    ieee: true
body: |
  bb.1:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_max_min_ValK1_K0_f32
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
    ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_FMED3 [[COPY]], [[COPY2]], [[COPY1]]
    ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)
    %0:vgpr(s32) = COPY $vgpr0
    %2:sgpr(s32) = G_FCONSTANT float 4.000000e+00
    %7:vgpr(s32) = COPY %2(s32)
    %3:vgpr(s32) = nnan G_FMINNUM_IEEE %0, %7
    %4:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    %8:vgpr(s32) = COPY %4(s32)
    %5:vgpr(s32) = nnan G_FMAXNUM_IEEE %3, %8
    $vgpr0 = COPY %5(s32)
...

---
name: test_max_min_K1Val_K0_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo:
  mode:
    ieee: false
body: |
  bb.1:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_max_min_K1Val_K0_f32
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
    ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_FMED3 [[COPY]], [[COPY2]], [[COPY1]]
    ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)
    %0:vgpr(s32) = COPY $vgpr0
    %2:sgpr(s32) = G_FCONSTANT float 4.000000e+00
    %7:vgpr(s32) = COPY %2(s32)
    %3:vgpr(s32) = nnan G_FMINNUM %7, %0
    %4:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    %8:vgpr(s32) = COPY %4(s32)
    %5:vgpr(s32) = nnan G_FMAXNUM %3, %8
    $vgpr0 = COPY %5(s32)
...

---
name: test_max_K0min_ValK1_f16
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo:
  mode:
    ieee: true
body: |
  bb.1:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_max_K0min_ValK1_f16
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4400
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[C1]](s16)
    ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_FMED3 [[TRUNC]], [[COPY2]], [[COPY1]]
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_FMED3_]](s16)
    ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
    %2:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s16) = G_TRUNC %2(s32)
    %3:sgpr(s16) = G_FCONSTANT half 0xH4400
    %9:vgpr(s16) = COPY %3(s16)
    %4:vgpr(s16) = nnan G_FMINNUM_IEEE %0, %9
    %5:sgpr(s16) = G_FCONSTANT half 0xH4000
    %10:vgpr(s16) = COPY %5(s16)
    %6:vgpr(s16) = nnan G_FMAXNUM_IEEE %10, %4
    %8:vgpr(s32) = G_ANYEXT %6(s16)
    $vgpr0 = COPY %8(s32)
...

---
name: test_max_K0min_K1Val_f16
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo:
  mode:
    ieee: false
body: |
  bb.1:
    liveins: $vgpr0, $sgpr30_sgpr31

    ; CHECK-LABEL: name: test_max_K0min_K1Val_f16
    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4400
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[C1]](s16)
    ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_FMED3 [[TRUNC]], [[COPY2]], [[COPY1]]
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_FMED3_]](s16)
    ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
    %2:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s16) = G_TRUNC %2(s32)
    %3:sgpr(s16) = G_FCONSTANT half 0xH4400
    %9:vgpr(s16) = COPY %3(s16)
    %4:vgpr(s16) = nnan G_FMINNUM %9, %0
    %5:sgpr(s16) = G_FCONSTANT half 0xH4000
    %10:vgpr(s16) = COPY %5(s16)
    %6:vgpr(s16) = nnan G_FMAXNUM %10, %4
    %8:vgpr(s32) = G_ANYEXT %6(s16)
    $vgpr0 = COPY %8(s32)
...

# FixMe: add tests with attributes #2 = {"no-nans-fp-math"="true"}

---
name: test_min_max_K0_gt_K1
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo:
  mode:
    ieee: true
body: |
  bb.1:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_min_max_K0_gt_K1
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
    ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
    ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
    ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[COPY2]]
    ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
    %0:vgpr(s32) = COPY $vgpr0
    %2:sgpr(s32) = G_FCONSTANT float 4.000000e+00
    %7:vgpr(s32) = COPY %2(s32)
    %3:vgpr(s32) = nnan G_FMAXNUM_IEEE %0, %7
    %4:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    %8:vgpr(s32) = COPY %4(s32)
    %5:vgpr(s32) = nnan G_FMINNUM_IEEE %3, %8
    $vgpr0 = COPY %5(s32)
...

---
name: test_max_min_K0_gt_K1
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo:
  mode:
    ieee: true
body: |
  bb.1:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_max_min_K0_gt_K1
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
    ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]]
    ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
    ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[COPY2]]
    ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
    %0:vgpr(s32) = COPY $vgpr0
    %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    %7:vgpr(s32) = COPY %2(s32)
    %3:vgpr(s32) = nnan G_FMINNUM_IEEE %0, %7
    %4:sgpr(s32) = G_FCONSTANT float 4.000000e+00
    %8:vgpr(s32) = COPY %4(s32)
    %5:vgpr(s32) = nnan G_FMAXNUM_IEEE %3, %8
    $vgpr0 = COPY %5(s32)
...

---
name: test_min_max_non_inline_const
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo:
  mode:
    ieee: true
body: |
  bb.1:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_min_max_non_inline_const
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
    ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
    ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 8.000000e+00
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
    ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[COPY2]]
    ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
    %0:vgpr(s32) = COPY $vgpr0
    %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    %7:vgpr(s32) = COPY %2(s32)
    %3:vgpr(s32) = nnan G_FMAXNUM_IEEE %0, %7
    %4:sgpr(s32) = G_FCONSTANT float 8.000000e+00
    %8:vgpr(s32) = COPY %4(s32)
    %5:vgpr(s32) = nnan G_FMINNUM_IEEE %3, %8
    $vgpr0 = COPY %5(s32)
...

---
name: test_min_max_f64
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo:
  mode:
    ieee: true
body: |
  bb.1:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: test_min_max_f64
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_FCONSTANT double 2.000000e+00
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[C]](s64)
    ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s64) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
    ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s64) = G_FCONSTANT double 4.000000e+00
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[C1]](s64)
    ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s64) = nnan G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[COPY2]]
    ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FMINNUM_IEEE]](s64)
    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %4:sgpr(s64) = G_FCONSTANT double 2.000000e+00
    %11:vgpr(s64) = COPY %4(s64)
    %5:vgpr(s64) = nnan G_FMAXNUM_IEEE %0, %11
    %6:sgpr(s64) = G_FCONSTANT double 4.000000e+00
    %12:vgpr(s64) = COPY %6(s64)
    %7:vgpr(s64) = nnan G_FMINNUM_IEEE %5, %12
    $vgpr0_vgpr1 = COPY %7(s64)
...

---
name: test_min_max_v2f16
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo:
  mode:
    ieee: true
body: |
  bb.1:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_min_max_v2f16
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[C]](s16)
    ; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4400
    ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[C1]](s16)
    ; CHECK-NEXT: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT1]](s32), [[ANYEXT1]](s32)
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
    ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(<2 x s16>) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
    ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(<2 x s16>) = nnan G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[COPY2]]
    ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](<2 x s16>)
    %0:vgpr(<2 x s16>) = COPY $vgpr0
    %3:sgpr(s16) = G_FCONSTANT half 0xH4000
    %9:sgpr(s32) = G_ANYEXT %3(s16)
    %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %9(s32), %9(s32)
    %6:sgpr(s16) = G_FCONSTANT half 0xH4400
    %10:sgpr(s32) = G_ANYEXT %6(s16)
    %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %10(s32), %10(s32)
    %11:vgpr(<2 x s16>) = COPY %2(<2 x s16>)
    %4:vgpr(<2 x s16>) = nnan G_FMAXNUM_IEEE %0, %11
    %12:vgpr(<2 x s16>) = COPY %5(<2 x s16>)
    %7:vgpr(<2 x s16>) = nnan G_FMINNUM_IEEE %4, %12
    $vgpr0 = COPY %7(<2 x s16>)
...

---
name: test_min_max_maybe_NaN_input_ieee_false
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo:
  mode:
    ieee: false
body: |
  bb.1:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_min_max_maybe_NaN_input_ieee_false
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
    ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:vgpr(s32) = G_FMAXNUM [[COPY]], [[COPY1]]
    ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
    ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:vgpr(s32) = G_FMINNUM [[FMAXNUM]], [[COPY2]]
    ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM]](s32)
    %0:vgpr(s32) = COPY $vgpr0
    %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    %7:vgpr(s32) = COPY %2(s32)
    %3:vgpr(s32) = G_FMAXNUM %0, %7
    %4:sgpr(s32) = G_FCONSTANT float 4.000000e+00
    %8:vgpr(s32) = COPY %4(s32)
    %5:vgpr(s32) = G_FMINNUM %3, %8
    $vgpr0 = COPY %5(s32)
...

---
name: test_max_min_maybe_NaN_input_ieee_false
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo:
  mode:
    ieee: false
body: |
  bb.1:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_max_min_maybe_NaN_input_ieee_false
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
    ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:vgpr(s32) = G_FMINNUM [[COPY]], [[COPY1]]
    ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
    ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:vgpr(s32) = G_FMAXNUM [[FMINNUM]], [[COPY2]]
    ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM]](s32)
    %0:vgpr(s32) = COPY $vgpr0
    %2:sgpr(s32) = G_FCONSTANT float 4.000000e+00
    %7:vgpr(s32) = COPY %2(s32)
    %3:vgpr(s32) = G_FMINNUM %0, %7
    %4:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    %8:vgpr(s32) = COPY %4(s32)
    %5:vgpr(s32) = G_FMAXNUM %3, %8
    $vgpr0 = COPY %5(s32)
...

---
name: test_max_min_maybe_NaN_input_ieee_true
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo:
  mode:
    ieee: true
body: |
  bb.1:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_max_min_maybe_NaN_input_ieee_true
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00
    ; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s32) = G_FCANONICALIZE [[COPY]]
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
    ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
    ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
    ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[COPY2]]
    ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
    %0:vgpr(s32) = COPY $vgpr0
    %2:sgpr(s32) = G_FCONSTANT float 4.000000e+00
    %7:vgpr(s32) = G_FCANONICALIZE %0
    %8:vgpr(s32) = COPY %2(s32)
    %3:vgpr(s32) = G_FMINNUM_IEEE %7, %8
    %4:sgpr(s32) = G_FCONSTANT float 2.000000e+00
    %9:vgpr(s32) = COPY %4(s32)
    %5:vgpr(s32) = G_FMAXNUM_IEEE %3, %9
    $vgpr0 = COPY %5(s32)
...
llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-fmed3-minmax-const.mir
