# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
---
name: remove_and_255_zextload
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: remove_and_255_zextload
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p1) = COPY $vgpr0_vgpr1
; CHECK-NEXT: %and:_(s32) = G_ZEXTLOAD %ptr(p1) :: (load (s8), addrspace 1)
; CHECK-NEXT: $vgpr0 = COPY %and(s32)
%ptr:_(p1) = COPY $vgpr0_vgpr1
%load:_(s32) = G_ZEXTLOAD %ptr :: (load (s8), addrspace 1, align 1)
%mask:_(s32) = G_CONSTANT i32 255
%and:_(s32) = G_AND %load, %mask
$vgpr0 = COPY %and
...
---
name: remove_and_255_smin_zextload
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: remove_and_255_smin_zextload
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr0:_(p1) = COPY $vgpr0_vgpr1
; CHECK-NEXT: %ptr1:_(p1) = COPY $vgpr2_vgpr3
; CHECK-NEXT: %load0:_(s32) = G_ZEXTLOAD %ptr0(p1) :: (load (s8), addrspace 1)
; CHECK-NEXT: %load1:_(s32) = G_ZEXTLOAD %ptr1(p1) :: (load (s8), addrspace 1)
; CHECK-NEXT: %smin:_(s32) = G_SMIN %load0, %load1
; CHECK-NEXT: $vgpr0 = COPY %smin(s32)
%ptr0:_(p1) = COPY $vgpr0_vgpr1
%ptr1:_(p1) = COPY $vgpr2_vgpr3
%load0:_(s32) = G_ZEXTLOAD %ptr0 :: (load (s8), addrspace 1, align 1)
%load1:_(s32) = G_ZEXTLOAD %ptr1 :: (load (s8), addrspace 1, align 1)
%smin:_(s32) = G_SMIN %load0, %load1
%mask:_(s32) = G_CONSTANT i32 255
%and:_(s32) = G_AND %smin, %mask
$vgpr0 = COPY %and
...
---
name: remove_and_255_smax_zextload
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: remove_and_255_smax_zextload
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr0:_(p1) = COPY $vgpr0_vgpr1
; CHECK-NEXT: %ptr1:_(p1) = COPY $vgpr2_vgpr3
; CHECK-NEXT: %load0:_(s32) = G_ZEXTLOAD %ptr0(p1) :: (load (s8), addrspace 1)
; CHECK-NEXT: %load1:_(s32) = G_ZEXTLOAD %ptr1(p1) :: (load (s8), addrspace 1)
; CHECK-NEXT: %smax:_(s32) = G_SMAX %load0, %load1
; CHECK-NEXT: $vgpr0 = COPY %smax(s32)
%ptr0:_(p1) = COPY $vgpr0_vgpr1
%ptr1:_(p1) = COPY $vgpr2_vgpr3
%load0:_(s32) = G_ZEXTLOAD %ptr0 :: (load (s8), addrspace 1, align 1)
%load1:_(s32) = G_ZEXTLOAD %ptr1 :: (load (s8), addrspace 1, align 1)
%smax:_(s32) = G_SMAX %load0, %load1
%mask:_(s32) = G_CONSTANT i32 255
%and:_(s32) = G_AND %smax, %mask
$vgpr0 = COPY %and
...
---
name: remove_and_255_umin_zextload
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: remove_and_255_umin_zextload
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr0:_(p1) = COPY $vgpr0_vgpr1
; CHECK-NEXT: %ptr1:_(p1) = COPY $vgpr2_vgpr3
; CHECK-NEXT: %load0:_(s32) = G_ZEXTLOAD %ptr0(p1) :: (load (s8), addrspace 1)
; CHECK-NEXT: %load1:_(s32) = G_ZEXTLOAD %ptr1(p1) :: (load (s8), addrspace 1)
; CHECK-NEXT: %umin:_(s32) = G_UMIN %load0, %load1
; CHECK-NEXT: $vgpr0 = COPY %umin(s32)
%ptr0:_(p1) = COPY $vgpr0_vgpr1
%ptr1:_(p1) = COPY $vgpr2_vgpr3
%load0:_(s32) = G_ZEXTLOAD %ptr0 :: (load (s8), addrspace 1, align 1)
%load1:_(s32) = G_ZEXTLOAD %ptr1 :: (load (s8), addrspace 1, align 1)
%umin:_(s32) = G_UMIN %load0, %load1
%mask:_(s32) = G_CONSTANT i32 255
%and:_(s32) = G_AND %umin, %mask
$vgpr0 = COPY %and
...
---
name: remove_and_255_umax_zextload
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: remove_and_255_umax_zextload
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr0:_(p1) = COPY $vgpr0_vgpr1
; CHECK-NEXT: %ptr1:_(p1) = COPY $vgpr2_vgpr3
; CHECK-NEXT: %load0:_(s32) = G_ZEXTLOAD %ptr0(p1) :: (load (s8), addrspace 1)
; CHECK-NEXT: %load1:_(s32) = G_ZEXTLOAD %ptr1(p1) :: (load (s8), addrspace 1)
; CHECK-NEXT: %umax:_(s32) = G_UMAX %load0, %load1
; CHECK-NEXT: $vgpr0 = COPY %umax(s32)
%ptr0:_(p1) = COPY $vgpr0_vgpr1
%ptr1:_(p1) = COPY $vgpr2_vgpr3
%load0:_(s32) = G_ZEXTLOAD %ptr0 :: (load (s8), addrspace 1, align 1)
%load1:_(s32) = G_ZEXTLOAD %ptr1 :: (load (s8), addrspace 1, align 1)
%umax:_(s32) = G_UMAX %load0, %load1
%mask:_(s32) = G_CONSTANT i32 255
%and:_(s32) = G_AND %umax, %mask
$vgpr0 = COPY %and
...
# Don't have enough known bits for lhs
---
name: remove_and_255_smin_fail_lhs
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: remove_and_255_smin_fail_lhs
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr0:_(p1) = COPY $vgpr0_vgpr1
; CHECK-NEXT: %ptr1:_(p1) = COPY $vgpr2_vgpr3
; CHECK-NEXT: %load0:_(s32) = G_LOAD %ptr0(p1) :: (load (s32), addrspace 1)
; CHECK-NEXT: %load1:_(s32) = G_ZEXTLOAD %ptr1(p1) :: (load (s8), addrspace 1)
; CHECK-NEXT: %smin:_(s32) = G_SMIN %load0, %load1
; CHECK-NEXT: %mask:_(s32) = G_CONSTANT i32 255
; CHECK-NEXT: %and:_(s32) = G_AND %smin, %mask
; CHECK-NEXT: $vgpr0 = COPY %and(s32)
%ptr0:_(p1) = COPY $vgpr0_vgpr1
%ptr1:_(p1) = COPY $vgpr2_vgpr3
%load0:_(s32) = G_LOAD %ptr0 :: (load (s32), addrspace 1, align 4)
%load1:_(s32) = G_ZEXTLOAD %ptr1 :: (load (s8), addrspace 1, align 1)
%smin:_(s32) = G_SMIN %load0, %load1
%mask:_(s32) = G_CONSTANT i32 255
%and:_(s32) = G_AND %smin, %mask
$vgpr0 = COPY %and
...
# Don't have enough known bits for rhs
---
name: remove_and_255_smin_fail_rhs
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: remove_and_255_smin_fail_rhs
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr0:_(p1) = COPY $vgpr0_vgpr1
; CHECK-NEXT: %ptr1:_(p1) = COPY $vgpr2_vgpr3
; CHECK-NEXT: %load0:_(s32) = G_ZEXTLOAD %ptr0(p1) :: (load (s8), addrspace 1)
; CHECK-NEXT: %load1:_(s32) = G_LOAD %ptr1(p1) :: (load (s32), addrspace 1)
; CHECK-NEXT: %smin:_(s32) = G_SMIN %load0, %load1
; CHECK-NEXT: %mask:_(s32) = G_CONSTANT i32 255
; CHECK-NEXT: %and:_(s32) = G_AND %smin, %mask
; CHECK-NEXT: $vgpr0 = COPY %and(s32)
%ptr0:_(p1) = COPY $vgpr0_vgpr1
%ptr1:_(p1) = COPY $vgpr2_vgpr3
%load0:_(s32) = G_ZEXTLOAD %ptr0 :: (load (s8), addrspace 1, align 1)
%load1:_(s32) = G_LOAD %ptr1 :: (load (s32), addrspace 1, align 4)
%smin:_(s32) = G_SMIN %load0, %load1
%mask:_(s32) = G_CONSTANT i32 255
%and:_(s32) = G_AND %smin, %mask
$vgpr0 = COPY %and
...
# Test known bits for groupstaticsize is the maximum LDS size.
---
name: remove_and_65535_groupstaticsize
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: remove_and_65535_groupstaticsize
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p1) = COPY $vgpr0_vgpr1
; CHECK-NEXT: %lds_size:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.groupstaticsize)
; CHECK-NEXT: %mask:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: %and:_(s32) = G_AND %lds_size, %mask
; CHECK-NEXT: $vgpr0 = COPY %and(s32)
%ptr:_(p1) = COPY $vgpr0_vgpr1
%lds_size:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.groupstaticsize)
%mask:_(s32) = G_CONSTANT i32 65535
%and:_(s32) = G_AND %lds_size, %mask
$vgpr0 = COPY %and
...
---
name: remove_and_131071_groupstaticsize
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: remove_and_131071_groupstaticsize
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p1) = COPY $vgpr0_vgpr1
; CHECK-NEXT: %lds_size:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.groupstaticsize)
; CHECK-NEXT: $vgpr0 = COPY %lds_size(s32)
%ptr:_(p1) = COPY $vgpr0_vgpr1
%lds_size:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.groupstaticsize)
%mask:_(s32) = G_CONSTANT i32 131071
%and:_(s32) = G_AND %lds_size, %mask
$vgpr0 = COPY %and
...
---
name: no_remove_and_65536_groupstaticsize
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: no_remove_and_65536_groupstaticsize
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p1) = COPY $vgpr0_vgpr1
; CHECK-NEXT: %lds_size:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.groupstaticsize)
; CHECK-NEXT: %mask:_(s32) = G_CONSTANT i32 65536
; CHECK-NEXT: %and:_(s32) = G_AND %lds_size, %mask
; CHECK-NEXT: $vgpr0 = COPY %and(s32)
%ptr:_(p1) = COPY $vgpr0_vgpr1
%lds_size:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.groupstaticsize)
%mask:_(s32) = G_CONSTANT i32 65536
%and:_(s32) = G_AND %lds_size, %mask
$vgpr0 = COPY %and
...
---
name: no_remove_and_32767_groupstaticsize
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: no_remove_and_32767_groupstaticsize
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p1) = COPY $vgpr0_vgpr1
; CHECK-NEXT: %lds_size:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.groupstaticsize)
; CHECK-NEXT: %mask:_(s32) = G_CONSTANT i32 32767
; CHECK-NEXT: %and:_(s32) = G_AND %lds_size, %mask
; CHECK-NEXT: $vgpr0 = COPY %and(s32)
%ptr:_(p1) = COPY $vgpr0_vgpr1
%lds_size:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.groupstaticsize)
%mask:_(s32) = G_CONSTANT i32 32767
%and:_(s32) = G_AND %lds_size, %mask
$vgpr0 = COPY %and
...
# We can conclude the number of bits based only on one operand
---
name: remove_and_umin_lhs_only
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4
; CHECK-LABEL: name: remove_and_umin_lhs_only
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr0:_(p1) = COPY $vgpr0_vgpr1
; CHECK-NEXT: %ptr1:_(p1) = COPY $vgpr2_vgpr3
; CHECK-NEXT: %val:_(s32) = COPY $vgpr4
; CHECK-NEXT: %k255:_(s32) = G_CONSTANT i32 255
; CHECK-NEXT: %umin0:_(s32) = G_UMIN %val, %k255
; CHECK-NEXT: $vgpr0 = COPY %umin0(s32)
%ptr0:_(p1) = COPY $vgpr0_vgpr1
%ptr1:_(p1) = COPY $vgpr2_vgpr3
%val:_(s32) = COPY $vgpr4
%k255:_(s32) = G_CONSTANT i32 255
%umin0:_(s32) = G_UMIN %val, %k255
%and:_(s32) = G_AND %umin0, %k255
$vgpr0 = COPY %and
...
---
name: remove_and_umin_rhs_only
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4
; CHECK-LABEL: name: remove_and_umin_rhs_only
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr0:_(p1) = COPY $vgpr0_vgpr1
; CHECK-NEXT: %ptr1:_(p1) = COPY $vgpr2_vgpr3
; CHECK-NEXT: %val:_(s32) = COPY $vgpr4
; CHECK-NEXT: %k255:_(s32) = G_CONSTANT i32 255
; CHECK-NEXT: %umin0:_(s32) = G_UMIN %val, %k255
; CHECK-NEXT: $vgpr0 = COPY %umin0(s32)
%ptr0:_(p1) = COPY $vgpr0_vgpr1
%ptr1:_(p1) = COPY $vgpr2_vgpr3
%val:_(s32) = COPY $vgpr4
%k255:_(s32) = G_CONSTANT i32 255
%umin0:_(s32) = G_UMIN %k255, %val
%and:_(s32) = G_AND %umin0, %k255
$vgpr0 = COPY %and
...
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