llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-strict_fsub.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GCN %s

---
name: test_strict_fsub_s64
body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; GCN-LABEL: name: test_strict_fsub_s64
    ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
    ; GCN-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
    ; GCN-NEXT: [[STRICT_FADD:%[0-9]+]]:_(s64) = G_STRICT_FADD [[COPY]], [[FNEG]]
    ; GCN-NEXT: $vgpr0_vgpr1 = COPY [[STRICT_FADD]](s64)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s64) = COPY $vgpr2_vgpr3
    %2:_(s64) = G_STRICT_FSUB %0, %1
    $vgpr0_vgpr1 = COPY %2
...

---
name: test_strict_fsub_v2s16
body: |
  bb.0.entry:
    liveins: $vgpr0, $vgpr1

    ; GCN-LABEL: name: test_strict_fsub_v2s16
    ; GCN: liveins: $vgpr0, $vgpr1
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
    ; GCN-NEXT: [[FNEG:%[0-9]+]]:_(<2 x s16>) = G_FNEG [[COPY1]]
    ; GCN-NEXT: [[STRICT_FADD:%[0-9]+]]:_(<2 x s16>) = G_STRICT_FADD [[COPY]], [[FNEG]]
    ; GCN-NEXT: $vgpr0 = COPY [[STRICT_FADD]](<2 x s16>)
    %0:_(<2 x s16>) = COPY $vgpr0
    %1:_(<2 x s16>) = COPY $vgpr1
    %2:_(<2 x s16>) = G_STRICT_FSUB %0, %1
    $vgpr0 = COPY %2
...