# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE64 %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -O0 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE32 %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -O0 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE32 %s
---
name: legal_brcond_vcc
body: |
; WAVE64-LABEL: name: legal_brcond_vcc
; WAVE64: bb.0:
; WAVE64-NEXT: successors: %bb.1(0x80000000)
; WAVE64-NEXT: liveins: $vgpr0, $vgpr1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE64-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE64-NEXT: G_BRCOND [[ICMP]](s1), %bb.1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.1:
; WAVE32-LABEL: name: legal_brcond_vcc
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
; WAVE32-NEXT: liveins: $vgpr0, $vgpr1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE32-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE32-NEXT: G_BRCOND [[ICMP]](s1), %bb.1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.1:
bb.0:
successors: %bb.1
liveins: $vgpr0, $vgpr1
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1
G_BRCOND %2, %bb.1
bb.1:
...
---
name: legal_brcond_sgpr_s1
body: |
; WAVE64-LABEL: name: legal_brcond_sgpr_s1
; WAVE64: bb.0:
; WAVE64-NEXT: successors: %bb.1(0x80000000)
; WAVE64-NEXT: liveins: $sgpr0, $sgpr1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
; WAVE64-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
; WAVE64-NEXT: G_BRCOND [[ICMP]](s1), %bb.1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.1:
; WAVE32-LABEL: name: legal_brcond_sgpr_s1
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
; WAVE32-NEXT: liveins: $sgpr0, $sgpr1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
; WAVE32-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
; WAVE32-NEXT: G_BRCOND [[ICMP]](s1), %bb.1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.1:
bb.0:
liveins: $sgpr0, $sgpr1
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s1) = G_ICMP intpred(eq), %0, %1
G_BRCOND %2, %bb.1
bb.1:
...
---
name: legal_brcond_sgpr_s32
body: |
; WAVE64-LABEL: name: legal_brcond_sgpr_s32
; WAVE64: bb.0:
; WAVE64-NEXT: successors: %bb.1(0x80000000)
; WAVE64-NEXT: liveins: $sgpr0, $sgpr1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
; WAVE64-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
; WAVE64-NEXT: G_BRCOND [[ICMP]](s32), %bb.1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.1:
; WAVE32-LABEL: name: legal_brcond_sgpr_s32
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
; WAVE32-NEXT: liveins: $sgpr0, $sgpr1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
; WAVE32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
; WAVE32-NEXT: G_BRCOND [[ICMP]](s32), %bb.1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.1:
bb.0:
liveins: $sgpr0, $sgpr1
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = G_ICMP intpred(eq), %0, %1
G_BRCOND %2, %bb.1
bb.1:
...
---
name: brcond_si_if
body: |
; WAVE64-LABEL: name: brcond_si_if
; WAVE64: bb.0:
; WAVE64-NEXT: successors: %bb.1(0x80000000)
; WAVE64-NEXT: liveins: $vgpr0, $vgpr1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE64-NEXT: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE64-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE64-NEXT: G_BR %bb.1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.1:
; WAVE32-LABEL: name: brcond_si_if
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
; WAVE32-NEXT: liveins: $vgpr0, $vgpr1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE32-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE32-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE32-NEXT: G_BR %bb.1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.1:
bb.0:
successors: %bb.1
liveins: $vgpr0, $vgpr1
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
G_BRCOND %3, %bb.1
bb.1:
...
---
name: brcond_si_else
body: |
; WAVE64-LABEL: name: brcond_si_else
; WAVE64: bb.0:
; WAVE64-NEXT: successors: %bb.1(0x80000000)
; WAVE64-NEXT: liveins: $vgpr0, $vgpr1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE64-NEXT: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE64-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_64_xexec(s64) = SI_ELSE [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE64-NEXT: G_BR %bb.1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.1:
; WAVE32-LABEL: name: brcond_si_else
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
; WAVE32-NEXT: liveins: $vgpr0, $vgpr1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE32-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE32-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_ELSE [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE32-NEXT: G_BR %bb.1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.1:
bb.0:
successors: %bb.1
liveins: $vgpr0, $vgpr1
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.else), %2
G_BRCOND %3, %bb.1
bb.1:
...
---
name: brcond_si_loop_brcond
tracksRegLiveness: true
body: |
; WAVE64-LABEL: name: brcond_si_loop_brcond
; WAVE64: bb.0:
; WAVE64-NEXT: successors: %bb.1(0x80000000)
; WAVE64-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sreg_64_xexec(s64) = COPY $sgpr0_sgpr1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.1:
; WAVE64-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: S_NOP 0
; WAVE64-NEXT: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE64-NEXT: G_BR %bb.2
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.2:
; WAVE64-NEXT: S_NOP 0
; WAVE32-LABEL: name: brcond_si_loop_brcond
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
; WAVE32-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY $sgpr0_sgpr1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.1:
; WAVE32-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: S_NOP 0
; WAVE32-NEXT: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE32-NEXT: G_BR %bb.2
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.2:
; WAVE32-NEXT: S_NOP 0
bb.0:
liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s64) = COPY $sgpr0_sgpr1
bb.1:
successors: %bb.1, %bb.2
S_NOP 0
%3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2
G_BRCOND %3, %bb.2
G_BR %bb.1
bb.2:
S_NOP 0
...
# This usage is backwards from how the intrinsic is supposed to be
# used.
---
name: brcond_si_loop_brcond_back
tracksRegLiveness: true
body: |
; WAVE64-LABEL: name: brcond_si_loop_brcond_back
; WAVE64: bb.0:
; WAVE64-NEXT: successors: %bb.1(0x80000000)
; WAVE64-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sreg_64_xexec(s64) = COPY $sgpr0_sgpr1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.1:
; WAVE64-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: S_NOP 0
; WAVE64-NEXT: SI_LOOP [[COPY2]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE64-NEXT: G_BR %bb.1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.2:
; WAVE64-NEXT: S_NOP 0
; WAVE32-LABEL: name: brcond_si_loop_brcond_back
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
; WAVE32-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY $sgpr0_sgpr1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.1:
; WAVE32-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: S_NOP 0
; WAVE32-NEXT: SI_LOOP [[COPY2]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE32-NEXT: G_BR %bb.1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.2:
; WAVE32-NEXT: S_NOP 0
bb.0:
liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s64) = COPY $sgpr0_sgpr1
bb.1:
successors: %bb.1, %bb.2
S_NOP 0
%3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2
G_BRCOND %3, %bb.1
G_BR %bb.2
bb.2:
S_NOP 0
...
# This usage is backwards from how the intrinsic is supposed to be
# used.
---
name: brcond_si_loop_brcond_back_fallthrough
tracksRegLiveness: true
body: |
; WAVE64-LABEL: name: brcond_si_loop_brcond_back_fallthrough
; WAVE64: bb.0:
; WAVE64-NEXT: successors: %bb.1(0x80000000)
; WAVE64-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sreg_64_xexec(s64) = COPY $sgpr0_sgpr1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.1:
; WAVE64-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: S_NOP 0
; WAVE64-NEXT: SI_LOOP [[COPY2]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE64-NEXT: G_BR %bb.1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.2:
; WAVE32-LABEL: name: brcond_si_loop_brcond_back_fallthrough
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
; WAVE32-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY $sgpr0_sgpr1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.1:
; WAVE32-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: S_NOP 0
; WAVE32-NEXT: SI_LOOP [[COPY2]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE32-NEXT: G_BR %bb.1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.2:
bb.0:
liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s64) = COPY $sgpr0_sgpr1
bb.1:
successors: %bb.1, %bb.2
S_NOP 0
%3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2
G_BRCOND %3, %bb.1
bb.2:
...
# There's another instruction between the intrinsic and the
# conditional branch, so we need to move the insert point.
---
name: brcond_si_if_need_insert_terminator_point
body: |
; WAVE64-LABEL: name: brcond_si_if_need_insert_terminator_point
; WAVE64: bb.0:
; WAVE64-NEXT: successors: %bb.1(0x80000000)
; WAVE64-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE64-NEXT: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; WAVE64-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE64-NEXT: G_BR %bb.1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.1:
; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY2]](s32)
; WAVE32-LABEL: name: brcond_si_if_need_insert_terminator_point
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
; WAVE32-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE32-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; WAVE32-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE32-NEXT: G_BR %bb.1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.1:
; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY2]](s32)
bb.0:
successors: %bb.1
liveins: $vgpr0, $vgpr1, $vgpr2
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
%5:_(s32) = COPY $vgpr2
G_BRCOND %3, %bb.1
bb.1:
S_ENDPGM 0, implicit %5
...
---
name: brcond_si_loop_need_terminator_insert_point
tracksRegLiveness: true
body: |
; WAVE64-LABEL: name: brcond_si_loop_need_terminator_insert_point
; WAVE64: bb.0:
; WAVE64-NEXT: successors: %bb.1(0x80000000)
; WAVE64-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sreg_64_xexec(s64) = COPY $sgpr0_sgpr1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.1:
; WAVE64-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: S_NOP 0
; WAVE64-NEXT: S_NOP 0
; WAVE64-NEXT: S_NOP 0
; WAVE64-NEXT: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE64-NEXT: G_BR %bb.2
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.2:
; WAVE64-NEXT: S_NOP 0
; WAVE32-LABEL: name: brcond_si_loop_need_terminator_insert_point
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
; WAVE32-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY $sgpr0_sgpr1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.1:
; WAVE32-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: S_NOP 0
; WAVE32-NEXT: S_NOP 0
; WAVE32-NEXT: S_NOP 0
; WAVE32-NEXT: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE32-NEXT: G_BR %bb.2
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.2:
; WAVE32-NEXT: S_NOP 0
bb.0:
liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s64) = COPY $sgpr0_sgpr1
bb.1:
successors: %bb.1, %bb.2
S_NOP 0
%3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2
S_NOP 0
S_NOP 0
G_BRCOND %3, %bb.2
G_BR %bb.1
bb.2:
S_NOP 0
...
---
name: brcond_si_if_negated
body: |
; WAVE64-LABEL: name: brcond_si_if_negated
; WAVE64: bb.0:
; WAVE64-NEXT: successors: %bb.1(0x80000000)
; WAVE64-NEXT: liveins: $vgpr0, $vgpr1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE64-NEXT: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE64-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[ICMP]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE64-NEXT: G_BR %bb.1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.1:
; WAVE64-NEXT: successors: %bb.2(0x80000000)
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: S_NOP 0
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.2:
; WAVE64-NEXT: S_NOP 1
; WAVE32-LABEL: name: brcond_si_if_negated
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
; WAVE32-NEXT: liveins: $vgpr0, $vgpr1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE32-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE32-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[ICMP]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE32-NEXT: G_BR %bb.1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.1:
; WAVE32-NEXT: successors: %bb.2(0x80000000)
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: S_NOP 0
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.2:
; WAVE32-NEXT: S_NOP 1
bb.0:
successors: %bb.1
liveins: $vgpr0, $vgpr1
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
%5:_(s1) = G_CONSTANT i1 true
%6:_(s1) = G_XOR %3, %5
G_BRCOND %6, %bb.2
bb.1:
S_NOP 0
bb.2:
S_NOP 1
...
---
name: brcond_si_if_br_negated
body: |
; WAVE64-LABEL: name: brcond_si_if_br_negated
; WAVE64: bb.0:
; WAVE64-NEXT: successors: %bb.1(0x80000000)
; WAVE64-NEXT: liveins: $vgpr0, $vgpr1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE64-NEXT: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE64-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[ICMP]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE64-NEXT: G_BR %bb.3
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.1:
; WAVE64-NEXT: successors: %bb.2(0x80000000)
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: S_NOP 0
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.2:
; WAVE64-NEXT: successors: %bb.3(0x80000000)
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: S_NOP 1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.3:
; WAVE64-NEXT: S_NOP 2
; WAVE32-LABEL: name: brcond_si_if_br_negated
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
; WAVE32-NEXT: liveins: $vgpr0, $vgpr1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE32-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE32-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[ICMP]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE32-NEXT: G_BR %bb.3
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.1:
; WAVE32-NEXT: successors: %bb.2(0x80000000)
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: S_NOP 0
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.2:
; WAVE32-NEXT: successors: %bb.3(0x80000000)
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: S_NOP 1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.3:
; WAVE32-NEXT: S_NOP 2
bb.0:
successors: %bb.1
liveins: $vgpr0, $vgpr1
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
%5:_(s1) = G_CONSTANT i1 true
%6:_(s1) = G_XOR %3, %5
G_BRCOND %6, %bb.2
G_BR %bb.3
bb.1:
S_NOP 0
bb.2:
S_NOP 1
bb.3:
S_NOP 2
...
---
name: brcond_si_loop_brcond_negated
tracksRegLiveness: true
body: |
; WAVE64-LABEL: name: brcond_si_loop_brcond_negated
; WAVE64: bb.0:
; WAVE64-NEXT: successors: %bb.1(0x80000000)
; WAVE64-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sreg_64_xexec(s64) = COPY $sgpr0_sgpr1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.1:
; WAVE64-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: S_NOP 0
; WAVE64-NEXT: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE64-NEXT: G_BR %bb.2
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.2:
; WAVE64-NEXT: S_NOP 0
; WAVE32-LABEL: name: brcond_si_loop_brcond_negated
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
; WAVE32-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY $sgpr0_sgpr1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.1:
; WAVE32-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: S_NOP 0
; WAVE32-NEXT: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE32-NEXT: G_BR %bb.2
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.2:
; WAVE32-NEXT: S_NOP 0
bb.0:
liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s64) = COPY $sgpr0_sgpr1
bb.1:
successors: %bb.1, %bb.2
S_NOP 0
%3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2
%4:_(s1) = G_CONSTANT i1 true
%5:_(s1) = G_XOR %3, %4
G_BRCOND %5, %bb.1
bb.2:
S_NOP 0
...
---
name: brcond_si_loop_brcond_br_negated
tracksRegLiveness: true
body: |
; WAVE64-LABEL: name: brcond_si_loop_brcond_br_negated
; WAVE64: bb.0:
; WAVE64-NEXT: successors: %bb.1(0x80000000)
; WAVE64-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sreg_64_xexec(s64) = COPY $sgpr0_sgpr1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.1:
; WAVE64-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: S_NOP 0
; WAVE64-NEXT: SI_LOOP [[COPY2]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE64-NEXT: G_BR %bb.1
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: bb.2:
; WAVE64-NEXT: S_NOP 0
; WAVE32-LABEL: name: brcond_si_loop_brcond_br_negated
; WAVE32: bb.0:
; WAVE32-NEXT: successors: %bb.1(0x80000000)
; WAVE32-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY $sgpr0_sgpr1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.1:
; WAVE32-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: S_NOP 0
; WAVE32-NEXT: SI_LOOP [[COPY2]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE32-NEXT: G_BR %bb.1
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: bb.2:
; WAVE32-NEXT: S_NOP 0
bb.0:
liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s64) = COPY $sgpr0_sgpr1
bb.1:
successors: %bb.1, %bb.2
S_NOP 0
%3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2
%4:_(s1) = G_CONSTANT i1 true
%5:_(s1) = G_XOR %3, %4
G_BRCOND %5, %bb.2
G_BR %bb.1
bb.2:
S_NOP 0
...
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