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llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir 

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s

---
name:            test_ashr_i44
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; CHECK-LABEL: name: test_ashr_i44
    ; CHECK: liveins: $vgpr0, $vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
    ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s44) = G_TRUNC [[MV]](s64)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s44) = G_CONSTANT i44 43
    ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s44) = G_ASHR [[TRUNC]], [[C]](s44)
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ASHR]](s44)
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ANYEXT]](s64)
    ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
    ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)
    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
    %1:_(s32) = COPY $vgpr0
    %2:_(s32) = COPY $vgpr1
    %3:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
    %4:_(s44) = G_TRUNC %3(s64)
    %5:_(s44) = G_CONSTANT i44 22
    %6:_(s44) = G_ASHR %4, %5(s44)
    %7:_(s44) = G_ASHR %6, %5(s44)
    %8:_(s64) = G_ANYEXT %7(s44)
    %9:_(s32), %10:_(s32) = G_UNMERGE_VALUES %8(s64)
    $vgpr0 = COPY %9(s32)
    $vgpr1 = COPY %10(s32)
    SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

...
---
name:            test_ashr_i55
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0, $sgpr1

    ; CHECK-LABEL: name: test_ashr_i55
    ; CHECK: liveins: $sgpr0, $sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
    ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s55) = G_TRUNC [[MV]](s64)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s55) = G_CONSTANT i55 53
    ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s55) = G_ASHR [[TRUNC]], [[C]](s55)
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ASHR]](s55)
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ANYEXT]](s64)
    ; CHECK-NEXT: $sgpr0 = COPY [[UV]](s32)
    ; CHECK-NEXT: $sgpr1 = COPY [[UV1]](s32)
    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
    %1:_(s32) = COPY $sgpr0
    %2:_(s32) = COPY $sgpr1
    %3:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
    %4:_(s55) = G_TRUNC %3(s64)
    %5:_(s55) = G_CONSTANT i55 50
    %7:_(s55) = G_CONSTANT i55 3
    %6:_(s55) = G_ASHR %4, %5(s55)
    %8:_(s55) = G_ASHR %6, %7(s55)
    %9:_(s64) = G_ANYEXT %8(s55)
    %10:_(s32), %11:_(s32) = G_UNMERGE_VALUES %9(s64)
    $sgpr0 = COPY %10(s32)
    $sgpr1 = COPY %11(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1

...
---
name:            test_lshr_i44
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0, $sgpr1

    ; CHECK-LABEL: name: test_lshr_i44
    ; CHECK: liveins: $sgpr0, $sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: $sgpr0 = COPY [[C]](s32)
    ; CHECK-NEXT: $sgpr1 = COPY [[C]](s32)
    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
    %1:_(s32) = COPY $sgpr0
    %2:_(s32) = COPY $sgpr1
    %3:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
    %4:_(s44) = G_TRUNC %3(s64)
    %5:_(s44) = G_CONSTANT i44 22
    %6:_(s44) = G_LSHR %4, %5(s44)
    %7:_(s44) = G_LSHR %6, %5(s44)
    %8:_(s64) = G_ANYEXT %7(s44)
    %9:_(s32), %10:_(s32) = G_UNMERGE_VALUES %8(s64)
    $sgpr0 = COPY %9(s32)
    $sgpr1 = COPY %10(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1

...
---
name:            test_lshr_i55
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; CHECK-LABEL: name: test_lshr_i55
    ; CHECK: liveins: $vgpr0, $vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
    ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s55) = G_TRUNC [[MV]](s64)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s55) = G_CONSTANT i55 53
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s55) = G_LSHR [[TRUNC]], [[C]](s55)
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s55)
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ANYEXT]](s64)
    ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
    ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)
    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
    %1:_(s32) = COPY $vgpr0
    %2:_(s32) = COPY $vgpr1
    %3:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
    %4:_(s55) = G_TRUNC %3(s64)
    %5:_(s55) = G_CONSTANT i55 50
    %7:_(s55) = G_CONSTANT i55 3
    %6:_(s55) = G_LSHR %4, %5(s55)
    %8:_(s55) = G_LSHR %6, %7(s55)
    %9:_(s64) = G_ANYEXT %8(s55)
    %10:_(s32), %11:_(s32) = G_UNMERGE_VALUES %9(s64)
    $vgpr0 = COPY %10(s32)
    $vgpr1 = COPY %11(s32)
    SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

...
---
name:            test_shl_i44
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; CHECK-LABEL: name: test_shl_i44
    ; CHECK: liveins: $vgpr0, $vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)
    ; CHECK-NEXT: $vgpr1 = COPY [[C]](s32)
    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
    %1:_(s32) = COPY $vgpr0
    %2:_(s32) = COPY $vgpr1
    %3:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
    %4:_(s44) = G_TRUNC %3(s64)
    %5:_(s44) = G_CONSTANT i44 22
    %6:_(s44) = G_SHL %4, %5(s44)
    %7:_(s44) = G_SHL %6, %5(s44)
    %8:_(s64) = G_ANYEXT %7(s44)
    %9:_(s32), %10:_(s32) = G_UNMERGE_VALUES %8(s64)
    $vgpr0 = COPY %9(s32)
    $vgpr1 = COPY %10(s32)
    SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

...
---
name:            test_shl_i55
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0, $sgpr1

    ; CHECK-LABEL: name: test_shl_i55
    ; CHECK: liveins: $sgpr0, $sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
    ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s55) = G_TRUNC [[MV]](s64)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s55) = G_CONSTANT i55 53
    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s55) = G_SHL [[TRUNC]], [[C]](s55)
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s55)
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ANYEXT]](s64)
    ; CHECK-NEXT: $sgpr0 = COPY [[UV]](s32)
    ; CHECK-NEXT: $sgpr1 = COPY [[UV1]](s32)
    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
    %1:_(s32) = COPY $sgpr0
    %2:_(s32) = COPY $sgpr1
    %3:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
    %4:_(s55) = G_TRUNC %3(s64)
    %5:_(s55) = G_CONSTANT i55 50
    %7:_(s55) = G_CONSTANT i55 3
    %6:_(s55) = G_SHL %4, %5(s55)
    %8:_(s55) = G_SHL %6, %7(s55)
    %9:_(s64) = G_ANYEXT %8(s55)
    %10:_(s32), %11:_(s32) = G_UNMERGE_VALUES %9(s64)
    $sgpr0 = COPY %10(s32)
    $sgpr1 = COPY %11(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1

...
---
name:            sshlsat_i44
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0, $sgpr1

    ; CHECK-LABEL: name: sshlsat_i44
    ; CHECK: liveins: $sgpr0, $sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
    ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s44) = G_TRUNC [[MV]](s64)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s44) = G_CONSTANT i44 43
    ; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(s44) = G_SSHLSAT [[TRUNC]], [[C]](s44)
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SSHLSAT]](s44)
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ANYEXT]](s64)
    ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32)
    ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)
    ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32)
    ; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32)
    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
    %1:_(s32) = COPY $sgpr0
    %2:_(s32) = COPY $sgpr1
    %3:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
    %0:_(s44) = G_TRUNC %3(s64)
    %5:_(s44) = G_CONSTANT i44 22
    %6:_(s44) = G_SSHLSAT %0, %5(s44)
    %7:_(s44) = G_SSHLSAT %6, %5(s44)
    %8:_(s64) = G_ANYEXT %7(s44)
    %9:_(s32), %10:_(s32) = G_UNMERGE_VALUES %8(s64)
    %11:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), %9(s32)
    $sgpr0 = COPY %11(s32)
    %12:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), %10(s32)
    $sgpr1 = COPY %12(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1

...
---
name:            sshlsat_i55
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; CHECK-LABEL: name: sshlsat_i55
    ; CHECK: liveins: $vgpr0, $vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
    ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s55) = G_TRUNC [[MV]](s64)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s55) = G_CONSTANT i55 53
    ; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(s55) = G_SSHLSAT [[TRUNC]], [[C]](s55)
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SSHLSAT]](s55)
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ANYEXT]](s64)
    ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32)
    ; CHECK-NEXT: $vgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)
    ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32)
    ; CHECK-NEXT: $vgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32)
    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
    %1:_(s32) = COPY $vgpr0
    %2:_(s32) = COPY $vgpr1
    %3:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
    %0:_(s55) = G_TRUNC %3(s64)
    %5:_(s55) = G_CONSTANT i55 50
    %7:_(s55) = G_CONSTANT i55 3
    %6:_(s55) = G_SSHLSAT %0, %5(s55)
    %8:_(s55) = G_SSHLSAT %6, %7(s55)
    %9:_(s64) = G_ANYEXT %8(s55)
    %10:_(s32), %11:_(s32) = G_UNMERGE_VALUES %9(s64)
    %12:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), %10(s32)
    $vgpr0 = COPY %12(s32)
    %13:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), %11(s32)
    $vgpr1 = COPY %13(s32)
    SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1

...
---
name:            ushlsat_i44
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31

    ; CHECK-LABEL: name: ushlsat_i44
    ; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
    ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s44) = G_TRUNC [[MV]](s64)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s44) = G_CONSTANT i44 22
    ; CHECK-NEXT: [[USHLSAT:%[0-9]+]]:_(s44) = G_USHLSAT [[TRUNC]], [[C]](s44)
    ; CHECK-NEXT: [[USHLSAT1:%[0-9]+]]:_(s44) = G_USHLSAT [[USHLSAT]], [[C]](s44)
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[USHLSAT1]](s44)
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ANYEXT]](s64)
    ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
    ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)
    ; CHECK-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1
    %2:_(s32) = COPY $vgpr0
    %3:_(s32) = COPY $vgpr1
    %4:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
    %0:_(s44) = G_TRUNC %4(s64)
    %5:_(s44) = G_CONSTANT i44 22
    %6:_(s44) = G_USHLSAT %0, %5(s44)
    %7:_(s44) = G_USHLSAT %6, %5(s44)
    %9:_(s64) = G_ANYEXT %7(s44)
    %10:_(s32), %11:_(s32) = G_UNMERGE_VALUES %9(s64)
    $vgpr0 = COPY %10(s32)
    $vgpr1 = COPY %11(s32)
    S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1

...
---
name:            ushlsat_i55
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; CHECK-LABEL: name: ushlsat_i55
    ; CHECK: liveins: $vgpr0, $vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
    ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s55) = G_TRUNC [[MV]](s64)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s55) = G_CONSTANT i55 53
    ; CHECK-NEXT: [[USHLSAT:%[0-9]+]]:_(s55) = G_USHLSAT [[TRUNC]], [[C]](s55)
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[USHLSAT]](s55)
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ANYEXT]](s64)
    ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
    ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)
    ; CHECK-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1
    %2:_(s32) = COPY $vgpr0
    %3:_(s32) = COPY $vgpr1
    %4:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
    %0:_(s55) = G_TRUNC %4(s64)
    %5:_(s55) = G_CONSTANT i55 50
    %7:_(s55) = G_CONSTANT i55 3
    %6:_(s55) = G_USHLSAT %0, %5(s55)
    %8:_(s55) = G_USHLSAT %6, %7(s55)
    %10:_(s64) = G_ANYEXT %8(s55)
    %11:_(s32), %12:_(s32) = G_UNMERGE_VALUES %10(s64)
    $vgpr0 = COPY %11(s32)
    $vgpr1 = COPY %12(s32)
    S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1

...