combine-shift-imm-chain-shlsat.mir | Explore in Territory

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s

---
name:            sshlsat_1
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: sshlsat_1
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
    ; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C]](s32)
    ; CHECK-NEXT: $vgpr0 = COPY [[SSHLSAT]](s32)
    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
    %0:_(s32) = COPY $vgpr0
    %2:_(s32) = G_CONSTANT i32 2
    %3:_(s32) = G_SSHLSAT %0, %2(s32)
    %4:_(s32) = G_SSHLSAT %3, %2(s32)
    $vgpr0 = COPY %4(s32)
    SI_RETURN_TO_EPILOG implicit $vgpr0

...
---
name:            sshlsat_2
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: sshlsat_2
    ; CHECK: liveins: $sgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
    ; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C]](s32)
    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[SSHLSAT]](s32)
    ; CHECK-NEXT: $sgpr0 = COPY [[INT]](s32)
    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0
    %0:_(s32) = COPY $sgpr0
    %2:_(s32) = G_CONSTANT i32 1
    %4:_(s32) = G_CONSTANT i32 2
    %6:_(s32) = G_CONSTANT i32 3
    %8:_(s32) = G_CONSTANT i32 4
    %3:_(s32) = G_SSHLSAT %0, %2(s32)
    %5:_(s32) = G_SSHLSAT %3, %4(s32)
    %7:_(s32) = G_SSHLSAT %5, %6(s32)
    %9:_(s32) = G_SSHLSAT %7, %8(s32)
    %10:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), %9(s32)
    $sgpr0 = COPY %10(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0

...
---
name:            sshlsat_i32
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: sshlsat_i32
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
    ; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C]](s32)
    ; CHECK-NEXT: $vgpr0 = COPY [[SSHLSAT]](s32)
    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
    %0:_(s32) = COPY $vgpr0
    %2:_(s32) = G_CONSTANT i32 10
    %3:_(s32) = G_SSHLSAT %0, %2(s32)
    %4:_(s32) = G_SSHLSAT %3, %2(s32)
    %5:_(s32) = G_SSHLSAT %4, %2(s32)
    %6:_(s32) = G_SSHLSAT %5, %2(s32)
    $vgpr0 = COPY %6(s32)
    SI_RETURN_TO_EPILOG implicit $vgpr0

...
---
name:            sshlsat_i64
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0, $sgpr1

    ; CHECK-LABEL: name: sshlsat_i64
    ; CHECK: liveins: $sgpr0, $sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
    ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 62
    ; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(s64) = G_SSHLSAT [[MV]], [[C]](s64)
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSHLSAT]](s64)
    ; CHECK-NEXT: $sgpr0 = COPY [[UV]](s32)
    ; CHECK-NEXT: $sgpr1 = COPY [[UV1]](s32)
    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
    %1:_(s32) = COPY $sgpr0
    %2:_(s32) = COPY $sgpr1
    %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
    %4:_(s64) = G_CONSTANT i64 10
    %11:_(s64) = G_CONSTANT i64 2
    %5:_(s64) = G_SSHLSAT %0, %4(s64)
    %6:_(s64) = G_SSHLSAT %5, %4(s64)
    %7:_(s64) = G_SSHLSAT %6, %4(s64)
    %8:_(s64) = G_SSHLSAT %7, %4(s64)
    %9:_(s64) = G_SSHLSAT %8, %4(s64)
    %10:_(s64) = G_SSHLSAT %9, %4(s64)
    %12:_(s64) = G_SSHLSAT %10, %11(s64)
    %13:_(s32), %14:_(s32) = G_UNMERGE_VALUES %12(s64)
    $sgpr0 = COPY %13(s32)
    $sgpr1 = COPY %14(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1

...
---
name:            ushlsat_1
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: ushlsat_1
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
    ; CHECK-NEXT: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C]](s32)
    ; CHECK-NEXT: $vgpr0 = COPY [[USHLSAT]](s32)
    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
    %0:_(s32) = COPY $vgpr0
    %2:_(s32) = G_CONSTANT i32 2
    %3:_(s32) = G_USHLSAT %0, %2(s32)
    %4:_(s32) = G_USHLSAT %3, %2(s32)
    $vgpr0 = COPY %4(s32)
    SI_RETURN_TO_EPILOG implicit $vgpr0

...
---
name:            ushlsat_2
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: ushlsat_2
    ; CHECK: liveins: $sgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
    ; CHECK-NEXT: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C]](s32)
    ; CHECK-NEXT: $sgpr0 = COPY [[USHLSAT]](s32)
    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0
    %0:_(s32) = COPY $sgpr0
    %2:_(s32) = G_CONSTANT i32 1
    %4:_(s32) = G_CONSTANT i32 2
    %6:_(s32) = G_CONSTANT i32 3
    %8:_(s32) = G_CONSTANT i32 4
    %3:_(s32) = G_USHLSAT %0, %2(s32)
    %5:_(s32) = G_USHLSAT %3, %4(s32)
    %7:_(s32) = G_USHLSAT %5, %6(s32)
    %9:_(s32) = G_USHLSAT %7, %8(s32)
    $sgpr0 = COPY %9(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0

...
---
name:            ushlsat_i32
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: ushlsat_i32
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 30
    ; CHECK-NEXT: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C1]](s32)
    ; CHECK-NEXT: [[USHLSAT1:%[0-9]+]]:_(s32) = G_USHLSAT [[USHLSAT]], [[C]](s32)
    ; CHECK-NEXT: $vgpr0 = COPY [[USHLSAT1]](s32)
    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
    %0:_(s32) = COPY $vgpr0
    %2:_(s32) = G_CONSTANT i32 10
    %3:_(s32) = G_USHLSAT %0, %2(s32)
    %4:_(s32) = G_USHLSAT %3, %2(s32)
    %5:_(s32) = G_USHLSAT %4, %2(s32)
    %6:_(s32) = G_USHLSAT %5, %2(s32)
    $vgpr0 = COPY %6(s32)
    SI_RETURN_TO_EPILOG implicit $vgpr0

...
---
name:            ushlsat_i64
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0, $sgpr1

    ; CHECK-LABEL: name: ushlsat_i64
    ; CHECK: liveins: $sgpr0, $sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
    ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 10
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 60
    ; CHECK-NEXT: [[USHLSAT:%[0-9]+]]:_(s64) = G_USHLSAT [[MV]], [[C1]](s64)
    ; CHECK-NEXT: [[USHLSAT1:%[0-9]+]]:_(s64) = G_USHLSAT [[USHLSAT]], [[C]](s64)
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[USHLSAT1]](s64)
    ; CHECK-NEXT: $sgpr0 = COPY [[UV]](s32)
    ; CHECK-NEXT: $sgpr1 = COPY [[UV1]](s32)
    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
    %1:_(s32) = COPY $sgpr0
    %2:_(s32) = COPY $sgpr1
    %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
    %4:_(s64) = G_CONSTANT i64 10
    %5:_(s64) = G_USHLSAT %0, %4(s64)
    %6:_(s64) = G_USHLSAT %5, %4(s64)
    %7:_(s64) = G_USHLSAT %6, %4(s64)
    %8:_(s64) = G_USHLSAT %7, %4(s64)
    %9:_(s64) = G_USHLSAT %8, %4(s64)
    %10:_(s64) = G_USHLSAT %9, %4(s64)
    %11:_(s64) = G_USHLSAT %10, %4(s64)
    %12:_(s32), %13:_(s32) = G_UNMERGE_VALUES %11(s64)
    $sgpr0 = COPY %12(s32)
    $sgpr1 = COPY %13(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1

...
llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-shlsat.mir
