legalize-amdgcn.workitem.id.mir | Explore in Territory

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx90a -run-pass=legalizer -o - %s | FileCheck -check-prefix=GCN %s

--- |
  define amdgpu_kernel void @test_workitem_id_x_unpacked() !reqd_work_group_size !0 {
    ret void
  }

  define amdgpu_kernel void @test_workitem_id_y_unpacked() !reqd_work_group_size !0 {
    ret void
  }

  define amdgpu_kernel void @test_workitem_id_z_unpacked() !reqd_work_group_size !0 {
    ret void
  }

  define amdgpu_kernel void @test_workitem_id_x_packed() !reqd_work_group_size !0 {
    ret void
  }

  define amdgpu_kernel void @test_workitem_id_y_packed() !reqd_work_group_size !0 {
    ret void
  }

  define amdgpu_kernel void @test_workitem_id_z_packed() !reqd_work_group_size !0 {
    ret void
  }

  define amdgpu_kernel void @missing_arg_info() "amdgpu-no-workitem-id-x" {
    ret void
  }

  !0 = !{i32 256, i32 8, i32 4}
...
---
name: test_workitem_id_x_unpacked
machineFunctionInfo:
  argumentInfo:
    workGroupIDX:    { reg: '$sgpr2' }
    workItemIDX:     { reg: '$vgpr0' }
    workItemIDY:     { reg: '$vgpr1' }
    workItemIDZ:     { reg: '$vgpr2' }
body: |
  bb.0:
    ; GCN-LABEL: name: test_workitem_id_x_unpacked
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
    ; GCN-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 8
    ; GCN-NEXT: S_ENDPGM 0, implicit [[ASSERT_ZEXT]](s32)
    %0:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.x)
    S_ENDPGM 0, implicit %0
...

---
name: test_workitem_id_y_unpacked
machineFunctionInfo:
  argumentInfo:
    workGroupIDX:    { reg: '$sgpr2' }
    workItemIDX:     { reg: '$vgpr0' }
    workItemIDY:     { reg: '$vgpr1' }
    workItemIDZ:     { reg: '$vgpr2' }
body: |
  bb.0:
    ; GCN-LABEL: name: test_workitem_id_y_unpacked
    ; GCN: liveins: $vgpr1
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
    ; GCN-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 3
    ; GCN-NEXT: S_ENDPGM 0, implicit [[ASSERT_ZEXT]](s32)
    %0:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.y)
    S_ENDPGM 0, implicit %0
...

---
name: test_workitem_id_z_unpacked
machineFunctionInfo:
  argumentInfo:
    workGroupIDX:    { reg: '$sgpr2' }
    workItemIDX:     { reg: '$vgpr0' }
    workItemIDY:     { reg: '$vgpr1' }
    workItemIDZ:     { reg: '$vgpr2' }
body: |
  bb.0:
    ; GCN-LABEL: name: test_workitem_id_z_unpacked
    ; GCN: liveins: $vgpr2
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
    ; GCN-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 2
    ; GCN-NEXT: S_ENDPGM 0, implicit [[ASSERT_ZEXT]](s32)
    %0:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.z)
    S_ENDPGM 0, implicit %0
...

---
name: test_workitem_id_x_packed
machineFunctionInfo:
  argumentInfo:
    workItemIDX:     { reg: '$vgpr0', mask: 1023 }
    workItemIDY:     { reg: '$vgpr0', mask: 1047552 }
    workItemIDZ:     { reg: '$vgpr0', mask: 1072693248 }
body: |
  bb.0:
    ; GCN-LABEL: name: test_workitem_id_x_packed
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
    ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023
    ; GCN-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
    ; GCN-NEXT: S_ENDPGM 0, implicit [[AND]](s32)
    %0:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.x)
    S_ENDPGM 0, implicit %0
...

---
name: test_workitem_id_y_packed
machineFunctionInfo:
  argumentInfo:
    workItemIDX:     { reg: '$vgpr0', mask: 1023 }
    workItemIDY:     { reg: '$vgpr0', mask: 1047552 }
    workItemIDZ:     { reg: '$vgpr0', mask: 1072693248 }
body: |
  bb.0:
    ; GCN-LABEL: name: test_workitem_id_y_packed
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
    ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
    ; GCN-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
    ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023
    ; GCN-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
    ; GCN-NEXT: S_ENDPGM 0, implicit [[AND]](s32)
    %0:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.y)
    S_ENDPGM 0, implicit %0
...

---
name: test_workitem_id_z_packed
machineFunctionInfo:
  argumentInfo:
    workItemIDX:     { reg: '$vgpr0', mask: 1023 }
    workItemIDY:     { reg: '$vgpr0', mask: 1047552 }
    workItemIDZ:     { reg: '$vgpr0', mask: 1072693248 }
body: |
  bb.0:
    ; GCN-LABEL: name: test_workitem_id_z_packed
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
    ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
    ; GCN-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
    ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023
    ; GCN-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
    ; GCN-NEXT: S_ENDPGM 0, implicit [[AND]](s32)
    %0:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.z)
    S_ENDPGM 0, implicit %0
...

---
name: missing_arg_info
body: |
  bb.0:
    ; GCN-LABEL: name: missing_arg_info
    ; GCN: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
    ; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]](s32)
    %0:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.z)
    S_ENDPGM 0, implicit %0
...
llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.workitem.id.mir
