regbankselect-lshr.mir | Explore in Territory

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=amdgpu-regbankselect -regbankselect-fast -o - %s | FileCheck %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=amdgpu-regbankselect -regbankselect-greedy -o - %s | FileCheck %s

---
name: lshr_s32_ss
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1
    ; CHECK-LABEL: name: lshr_s32_ss
    ; CHECK: liveins: $sgpr0, $sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[LSHR]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = COPY $sgpr1
    %2:_(s32) = G_LSHR %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: lshr_s32_sv
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0
    ; CHECK-LABEL: name: lshr_s32_sv
    ; CHECK: liveins: $sgpr0, $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:vgpr(s32) = G_LSHR [[COPY2]], [[COPY1]](s32)
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[LSHR]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = COPY $vgpr0
    %2:_(s32) = G_LSHR %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: lshr_s32_vs
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0
    ; CHECK-LABEL: name: lshr_s32_vs
    ; CHECK: liveins: $sgpr0, $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:vgpr(s32) = G_LSHR [[COPY]], [[COPY2]](s32)
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[LSHR]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $sgpr0
    %2:_(s32) = G_LSHR %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: lshr_s32_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; CHECK-LABEL: name: lshr_s32_vv
    ; CHECK: liveins: $vgpr0, $vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:vgpr(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[LSHR]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s32) = G_LSHR %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: lshr_s16_ss
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1
    ; CHECK-LABEL: name: lshr_s16_ss
    ; CHECK: liveins: $sgpr0, $sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s16)
    ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s16)
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[ZEXT]], [[ZEXT1]](s32)
    ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[LSHR]](s32)
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[TRUNC2]](s16)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = COPY $sgpr1
    %2:_(s16) = G_TRUNC %0
    %3:_(s16) = G_TRUNC %1
    %4:_(s16) = G_LSHR %2, %3
    S_ENDPGM 0, implicit %4
...

---
name: lshr_s16_sv
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0

    ; CHECK-LABEL: name: lshr_s16_sv
    ; CHECK: liveins: $sgpr0, $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:vgpr(s16) = G_LSHR [[COPY2]], [[TRUNC1]](s16)
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[LSHR]](s16)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = COPY $vgpr0
    %2:_(s16) = G_TRUNC %0
    %3:_(s16) = G_TRUNC %1
    %4:_(s16) = G_LSHR %2, %3
    S_ENDPGM 0, implicit %4
...

---
name: lshr_s16_vs
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0
    ; CHECK-LABEL: name: lshr_s16_vs
    ; CHECK: liveins: $sgpr0, $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC1]](s16)
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:vgpr(s16) = G_LSHR [[TRUNC]], [[COPY2]](s16)
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[LSHR]](s16)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $sgpr0
    %2:_(s16) = G_TRUNC %0
    %3:_(s16) = G_TRUNC %1
    %4:_(s16) = G_LSHR %2, %3
    S_ENDPGM 0, implicit %4

...

---
name: lshr_s16_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; CHECK-LABEL: name: lshr_s16_vv
    ; CHECK: liveins: $vgpr0, $vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:vgpr(s16) = G_LSHR [[TRUNC]], [[TRUNC1]](s16)
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[LSHR]](s16)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s16) = G_TRUNC %0
    %3:_(s16) = G_TRUNC %1
    %4:_(s16) = G_LSHR %2, %3
    S_ENDPGM 0, implicit %4

...

---
name: lshr_v2s16_ss
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1
    ; CHECK-LABEL: name: lshr_v2s16_ss
    ; CHECK: liveins: $sgpr0, $sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY]](<2 x s16>)
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST]], [[C]](s32)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65535
    ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[BITCAST]], [[C1]]
    ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY1]](<2 x s16>)
    ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
    ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
    ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65535
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:sgpr(s32) = G_AND [[BITCAST1]], [[C3]]
    ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:sgpr(s32) = G_LSHR [[AND]], [[AND1]](s32)
    ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:sgpr(s32) = G_LSHR [[LSHR]], [[LSHR1]](s32)
    ; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[LSHR3]](s32)
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR_TRUNC]](<2 x s16>)
    %0:_(<2 x s16>) = COPY $sgpr0
    %1:_(<2 x s16>) = COPY $sgpr1
    %2:_(<2 x s16>) = G_LSHR %0, %1
    S_ENDPGM 0, implicit %2

...

---
name: lshr_v2s16_sv
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0
    ; CHECK-LABEL: name: lshr_v2s16_sv
    ; CHECK: liveins: $sgpr0, $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY]](<2 x s16>)
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:vgpr(<2 x s16>) = G_LSHR [[COPY2]], [[COPY1]](<2 x s16>)
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[LSHR]](<2 x s16>)
    %0:_(<2 x s16>) = COPY $sgpr0
    %1:_(<2 x s16>) = COPY $vgpr0
    %2:_(<2 x s16>) = G_LSHR %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: lshr_v2s16_vs
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0
    ; CHECK-LABEL: name: lshr_v2s16_vs
    ; CHECK: liveins: $sgpr0, $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY1]](<2 x s16>)
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:vgpr(<2 x s16>) = G_LSHR [[COPY]], [[COPY2]](<2 x s16>)
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[LSHR]](<2 x s16>)
    %0:_(<2 x s16>) = COPY $vgpr0
    %1:_(<2 x s16>) = COPY $sgpr0
    %2:_(<2 x s16>) = G_LSHR %0, %1
    S_ENDPGM 0, implicit %2

...

---
name: lshr_v2s16_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; CHECK-LABEL: name: lshr_v2s16_vv
    ; CHECK: liveins: $vgpr0, $vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:vgpr(<2 x s16>) = G_LSHR [[COPY]], [[COPY1]](<2 x s16>)
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[LSHR]](<2 x s16>)
    %0:_(<2 x s16>) = COPY $vgpr0
    %1:_(<2 x s16>) = COPY $vgpr1
    %2:_(<2 x s16>) = G_LSHR %0, %1
    S_ENDPGM 0, implicit %2

...
llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
