llvm/llvm/test/CodeGen/AArch64/pr79100.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK
; RUN: llc < %s -mtriple=aarch64 -global-isel 2>&1 | FileCheck %s --check-prefixes=CHECK

define <16 x i8> @test_2(i64 %0) {
; CHECK-LABEL: test_2:
; CHECK:       // %bb.0: // %Entry
; CHECK-NEXT:    fmov d1, x0
; CHECK-NEXT:    movi v0.16b, #15
; CHECK-NEXT:    ushr v2.8b, v1.8b, #4
; CHECK-NEXT:    zip1 v1.16b, v1.16b, v2.16b
; CHECK-NEXT:    and v0.16b, v1.16b, v0.16b
; CHECK-NEXT:    ret
Entry:
  %1 = bitcast i64 %0 to <8 x i8>
  %2 = lshr <8 x i8> %1, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
  %3 = shufflevector <8 x i8> %1, <8 x i8> %2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
  %4 = and <16 x i8> %3, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>
  ret <16 x i8> %4
}

define <16 x i8> @test_3(i64 %0) {
; CHECK-LABEL: test_3:
; CHECK:       // %bb.0: // %Entry
; CHECK-NEXT:    movi v0.8b, #15
; CHECK-NEXT:    fmov d1, x0
; CHECK-NEXT:    ushr v2.8b, v1.8b, #4
; CHECK-NEXT:    and v0.8b, v1.8b, v0.8b
; CHECK-NEXT:    zip1 v0.16b, v0.16b, v2.16b
; CHECK-NEXT:    ret
Entry:
  %1 = bitcast i64 %0 to <8 x i8>
  %2 = and <8 x i8> %1, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>
  %3 = lshr <8 x i8> %1, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
  %4 = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
  ret <16 x i8> %4
}