llvm/llvm/test/CodeGen/AArch64/srem-vec-crash.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -mtriple=aarch64-unknown-unknown < %s | FileCheck %s

define i32 @pr84830(i1 %arg) {
; CHECK-LABEL: pr84830:
; CHECK:       // %bb.0: // %bb
; CHECK-NEXT:    mov w0, #1 // =0x1
; CHECK-NEXT:    ret
bb:
  %new0 = srem i1 %arg, true
  %last = zext i1 %new0 to i32
  %i = icmp ne i32 %last, 0
  %i1 = select i1 %i, i32 0, i32 1
  ret i32 %i1
}