llvm/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmul_lane.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -mattr=+sve-b16b16 -verify-machineinstrs < %s | FileCheck %s

define <vscale x 8 x bfloat> @bfmul_lane_idx1(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
; CHECK-LABEL: bfmul_lane_idx1:
; CHECK:       // %bb.0:
; CHECK-NEXT:    bfmul z0.h, z0.h, z1.h[1]
; CHECK-NEXT:    ret
  %out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat> %a,
                                                                          <vscale x 8 x bfloat> %b,
                                                                          i32 1)
  ret <vscale x 8 x bfloat> %out
}

define <vscale x 8 x bfloat> @bfmul_lane_idx3(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
; CHECK-LABEL: bfmul_lane_idx3:
; CHECK:       // %bb.0:
; CHECK-NEXT:    bfmul z0.h, z0.h, z1.h[3]
; CHECK-NEXT:    ret
  %out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat> %a,
                                                                          <vscale x 8 x bfloat> %b,
                                                                          i32 3)
  ret <vscale x 8 x bfloat> %out
}

define <vscale x 8 x bfloat> @bfmul_lane_idx7(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
; CHECK-LABEL: bfmul_lane_idx7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    bfmul z0.h, z0.h, z1.h[7]
; CHECK-NEXT:    ret
  %out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat> %a,
                                                                          <vscale x 8 x bfloat> %b,
                                                                          i32 7)
  ret <vscale x 8 x bfloat> %out
}

declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32)