combine-commute-int-const-lhs.mir | Explore in Territory

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
---
name:            add
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: add
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst:_(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: %add:_(s32) = G_ADD [[COPY]], %cst
    ; CHECK-NEXT: $s0 = COPY %add(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(s32) = COPY $s0
    %cst:_(s32) = G_CONSTANT i32 1
    %add:_(s32) = G_ADD %cst, %0
    $s0 = COPY %add
    RET_ReallyLR

...
---
name:            mul
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: mul
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst:_(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: %mul:_(s32) = G_MUL [[COPY]], %cst
    ; CHECK-NEXT: $s0 = COPY %mul(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(s32) = COPY $s0
    %cst:_(s32) = G_CONSTANT i32 3
    %mul:_(s32) = G_MUL %cst, %0
    $s0 = COPY %mul
    RET_ReallyLR
...
---
name:            and
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: and
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst:_(s32) = G_CONSTANT i32 5
    ; CHECK-NEXT: %and:_(s32) = G_AND [[COPY]], %cst
    ; CHECK-NEXT: $s0 = COPY %and(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(s32) = COPY $s0
    %cst:_(s32) = G_CONSTANT i32 5
    %and:_(s32) = G_AND %cst, %0
    $s0 = COPY %and
    RET_ReallyLR
...
---
name:            or
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: or
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst:_(s32) = G_CONSTANT i32 5
    ; CHECK-NEXT: %or:_(s32) = G_OR [[COPY]], %cst
    ; CHECK-NEXT: $s0 = COPY %or(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(s32) = COPY $s0
    %cst:_(s32) = G_CONSTANT i32 5
    %or:_(s32) = G_OR %cst, %0
    $s0 = COPY %or
    RET_ReallyLR
...
---
name:            xor
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: xor
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst:_(s32) = G_CONSTANT i32 5
    ; CHECK-NEXT: %xor:_(s32) = G_XOR [[COPY]], %cst
    ; CHECK-NEXT: $s0 = COPY %xor(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(s32) = COPY $s0
    %cst:_(s32) = G_CONSTANT i32 5
    %xor:_(s32) = G_XOR %cst, %0
    $s0 = COPY %xor
    RET_ReallyLR
...
---
name:            smin
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: smin
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst:_(s32) = G_CONSTANT i32 10
    ; CHECK-NEXT: %min:_(s32) = G_SMIN [[COPY]], %cst
    ; CHECK-NEXT: $s0 = COPY %min(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(s32) = COPY $s0
    %cst:_(s32) = G_CONSTANT i32 10
    %min:_(s32) = G_SMIN %cst, %0
    $s0 = COPY %min
    RET_ReallyLR
...
---
name:            smax
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: smax
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst:_(s32) = G_CONSTANT i32 10
    ; CHECK-NEXT: %max:_(s32) = G_SMAX [[COPY]], %cst
    ; CHECK-NEXT: $s0 = COPY %max(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(s32) = COPY $s0
    %cst:_(s32) = G_CONSTANT i32 10
    %max:_(s32) = G_SMAX %cst, %0
    $s0 = COPY %max
    RET_ReallyLR
...
---
name:            umin
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: umin
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst:_(s32) = G_CONSTANT i32 10
    ; CHECK-NEXT: %min:_(s32) = G_UMIN [[COPY]], %cst
    ; CHECK-NEXT: $s0 = COPY %min(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(s32) = COPY $s0
    %cst:_(s32) = G_CONSTANT i32 10
    %min:_(s32) = G_UMIN %cst, %0
    $s0 = COPY %min
    RET_ReallyLR
...
---
name:            umax
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: umax
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst:_(s32) = G_CONSTANT i32 10
    ; CHECK-NEXT: %max:_(s32) = G_UMAX [[COPY]], %cst
    ; CHECK-NEXT: $s0 = COPY %max(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(s32) = COPY $s0
    %cst:_(s32) = G_CONSTANT i32 10
    %max:_(s32) = G_UMAX %cst, %0
    $s0 = COPY %max
    RET_ReallyLR
...
---
name:            uaddo
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: uaddo
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst:_(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: %add:_(s32), %overflow:_(s1) = G_UADDO [[COPY]], %cst
    ; CHECK-NEXT: %ret:_(s32) = G_ANYEXT %overflow(s1)
    ; CHECK-NEXT: $s0 = COPY %ret(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(s32) = COPY $s0
    %cst:_(s32) = G_CONSTANT i32 1
    %add:_(s32), %overflow:_(s1) = G_UADDO %cst, %0
    %ret:_(s32) = G_ANYEXT %overflow
    $s0 = COPY %ret
    RET_ReallyLR

...
---
name:            saddo
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: saddo
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst:_(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: %add:_(s32), %overflow:_(s1) = G_SADDO [[COPY]], %cst
    ; CHECK-NEXT: %ret:_(s32) = G_ANYEXT %overflow(s1)
    ; CHECK-NEXT: $s0 = COPY %ret(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(s32) = COPY $s0
    %cst:_(s32) = G_CONSTANT i32 1
    %add:_(s32), %overflow:_(s1) = G_SADDO %cst, %0
    %ret:_(s32) = G_ANYEXT %overflow
    $s0 = COPY %ret
    RET_ReallyLR

...
---
name:            umulo
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: umulo
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst:_(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: %mul:_(s32), %overflow:_(s1) = G_UMULO [[COPY]], %cst
    ; CHECK-NEXT: %ret:_(s32) = G_ANYEXT %overflow(s1)
    ; CHECK-NEXT: $s0 = COPY %ret(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(s32) = COPY $s0
    %cst:_(s32) = G_CONSTANT i32 3
    %mul:_(s32), %overflow:_(s1) = G_UMULO %cst, %0
    %ret:_(s32) = G_ANYEXT %overflow
    $s0 = COPY %ret
    RET_ReallyLR
...
---
name:            smulo
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: smulo
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst:_(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: %mul:_(s32), %overflow:_(s1) = G_SMULO [[COPY]], %cst
    ; CHECK-NEXT: %ret:_(s32) = G_ANYEXT %overflow(s1)
    ; CHECK-NEXT: $s0 = COPY %ret(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(s32) = COPY $s0
    %cst:_(s32) = G_CONSTANT i32 3
    %mul:_(s32), %overflow:_(s1) = G_SMULO %cst, %0
    %ret:_(s32) = G_ANYEXT %overflow
    $s0 = COPY %ret
    RET_ReallyLR
...
---
name:            umulh
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: umulh
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst:_(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: %mul:_(s32) = G_UMULH [[COPY]], %cst
    ; CHECK-NEXT: $s0 = COPY %mul(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(s32) = COPY $s0
    %cst:_(s32) = G_CONSTANT i32 3
    %mul:_(s32) = G_UMULH %cst, %0
    $s0 = COPY %mul
    RET_ReallyLR
...
---
name:            smulh
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: smulh
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst:_(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: %mul:_(s32) = G_UMULH [[COPY]], %cst
    ; CHECK-NEXT: $s0 = COPY %mul(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(s32) = COPY $s0
    %cst:_(s32) = G_CONSTANT i32 3
    %mul:_(s32) = G_UMULH %cst, %0
    $s0 = COPY %mul
    RET_ReallyLR
...
---
name:            uaddsat
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: uaddsat
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst:_(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: %add:_(s32) = G_UADDSAT [[COPY]], %cst
    ; CHECK-NEXT: $s0 = COPY %add(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(s32) = COPY $s0
    %cst:_(s32) = G_CONSTANT i32 1
    %add:_(s32) = G_UADDSAT %cst, %0
    $s0 = COPY %add
    RET_ReallyLR

...
---
name:            saddsat
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: saddsat
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst:_(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: %add:_(s32) = G_SADDSAT [[COPY]], %cst
    ; CHECK-NEXT: $s0 = COPY %add(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(s32) = COPY $s0
    %cst:_(s32) = G_CONSTANT i32 1
    %add:_(s32) = G_SADDSAT %cst, %0
    $s0 = COPY %add
    RET_ReallyLR

...
---
name:            smulfix
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: smulfix
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst:_(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: %mul:_(s32) = G_SMULFIX [[COPY]], %cst, 7
    ; CHECK-NEXT: $s0 = COPY %mul(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(s32) = COPY $s0
    %cst:_(s32) = G_CONSTANT i32 3
    %mul:_(s32) = G_SMULFIX %cst, %0, 7
    $s0 = COPY %mul
    RET_ReallyLR
...
---
name:            umulfix
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: umulfix
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst:_(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: %mul:_(s32) = G_UMULFIX [[COPY]], %cst, 7
    ; CHECK-NEXT: $s0 = COPY %mul(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(s32) = COPY $s0
    %cst:_(s32) = G_CONSTANT i32 3
    %mul:_(s32) = G_UMULFIX %cst, %0, 7
    $s0 = COPY %mul
    RET_ReallyLR
...
---
name:            smulfixsat
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: smulfixsat
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst:_(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: %mul:_(s32) = G_SMULFIXSAT [[COPY]], %cst, 7
    ; CHECK-NEXT: $s0 = COPY %mul(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(s32) = COPY $s0
    %cst:_(s32) = G_CONSTANT i32 3
    %mul:_(s32) = G_SMULFIXSAT %cst, %0, 7
    $s0 = COPY %mul
    RET_ReallyLR
...
---
name:            umulfixsat
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: umulfixsat
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst:_(s32) = G_CONSTANT i32 3
    ; CHECK-NEXT: %mul:_(s32) = G_UMULFIXSAT [[COPY]], %cst, 7
    ; CHECK-NEXT: $s0 = COPY %mul(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(s32) = COPY $s0
    %cst:_(s32) = G_CONSTANT i32 3
    %mul:_(s32) = G_UMULFIXSAT %cst, %0, 7
    $s0 = COPY %mul
    RET_ReallyLR
...
llvm/llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-int-const-lhs.mir
