llvm/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-fminmax.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=aarch64 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s

---
name:            fmin_v2s32
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $d0

    ; CHECK-LABEL: name: fmin_v2s32
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
    ; CHECK-NEXT: [[VECREDUCE_FMIN:%[0-9]+]]:_(s32) = G_VECREDUCE_FMIN [[COPY]](<2 x s32>)
    ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMIN]](s32)
    ; CHECK-NEXT: RET_ReallyLR implicit $s0
    %0:_(<2 x s32>) = COPY $d0
    %1:_(s32) = G_VECREDUCE_FMIN %0(<2 x s32>)
    $s0 = COPY %1(s32)
    RET_ReallyLR implicit $s0

...
---
name:            fmax_v8s16
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $q0

    ; CHECK-LABEL: name: fmax_v8s16
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s16>), [[UV1:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
    ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV]](<4 x s16>)
    ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV1]](<4 x s16>)
    ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:_(<4 x s32>) = G_FMAXNUM [[FPEXT]], [[FPEXT1]]
    ; CHECK-NEXT: [[VECREDUCE_FMAX:%[0-9]+]]:_(s32) = G_VECREDUCE_FMAX [[FMAXNUM]](<4 x s32>)
    ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[VECREDUCE_FMAX]](s32)
    ; CHECK-NEXT: $h0 = COPY [[FPTRUNC]](s16)
    ; CHECK-NEXT: RET_ReallyLR implicit $h0
    %0:_(<8 x s16>) = COPY $q0
    %1:_(s16) = G_VECREDUCE_FMAX %0(<8 x s16>)
    $h0 = COPY %1(s16)
    RET_ReallyLR implicit $h0

...
---
name:            fminimum_v2s32
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $d0

    ; CHECK-LABEL: name: fminimum_v2s32
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
    ; CHECK-NEXT: [[VECREDUCE_FMINIMUM:%[0-9]+]]:_(s32) = G_VECREDUCE_FMINIMUM [[COPY]](<2 x s32>)
    ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMINIMUM]](s32)
    ; CHECK-NEXT: RET_ReallyLR implicit $s0
    %0:_(<2 x s32>) = COPY $d0
    %1:_(s32) = G_VECREDUCE_FMINIMUM %0(<2 x s32>)
    $s0 = COPY %1(s32)
    RET_ReallyLR implicit $s0

...
---
name:            fmaximum_v8s16
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $q0

    ; CHECK-LABEL: name: fmaximum_v8s16
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s16>), [[UV1:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
    ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV]](<4 x s16>)
    ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV1]](<4 x s16>)
    ; CHECK-NEXT: [[FMAXIMUM:%[0-9]+]]:_(<4 x s32>) = G_FMAXIMUM [[FPEXT]], [[FPEXT1]]
    ; CHECK-NEXT: [[VECREDUCE_FMAXIMUM:%[0-9]+]]:_(s32) = G_VECREDUCE_FMAXIMUM [[FMAXIMUM]](<4 x s32>)
    ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[VECREDUCE_FMAXIMUM]](s32)
    ; CHECK-NEXT: $h0 = COPY [[FPTRUNC]](s16)
    ; CHECK-NEXT: RET_ReallyLR implicit $h0
    %0:_(<8 x s16>) = COPY $q0
    %1:_(s16) = G_VECREDUCE_FMAXIMUM %0(<8 x s16>)
    $h0 = COPY %1(s16)
    RET_ReallyLR implicit $h0

...