# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -O0 -mtriple=arm64-unknown-unknown -global-isel -run-pass=legalizer -global-isel-abort=2 %s -o - | FileCheck %s
---
name: xtn_v2i64_v2i8
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: xtn_v2i64_v2i8
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[COPY]](<2 x s64>)
; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:_(<2 x s64>) = COPY $q0
%1:_(<2 x s8>) = G_TRUNC %0(<2 x s64>)
%2:_(<2 x s32>) = G_ANYEXT %1(<2 x s8>)
$d0 = COPY %2(<2 x s32>)
RET_ReallyLR implicit $d0
...
---
name: xtn_v2i128_v2i8
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: xtn_v2i128_v2i8
; CHECK: liveins: $x0, $x1, $x2, $x3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[BUILD_VECTOR]](<2 x s64>)
; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%1:_(s64) = COPY $x0
%2:_(s64) = COPY $x1
%3:_(s64) = COPY $x2
%4:_(s64) = COPY $x3
%5:_(s128) = G_MERGE_VALUES %1(s64), %2(s64)
%6:_(s128) = G_MERGE_VALUES %3(s64), %4(s64)
%0:_(<2 x s128>) = G_BUILD_VECTOR %5(s128), %6(s128)
%7:_(<2 x s8>) = G_TRUNC %0(<2 x s128>)
%8:_(<2 x s32>) = G_ANYEXT %7(<2 x s8>)
$d0 = COPY %8(<2 x s32>)
RET_ReallyLR implicit $d0
...
---
name: xtn_v2i64_v2i16
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: xtn_v2i64_v2i16
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[COPY]](<2 x s64>)
; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:_(<2 x s64>) = COPY $q0
%1:_(<2 x s16>) = G_TRUNC %0(<2 x s64>)
%2:_(<2 x s32>) = G_ANYEXT %1(<2 x s16>)
$d0 = COPY %2(<2 x s32>)
RET_ReallyLR implicit $d0
...
---
name: xtn_v2i128_v2i16
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: xtn_v2i128_v2i16
; CHECK: liveins: $x0, $x1, $x2, $x3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[BUILD_VECTOR]](<2 x s64>)
; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%1:_(s64) = COPY $x0
%2:_(s64) = COPY $x1
%3:_(s64) = COPY $x2
%4:_(s64) = COPY $x3
%5:_(s128) = G_MERGE_VALUES %1(s64), %2(s64)
%6:_(s128) = G_MERGE_VALUES %3(s64), %4(s64)
%0:_(<2 x s128>) = G_BUILD_VECTOR %5(s128), %6(s128)
%7:_(<2 x s16>) = G_TRUNC %0(<2 x s128>)
%8:_(<2 x s32>) = G_ANYEXT %7(<2 x s16>)
$d0 = COPY %8(<2 x s32>)
RET_ReallyLR implicit $d0
...
---
name: xtn_v2i128_v2i32
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: xtn_v2i128_v2i32
; CHECK: liveins: $x0, $x1, $x2, $x3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[BUILD_VECTOR]](<2 x s64>)
; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%1:_(s64) = COPY $x0
%2:_(s64) = COPY $x1
%3:_(s64) = COPY $x2
%4:_(s64) = COPY $x3
%5:_(s128) = G_MERGE_VALUES %1(s64), %2(s64)
%6:_(s128) = G_MERGE_VALUES %3(s64), %4(s64)
%0:_(<2 x s128>) = G_BUILD_VECTOR %5(s128), %6(s128)
%7:_(<2 x s32>) = G_TRUNC %0(<2 x s128>)
$d0 = COPY %7(<2 x s32>)
RET_ReallyLR implicit $d0
...
---
name: xtn_v2i128_v2i64
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: xtn_v2i128_v2i64
; CHECK: liveins: $x0, $x1, $x2, $x3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY [[BUILD_VECTOR]](<2 x s64>)
; CHECK-NEXT: $q0 = COPY [[COPY2]](<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%1:_(s64) = COPY $x0
%2:_(s64) = COPY $x1
%3:_(s64) = COPY $x2
%4:_(s64) = COPY $x3
%5:_(s128) = G_MERGE_VALUES %1(s64), %2(s64)
%6:_(s128) = G_MERGE_VALUES %3(s64), %4(s64)
%0:_(<2 x s128>) = G_BUILD_VECTOR %5(s128), %6(s128)
%7:_(<2 x s64>) = G_TRUNC %0(<2 x s128>)
$q0 = COPY %7(<2 x s64>)
RET_ReallyLR implicit $q0
...
---
name: xtn_v3i16_v3i8
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: xtn_v3i16_v3i8
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: $w1 = COPY [[ANYEXT1]](s32)
; CHECK-NEXT: $w2 = COPY [[ANYEXT2]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1, implicit $w2
%1:_(<4 x s16>) = COPY $d0
%2:_(s16), %3:_(s16), %4:_(s16), %5:_(s16) = G_UNMERGE_VALUES %1(<4 x s16>)
%0:_(<3 x s16>) = G_BUILD_VECTOR %2(s16), %3(s16), %4(s16)
%6:_(<3 x s8>) = G_TRUNC %0(<3 x s16>)
%10:_(s8), %11:_(s8), %12:_(s8) = G_UNMERGE_VALUES %6(<3 x s8>)
%7:_(s32) = G_ANYEXT %10(s8)
%8:_(s32) = G_ANYEXT %11(s8)
%9:_(s32) = G_ANYEXT %12(s8)
$w0 = COPY %7(s32)
$w1 = COPY %8(s32)
$w2 = COPY %9(s32)
RET_ReallyLR implicit $w0, implicit $w1, implicit $w2
...
---
name: xtn_v3i32_v3i8
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: xtn_v3i32_v3i8
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
; CHECK-NEXT: $w0 = COPY [[UV]](s32)
; CHECK-NEXT: $w1 = COPY [[UV1]](s32)
; CHECK-NEXT: $w2 = COPY [[UV2]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1, implicit $w2
%1:_(<4 x s32>) = COPY $q0
%2:_(s32), %3:_(s32), %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %1(<4 x s32>)
%0:_(<3 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32), %4(s32)
%6:_(<3 x s8>) = G_TRUNC %0(<3 x s32>)
%10:_(s8), %11:_(s8), %12:_(s8) = G_UNMERGE_VALUES %6(<3 x s8>)
%7:_(s32) = G_ANYEXT %10(s8)
%8:_(s32) = G_ANYEXT %11(s8)
%9:_(s32) = G_ANYEXT %12(s8)
$w0 = COPY %7(s32)
$w1 = COPY %8(s32)
$w2 = COPY %9(s32)
RET_ReallyLR implicit $w0, implicit $w1, implicit $w2
...
---
name: xtn_v3i64_v3i8
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2
; CHECK-LABEL: name: xtn_v3i64_v3i8
; CHECK: liveins: $d0, $d1, $d2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $d1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $d2
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
; CHECK-NEXT: $w1 = COPY [[TRUNC1]](s32)
; CHECK-NEXT: $w2 = COPY [[TRUNC2]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1, implicit $w2
%1:_(s64) = COPY $d0
%2:_(s64) = COPY $d1
%3:_(s64) = COPY $d2
%0:_(<3 x s64>) = G_BUILD_VECTOR %1(s64), %2(s64), %3(s64)
%4:_(<3 x s8>) = G_TRUNC %0(<3 x s64>)
%8:_(s8), %9:_(s8), %10:_(s8) = G_UNMERGE_VALUES %4(<3 x s8>)
%5:_(s32) = G_ANYEXT %8(s8)
%6:_(s32) = G_ANYEXT %9(s8)
%7:_(s32) = G_ANYEXT %10(s8)
$w0 = COPY %5(s32)
$w1 = COPY %6(s32)
$w2 = COPY %7(s32)
RET_ReallyLR implicit $w0, implicit $w1, implicit $w2
...
---
name: xtn_v3i64_v3i16
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2
; CHECK-LABEL: name: xtn_v3i64_v3i16
; CHECK: liveins: $d0, $d1, $d2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $d1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $d2
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s64)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16), [[DEF]](s16)
; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%1:_(s64) = COPY $d0
%2:_(s64) = COPY $d1
%3:_(s64) = COPY $d2
%0:_(<3 x s64>) = G_BUILD_VECTOR %1(s64), %2(s64), %3(s64)
%4:_(<3 x s16>) = G_TRUNC %0(<3 x s64>)
%5:_(s16), %6:_(s16), %7:_(s16) = G_UNMERGE_VALUES %4(<3 x s16>)
%8:_(s16) = G_IMPLICIT_DEF
%9:_(<4 x s16>) = G_BUILD_VECTOR %5(s16), %6(s16), %7(s16), %8(s16)
$d0 = COPY %9(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: xtn_v3i64_v3i32
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2
; CHECK-LABEL: name: xtn_v3i64_v3i32
; CHECK: liveins: $d0, $d1, $d2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $d1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $d2
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[TRUNC]](s32), [[TRUNC1]](s32), [[TRUNC2]](s32), [[DEF]](s32)
; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%1:_(s64) = COPY $d0
%2:_(s64) = COPY $d1
%3:_(s64) = COPY $d2
%0:_(<3 x s64>) = G_BUILD_VECTOR %1(s64), %2(s64), %3(s64)
%4:_(<3 x s32>) = G_TRUNC %0(<3 x s64>)
%5:_(s32), %6:_(s32), %7:_(s32) = G_UNMERGE_VALUES %4(<3 x s32>)
%8:_(s32) = G_IMPLICIT_DEF
%9:_(<4 x s32>) = G_BUILD_VECTOR %5(s32), %6(s32), %7(s32), %8(s32)
$q0 = COPY %9(<4 x s32>)
RET_ReallyLR implicit $q0
...
---
name: xtn_v4i32_v4i8
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: xtn_v4i32_v4i8
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[COPY]](<4 x s32>)
; CHECK-NEXT: $d0 = COPY [[TRUNC]](<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:_(<4 x s32>) = COPY $q0
%1:_(<4 x s8>) = G_TRUNC %0(<4 x s32>)
%2:_(<4 x s16>) = G_ANYEXT %1(<4 x s8>)
$d0 = COPY %2(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: xtn_v4i64_v4i8
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: xtn_v4i64_v4i8
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[COPY]](<2 x s64>)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[COPY1]](<2 x s64>)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[TRUNC]](<2 x s32>), [[TRUNC1]](<2 x s32>)
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[CONCAT_VECTORS]](<4 x s32>)
; CHECK-NEXT: $d0 = COPY [[TRUNC2]](<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%1:_(<2 x s64>) = COPY $q0
%2:_(<2 x s64>) = COPY $q1
%0:_(<4 x s64>) = G_CONCAT_VECTORS %1(<2 x s64>), %2(<2 x s64>)
%3:_(<4 x s8>) = G_TRUNC %0(<4 x s64>)
%4:_(<4 x s16>) = G_ANYEXT %3(<4 x s8>)
$d0 = COPY %4(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: xtn_v4i64_v4i16
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: xtn_v4i64_v4i16
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[COPY]](<2 x s64>)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[COPY1]](<2 x s64>)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[TRUNC]](<2 x s32>), [[TRUNC1]](<2 x s32>)
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[CONCAT_VECTORS]](<4 x s32>)
; CHECK-NEXT: $d0 = COPY [[TRUNC2]](<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%1:_(<2 x s64>) = COPY $q0
%2:_(<2 x s64>) = COPY $q1
%0:_(<4 x s64>) = G_CONCAT_VECTORS %1(<2 x s64>), %2(<2 x s64>)
%3:_(<4 x s16>) = G_TRUNC %0(<4 x s64>)
$d0 = COPY %3(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: xtn_v4i64_v4i32
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: xtn_v4i64_v4i32
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[COPY]](<2 x s64>)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[COPY1]](<2 x s64>)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[TRUNC]](<2 x s32>), [[TRUNC1]](<2 x s32>)
; CHECK-NEXT: $q0 = COPY [[CONCAT_VECTORS]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%1:_(<2 x s64>) = COPY $q0
%2:_(<2 x s64>) = COPY $q1
%0:_(<4 x s64>) = G_CONCAT_VECTORS %1(<2 x s64>), %2(<2 x s64>)
%3:_(<4 x s32>) = G_TRUNC %0(<4 x s64>)
$q0 = COPY %3(<4 x s32>)
RET_ReallyLR implicit $q0
...
---
name: xtn_v8i32_v8i8
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: xtn_v8i32_v8i8
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[COPY]](<4 x s32>)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[COPY1]](<4 x s32>)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>)
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>)
; CHECK-NEXT: $d0 = COPY [[TRUNC2]](<8 x s8>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%1:_(<4 x s32>) = COPY $q0
%2:_(<4 x s32>) = COPY $q1
%0:_(<8 x s32>) = G_CONCAT_VECTORS %1(<4 x s32>), %2(<4 x s32>)
%3:_(<8 x s8>) = G_TRUNC %0(<8 x s32>)
$d0 = COPY %3(<8 x s8>)
RET_ReallyLR implicit $d0
...
---
name: xtn_v8i32_v8i16
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: xtn_v8i32_v8i16
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[COPY]](<4 x s32>)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[COPY1]](<4 x s32>)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>)
; CHECK-NEXT: $q0 = COPY [[CONCAT_VECTORS]](<8 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%1:_(<4 x s32>) = COPY $q0
%2:_(<4 x s32>) = COPY $q1
%0:_(<8 x s32>) = G_CONCAT_VECTORS %1(<4 x s32>), %2(<4 x s32>)
%3:_(<8 x s16>) = G_TRUNC %0(<8 x s32>)
$q0 = COPY %3(<8 x s16>)
RET_ReallyLR implicit $q0
...
---
name: xtn_v16i16_v16i8
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: xtn_v16i16_v16i8
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[COPY]](<8 x s16>)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[COPY1]](<8 x s16>)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s8>) = G_CONCAT_VECTORS [[TRUNC]](<8 x s8>), [[TRUNC1]](<8 x s8>)
; CHECK-NEXT: $q0 = COPY [[CONCAT_VECTORS]](<16 x s8>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%1:_(<8 x s16>) = COPY $q0
%2:_(<8 x s16>) = COPY $q1
%0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
%3:_(<16 x s8>) = G_TRUNC %0(<16 x s16>)
$q0 = COPY %3(<16 x s8>)
RET_ReallyLR implicit $q0
...
---
name: pr81244
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: pr81244
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UV]](s32)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[UV1]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[TRUNC]](s8), [[TRUNC1]](s8), [[TRUNC]](s8), [[TRUNC1]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[BUILD_VECTOR]](<8 x s8>)
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<4 x s16>), [[UV3:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[ANYEXT]](<8 x s16>)
; CHECK-NEXT: $d0 = COPY [[UV2]](<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s8>) = G_TRUNC %0(<2 x s32>)
%2:_(<4 x s8>) = G_CONCAT_VECTORS %1(<2 x s8>), %1(<2 x s8>)
%3:_(<4 x s16>) = G_ANYEXT %2(<4 x s8>)
$d0 = COPY %3(<4 x s16>)
RET_ReallyLR implicit $d0
...
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