# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=legalizer -verify-machineinstrs -global-isel-abort=0 %s -o - | FileCheck %s
...
---
name: s32
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: s32
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:_(s32) = COPY $w0
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[SADDO:%[0-9]+]]:_(s32), [[SADDO1:%[0-9]+]]:_(s32) = G_SADDO %x, %y
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SADDO]], [[C]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C1]]
; CHECK-NEXT: %saddsat:_(s32) = G_SELECT [[SADDO1]](s32), [[ADD]], [[SADDO]]
; CHECK-NEXT: $w0 = COPY %saddsat(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%saddsat:_(s32) = G_SADDSAT %x, %y
$w0 = COPY %saddsat(s32)
RET_ReallyLR implicit $w0
...
---
name: s64
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: s64
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:_(s64) = COPY $x0
; CHECK-NEXT: %y:_(s64) = COPY $x1
; CHECK-NEXT: [[SADDO:%[0-9]+]]:_(s64), [[SADDO1:%[0-9]+]]:_(s32) = G_SADDO %x, %y
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SADDO]], [[C]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C1]]
; CHECK-NEXT: %saddsat:_(s64) = G_SELECT [[SADDO1]](s32), [[ADD]], [[SADDO]]
; CHECK-NEXT: $x0 = COPY %saddsat(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%x:_(s64) = COPY $x0
%y:_(s64) = COPY $x1
%saddsat:_(s64) = G_SADDSAT %x, %y
$x0 = COPY %saddsat(s64)
RET_ReallyLR implicit $x0
...
---
name: s16
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: s16
; CHECK: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy_1:_(s32) = COPY $w0
; CHECK-NEXT: %copy_2:_(s32) = COPY $w1
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_1, 16
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_2, 16
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 16
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[SEXT_INREG2]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG2]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C1]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD1]], [[ADD]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
%x:_(s16) = G_TRUNC %copy_1(s32)
%copy_2:_(s32) = COPY $w1
%y:_(s16) = G_TRUNC %copy_2(s32)
%saddsat:_(s16) = G_SADDSAT %x, %y
%ext:_(s32) = G_ANYEXT %saddsat(s16)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: s1
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: s1
; CHECK: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy_1:_(s32) = COPY $w0
; CHECK-NEXT: %copy_2:_(s32) = COPY $w1
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_1, 1
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_2, 1
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[SEXT_INREG2]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG2]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C1]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD1]], [[ADD]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
%x:_(s1) = G_TRUNC %copy_1(s32)
%copy_2:_(s32) = COPY $w1
%y:_(s1) = G_TRUNC %copy_2(s32)
%saddsat:_(s1) = G_SADDSAT %x, %y
%ext:_(s32) = G_ANYEXT %saddsat(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: s3
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: s3
; CHECK: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy_1:_(s32) = COPY $w0
; CHECK-NEXT: %copy_2:_(s32) = COPY $w1
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_1, 3
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_2, 3
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 3
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[SEXT_INREG2]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG2]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C1]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD1]], [[ADD]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
%x:_(s3) = G_TRUNC %copy_1(s32)
%copy_2:_(s32) = COPY $w1
%y:_(s3) = G_TRUNC %copy_2(s32)
%saddsat:_(s3) = G_SADDSAT %x, %y
%ext:_(s32) = G_ANYEXT %saddsat(s3)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: s36
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: s36
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy_1:_(s64) = COPY $x0
; CHECK-NEXT: %copy_2:_(s64) = COPY $x1
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG %copy_1, 36
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG %copy_2, 36
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 36
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s64), [[SEXT_INREG2]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 35
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[SEXT_INREG2]](s64)
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738368
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C1]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[ADD1]], [[ADD]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%copy_1:_(s64) = COPY $x0
%x:_(s36) = G_TRUNC %copy_1(s64)
%copy_2:_(s64) = COPY $x1
%y:_(s36) = G_TRUNC %copy_2(s64)
%saddsat:_(s36) = G_SADDSAT %x, %y
%ext:_(s64) = G_ANYEXT %saddsat(s36)
$x0 = COPY %ext(s64)
RET_ReallyLR implicit $x0
...
---
name: s88
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $x0
; CHECK-LABEL: name: s88
; CHECK: liveins: $q0, $q1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy_1:_(s128) = COPY $q0
; CHECK-NEXT: %copy_2:_(s128) = COPY $q1
; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT %copy_1(s128), 0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %copy_1(s128)
; CHECK-NEXT: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT %copy_2(s128), 0
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %copy_2(s128)
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[EXTRACT]], [[EXTRACT1]]
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV1]](s64)
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 24
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV3]](s64)
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 24
; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[SEXT_INREG]], [[SEXT_INREG1]], [[UADDO1]]
; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UADDE]], 24
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UADDE]](s32), [[SEXT_INREG2]]
; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[UADDE]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[DEF1]](s32)
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV4]](s8), [[UV5]](s8), [[UV6]](s8), [[DEF]](s8)
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV8]](s8), [[UV9]](s8), [[UV10]](s8), [[UV8]](s8)
; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MV]](s32), [[MV1]](s32)
; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[MV2]], 24
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 23
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG3]], [[C1]](s64)
; CHECK-NEXT: [[UADDO2:%[0-9]+]]:_(s64), [[UADDO3:%[0-9]+]]:_(s32) = G_UADDO [[ASHR]], [[C]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[UADDO2]], [[UADDO]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%copy_1:_(s128) = COPY $q0
%x:_(s88) = G_TRUNC %copy_1(s128)
%copy_2:_(s128) = COPY $q1
%y:_(s88) = G_TRUNC %copy_2(s128)
%saddsat:_(s88) = G_SADDSAT %x, %y
%trunc:_(s64) = G_TRUNC %saddsat(s88)
$x0 = COPY %trunc(s64)
RET_ReallyLR implicit $x0
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