# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
# Check that we select a 32-bit GPR G_ADD into ADDWrr on GPR32.
# Also check that we constrain the register class of the COPY to GPR32.
name: add_s32_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: add_s32_gpr
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[ADDWrr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_ADD %0, %1
$w0 = COPY %2(s32)
...
---
# Same as add_s32_gpr, for 64-bit operations.
name: add_s64_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: add_s64_gpr
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[ADDXrr]]
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_ADD %0, %1
$x0 = COPY %2(s64)
...
---
name: add_imm_s32_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: add_imm_s32_gpr
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0
; CHECK-NEXT: $w0 = COPY [[ADDWri]]
%0(s32) = COPY $w0
%1(s32) = G_CONSTANT i32 1
%2(s32) = G_ADD %0, %1
$w0 = COPY %2(s32)
...
---
name: add_imm_s64_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $x0, $w1
; CHECK-LABEL: name: add_imm_s64_gpr
; CHECK: liveins: $x0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 1, 0
; CHECK-NEXT: $x0 = COPY [[ADDXri]]
%0(s64) = COPY $x0
%1(s64) = G_CONSTANT i64 1
%2(s64) = G_ADD %0, %1
$x0 = COPY %2(s64)
...
---
name: add_neg_s32_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $w1, $w2
; We should be able to turn the ADD into a SUB.
; CHECK-LABEL: name: add_neg_s32_gpr
; CHECK: liveins: $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w1
; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def dead $nzcv
; CHECK-NEXT: $w2 = COPY [[SUBSWri]]
%0(s32) = COPY $w1
%1(s32) = G_CONSTANT i32 -1
%2(s32) = G_ADD %0, %1
$w2 = COPY %2(s32)
...
---
name: add_neg_s64_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $x0, $x1
; We should be able to turn the ADD into a SUB.
; CHECK-LABEL: name: add_neg_s64_gpr
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 1, 0, implicit-def dead $nzcv
; CHECK-NEXT: $x0 = COPY [[SUBSXri]]
%0(s64) = COPY $x0
%1(s64) = G_CONSTANT i64 -1
%2(s64) = G_ADD %0, %1
$x0 = COPY %2(s64)
...
---
name: add_neg_invalid_immed_s32
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $x0, $x1
; We can't select this if the value is out of range.
; CHECK-LABEL: name: add_neg_invalid_immed_s32
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -5000
; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[MOVi64imm]]
; CHECK-NEXT: $x0 = COPY [[ADDXrr]]
%0(s64) = COPY $x0
%1(s64) = G_CONSTANT i64 -5000
%2(s64) = G_ADD %0, %1
$x0 = COPY %2(s64)
...
---
name: add_neg_invalid_immed_s64
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $x0, $x1
; We can't select this if the value is out of range.
; CHECK-LABEL: name: add_neg_invalid_immed_s64
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -5000
; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[MOVi64imm]]
; CHECK-NEXT: $x0 = COPY [[ADDXrr]]
%0(s64) = COPY $x0
%1(s64) = G_CONSTANT i64 -5000
%2(s64) = G_ADD %0, %1
$x0 = COPY %2(s64)
...
---
name: add_imm_0_s32
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $x0, $x1
; We shouldn't get a SUB here, because "cmp wN, $0" and "cmp wN, #0" have
; opposite effects on the C flag.
; CHECK-LABEL: name: add_imm_0_s32
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 0, 0
; CHECK-NEXT: $x0 = COPY [[ADDXri]]
%0(s64) = COPY $x0
%1(s64) = G_CONSTANT i64 0
%2(s64) = G_ADD %0, %1
$x0 = COPY %2(s64)
...
---
name: add_imm_0_s64
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $x0, $x1
; We shouldn't get a SUB here, because "cmp xN, $0" and "cmp xN, #0" have
; opposite effects on the C flag.
; CHECK-LABEL: name: add_imm_0_s64
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 0, 0
; CHECK-NEXT: $x0 = COPY [[ADDXri]]
%0(s64) = COPY $x0
%1(s64) = G_CONSTANT i64 0
%2(s64) = G_ADD %0, %1
$x0 = COPY %2(s64)
...
---
name: add_imm_s32_gpr_bb
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
; CHECK-LABEL: name: add_imm_s32_gpr_bb
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0
; CHECK-NEXT: $w0 = COPY [[ADDWri]]
bb.0:
liveins: $w0, $w1
successors: %bb.1
%0(s32) = COPY $w0
%1(s32) = G_CONSTANT i32 1
G_BR %bb.1
bb.1:
%2(s32) = G_ADD %0, %1
$w0 = COPY %2(s32)
...
---
# Same as add_s32_gpr, for G_SUB operations.
name: sub_s32_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: sub_s32_gpr
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def dead $nzcv
; CHECK-NEXT: $w0 = COPY [[SUBSWrr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_SUB %0, %1
$w0 = COPY %2(s32)
...
---
# Same as add_s64_gpr, for G_SUB operations.
name: sub_s64_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: sub_s64_gpr
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def dead $nzcv
; CHECK-NEXT: $x0 = COPY [[SUBSXrr]]
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_SUB %0, %1
$x0 = COPY %2(s64)
...
---
# Same as add_s32_gpr, for G_OR operations.
name: or_s32_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: or_s32_gpr
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[ORRWrr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_OR %0, %1
$w0 = COPY %2(s32)
...
---
# Same as add_s64_gpr, for G_OR operations.
name: or_s64_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: or_s64_gpr
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[ORRXrr:%[0-9]+]]:gpr64 = ORRXrr [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[ORRXrr]]
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_OR %0, %1
$x0 = COPY %2(s64)
...
---
# 64-bit G_OR on vector registers.
name: or_v2s32_fpr
legalized: true
regBankSelected: true
#
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
# The actual OR does not matter as long as it is operating
# on 64-bit width vector.
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: or_v2s32_fpr
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[ORRv8i8_]]
%0(<2 x s32>) = COPY $d0
%1(<2 x s32>) = COPY $d1
%2(<2 x s32>) = G_OR %0, %1
$d0 = COPY %2(<2 x s32>)
...
---
# Same as add_s32_gpr, for G_AND operations.
name: and_s32_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: and_s32_gpr
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[ANDWrr:%[0-9]+]]:gpr32 = ANDWrr [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[ANDWrr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_AND %0, %1
$w0 = COPY %2(s32)
...
---
# Same as add_s64_gpr, for G_AND operations.
name: and_s64_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: and_s64_gpr
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[ANDXrr:%[0-9]+]]:gpr64 = ANDXrr [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[ANDXrr]]
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_AND %0, %1
$x0 = COPY %2(s64)
...
---
# Same as add_s32_gpr, for G_SHL operations.
name: shl_s32_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: shl_s32_gpr
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[LSLVWr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_SHL %0, %1
$w0 = COPY %2(s32)
...
---
name: shl_s32_64_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $w0, $x1
; CHECK-LABEL: name: shl_s32_64_gpr
; CHECK: liveins: $w0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64all = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]].sub_32
; CHECK-NEXT: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY2]]
; CHECK-NEXT: $w0 = COPY [[LSLVWr]]
%0(s32) = COPY $w0
%1(s64) = COPY $x1
%2(s32) = G_SHL %0, %1
$w0 = COPY %2(s32)
...
---
# Same as add_s64_gpr, for G_SHL operations.
name: shl_s64_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: shl_s64_gpr
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[LSLVXr:%[0-9]+]]:gpr64 = LSLVXr [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[LSLVXr]]
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_SHL %0, %1
$x0 = COPY %2(s64)
...
---
# Same as add_s32_gpr, for G_LSHR operations.
name: lshr_s32_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: lshr_s32_gpr
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[LSRVWr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_LSHR %0, %1
$w0 = COPY %2(s32)
...
---
# Same as add_s64_gpr, for G_LSHR operations.
name: lshr_s64_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: lshr_s64_gpr
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[LSRVXr:%[0-9]+]]:gpr64 = LSRVXr [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[LSRVXr]]
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_LSHR %0, %1
$x0 = COPY %2(s64)
...
---
# Same as add_s32_gpr, for G_ASHR operations.
name: ashr_s32_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: ashr_s32_gpr
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[ASRVWr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_ASHR %0, %1
$w0 = COPY %2(s32)
...
---
# Same as add_s64_gpr, for G_ASHR operations.
name: ashr_s64_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: ashr_s64_gpr
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[ASRVXr:%[0-9]+]]:gpr64 = ASRVXr [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[ASRVXr]]
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_ASHR %0, %1
$x0 = COPY %2(s64)
...
---
# Check that we select s32 GPR G_MUL. This is trickier than other binops because
# there is only MADDWrrr, and we have to use the WZR physreg.
name: mul_s32_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: mul_s32_gpr
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[COPY1]], $wzr
; CHECK-NEXT: $w0 = COPY [[MADDWrrr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_MUL %0, %1
$w0 = COPY %2(s32)
...
---
# Same as mul_s32_gpr for the s64 type.
name: mul_s64_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: mul_s64_gpr
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY1]], $xzr
; CHECK-NEXT: $x0 = COPY [[MADDXrrr]]
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_MUL %0, %1
$x0 = COPY %2(s64)
...
---
# Same as mul_s32_gpr for the s64 type.
name: mulh_s64_gpr
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: mulh_s64_gpr
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[SMULHrr:%[0-9]+]]:gpr64 = SMULHrr [[COPY]], [[COPY1]]
; CHECK-NEXT: [[UMULHrr:%[0-9]+]]:gpr64 = UMULHrr [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[SMULHrr]]
; CHECK-NEXT: $x0 = COPY [[UMULHrr]]
%0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1
%2:gpr(s64) = G_SMULH %0, %1
%3:gpr(s64) = G_UMULH %0, %1
$x0 = COPY %2(s64)
$x0 = COPY %3(s64)
...
---
# Same as add_s32_gpr, for G_SDIV operations.
name: sdiv_s32_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: sdiv_s32_gpr
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[SDIVWr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_SDIV %0, %1
$w0 = COPY %2(s32)
...
---
# Same as add_s64_gpr, for G_SDIV operations.
name: sdiv_s64_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: sdiv_s64_gpr
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[SDIVXr:%[0-9]+]]:gpr64 = SDIVXr [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[SDIVXr]]
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_SDIV %0, %1
$x0 = COPY %2(s64)
...
---
# Same as add_s32_gpr, for G_UDIV operations.
name: udiv_s32_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: udiv_s32_gpr
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[UDIVWr:%[0-9]+]]:gpr32 = UDIVWr [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[UDIVWr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_UDIV %0, %1
$w0 = COPY %2(s32)
...
---
# Same as add_s64_gpr, for G_UDIV operations.
name: udiv_s64_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: udiv_s64_gpr
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[UDIVXr:%[0-9]+]]:gpr64 = UDIVXr [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[UDIVXr]]
%0(s64) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_UDIV %0, %1
$x0 = COPY %2(s64)
...
---
# Check that we select a s32 FPR G_FADD into FADDSrr.
name: fadd_s32_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
body: |
bb.0:
liveins: $s0, $s1
; CHECK-LABEL: name: fadd_s32_fpr
; CHECK: liveins: $s0, $s1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FADDSrr]]
%0(s32) = COPY $s0
%1(s32) = COPY $s1
%2(s32) = G_FADD %0, %1
$s0 = COPY %2(s32)
...
---
name: fadd_s64_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: fadd_s64_fpr
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FADDDrr]]
%0(s64) = COPY $d0
%1(s64) = COPY $d1
%2(s64) = G_FADD %0, %1
$d0 = COPY %2(s64)
...
---
name: fsub_s32_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
body: |
bb.0:
liveins: $s0, $s1
; CHECK-LABEL: name: fsub_s32_fpr
; CHECK: liveins: $s0, $s1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK-NEXT: [[FSUBSrr:%[0-9]+]]:fpr32 = nofpexcept FSUBSrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FSUBSrr]]
%0(s32) = COPY $s0
%1(s32) = COPY $s1
%2(s32) = G_FSUB %0, %1
$s0 = COPY %2(s32)
...
---
name: fsub_s64_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: fsub_s64_fpr
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[FSUBDrr:%[0-9]+]]:fpr64 = nofpexcept FSUBDrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FSUBDrr]]
%0(s64) = COPY $d0
%1(s64) = COPY $d1
%2(s64) = G_FSUB %0, %1
$d0 = COPY %2(s64)
...
---
name: fmul_s32_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
body: |
bb.0:
liveins: $s0, $s1
; CHECK-LABEL: name: fmul_s32_fpr
; CHECK: liveins: $s0, $s1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK-NEXT: [[FMULSrr:%[0-9]+]]:fpr32 = nofpexcept FMULSrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FMULSrr]]
%0(s32) = COPY $s0
%1(s32) = COPY $s1
%2(s32) = G_FMUL %0, %1
$s0 = COPY %2(s32)
...
---
name: fmul_s64_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: fmul_s64_fpr
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[FMULDrr:%[0-9]+]]:fpr64 = nofpexcept FMULDrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FMULDrr]]
%0(s64) = COPY $d0
%1(s64) = COPY $d1
%2(s64) = G_FMUL %0, %1
$d0 = COPY %2(s64)
...
---
name: fdiv_s32_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
body: |
bb.0:
liveins: $s0, $s1
; CHECK-LABEL: name: fdiv_s32_fpr
; CHECK: liveins: $s0, $s1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK-NEXT: [[FDIVSrr:%[0-9]+]]:fpr32 = nofpexcept FDIVSrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FDIVSrr]]
%0(s32) = COPY $s0
%1(s32) = COPY $s1
%2(s32) = G_FDIV %0, %1
$s0 = COPY %2(s32)
...
---
name: fdiv_s64_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: fdiv_s64_fpr
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[FDIVDrr:%[0-9]+]]:fpr64 = nofpexcept FDIVDrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FDIVDrr]]
%0(s64) = COPY $d0
%1(s64) = COPY $d1
%2(s64) = G_FDIV %0, %1
$d0 = COPY %2(s64)
...
---
name: add_v8i16
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
machineFunctionInfo: {}
body: |
bb.1:
liveins: $q0, $q1
; CHECK-LABEL: name: add_v8i16
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK-NEXT: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[ADDv8i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:fpr(<8 x s16>) = COPY $q0
%1:fpr(<8 x s16>) = COPY $q1
%2:fpr(<8 x s16>) = G_ADD %0, %1
$q0 = COPY %2(<8 x s16>)
RET_ReallyLR implicit $q0
...
---
name: add_v16i8
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
machineFunctionInfo: {}
body: |
bb.1:
liveins: $q0, $q1
; CHECK-LABEL: name: add_v16i8
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK-NEXT: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[ADDv16i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:fpr(<16 x s8>) = COPY $q0
%1:fpr(<16 x s8>) = COPY $q1
%2:fpr(<16 x s8>) = G_ADD %0, %1
$q0 = COPY %2(<16 x s8>)
RET_ReallyLR implicit $q0
...
---
name: add_v4i16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $d0, $d1
; CHECK-LABEL: name: add_v4i16
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[ADDv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:fpr(<4 x s16>) = COPY $d0
%1:fpr(<4 x s16>) = COPY $d1
%2:fpr(<4 x s16>) = G_ADD %0, %1
$d0 = COPY %2(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: or_v4i16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $d0, $d1
; CHECK-LABEL: name: or_v4i16
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[ORRv8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:fpr(<4 x s16>) = COPY $d0
%1:fpr(<4 x s16>) = COPY $d1
%2:fpr(<4 x s16>) = G_OR %0, %1
$d0 = COPY %2(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: xor_v4i16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $d0, $d1
; CHECK-LABEL: name: xor_v4i16
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[EORv8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:fpr(<4 x s16>) = COPY $d0
%1:fpr(<4 x s16>) = COPY $d1
%2:fpr(<4 x s16>) = G_XOR %0, %1
$d0 = COPY %2(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: mul_v4i16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $d0, $d1
; CHECK-LABEL: name: mul_v4i16
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[MULv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:fpr(<4 x s16>) = COPY $d0
%1:fpr(<4 x s16>) = COPY $d1
%2:fpr(<4 x s16>) = G_MUL %0, %1
$d0 = COPY %2(<4 x s16>)
RET_ReallyLR implicit $d0
...
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