# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=arm64-unknown-unknown -global-isel -run-pass=instruction-select -global-isel-abort=1 %s -o - | FileCheck %s
name: test_v8s8
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: test_v8s8
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[CLZv8i8_:%[0-9]+]]:fpr64 = CLZv8i8 [[COPY]]
; CHECK: $d0 = COPY [[CLZv8i8_]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<8 x s8>) = COPY $d0
%1:fpr(<8 x s8>) = G_CTLZ %0(<8 x s8>)
$d0 = COPY %1(<8 x s8>)
RET_ReallyLR implicit $d0
...
---
name: test_v4s16
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: test_v4s16
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[CLZv4i16_:%[0-9]+]]:fpr64 = CLZv4i16 [[COPY]]
; CHECK: $d0 = COPY [[CLZv4i16_]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<4 x s16>) = COPY $d0
%1:fpr(<4 x s16>) = G_CTLZ %0(<4 x s16>)
$d0 = COPY %1(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: test_v2s32
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: test_v2s32
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[CLZv2i32_:%[0-9]+]]:fpr64 = CLZv2i32 [[COPY]]
; CHECK: $d0 = COPY [[CLZv2i32_]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<2 x s32>) = COPY $d0
%1:fpr(<2 x s32>) = G_CTLZ %0(<2 x s32>)
$d0 = COPY %1(<2 x s32>)
RET_ReallyLR implicit $d0
...
---
name: test_s64
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: test_s64
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
; CHECK: [[CLZXr:%[0-9]+]]:gpr64 = CLZXr [[COPY1]]
; CHECK: $d0 = COPY [[CLZXr]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(s64) = COPY $d0
%2:gpr(s64) = COPY %0(s64)
%1:gpr(s64) = G_CTLZ %2(s64)
$d0 = COPY %1(s64)
RET_ReallyLR implicit $d0
...
---
name: test_s32
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $s0
; CHECK-LABEL: name: test_s32
; CHECK: liveins: $s0
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
; CHECK: [[CLZWr:%[0-9]+]]:gpr32 = CLZWr [[COPY1]]
; CHECK: $s0 = COPY [[CLZWr]]
; CHECK: RET_ReallyLR implicit $s0
%0:fpr(s32) = COPY $s0
%2:gpr(s32) = COPY %0(s32)
%1:gpr(s32) = G_CTLZ %2(s32)
$s0 = COPY %1(s32)
RET_ReallyLR implicit $s0
...
---
name: test_v16s8
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_v16s8
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[CLZv16i8_:%[0-9]+]]:fpr128 = CLZv16i8 [[COPY]]
; CHECK: $q0 = COPY [[CLZv16i8_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<16 x s8>) = COPY $q0
%1:fpr(<16 x s8>) = G_CTLZ %0(<16 x s8>)
$q0 = COPY %1(<16 x s8>)
RET_ReallyLR implicit $q0
...
---
name: test_v8s16
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_v8s16
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[CLZv8i16_:%[0-9]+]]:fpr128 = CLZv8i16 [[COPY]]
; CHECK: $q0 = COPY [[CLZv8i16_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<8 x s16>) = COPY $q0
%1:fpr(<8 x s16>) = G_CTLZ %0(<8 x s16>)
$q0 = COPY %1(<8 x s16>)
RET_ReallyLR implicit $q0
...
---
name: test_v4s32
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_v4s32
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[CLZv4i32_:%[0-9]+]]:fpr128 = CLZv4i32 [[COPY]]
; CHECK: $q0 = COPY [[CLZv4i32_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<4 x s32>) = COPY $q0
%1:fpr(<4 x s32>) = G_CTLZ %0(<4 x s32>)
$q0 = COPY %1(<4 x s32>)
RET_ReallyLR implicit $q0
...
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