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llvm/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir 

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=instruction-select -global-isel-abort=1 %s -o - | FileCheck %s
...
---
name:            v2s32_fpr
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: gpr }
  - { id: 3, class: fpr }
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: v2s32_fpr
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
    ; CHECK-NEXT: [[DUPi32_:%[0-9]+]]:fpr32 = DUPi32 [[INSERT_SUBREG]], 1
    ; CHECK-NEXT: $s0 = COPY [[DUPi32_]]
    ; CHECK-NEXT: RET_ReallyLR implicit $s0
    %0:fpr(<2 x s32>) = COPY $d0
    %2:gpr(s64) = G_CONSTANT i64 1
    %3:fpr(s64) = COPY %2(s64)
    %1:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
    $s0 = COPY %1(s32)
    RET_ReallyLR implicit $s0

...
---
name:            v2s32_fpr_idx0
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $d0
    ; CHECK-LABEL: name: v2s32_fpr_idx0
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
    ; CHECK-NEXT: $s0 = COPY [[COPY1]]
    ; CHECK-NEXT: RET_ReallyLR implicit $s0
    %0:fpr(<2 x s32>) = COPY $d0
    %2:gpr(s64) = G_CONSTANT i64 0
    %3:fpr(s64) = COPY %2(s64)
    %1:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
    $s0 = COPY %1(s32)
    RET_ReallyLR implicit $s0

...
---
name:            v2s64_fpr
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: gpr }
  - { id: 3, class: fpr }
body:             |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: v2s64_fpr
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK-NEXT: [[DUPi64_:%[0-9]+]]:fpr64 = DUPi64 [[COPY]], 2
    ; CHECK-NEXT: $d0 = COPY [[DUPi64_]]
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s64>) = COPY $q0
    %2:gpr(s64) = G_CONSTANT i64 2
    %3:fpr(s64) = COPY %2(s64)
    %1:fpr(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %3(s64)
    $d0 = COPY %1(s64)
    RET_ReallyLR implicit $d0

...
---
name:            v4s16_fpr
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: gpr }
  - { id: 3, class: fpr }
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: v4s16_fpr
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
    ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG]], 1
    ; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
    ; CHECK-NEXT: RET_ReallyLR implicit $h0
    %0:fpr(<4 x s16>) = COPY $d0
    %2:gpr(s64) = G_CONSTANT i64 1
    %3:fpr(s64) = COPY %2(s64)
    %1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %3(s64)
    $h0 = COPY %1(s16)
    RET_ReallyLR implicit $h0

...
---
name:            v8s16_fpr
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $q0
    ; CHECK-LABEL: name: v8s16_fpr
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
    ; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
    ; CHECK-NEXT: RET_ReallyLR implicit $h0
    %0:fpr(<8 x s16>) = COPY $q0
    %2:gpr(s64) = G_CONSTANT i64 1
    %3:fpr(s64) = COPY %2(s64)
    %1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
    $h0 = COPY %1(s16)
    RET_ReallyLR implicit $h0

...
---
name:            v8s16_fpr_zext
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $q0
    ; CHECK-LABEL: name: v8s16_fpr_zext
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
    ; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
    ; CHECK-NEXT: RET_ReallyLR implicit $h0
    %0:fpr(<8 x s16>) = COPY $q0
    %1:gpr(s32) = G_CONSTANT i32 1
    %2:gpr(s64) = G_ZEXT %1
    %3:fpr(s64) = COPY %2(s64)
    %4:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
    $h0 = COPY %4(s16)
    RET_ReallyLR implicit $h0

...
---
name:            v8s16_fpr_sext
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $q0
    ; CHECK-LABEL: name: v8s16_fpr_sext
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
    ; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
    ; CHECK-NEXT: RET_ReallyLR implicit $h0
    %0:fpr(<8 x s16>) = COPY $q0
    %1:gpr(s32) = G_CONSTANT i32 1
    %2:gpr(s64) = G_SEXT %1
    %3:fpr(s64) = COPY %2(s64)
    %4:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
    $h0 = COPY %4(s16)
    RET_ReallyLR implicit $h0

...
---
name:            v8s16_fpr_trunc
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $q0
    ; CHECK-LABEL: name: v8s16_fpr_trunc
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
    ; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
    ; CHECK-NEXT: RET_ReallyLR implicit $h0
    %0:fpr(<8 x s16>) = COPY $q0
    %1:gpr(s64) = G_CONSTANT i64 1
    %2:gpr(s32) = G_TRUNC %1
    %3:gpr(s64) = G_SEXT %2
    %4:fpr(s64) = COPY %3(s64)
    %5:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %4(s64)
    $h0 = COPY %5(s16)
    RET_ReallyLR implicit $h0
...
---
name:            v16s8
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
liveins:
  - { reg: '$q0' }
body:             |
  bb.1:
    liveins: $q0

    ; CHECK-LABEL: name: v16s8
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK-NEXT: [[UMOVvi8_:%[0-9]+]]:gpr32 = UMOVvi8 [[COPY]], 0
    ; CHECK-NEXT: $w0 = COPY [[UMOVvi8_]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %0:fpr(<16 x s8>) = COPY $q0
    %2:gpr(s64) = G_CONSTANT i64 0
    %1:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<16 x s8>), %2(s64)
    %4:gpr(s8) = COPY %1(s8)
    %3:gpr(s32) = G_ANYEXT %4(s8)
    $w0 = COPY %3(s32)
    RET_ReallyLR implicit $w0

...
---
name:            v8s8
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
liveins:
  - { reg: '$q0' }
body:             |
  bb.1:
    liveins: $d0

    ; CHECK-LABEL: name: v8s8
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
    ; CHECK-NEXT: [[UMOVvi8_:%[0-9]+]]:gpr32 = UMOVvi8 [[INSERT_SUBREG]], 0
    ; CHECK-NEXT: $w0 = COPY [[UMOVvi8_]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %0:fpr(<8 x s8>) = COPY $d0
    %2:gpr(s64) = G_CONSTANT i64 0
    %1:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<8 x s8>), %2(s64)
    %4:gpr(s8) = COPY %1(s8)
    %3:gpr(s32) = G_ANYEXT %4(s8)
    $w0 = COPY %3(s32)
    RET_ReallyLR implicit $w0

...
---
name:            v2p0
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: v2p0
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK-NEXT: [[DUPi64_:%[0-9]+]]:fpr64 = DUPi64 [[COPY]], 1
    ; CHECK-NEXT: $d0 = COPY [[DUPi64_]]
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:fpr(<2 x p0>) = COPY $q0
    %2:gpr(s64) = G_CONSTANT i64 1
    %1:fpr(p0) = G_EXTRACT_VECTOR_ELT %0(<2 x p0>), %2(s64)
    $d0 = COPY %1(p0)
    RET_ReallyLR implicit $d0

...