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llvm/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir 

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-lowering -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=LOWER
# RUN: llc -mtriple aarch64 -O2 -start-before=aarch64-postlegalizer-lowering -stop-after=instruction-select -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=SELECT
...
---
name:            same_reg
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $d0
    ; LOWER-LABEL: name: same_reg
    ; LOWER: liveins: $d0
    ; LOWER-NEXT: {{  $}}
    ; LOWER-NEXT: %r:_(s8) = G_IMPLICIT_DEF
    ; LOWER-NEXT: %build_vector:_(<8 x s8>) = G_DUP %r(s8)
    ; LOWER-NEXT: $d0 = COPY %build_vector(<8 x s8>)
    ; LOWER-NEXT: RET_ReallyLR implicit $d0
    ;
    ; SELECT-LABEL: name: same_reg
    ; SELECT: liveins: $d0
    ; SELECT-NEXT: {{  $}}
    ; SELECT-NEXT: %r:gpr32 = IMPLICIT_DEF
    ; SELECT-NEXT: %build_vector:fpr64 = DUPv8i8gpr %r
    ; SELECT-NEXT: $d0 = COPY %build_vector
    ; SELECT-NEXT: RET_ReallyLR implicit $d0
    %r:_(s8) = G_IMPLICIT_DEF
    %build_vector:_(<8 x s8>) = G_BUILD_VECTOR %r, %r, %r, %r, %r, %r, %r, %r
    $d0 = COPY %build_vector(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            dont_combine_different_reg
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $d0, $w0, $w1
    ; LOWER-LABEL: name: dont_combine_different_reg
    ; LOWER: liveins: $d0, $w0, $w1
    ; LOWER-NEXT: {{  $}}
    ; LOWER-NEXT: %r:_(s32) = COPY $w0
    ; LOWER-NEXT: %q:_(s32) = COPY $w1
    ; LOWER-NEXT: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
    ; LOWER-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
    ; LOWER-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], %r(s32), [[C]](s64)
    ; LOWER-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
    ; LOWER-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[IVEC]], %q(s32), [[C1]](s64)
    ; LOWER-NEXT: %build_vector:_(<2 x s32>) = COPY [[IVEC1]](<2 x s32>)
    ; LOWER-NEXT: $d0 = COPY %build_vector(<2 x s32>)
    ; LOWER-NEXT: RET_ReallyLR implicit $d0
    ;
    ; SELECT-LABEL: name: dont_combine_different_reg
    ; SELECT: liveins: $d0, $w0, $w1
    ; SELECT-NEXT: {{  $}}
    ; SELECT-NEXT: %r:gpr32 = COPY $w0
    ; SELECT-NEXT: %q:gpr32 = COPY $w1
    ; SELECT-NEXT: [[DEF:%[0-9]+]]:fpr64 = IMPLICIT_DEF
    ; SELECT-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; SELECT-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[DEF]], %subreg.dsub
    ; SELECT-NEXT: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 0, %r
    ; SELECT-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
    ; SELECT-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; SELECT-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY]], %subreg.dsub
    ; SELECT-NEXT: [[INSvi32gpr1:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG1]], 1, %q
    ; SELECT-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr1]].dsub
    ; SELECT-NEXT: $d0 = COPY [[COPY1]]
    ; SELECT-NEXT: RET_ReallyLR implicit $d0
    %r:_(s32) = COPY $w0
    %q:_(s32) = COPY $w1
    %build_vector:_(<2 x s32>) = G_BUILD_VECTOR %r, %q
    $d0 = COPY %build_vector(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            dont_combine_zero
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $d0

    ; LOWER-LABEL: name: dont_combine_zero
    ; LOWER: liveins: $d0
    ; LOWER-NEXT: {{  $}}
    ; LOWER-NEXT: %r:_(s8) = G_CONSTANT i8 0
    ; LOWER-NEXT: %build_vector:_(<8 x s8>) = G_BUILD_VECTOR %r(s8), %r(s8), %r(s8), %r(s8), %r(s8), %r(s8), %r(s8), %r(s8)
    ; LOWER-NEXT: $d0 = COPY %build_vector(<8 x s8>)
    ; LOWER-NEXT: RET_ReallyLR implicit $d0
    ;
    ; SELECT-LABEL: name: dont_combine_zero
    ; SELECT: liveins: $d0
    ; SELECT-NEXT: {{  $}}
    ; SELECT-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
    ; SELECT-NEXT: %build_vector:fpr64 = COPY [[MOVIv2d_ns]].dsub
    ; SELECT-NEXT: $d0 = COPY %build_vector
    ; SELECT-NEXT: RET_ReallyLR implicit $d0
    %r:_(s8) = G_CONSTANT i8 0
    %build_vector:_(<8 x s8>) = G_BUILD_VECTOR %r, %r, %r, %r, %r, %r, %r, %r
    $d0 = COPY %build_vector(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            dont_combine_all_ones
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $d0

    ; LOWER-LABEL: name: dont_combine_all_ones
    ; LOWER: liveins: $d0
    ; LOWER-NEXT: {{  $}}
    ; LOWER-NEXT: %r:_(s8) = G_CONSTANT i8 -1
    ; LOWER-NEXT: %build_vector:_(<8 x s8>) = G_BUILD_VECTOR %r(s8), %r(s8), %r(s8), %r(s8), %r(s8), %r(s8), %r(s8), %r(s8)
    ; LOWER-NEXT: $d0 = COPY %build_vector(<8 x s8>)
    ; LOWER-NEXT: RET_ReallyLR implicit $d0
    ;
    ; SELECT-LABEL: name: dont_combine_all_ones
    ; SELECT: liveins: $d0
    ; SELECT-NEXT: {{  $}}
    ; SELECT-NEXT: %build_vector:fpr64 = MOVID 255
    ; SELECT-NEXT: $d0 = COPY %build_vector
    ; SELECT-NEXT: RET_ReallyLR implicit $d0
    %r:_(s8) = G_CONSTANT i8 -1
    %build_vector:_(<8 x s8>) = G_BUILD_VECTOR %r, %r, %r, %r, %r, %r, %r, %r
    $d0 = COPY %build_vector(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            all_zeros_pat_example
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $d0

    ; LOWER-LABEL: name: all_zeros_pat_example
    ; LOWER: liveins: $d0
    ; LOWER-NEXT: {{  $}}
    ; LOWER-NEXT: %v:_(<2 x s32>) = COPY $d0
    ; LOWER-NEXT: %cst:_(s32) = G_CONSTANT i32 0
    ; LOWER-NEXT: %build_vector:_(<2 x s32>) = G_BUILD_VECTOR %cst(s32), %cst(s32)
    ; LOWER-NEXT: %sub:_(<2 x s32>) = G_SUB %build_vector, %v
    ; LOWER-NEXT: $d0 = COPY %sub(<2 x s32>)
    ; LOWER-NEXT: RET_ReallyLR implicit $d0
    ;
    ; SELECT-LABEL: name: all_zeros_pat_example
    ; SELECT: liveins: $d0
    ; SELECT-NEXT: {{  $}}
    ; SELECT-NEXT: %v:fpr64 = COPY $d0
    ; SELECT-NEXT: %sub:fpr64 = NEGv2i32 %v
    ; SELECT-NEXT: $d0 = COPY %sub
    ; SELECT-NEXT: RET_ReallyLR implicit $d0
      %v:_(<2 x s32>) = COPY $d0
    %cst:_(s32) = G_CONSTANT i32 0
    %build_vector:_(<2 x s32>) = G_BUILD_VECTOR %cst, %cst
    %sub:_(<2 x s32>) = G_SUB %build_vector, %v
    $d0 = COPY %sub(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            all_ones_pat_example
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $d0, $d1

    ; LOWER-LABEL: name: all_ones_pat_example
    ; LOWER: liveins: $d0, $d1
    ; LOWER-NEXT: {{  $}}
    ; LOWER-NEXT: %v0:_(<2 x s32>) = COPY $d0
    ; LOWER-NEXT: %v1:_(<2 x s32>) = COPY $d1
    ; LOWER-NEXT: %cst:_(s32) = G_CONSTANT i32 -1
    ; LOWER-NEXT: %build_vector:_(<2 x s32>) = G_BUILD_VECTOR %cst(s32), %cst(s32)
    ; LOWER-NEXT: %xor:_(<2 x s32>) = G_XOR %v0, %build_vector
    ; LOWER-NEXT: %and:_(<2 x s32>) = G_AND %v1, %xor
    ; LOWER-NEXT: $d0 = COPY %and(<2 x s32>)
    ; LOWER-NEXT: RET_ReallyLR implicit $d0
    ;
    ; SELECT-LABEL: name: all_ones_pat_example
    ; SELECT: liveins: $d0, $d1
    ; SELECT-NEXT: {{  $}}
    ; SELECT-NEXT: %v0:fpr64 = COPY $d0
    ; SELECT-NEXT: %v1:fpr64 = COPY $d1
    ; SELECT-NEXT: %and:fpr64 = BICv8i8 %v1, %v0
    ; SELECT-NEXT: $d0 = COPY %and
    ; SELECT-NEXT: RET_ReallyLR implicit $d0
    %v0:_(<2 x s32>) = COPY $d0
    %v1:_(<2 x s32>) = COPY $d1
    %cst:_(s32) = G_CONSTANT i32 -1
    %build_vector:_(<2 x s32>) = G_BUILD_VECTOR %cst, %cst
    %xor:_(<2 x s32>) = G_XOR %v0, %build_vector
    %and:_(<2 x s32>) = G_AND %v1, %xor
    $d0 = COPY %and(<2 x s32>)
    RET_ReallyLR implicit $d0