Codebase Browser
llvm
Go to App

llvm/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir 

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

---
name:            si64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0, $w0

    ; CHECK-LABEL: name: si64
    ; CHECK: liveins: $q0, $w0
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[SMOVvi32to64_:%[0-9]+]]:gpr64 = SMOVvi32to64 [[COPY]], 1
    ; CHECK: $x0 = COPY [[SMOVvi32to64_]]
    ; CHECK: RET_ReallyLR implicit $x0
    %0:fpr(<4 x s32>) = COPY $q0
    %3:gpr(s64) = G_CONSTANT i64 1
    %2:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<4 x s32>), %3(s64)
    %5:gpr(s32) = COPY %2(s32)
    %4:gpr(s64) = G_SEXT %5(s32)
    $x0 = COPY %4(s64)
    RET_ReallyLR implicit $x0

...
---
name:            si64_2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $d0, $w0

    ; CHECK-LABEL: name: si64_2
    ; CHECK: liveins: $d0, $w0
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
    ; CHECK: [[SMOVvi32to64_:%[0-9]+]]:gpr64 = SMOVvi32to64 [[INSERT_SUBREG]], 1
    ; CHECK: $x0 = COPY [[SMOVvi32to64_]]
    ; CHECK: RET_ReallyLR implicit $x0
    %0:fpr(<2 x s32>) = COPY $d0
    %3:gpr(s64) = G_CONSTANT i64 1
    %2:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
    %5:gpr(s32) = COPY %2(s32)
    %4:gpr(s64) = G_SEXT %5(s32)
    $x0 = COPY %4(s64)
    RET_ReallyLR implicit $x0

...
---
name:            zi64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0, $w0

    ; CHECK-LABEL: name: zi64
    ; CHECK: liveins: $q0, $w0
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[UMOVvi32_:%[0-9]+]]:gpr32 = UMOVvi32 [[COPY]], 1
    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[UMOVvi32_]], %subreg.sub_32
    ; CHECK: $x0 = COPY [[SUBREG_TO_REG]]
    ; CHECK: RET_ReallyLR implicit $x0
    %0:fpr(<4 x s32>) = COPY $q0
    %3:gpr(s64) = G_CONSTANT i64 1
    %2:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<4 x s32>), %3(s64)
    %5:gpr(s32) = COPY %2(s32)
    %4:gpr(s64) = G_ZEXT %5(s32)
    $x0 = COPY %4(s64)
    RET_ReallyLR implicit $x0

...
---
name:            zi64_2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $d0, $w0

    ; CHECK-LABEL: name: zi64_2
    ; CHECK: liveins: $d0, $w0
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
    ; CHECK: [[UMOVvi32_:%[0-9]+]]:gpr32 = UMOVvi32 [[INSERT_SUBREG]], 1
    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[UMOVvi32_]], %subreg.sub_32
    ; CHECK: $x0 = COPY [[SUBREG_TO_REG]]
    ; CHECK: RET_ReallyLR implicit $x0
     %0:fpr(<2 x s32>) = COPY $d0
    %3:gpr(s64) = G_CONSTANT i64 1
    %2:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
    %5:gpr(s32) = COPY %2(s32)
    %4:gpr(s64) = G_ZEXT %5(s32)
    $x0 = COPY %4(s64)
    RET_ReallyLR implicit $x0

...
---
name:            si32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0, $w0

    ; CHECK-LABEL: name: si32
    ; CHECK: liveins: $q0, $w0
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[SMOVvi16to32_:%[0-9]+]]:gpr32 = SMOVvi16to32 [[COPY]], 1
    ; CHECK: $w0 = COPY [[SMOVvi16to32_]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:fpr(<8 x s16>) = COPY $q0
    %4:gpr(s64) = G_CONSTANT i64 1
    %3:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %4(s64)
    %6:gpr(s16) = COPY %3(s16)
    %5:gpr(s32) = G_SEXT %6(s16)
    $w0 = COPY %5(s32)
    RET_ReallyLR implicit $w0

...
---
name:            zi32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0, $w0

    ; CHECK-LABEL: name: zi32
    ; CHECK: liveins: $q0, $w0
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[UMOVvi16_:%[0-9]+]]:gpr32 = UMOVvi16 [[COPY]], 1
    ; CHECK: $w0 = COPY [[UMOVvi16_]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:fpr(<8 x s16>) = COPY $q0
    %4:gpr(s64) = G_CONSTANT i64 1
    %3:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %4(s64)
    %6:gpr(s16) = COPY %3(s16)
    %5:gpr(s32) = G_ZEXT %6(s16)
    $w0 = COPY %5(s32)
    RET_ReallyLR implicit $w0

...
---
name:            si32_2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $d0, $w0

    ; CHECK-LABEL: name: si32_2
    ; CHECK: liveins: $d0, $w0
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
    ; CHECK: [[SMOVvi16to32_:%[0-9]+]]:gpr32 = SMOVvi16to32 [[INSERT_SUBREG]], 1
    ; CHECK: $w0 = COPY [[SMOVvi16to32_]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:fpr(<4 x s16>) = COPY $d0
    %4:gpr(s64) = G_CONSTANT i64 1
    %3:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %4(s64)
    %6:gpr(s16) = COPY %3(s16)
    %5:gpr(s32) = G_SEXT %6(s16)
    $w0 = COPY %5(s32)
    RET_ReallyLR implicit $w0

...
---
name:            zi32_2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $d0, $w0

    ; CHECK-LABEL: name: zi32_2
    ; CHECK: liveins: $d0, $w0
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
    ; CHECK: [[UMOVvi16_:%[0-9]+]]:gpr32 = UMOVvi16 [[INSERT_SUBREG]], 1
    ; CHECK: $w0 = COPY [[UMOVvi16_]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:fpr(<4 x s16>) = COPY $d0
    %4:gpr(s64) = G_CONSTANT i64 1
    %3:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %4(s64)
    %6:gpr(s16) = COPY %3(s16)
    %5:gpr(s32) = G_ZEXT %6(s16)
    $w0 = COPY %5(s32)
    RET_ReallyLR implicit $w0

...
---
name:            si16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0, $w0

    ; CHECK-LABEL: name: si16
    ; CHECK: liveins: $q0, $w0
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[SMOVvi8to32_:%[0-9]+]]:gpr32 = SMOVvi8to32 [[COPY]], 1
    ; CHECK: $w0 = COPY [[SMOVvi8to32_]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:fpr(<16 x s8>) = COPY $q0
    %4:gpr(s64) = G_CONSTANT i64 1
    %3:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<16 x s8>), %4(s64)
    %7:gpr(s8) = COPY %3(s8)
    %6:gpr(s32) = G_SEXT %7(s8)
    $w0 = COPY %6(s32)
    RET_ReallyLR implicit $w0
...
---
name:            zi16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0, $w0

    ; CHECK-LABEL: name: zi16
    ; CHECK: liveins: $q0, $w0
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[UMOVvi8_:%[0-9]+]]:gpr32 = UMOVvi8 [[COPY]], 1
    ; CHECK: $w0 = COPY [[UMOVvi8_]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:fpr(<16 x s8>) = COPY $q0
    %4:gpr(s64) = G_CONSTANT i64 1
    %3:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<16 x s8>), %4(s64)
    %7:gpr(s8) = COPY %3(s8)
    %6:gpr(s32) = G_ZEXT %7(s8)
    $w0 = COPY %6(s32)
    RET_ReallyLR implicit $w0

...
---
name:            si16_2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $d0, $w0

    ; CHECK-LABEL: name: si16_2
    ; CHECK: liveins: $d0, $w0
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
    ; CHECK: [[SMOVvi8to32_:%[0-9]+]]:gpr32 = SMOVvi8to32 [[INSERT_SUBREG]], 1
    ; CHECK: $w0 = COPY [[SMOVvi8to32_]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:fpr(<8 x s8>) = COPY $d0
    %4:gpr(s64) = G_CONSTANT i64 1
    %3:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<8 x s8>), %4(s64)
    %7:gpr(s8) = COPY %3(s8)
    %6:gpr(s32) = G_SEXT %7(s8)
    $w0 = COPY %6(s32)
    RET_ReallyLR implicit $w0
...
---
name:            zi16_2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $d0, $w0

    ; CHECK-LABEL: name: zi16_2
    ; CHECK: liveins: $d0, $w0
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
    ; CHECK: [[UMOVvi8_:%[0-9]+]]:gpr32 = UMOVvi8 [[INSERT_SUBREG]], 1
    ; CHECK: $w0 = COPY [[UMOVvi8_]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:fpr(<8 x s8>) = COPY $d0
    %4:gpr(s64) = G_CONSTANT i64 1
    %3:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<8 x s8>), %4(s64)
    %7:gpr(s8) = COPY %3(s8)
    %6:gpr(s32) = G_ZEXT %7(s8)
    $w0 = COPY %6(s32)
    RET_ReallyLR implicit $w0

...
---
name:            skip_anyext_to_16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    %5:fpr(<16 x s8>) = G_IMPLICIT_DEF
    %12:gpr(s64) = G_CONSTANT i64 0
    %4:fpr(s8) = G_EXTRACT_VECTOR_ELT %5(<16 x s8>), %12(s64)
    %11:gpr(s8) = COPY %4(s8)
    %8:gpr(s16) = G_ANYEXT %11(s8)
    %ext:gpr(s32) = G_ANYEXT %8(s16)
    $w0 = COPY %ext(s32)
...