llvm/llvm/test/CodeGen/AArch64/GlobalISel/select-fp16-fconstant.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-unknown-unknown -mattr=+fullfp16 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

---
name:            positive_zero
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: positive_zero
    ; CHECK: [[FMOVH0_:%[0-9]+]]:fpr16 = FMOVH0
    ; CHECK: $h0 = COPY [[FMOVH0_]]
    ; CHECK: RET_ReallyLR implicit $h0
    %0:fpr(s16) = G_FCONSTANT half 0.0
    $h0 = COPY %0(s16)
    RET_ReallyLR implicit $h0
...
---
name:            one
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: one
    ; CHECK: [[FMOVHi:%[0-9]+]]:fpr16 = FMOVHi 112
    ; CHECK: $h0 = COPY [[FMOVHi]]
    ; CHECK: RET_ReallyLR implicit $h0
    %0:fpr(s16) = G_FCONSTANT half 1.0
    $h0 = COPY %0(s16)
    RET_ReallyLR implicit $h0
...
---
name:            constant_pool_load
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: constant_pool_load
    ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
    ; CHECK: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s16) from constant-pool)
    ; CHECK: $h0 = COPY [[LDRHui]]
    ; CHECK: RET_ReallyLR implicit $h0
    %0:fpr(s16) = G_FCONSTANT half 0xH000B
    $h0 = COPY %0(s16)
    RET_ReallyLR implicit $h0