# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -global-isel-abort=1 --code-model=tiny -verify-machineinstrs %s -o - | FileCheck -check-prefix=CHECK-TINY %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
define void @imm_s32_gpr() { ret void }
define void @imm_s64_gpr() { ret void }
define void @test_f64_cp() { ret void }
define void @test_f32_cp_optsize() #0 { ret void }
define void @test_f32_cp_minsize() #1 { ret void }
attributes #0 = { optsize }
attributes #1 = { minsize }
...
---
# Check that we select a 32-bit immediate into a MOVi32imm.
name: imm_s32_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: imm_s32_gpr
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm -1234
; CHECK-NEXT: $w0 = COPY [[MOVi32imm]]
; CHECK-TINY-LABEL: name: imm_s32_gpr
; CHECK-TINY: liveins: $w0, $w1
; CHECK-TINY-NEXT: {{ $}}
; CHECK-TINY-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm -1234
; CHECK-TINY-NEXT: $w0 = COPY [[MOVi32imm]]
%0(s32) = G_CONSTANT i32 -1234
$w0 = COPY %0(s32)
...
---
# Check that we select a 64-bit immediate into a MOVi64imm.
name: imm_s64_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: imm_s64_gpr
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1234
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
; CHECK-TINY-LABEL: name: imm_s64_gpr
; CHECK-TINY: liveins: $w0, $w1
; CHECK-TINY-NEXT: {{ $}}
; CHECK-TINY-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1234
; CHECK-TINY-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK-TINY-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
%0(s64) = G_CONSTANT i64 1234
$x0 = COPY %0(s64)
...
# 64b FP immediates need to be loaded.
---
name: test_f64_cp
legalized: true
regBankSelected: true
liveins:
- { reg: '$d0' }
body: |
bb.1 (%ir-block.0):
liveins: $d0
; CHECK-LABEL: name: test_f64_cp
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s64) from constant-pool)
; CHECK-NEXT: %2:fpr64 = nofpexcept FADDDrr [[COPY]], [[LDRDui]]
; CHECK-NEXT: $d0 = COPY %2
; CHECK-NEXT: RET_ReallyLR implicit $d0
; CHECK-TINY-LABEL: name: test_f64_cp
; CHECK-TINY: liveins: $d0
; CHECK-TINY-NEXT: {{ $}}
; CHECK-TINY-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-TINY-NEXT: [[LDRDl:%[0-9]+]]:fpr64 = LDRDl %const.0 :: (load (s64) from constant-pool)
; CHECK-TINY-NEXT: %2:fpr64 = nofpexcept FADDDrr [[COPY]], [[LDRDl]]
; CHECK-TINY-NEXT: $d0 = COPY %2
; CHECK-TINY-NEXT: RET_ReallyLR implicit $d0
%0:fpr(s64) = COPY $d0
%1:fpr(s64) = G_FCONSTANT double 0x3FEFF7CED916872B
%2:fpr(s64) = G_FADD %0, %1
$d0 = COPY %2(s64)
RET_ReallyLR implicit $d0
...
# 32b FP immediates need to be loaded if using optsize.
---
name: test_f32_cp_optsize
legalized: true
regBankSelected: true
liveins:
- { reg: '$s0' }
body: |
bb.1 (%ir-block.0):
liveins: $s0
; CHECK-LABEL: name: test_f32_cp_optsize
; CHECK: liveins: $s0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK-NEXT: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s32) from constant-pool)
; CHECK-NEXT: %2:fpr32 = nofpexcept FADDSrr [[COPY]], [[LDRSui]]
; CHECK-NEXT: $s0 = COPY %2
; CHECK-NEXT: RET_ReallyLR implicit $s0
; CHECK-TINY-LABEL: name: test_f32_cp_optsize
; CHECK-TINY: liveins: $s0
; CHECK-TINY-NEXT: {{ $}}
; CHECK-TINY-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-TINY-NEXT: [[LDRSl:%[0-9]+]]:fpr32 = LDRSl %const.0 :: (load (s32) from constant-pool)
; CHECK-TINY-NEXT: %2:fpr32 = nofpexcept FADDSrr [[COPY]], [[LDRSl]]
; CHECK-TINY-NEXT: $s0 = COPY %2
; CHECK-TINY-NEXT: RET_ReallyLR implicit $s0
%0:fpr(s32) = COPY $s0
%1:fpr(s32) = G_FCONSTANT float 0x3FDB267DE0000000
%2:fpr(s32) = G_FADD %0, %1
$s0 = COPY %2(s32)
RET_ReallyLR implicit $s0
...
# 32b FP immediates need to be loaded if using minsize.
---
name: test_f32_cp_minsize
legalized: true
regBankSelected: true
liveins:
- { reg: '$s0' }
body: |
bb.1 (%ir-block.0):
liveins: $s0
; CHECK-LABEL: name: test_f32_cp_minsize
; CHECK: liveins: $s0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK-NEXT: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s32) from constant-pool)
; CHECK-NEXT: %2:fpr32 = nofpexcept FADDSrr [[COPY]], [[LDRSui]]
; CHECK-NEXT: $s0 = COPY %2
; CHECK-NEXT: RET_ReallyLR implicit $s0
; CHECK-TINY-LABEL: name: test_f32_cp_minsize
; CHECK-TINY: liveins: $s0
; CHECK-TINY-NEXT: {{ $}}
; CHECK-TINY-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-TINY-NEXT: [[LDRSl:%[0-9]+]]:fpr32 = LDRSl %const.0 :: (load (s32) from constant-pool)
; CHECK-TINY-NEXT: %2:fpr32 = nofpexcept FADDSrr [[COPY]], [[LDRSl]]
; CHECK-TINY-NEXT: $s0 = COPY %2
; CHECK-TINY-NEXT: RET_ReallyLR implicit $s0
%0:fpr(s32) = COPY $s0
%1:fpr(s32) = G_FCONSTANT float 0x3FDB267DE0000000
%2:fpr(s32) = G_FADD %0, %1
$s0 = COPY %2(s32)
RET_ReallyLR implicit $s0
...
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